CPUMR0.cpp@ 87758

Last change on this file since 87758 was 87361, checked in by vboxsync, 4 years ago
VMM/CPUM,HMSVM: Mirror the state of fUseFlags[CPUM_USED_FPU_GUEST] in CPUMCTX::fUsedFpuGuest so the HM switcher code can get at it (only relevant for windows) and avoid a call to CPUMIsGuestFPUStateActive/Loaded.
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File size: 35.7 KB

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1	/* $Id: CPUMR0.cpp 87361 2021-01-21 21:13:55Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vmcc.h>
26	#include <VBox/vmm/gvm.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#include <VBox/vmm/hm.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm-amd64-x86.h>
32	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
33	# include <iprt/mem.h>
34	# include <iprt/memobj.h>
35	# include <VBox/apic.h>
36	#endif
37	#include <iprt/x86.h>
38
39
40	/*********************************************************************************************************************************
41	* Structures and Typedefs *
42	*********************************************************************************************************************************/
43	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
44	/**
45	* Local APIC mappings.
46	*/
47	typedef struct CPUMHOSTLAPIC
48	{
49	/** Indicates that the entry is in use and have valid data. */
50	bool fEnabled;
51	/** Whether it's operating in X2APIC mode (EXTD). */
52	bool fX2Apic;
53	/** The APIC version number. */
54	uint32_t uVersion;
55	/** The physical address of the APIC registers. */
56	RTHCPHYS PhysBase;
57	/** The memory object entering the physical address. */
58	RTR0MEMOBJ hMemObj;
59	/** The mapping object for hMemObj. */
60	RTR0MEMOBJ hMapObj;
61	/** The mapping address APIC registers.
62	* @remarks Different CPUs may use the same physical address to map their
63	* APICs, so this pointer is only valid when on the CPU owning the
64	* APIC. */
65	void *pv;
66	} CPUMHOSTLAPIC;
67	#endif
68
69
70	/*********************************************************************************************************************************
71	* Global Variables *
72	*********************************************************************************************************************************/
73	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
74	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
75	#endif
76
77	/**
78	* CPUID bits to unify among all cores.
79	*/
80	static struct
81	{
82	uint32_t uLeaf; /*< Leaf to check. /
83	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
84	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
85	}
86	const g_aCpuidUnifyBits[] =
87	{
88	{
89	0x00000001,
90	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
91	X86_CPUID_FEATURE_EDX_CX8
92	}
93	};
94
95
96
97	/*********************************************************************************************************************************
98	* Internal Functions *
99	*********************************************************************************************************************************/
100	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
101	static int cpumR0MapLocalApics(void);
102	static void cpumR0UnmapLocalApics(void);
103	#endif
104	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
105
106
107	/**
108	* Does the Ring-0 CPU initialization once during module load.
109	* XXX Host-CPU hot-plugging?
110	*/
111	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
112	{
113	int rc = VINF_SUCCESS;
114	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
115	rc = cpumR0MapLocalApics();
116	#endif
117	return rc;
118	}
119
120
121	/**
122	* Terminate the module.
123	*/
124	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
125	{
126	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
127	cpumR0UnmapLocalApics();
128	#endif
129	return VINF_SUCCESS;
130	}
131
132
133	/**
134	* Check the CPUID features of this particular CPU and disable relevant features
135	* for the guest which do not exist on this CPU. We have seen systems where the
136	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
137	* @bugref{5436}.
138	*
139	* @note This function might be called simultaneously on more than one CPU!
140	*
141	* @param idCpu The identifier for the CPU the function is called on.
142	* @param pvUser1 Pointer to the VM structure.
143	* @param pvUser2 Ignored.
144	*/
145	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
146	{
147	PVMCC pVM = (PVMCC)pvUser1;
148
149	NOREF(idCpu); NOREF(pvUser2);
150	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
151	{
152	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
153	necessarily in the VM process context. So, we using the
154	legacy arrays as temporary storage. */
155
156	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
157	PCPUMCPUID pLegacyLeaf;
158	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
159	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
160	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
161	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
162	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
163	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
164	else
165	continue;
166
167	uint32_t eax, ebx, ecx, edx;
168	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
169
170	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
171	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
172	}
173	}
174
175
176	/**
177	* Does Ring-0 CPUM initialization.
178	*
179	* This is mainly to check that the Host CPU mode is compatible
180	* with VBox.
181	*
182	* @returns VBox status code.
183	* @param pVM The cross context VM structure.
184	*/
185	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
186	{
187	LogFlow(("CPUMR0Init: %p\n", pVM));
188
189	/*
190	* Check CR0 & CR4 flags.
191	*/
192	uint32_t u32CR0 = ASMGetCR0();
193	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
194	{
195	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
196	return VERR_UNSUPPORTED_CPU_MODE;
197	}
198
199	/*
200	* Check for sysenter and syscall usage.
201	*/
202	if (ASMHasCpuId())
203	{
204	/*
205	* SYSENTER/SYSEXIT
206	*
207	* Intel docs claim you should test both the flag and family, model &
208	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
209	* but don't support it. AMD CPUs may support this feature in legacy
210	* mode, they've banned it from long mode. Since we switch to 32-bit
211	* mode when entering raw-mode context the feature would become
212	* accessible again on AMD CPUs, so we have to check regardless of
213	* host bitness.
214	*/
215	uint32_t u32CpuVersion;
216	uint32_t u32Dummy;
217	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
218	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
219	uint32_t const u32Family = u32CpuVersion >> 8;
220	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
221	uint32_t const u32Stepping = u32CpuVersion & 0xF;
222	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
223	&& ( u32Family != 6 /* (> pentium pro) */
224	\|\| u32Model >= 3
225	\|\| u32Stepping >= 3
226	\|\| !ASMIsIntelCpu())
227	)
228	{
229	/*
230	* Read the MSR and see if it's in use or not.
231	*/
232	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
233	if (u32)
234	{
235	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
236	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
237	}
238	}
239
240	/*
241	* SYSCALL/SYSRET
242	*
243	* This feature is indicated by the SEP bit returned in EDX by CPUID
244	* function 0x80000001. Intel CPUs only supports this feature in
245	* long mode. Since we're not running 64-bit guests in raw-mode there
246	* are no issues with 32-bit intel hosts.
247	*/
248	uint32_t cExt = 0;
249	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
250	if (ASMIsValidExtRange(cExt))
251	{
252	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
253	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
254	{
255	#ifdef RT_ARCH_X86
256	if (!ASMIsIntelCpu())
257	#endif
258	{
259	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
260	if (fEfer & MSR_K6_EFER_SCE)
261	{
262	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
263	Log(("CPUMR0Init: host uses syscall\n"));
264	}
265	}
266	}
267	}
268
269	/*
270	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
271	* structure and as well as the guest MSR.
272	* Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
273	*/
274	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
275	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
276	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
277	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
278	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
279	uint32_t const cStdRange = ASMCpuId_EAX(0);
280	if ( ASMIsValidStdRange(cStdRange)
281	&& cStdRange >= 7)
282	{
283	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
284	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
285	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
286	{
287	/* Host: */
288	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
289	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
290	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
291	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
292	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
293	pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
294
295	/* guest: */
296	if (!pVM->cpum.s.GuestFeatures.fArchCap)
297	fArchVal = 0;
298	else if (!pVM->cpum.s.GuestFeatures.fIbrs)
299	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
300	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
301	pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
302	pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
303	pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
304	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
305	pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
306	}
307	else
308	pVM->cpum.s.HostFeatures.fArchCap = 0;
309	}
310
311	/*
312	* Unify/cross check some CPUID feature bits on all available CPU cores
313	* and threads. We've seen CPUs where the monitor support differed.
314	*
315	* Because the hyper heap isn't always mapped into ring-0, we cannot
316	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
317	* as temp ring-0 accessible memory instead, ASSUMING that they're all
318	* up to date when we get here.
319	*/
320	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
321
322	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
323	{
324	bool fIgnored;
325	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
326	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
327	if (pLeaf)
328	{
329	PCPUMCPUID pLegacyLeaf;
330	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
331	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
332	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
333	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
334	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
335	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
336	else
337	continue;
338
339	pLeaf->uEcx = pLegacyLeaf->uEcx;
340	pLeaf->uEdx = pLegacyLeaf->uEdx;
341	}
342	}
343
344	}
345
346
347	/*
348	* Check if debug registers are armed.
349	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
350	*/
351	uint32_t u32DR7 = ASMGetDR7();
352	if (u32DR7 & X86_DR7_ENABLED_MASK)
353	{
354	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
355	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
356	}
357
358	return VINF_SUCCESS;
359	}
360
361
362	/**
363	* Trap handler for device-not-available fault (\#NM).
364	* Device not available, FP or (F)WAIT instruction.
365	*
366	* @returns VBox status code.
367	* @retval VINF_SUCCESS if the guest FPU state is loaded.
368	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
369	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
370	*
371	* @param pVM The cross context VM structure.
372	* @param pVCpu The cross context virtual CPU structure.
373	*/
374	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
375	{
376	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
377	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
378
379	/* If the FPU state has already been loaded, then it's a guest trap. */
380	if (CPUMIsGuestFPUStateActive(pVCpu))
381	{
382	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
383	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
384	return VINF_EM_RAW_GUEST_TRAP;
385	}
386
387	/*
388	* There are two basic actions:
389	* 1. Save host fpu and restore guest fpu.
390	* 2. Generate guest trap.
391	*
392	* When entering the hypervisor we'll always enable MP (for proper wait
393	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
394	* is taken from the guest OS in order to get proper SSE handling.
395	*
396	*
397	* Actions taken depending on the guest CR0 flags:
398	*
399	* 3 2 1
400	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
401	* ------------------------------------------------------------------------
402	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
403	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
404	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
405	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
406	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
407	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
408	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
409	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
410	*/
411
412	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
413	{
414	case X86_CR0_MP \| X86_CR0_TS:
415	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
416	return VINF_EM_RAW_GUEST_TRAP;
417	default:
418	break;
419	}
420
421	return CPUMR0LoadGuestFPU(pVM, pVCpu);
422	}
423
424
425	/**
426	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
427	* state into the CPU.
428	*
429	* @returns VINF_SUCCESS on success, host CR0 unmodified.
430	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
431	* modified and VT-x needs to update the value in the VMCS.
432	*
433	* @param pVM The cross context VM structure.
434	* @param pVCpu The cross context virtual CPU structure.
435	*/
436	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
437	{
438	int rc;
439	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
440	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
441
442	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
443	{
444	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
445	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
446	}
447	else
448	{
449	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
450	/** @todo r=ramshankar: Can't we used a cached value here
451	* instead of reading the MSR? host EFER doesn't usually
452	* change. */
453	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
454	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
455	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
456	else
457	{
458	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
459	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
460	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
461	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
462	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
463	ASMSetFlags(uSavedFlags);
464	}
465	}
466	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
467	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
468	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
469	return rc;
470	}
471
472
473	/**
474	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
475	* needed.
476	*
477	* @returns true if we saved the guest state.
478	* @param pVCpu The cross context virtual CPU structure.
479	*/
480	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
481	{
482	bool fSavedGuest;
483	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
484	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
485	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
486	{
487	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
488	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
489	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
490	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
491	else
492	{
493	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
494	save/restore the XMM state with fxsave/fxrstor. */
495	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
496	if (uHostEfer & MSR_K6_EFER_FFXSR)
497	{
498	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
499	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
500	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
501	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
502	ASMSetFlags(uSavedFlags);
503	}
504	else
505	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
506	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
507	}
508	}
509	else
510	fSavedGuest = false;
511	Assert(!( pVCpu->cpum.s.fUseFlags
512	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)));
513	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
514	return fSavedGuest;
515	}
516
517
518	/**
519	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
520	* DR7 with safe values.
521	*
522	* @returns VBox status code.
523	* @param pVCpu The cross context virtual CPU structure.
524	*/
525	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
526	{
527	/*
528	* Save the host state.
529	*/
530	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
531	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
532	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
533	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
534	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
535	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
536	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
537
538	/* Preemption paranoia. */
539	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
540
541	/*
542	* Make sure DR7 is harmless or else we could trigger breakpoints when
543	* load guest or hypervisor DRx values later.
544	*/
545	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
546	ASMSetDR7(X86_DR7_INIT_VAL);
547
548	return VINF_SUCCESS;
549	}
550
551
552	/**
553	* Saves the guest DRx state residing in host registers and restore the host
554	* register values.
555	*
556	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
557	* since it's assumed that we're shadowing the guest DRx register values
558	* accurately when using the combined hypervisor debug register values
559	* (CPUMR0LoadHyperDebugState).
560	*
561	* @returns true if either guest or hypervisor debug registers were loaded.
562	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
563	* @param fDr6 Whether to include DR6 or not.
564	* @thread EMT(pVCpu)
565	*/
566	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
567	{
568	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
569	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
570
571	/*
572	* Do we need to save the guest DRx registered loaded into host registers?
573	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
574	*/
575	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
576	{
577	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
578	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
579	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
580	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
581	if (fDr6)
582	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
583	}
584	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
585
586	/*
587	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
588	*/
589	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
590	{
591	/* A bit of paranoia first... */
592	uint64_t uCurDR7 = ASMGetDR7();
593	if (uCurDR7 != X86_DR7_INIT_VAL)
594	ASMSetDR7(X86_DR7_INIT_VAL);
595
596	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
597	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
598	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
599	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
600	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
601	* expensive DRx reads are over DRx writes. */
602	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
603	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
604
605	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
606	}
607
608	return fDrXLoaded;
609	}
610
611
612	/**
613	* Saves the guest DRx state if it resides host registers.
614	*
615	* This does NOT clear any use flags, so the host registers remains loaded with
616	* the guest DRx state upon return. The purpose is only to make sure the values
617	* in the CPU context structure is up to date.
618	*
619	* @returns true if the host registers contains guest values, false if not.
620	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
621	* @param fDr6 Whether to include DR6 or not.
622	* @thread EMT(pVCpu)
623	*/
624	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
625	{
626	/*
627	* Do we need to save the guest DRx registered loaded into host registers?
628	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
629	*/
630	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
631	{
632	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
633	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
634	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
635	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
636	if (fDr6)
637	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
638	return true;
639	}
640	return false;
641	}
642
643
644	/**
645	* Lazily sync in the debug state.
646	*
647	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
648	* @param fDr6 Whether to include DR6 or not.
649	* @thread EMT(pVCpu)
650	*/
651	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
652	{
653	/*
654	* Save the host state and disarm all host BPs.
655	*/
656	cpumR0SaveHostDebugState(pVCpu);
657	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
658
659	/*
660	* Activate the guest state DR0-3.
661	* DR7 and DR6 (if fDr6 is true) are left to the caller.
662	*/
663	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
664	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
665	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
666	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
667	if (fDr6)
668	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
669
670	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
671	}
672
673
674	/**
675	* Lazily sync in the hypervisor debug state
676	*
677	* @returns VBox status code.
678	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
679	* @param fDr6 Whether to include DR6 or not.
680	* @thread EMT(pVCpu)
681	*/
682	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
683	{
684	/*
685	* Save the host state and disarm all host BPs.
686	*/
687	cpumR0SaveHostDebugState(pVCpu);
688	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
689
690	/*
691	* Make sure the hypervisor values are up to date.
692	*/
693	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
694
695	/*
696	* Activate the guest state DR0-3.
697	* DR7 and DR6 (if fDr6 is true) are left to the caller.
698	*/
699	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
700	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
701	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
702	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
703	if (fDr6)
704	ASMSetDR6(X86_DR6_INIT_VAL);
705
706	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
707	}
708
709	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
710
711	/**
712	* Per-CPU callback that probes the CPU for APIC support.
713	*
714	* @param idCpu The identifier for the CPU the function is called on.
715	* @param pvUser1 Ignored.
716	* @param pvUser2 Ignored.
717	*/
718	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
719	{
720	NOREF(pvUser1); NOREF(pvUser2);
721	int iCpu = RTMpCpuIdToSetIndex(idCpu);
722	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
723
724	/*
725	* Check for APIC support.
726	*/
727	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
728	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
729	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
730	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
731	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX)
732	\|\| ASMIsShanghaiCpuEx(u32EBX, u32ECX, u32EDX)
733	\|\| ASMIsHygonCpuEx(u32EBX, u32ECX, u32EDX))
734	&& ASMIsValidStdRange(uMaxLeaf))
735	{
736	uint32_t uDummy;
737	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
738	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
739	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
740	{
741	/*
742	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
743	*/
744	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
745	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
746
747	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
748	uint32_t uMaxExtLeaf;
749	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
750	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
751	&& ASMIsValidExtRange(uMaxExtLeaf))
752	{
753	uint32_t u32PhysBits;
754	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
755	u32PhysBits &= 0xff;
756	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
757	}
758
759	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
760	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
761	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
762	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
763	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
764	}
765	}
766	}
767
768
769
770	/**
771	* Per-CPU callback that verifies our APIC expectations.
772	*
773	* @param idCpu The identifier for the CPU the function is called on.
774	* @param pvUser1 Ignored.
775	* @param pvUser2 Ignored.
776	*/
777	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
778	{
779	NOREF(pvUser1); NOREF(pvUser2);
780
781	int iCpu = RTMpCpuIdToSetIndex(idCpu);
782	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
783	if (!g_aLApics[iCpu].fEnabled)
784	return;
785
786	/*
787	* 0x0X 82489 external APIC
788	* 0x1X Local APIC
789	* 0x2X..0xFF reserved
790	*/
791	uint32_t uApicVersion;
792	if (g_aLApics[iCpu].fX2Apic)
793	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
794	else
795	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
796	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
797	{
798	g_aLApics[iCpu].uVersion = uApicVersion;
799
800	# if 0 /* enable if you need it. */
801	if (g_aLApics[iCpu].fX2Apic)
802	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
803	iCpu, uApicVersion,
804	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
805	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
806	ApicX2RegRead32(APIC_REG_LVT_CMCI));
807	else
808	{
809	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
810	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
811	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
812	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
813	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
814	if (uApicVersion & 0x80000000)
815	{
816	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
817	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
818	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
819	iCpu,
820	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
821	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
822	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
823	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
824	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
825	}
826	}
827	# endif
828	}
829	else
830	{
831	g_aLApics[iCpu].fEnabled = false;
832	g_aLApics[iCpu].fX2Apic = false;
833	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
834	}
835	}
836
837
838	/**
839	* Map the MMIO page of each local APIC in the system.
840	*/
841	static int cpumR0MapLocalApics(void)
842	{
843	/*
844	* Check that we'll always stay within the array bounds.
845	*/
846	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
847	{
848	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
849	return VERR_TOO_MANY_CPUS;
850	}
851
852	/*
853	* Create mappings for all online CPUs we think have legacy APICs.
854	*/
855	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
856
857	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
858	{
859	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
860	{
861	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
862	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
863	if (RT_SUCCESS(rc))
864	{
865	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
866	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
867	if (RT_SUCCESS(rc))
868	{
869	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
870	continue;
871	}
872	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
873	}
874	g_aLApics[iCpu].fEnabled = false;
875	}
876	g_aLApics[iCpu].pv = NULL;
877	}
878
879	/*
880	* Check the APICs.
881	*/
882	if (RT_SUCCESS(rc))
883	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
884
885	if (RT_FAILURE(rc))
886	{
887	cpumR0UnmapLocalApics();
888	return rc;
889	}
890
891	# ifdef LOG_ENABLED
892	/*
893	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
894	* and !VBOX_WITH_R0_LOGGING).
895	*/
896	if (LogIsEnabled())
897	{
898	uint32_t cEnabled = 0;
899	uint32_t cX2Apics = 0;
900	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
901	if (g_aLApics[iCpu].fEnabled)
902	{
903	cEnabled++;
904	cX2Apics += g_aLApics[iCpu].fX2Apic;
905	}
906	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
907	}
908	# endif
909
910	return VINF_SUCCESS;
911	}
912
913
914	/**
915	* Unmap the Local APIC of all host CPUs.
916	*/
917	static void cpumR0UnmapLocalApics(void)
918	{
919	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
920	{
921	if (g_aLApics[iCpu].pv)
922	{
923	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
924	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
925	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
926	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
927	g_aLApics[iCpu].fEnabled = false;
928	g_aLApics[iCpu].fX2Apic = false;
929	g_aLApics[iCpu].pv = NULL;
930	}
931	}
932	}
933
934
935	/**
936	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
937	*
938	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
939	* the world switchers can access the APIC registers for the purpose of
940	* disabling and re-enabling the NMIs. Must be called with disabled preemption
941	* or disabled interrupts!
942	*
943	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
944	* @param iHostCpuSet The CPU set index of the current host CPU.
945	*/
946	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPUCC pVCpu, uint32_t iHostCpuSet)
947	{
948	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
949	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
950	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
951	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
952	}
953
954	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
955

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 87758

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