CPUMR0.cpp@ 19420

Last change on this file since 19420 was 18927, checked in by vboxsync, 16 years ago
Big step to separate VMM data structures for guest SMP. (pgm, em)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 15.6 KB

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1	/* $Id: CPUMR0.cpp 18927 2009-04-16 11:41:38Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter if it's used.
64	*/
65	if (ASMHasCpuId())
66	{
67	uint32_t u32CpuVersion;
68	uint32_t u32Dummy;
69	uint32_t u32Features;
70	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
71	uint32_t u32Family = u32CpuVersion >> 8;
72	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
73	uint32_t u32Stepping = u32CpuVersion & 0xF;
74
75	/*
76	* Intel docs claim you should test both the flag and family, model & stepping.
77	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
78	*/
79	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
80	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
81	{
82	/*
83	* Read the MSR and see if it's in use or not.
84	*/
85	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
86	if (u32)
87	{
88	for (unsigned i=0;i<pVM->cCPUs;i++)
89	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_SYSENTER;
90
91	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
92	}
93	}
94
95	/** @todo check for AMD and syscall!!!!!! */
96	}
97
98
99	/*
100	* Check if debug registers are armed.
101	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
102	*/
103	uint32_t u32DR7 = ASMGetDR7();
104	if (u32DR7 & X86_DR7_ENABLED_MASK)
105	{
106	for (unsigned i=0;i<pVM->cCPUs;i++)
107	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
108	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
109	}
110
111	return VINF_SUCCESS;
112	}
113
114
115	/**
116	* Lazily sync in the FPU/XMM state
117	*
118	* @returns VBox status code.
119	* @param pVM VM handle.
120	* @param pVCpu VMCPU handle.
121	* @param pCtx CPU context
122	*/
123	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
124	{
125	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
126	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
127
128	/* If the FPU state has already been loaded, then it's a guest trap. */
129	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
130	{
131	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
132	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135
136	/*
137	* There are two basic actions:
138	* 1. Save host fpu and restore guest fpu.
139	* 2. Generate guest trap.
140	*
141	* When entering the hypervisor we'll always enable MP (for proper wait
142	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
143	* is taken from the guest OS in order to get proper SSE handling.
144	*
145	*
146	* Actions taken depending on the guest CR0 flags:
147	*
148	* 3 2 1
149	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
150	* ------------------------------------------------------------------------
151	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
152	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
153	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
154	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
155	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
156	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
157	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
158	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
159	*/
160
161	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
162	{
163	case X86_CR0_MP \| X86_CR0_TS:
164	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
165	return VINF_EM_RAW_GUEST_TRAP;
166	default:
167	break;
168	}
169
170	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
171	if (CPUMIsGuestInLongModeEx(pCtx))
172	{
173	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
174
175	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
176	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
177
178	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
179	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
180	}
181	else
182	#endif
183	{
184	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
185	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 2.1. */
186	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
187	uint64_t SavedEFER = 0;
188	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
189	{
190	SavedEFER = ASMRdMsr(MSR_K6_EFER);
191	if (SavedEFER & MSR_K6_EFER_FFXSR)
192	{
193	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
194	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
195	}
196	}
197
198	/* Do the job and record that we've switched FPU state. */
199	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
200
201	/* Restore EFER. */
202	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
203	ASMWrMsr(MSR_K6_EFER, SavedEFER);
204
205	# else
206	uint64_t oldMsrEFERHost = 0;
207	uint32_t oldCR0 = ASMGetCR0();
208
209	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
210	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
211	{
212	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
213	* bird: what about starting by skipping the ASMWrMsr below if we didn't
214	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
215	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
216	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
217	{
218	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
219	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
220	}
221	}
222
223	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
224	int rc = CPUMHandleLazyFPU(pVCpu);
225	AssertRC(rc);
226	Assert(CPUMIsGuestFPUStateActive(pVCpu));
227
228	/* Restore EFER MSR */
229	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
230	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
231
232	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
233	ASMSetCR0(oldCR0);
234	# endif
235
236	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
237
238	/*
239	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
240	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
241	*/
242	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
243	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
244	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
245
246	cpumR0LoadFPU(pCtx);
247
248	/*
249	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
250	*
251	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
252	*/
253	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
254	{
255	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
256	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
257
258	if (msrEFERHost & MSR_K6_EFER_FFXSR)
259	{
260	/* fxrstor doesn't restore the XMM state! */
261	cpumR0LoadXMM(pCtx);
262	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
263	}
264	}
265
266	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
267	}
268
269	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
270	return VINF_SUCCESS;
271	}
272
273
274	/**
275	* Save guest FPU/XMM state
276	*
277	* @returns VBox status code.
278	* @param pVM VM handle.
279	* @param pVCpu VMCPU handle.
280	* @param pCtx CPU context
281	*/
282	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
283	{
284	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
285	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
286	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
287
288	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
289	if (CPUMIsGuestInLongModeEx(pCtx))
290	{
291	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
292	{
293	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
294	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
295	}
296	/* else nothing to do; we didn't perform a world switch */
297	}
298	else
299	#endif
300	{
301	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
302	uint64_t oldMsrEFERHost = 0;
303
304	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
305	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
306	{
307	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
308	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
309	}
310	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
311
312	/* Restore EFER MSR */
313	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
314	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
315
316	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
317	cpumR0SaveFPU(pCtx);
318	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
319	{
320	/* fxsave doesn't save the XMM state! */
321	cpumR0SaveXMM(pCtx);
322	}
323
324	/*
325	* Restore the original FPU control word and MXCSR.
326	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
327	*/
328	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
329	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
330	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
331	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
332	}
333
334	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
335	return VINF_SUCCESS;
336	}
337
338
339	/**
340	* Save guest debug state
341	*
342	* @returns VBox status code.
343	* @param pVM VM handle.
344	* @param pVCpu VMCPU handle.
345	* @param pCtx CPU context
346	* @param fDR6 Include DR6 or not
347	*/
348	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
349	{
350	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
351
352	/* Save the guest's debug state. The caller is responsible for DR7. */
353	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
354	if (CPUMIsGuestInLongModeEx(pCtx))
355	{
356	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
357	{
358	uint64_t dr6 = pCtx->dr[6];
359
360	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
361	if (!fDR6) /* dr6 was already up-to-date */
362	pCtx->dr[6] = dr6;
363	}
364	}
365	else
366	#endif
367	{
368	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
369	cpumR0SaveDRx(&pCtx->dr[0]);
370	#else
371	pCtx->dr[0] = ASMGetDR0();
372	pCtx->dr[1] = ASMGetDR1();
373	pCtx->dr[2] = ASMGetDR2();
374	pCtx->dr[3] = ASMGetDR3();
375	#endif
376	if (fDR6)
377	pCtx->dr[6] = ASMGetDR6();
378	}
379
380	/*
381	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
382	* DR7 contains 0x400 right now.
383	*/
384	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
385	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
386	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
387	#else
388	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
389	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
390	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
391	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
392	#endif
393	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
394	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
395
396	pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
397	return VINF_SUCCESS;
398	}
399
400
401	/**
402	* Lazily sync in the debug state
403	*
404	* @returns VBox status code.
405	* @param pVM VM handle.
406	* @param pVCpu VMCPU handle.
407	* @param pCtx CPU context
408	* @param fDR6 Include DR6 or not
409	*/
410	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
411	{
412	/* Save the host state. */
413	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
414	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
415	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
416	#else
417	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
418	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
419	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
420	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
421	#endif
422	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
423	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
424	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
425	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
426	ASMSetDR7(X86_DR7_INIT_VAL);
427
428	/* Activate the guest state DR0-3; DR7 is left to the caller. */
429	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
430	if (CPUMIsGuestInLongModeEx(pCtx))
431	{
432	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
433	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
434	}
435	else
436	#endif
437	{
438	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
439	cpumR0LoadDRx(&pCtx->dr[0]);
440	#else
441	ASMSetDR0(pCtx->dr[0]);
442	ASMSetDR1(pCtx->dr[1]);
443	ASMSetDR2(pCtx->dr[2]);
444	ASMSetDR3(pCtx->dr[3]);
445	#endif
446	if (fDR6)
447	ASMSetDR6(pCtx->dr[6]);
448	}
449
450	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
451	return VINF_SUCCESS;
452	}
453
454

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 19420

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