| 1 | /* $Id: TRPMGC.cpp 18927 2009-04-16 11:41:38Z vboxsync $ */
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| 2 | /** @file
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| 3 | * TRPM - The Trap Monitor, Guest Context
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | * additional information or have any questions.
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| 20 | */
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| 21 |
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| 22 |
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| 23 | /*******************************************************************************
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| 24 | * Header Files *
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| 25 | *******************************************************************************/
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| 26 | #define LOG_GROUP LOG_GROUP_TRPM
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| 27 | #include <VBox/trpm.h>
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| 28 | #include <VBox/cpum.h>
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| 29 | #include <VBox/vmm.h>
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| 30 | #include "TRPMInternal.h"
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| 31 | #include <VBox/vm.h>
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| 32 |
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| 33 | #include <VBox/err.h>
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| 34 | #include <VBox/x86.h>
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| 35 | #include <VBox/em.h>
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| 36 | #include <iprt/assert.h>
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| 37 | #include <iprt/asm.h>
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| 38 | #include <VBox/log.h>
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| 39 | #include <VBox/selm.h>
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| 40 |
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| 41 |
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| 42 |
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| 43 | /**
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| 44 | * Arms a temporary trap handler for traps in Hypervisor code.
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| 45 | *
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| 46 | * The operation is similar to a System V signal handler. I.e. when the handler
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| 47 | * is called it is first set to default action. So, if you need to handler more
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| 48 | * than one trap, you must reinstall the handler.
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| 49 | *
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| 50 | * To uninstall the temporary handler, call this function with pfnHandler set to NULL.
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| 51 | *
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| 52 | * @returns VBox status.
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| 53 | * @param pVM VM handle.
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| 54 | * @param iTrap Trap number to install handler [0..255].
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| 55 | * @param pfnHandler Pointer to the handler. Use NULL for uninstalling the handler.
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| 56 | */
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| 57 | VMMRCDECL(int) TRPMGCSetTempHandler(PVM pVM, unsigned iTrap, PFNTRPMGCTRAPHANDLER pfnHandler)
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| 58 | {
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| 59 | /*
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| 60 | * Validate input.
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| 61 | */
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| 62 | if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aTmpTrapHandlers))
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| 63 | {
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| 64 | AssertMsgFailed(("Trap handler iTrap=%u is out of range!\n", iTrap));
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| 65 | return VERR_INVALID_PARAMETER;
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| 66 | }
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| 67 |
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| 68 | /*
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| 69 | * Install handler.
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| 70 | */
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| 71 | pVM->trpm.s.aTmpTrapHandlers[iTrap] = (RTRCPTR)(uintptr_t)pfnHandler;
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| 72 | return VINF_SUCCESS;
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| 73 | }
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| 74 |
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| 75 |
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| 76 | /**
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| 77 | * Return to host context from a hypervisor trap handler.
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| 78 | *
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| 79 | * This function will *never* return.
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| 80 | * It will also reset any traps that are pending.
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| 81 | *
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| 82 | * @param pVM The VM handle.
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| 83 | * @param rc The return code for host context.
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| 84 | */
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| 85 | VMMRCDECL(void) TRPMGCHyperReturnToHost(PVM pVM, int rc)
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| 86 | {
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| 87 | PVMCPU pVCpu = VMMGetCpu0(pVM);
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| 88 |
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| 89 | LogFlow(("TRPMGCHyperReturnToHost: rc=%Rrc\n", rc));
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| 90 | TRPMResetTrap(pVM);
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| 91 | CPUMHyperSetCtxCore(pVCpu, NULL);
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| 92 | VMMGCGuestToHost(pVM, rc);
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| 93 | AssertReleaseFailed();
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| 94 | }
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| 95 |
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| 96 |
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| 97 | /**
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| 98 | * \#PF Virtual Handler callback for Guest write access to the Guest's own current IDT.
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| 99 | *
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| 100 | * @returns VBox status code (appropriate for trap handling and GC return).
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| 101 | * @param pVM VM Handle.
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| 102 | * @param uErrorCode CPU Error code.
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| 103 | * @param pRegFrame Trap register frame.
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| 104 | * @param pvFault The fault address (cr2).
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| 105 | * @param pvRange The base address of the handled virtual range.
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| 106 | * @param offRange The offset of the access into this range.
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| 107 | * (If it's a EIP range this's the EIP, if not it's pvFault.)
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| 108 | */
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| 109 | VMMRCDECL(int) trpmRCGuestIDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
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| 110 | {
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| 111 | PVMCPU pVCpu = VMMGetCpu0(pVM);
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| 112 | uint16_t cbIDT;
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| 113 | RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
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| 114 | #ifdef VBOX_STRICT
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| 115 | RTGCPTR GCPtrIDTEnd = (RTGCPTR)((RTGCUINTPTR)GCPtrIDT + cbIDT + 1);
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| 116 | #endif
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| 117 | uint32_t iGate = ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)GCPtrIDT)/sizeof(VBOXIDTE);
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| 118 |
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| 119 | AssertMsg(offRange < (uint32_t)cbIDT+1, ("pvFault=%RGv GCPtrIDT=%RGv-%RGv pvRange=%RGv\n", pvFault, GCPtrIDT, GCPtrIDTEnd, pvRange));
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| 120 | Assert((RTGCPTR)(RTRCUINTPTR)pvRange == GCPtrIDT);
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| 121 |
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| 122 | #if 0
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| 123 | /* Note! this causes problems in Windows XP as instructions following the update can be dangerous (str eax has been seen) */
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| 124 | /* Note! not going back to ring 3 could make the code scanner miss them. */
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| 125 | /* Check if we can handle the write here. */
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| 126 | if ( iGate != 3 /* Gate 3 is handled differently; could do it here as well, but let ring 3 handle this case for now. */
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| 127 | && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iGate)) /* Passthru gates need special attention too. */
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| 128 | {
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| 129 | uint32_t cb;
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| 130 | int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
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| 131 | if (RT_SUCCESS(rc) && cb)
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| 132 | {
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| 133 | uint32_t iGate1 = (offRange + cb - 1)/sizeof(VBOXIDTE);
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| 134 |
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| 135 | Log(("trpmRCGuestIDTWriteHandler: write to gate %x (%x) offset %x cb=%d\n", iGate, iGate1, offRange, cb));
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| 136 |
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| 137 | trpmClearGuestTrapHandler(pVM, iGate);
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| 138 | if (iGate != iGate1)
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| 139 | trpmClearGuestTrapHandler(pVM, iGate1);
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| 140 |
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| 141 | STAM_COUNTER_INC(&pVM->trpm.s.StatRCWriteGuestIDTHandled);
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| 142 | return VINF_SUCCESS;
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| 143 | }
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| 144 | }
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| 145 | #else
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| 146 | NOREF(iGate);
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| 147 | #endif
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| 148 |
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| 149 | Log(("trpmRCGuestIDTWriteHandler: eip=%RGv write to gate %x offset %x\n", pRegFrame->eip, iGate, offRange));
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| 150 |
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| 151 | /** @todo Check which IDT entry and keep the update cost low in TRPMR3SyncIDT() and CSAMCheckGates(). */
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| 152 | VM_FF_SET(pVM, VM_FF_TRPM_SYNC_IDT);
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| 153 |
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| 154 | STAM_COUNTER_INC(&pVM->trpm.s.StatRCWriteGuestIDTFault);
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| 155 | return VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT;
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| 156 | }
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| 157 |
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| 158 |
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| 159 | /**
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| 160 | * \#PF Virtual Handler callback for Guest write access to the VBox shadow IDT.
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| 161 | *
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| 162 | * @returns VBox status code (appropriate for trap handling and GC return).
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| 163 | * @param pVM VM Handle.
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| 164 | * @param uErrorCode CPU Error code.
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| 165 | * @param pRegFrame Trap register frame.
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| 166 | * @param pvFault The fault address (cr2).
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| 167 | * @param pvRange The base address of the handled virtual range.
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| 168 | * @param offRange The offset of the access into this range.
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| 169 | * (If it's a EIP range this's the EIP, if not it's pvFault.)
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| 170 | */
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| 171 | VMMRCDECL(int) trpmRCShadowIDTWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange)
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| 172 | {
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| 173 | PVMCPU pVCpu = VMMGetCpu0(pVM);
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| 174 | LogRel(("FATAL ERROR: trpmRCShadowIDTWriteHandler: eip=%08X pvFault=%RGv pvRange=%08X\r\n", pRegFrame->eip, pvFault, pvRange));
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| 175 |
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| 176 | /* If we ever get here, then the guest has executed an sidt instruction that we failed to patch. In theory this could be very bad, but
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| 177 | * there are nasty applications out there that install device drivers that mess with the guest's IDT. In those cases, it's quite ok
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| 178 | * to simply ignore the writes and pretend success.
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| 179 | */
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| 180 | RTGCPTR PC;
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| 181 | int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
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| 182 | if (rc == VINF_SUCCESS)
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| 183 | {
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| 184 | DISCPUSTATE Cpu;
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| 185 | uint32_t cbOp;
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| 186 | rc = EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
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| 187 | if (rc == VINF_SUCCESS)
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| 188 | {
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| 189 | /* Just ignore the write. */
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| 190 | pRegFrame->eip += Cpu.opsize;
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| 191 | return VINF_SUCCESS;
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| 192 | }
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| 193 | }
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| 194 |
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| 195 | return VERR_TRPM_SHADOW_IDT_WRITE;
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| 196 | }
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| 197 |
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