VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMGC/HWACCMGCA.asm@ 26600

Last change on this file since 26600 was 22079, checked in by vboxsync, 15 years ago

Back to manual msr save and restore.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 16.3 KB
Line 
1; $Id: HWACCMGCA.asm 22079 2009-08-07 16:26:25Z vboxsync $
2;; @file
3; VMXM - GC vmx helpers
4;
5
6;
7; Copyright (C) 2006-2007 Sun Microsystems, Inc.
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18; Clara, CA 95054 USA or visit http://www.sun.com if you need
19; additional information or have any questions.
20;
21
22;*******************************************************************************
23;* Header Files *
24;*******************************************************************************
25%undef RT_ARCH_X86
26%define RT_ARCH_AMD64
27%include "VBox/asmdefs.mac"
28%include "VBox/err.mac"
29%include "VBox/hwacc_vmx.mac"
30%include "VBox/cpum.mac"
31%include "VBox/x86.mac"
32%include "../HWACCMInternal.mac"
33
34%ifdef RT_OS_OS2 ;; @todo fix OMF support in yasm and kick nasm out completely.
35 %macro vmwrite 2,
36 int3
37 %endmacro
38 %define vmlaunch int3
39 %define vmresume int3
40 %define vmsave int3
41 %define vmload int3
42 %define vmrun int3
43 %define clgi int3
44 %define stgi int3
45 %macro invlpga 2,
46 int3
47 %endmacro
48%endif
49
50;; @def MYPUSHSEGS
51; Macro saving all segment registers on the stack.
52; @param 1 full width register name
53
54;; @def MYPOPSEGS
55; Macro restoring all segment registers on the stack
56; @param 1 full width register name
57
58 ; Load the corresponding guest MSR (trashes rdx & rcx)
59 %macro LOADGUESTMSR 2
60 mov rcx, %1
61 mov edx, dword [rsi + %2 + 4]
62 mov eax, dword [rsi + %2]
63 wrmsr
64 %endmacro
65
66 ; Save a guest MSR (trashes rdx & rcx)
67 ; Only really useful for gs kernel base as that one can be changed behind our back (swapgs)
68 %macro SAVEGUESTMSR 2
69 mov rcx, %1
70 rdmsr
71 mov dword [rsi + %2], eax
72 mov dword [rsi + %2 + 4], edx
73 %endmacro
74
75 %macro MYPUSHSEGS 1
76 mov %1, es
77 push %1
78 mov %1, ds
79 push %1
80 %endmacro
81
82 %macro MYPOPSEGS 1
83 pop %1
84 mov ds, %1
85 pop %1
86 mov es, %1
87 %endmacro
88
89BEGINCODE
90BITS 64
91
92
93;/**
94; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
95; *
96; * @returns VBox status code
97; * @param pPageCpuPhys VMXON physical address [rsp+8]
98; * @param pVMCSPhys VMCS physical address [rsp+16]
99; * @param pCache VMCS cache [rsp+24]
100; * @param pCtx Guest context (rsi)
101; */
102BEGINPROC VMXGCStartVM64
103 push rbp
104 mov rbp, rsp
105
106 ; Make sure VT-x instructions are allowed
107 mov rax, cr4
108 or rax, X86_CR4_VMXE
109 mov cr4, rax
110
111 ;/* Enter VMX Root Mode */
112 vmxon [rbp + 8 + 8]
113 jnc .vmxon_success
114 mov rax, VERR_VMX_INVALID_VMXON_PTR
115 jmp .vmstart64_vmxon_failed
116
117.vmxon_success:
118 jnz .vmxon_success2
119 mov rax, VERR_VMX_GENERIC
120 jmp .vmstart64_vmxon_failed
121
122.vmxon_success2:
123 ; Activate the VMCS pointer
124 vmptrld [rbp + 16 + 8]
125 jnc .vmptrld_success
126 mov rax, VERR_VMX_INVALID_VMCS_PTR
127 jmp .vmstart64_vmxoff_end
128
129.vmptrld_success:
130 jnz .vmptrld_success2
131 mov rax, VERR_VMX_GENERIC
132 jmp .vmstart64_vmxoff_end
133
134.vmptrld_success2:
135
136 ; Save the VMCS pointer on the stack
137 push qword [rbp + 16 + 8];
138
139 ;/* Save segment registers */
140 MYPUSHSEGS rax
141
142%ifdef VMX_USE_CACHED_VMCS_ACCESSES
143 ; Flush the VMCS write cache first (before any other vmreads/vmwrites!)
144 mov rbx, [rbp + 24 + 8] ; pCache
145
146%ifdef VBOX_WITH_CRASHDUMP_MAGIC
147 mov qword [rbx + VMCSCACHE.uPos], 2
148%endif
149
150%ifdef DEBUG
151 mov rax, [rbp + 8 + 8] ; pPageCpuPhys
152 mov [rbx + VMCSCACHE.TestIn.pPageCpuPhys], rax
153 mov rax, [rbp + 16 + 8] ; pVMCSPhys
154 mov [rbx + VMCSCACHE.TestIn.pVMCSPhys], rax
155 mov [rbx + VMCSCACHE.TestIn.pCache], rbx
156 mov [rbx + VMCSCACHE.TestIn.pCtx], rsi
157%endif
158
159 mov ecx, [rbx + VMCSCACHE.Write.cValidEntries]
160 cmp ecx, 0
161 je .no_cached_writes
162 mov rdx, rcx
163 mov rcx, 0
164 jmp .cached_write
165
166ALIGN(16)
167.cached_write:
168 mov eax, [rbx + VMCSCACHE.Write.aField + rcx*4]
169 vmwrite rax, qword [rbx + VMCSCACHE.Write.aFieldVal + rcx*8]
170 inc rcx
171 cmp rcx, rdx
172 jl .cached_write
173
174 mov dword [rbx + VMCSCACHE.Write.cValidEntries], 0
175.no_cached_writes:
176
177%ifdef VBOX_WITH_CRASHDUMP_MAGIC
178 mov qword [rbx + VMCSCACHE.uPos], 3
179%endif
180 ; Save the pCache pointer
181 push xBX
182%endif
183
184 ; Save the host state that's relevant in the temporary 64 bits mode
185 mov rdx, cr0
186 mov eax, VMX_VMCS_HOST_CR0
187 vmwrite rax, rdx
188
189 mov rdx, cr3
190 mov eax, VMX_VMCS_HOST_CR3
191 vmwrite rax, rdx
192
193 mov rdx, cr4
194 mov eax, VMX_VMCS_HOST_CR4
195 vmwrite rax, rdx
196
197 mov rdx, cs
198 mov eax, VMX_VMCS_HOST_FIELD_CS
199 vmwrite rax, rdx
200
201 mov rdx, ss
202 mov eax, VMX_VMCS_HOST_FIELD_SS
203 vmwrite rax, rdx
204
205 sub rsp, 8*2
206 sgdt [rsp]
207 mov eax, VMX_VMCS_HOST_GDTR_BASE
208 vmwrite rax, [rsp+2]
209 add rsp, 8*2
210
211%ifdef VBOX_WITH_CRASHDUMP_MAGIC
212 mov qword [rbx + VMCSCACHE.uPos], 4
213%endif
214
215 ; hopefully we can ignore TR (we restore it anyway on the way back to 32 bits mode)
216
217 ;/* First we have to save some final CPU context registers. */
218 lea rdx, [.vmlaunch64_done wrt rip]
219 mov rax, VMX_VMCS_HOST_RIP ;/* return address (too difficult to continue after VMLAUNCH?) */
220 vmwrite rax, rdx
221 ;/* Note: assumes success... */
222
223 ;/* Manual save and restore:
224 ; * - General purpose registers except RIP, RSP
225 ; *
226 ; * Trashed:
227 ; * - CR2 (we don't care)
228 ; * - LDTR (reset to 0)
229 ; * - DRx (presumably not changed at all)
230 ; * - DR7 (reset to 0x400)
231 ; * - EFLAGS (reset to RT_BIT(1); not relevant)
232 ; *
233 ; */
234
235 ; Load the guest LSTAR, CSTAR, SFMASK & KERNEL_GSBASE MSRs
236 ;; @todo use the automatic load feature for MSRs
237 LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
238%if 0 ; not supported on Intel CPUs
239 LOADGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
240%endif
241 LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
242 LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
243 LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
244
245%ifdef VBOX_WITH_CRASHDUMP_MAGIC
246 mov qword [rbx + VMCSCACHE.uPos], 5
247%endif
248
249 ; Save the pCtx pointer
250 push rsi
251
252 ; Restore CR2
253 mov rbx, qword [rsi + CPUMCTX.cr2]
254 mov cr2, rbx
255
256 mov eax, VMX_VMCS_HOST_RSP
257 vmwrite rax, rsp
258 ;/* Note: assumes success... */
259 ;/* Don't mess with ESP anymore!! */
260
261 ;/* Restore Guest's general purpose registers. */
262 mov rax, qword [rsi + CPUMCTX.eax]
263 mov rbx, qword [rsi + CPUMCTX.ebx]
264 mov rcx, qword [rsi + CPUMCTX.ecx]
265 mov rdx, qword [rsi + CPUMCTX.edx]
266 mov rbp, qword [rsi + CPUMCTX.ebp]
267 mov r8, qword [rsi + CPUMCTX.r8]
268 mov r9, qword [rsi + CPUMCTX.r9]
269 mov r10, qword [rsi + CPUMCTX.r10]
270 mov r11, qword [rsi + CPUMCTX.r11]
271 mov r12, qword [rsi + CPUMCTX.r12]
272 mov r13, qword [rsi + CPUMCTX.r13]
273 mov r14, qword [rsi + CPUMCTX.r14]
274 mov r15, qword [rsi + CPUMCTX.r15]
275
276 ;/* Restore rdi & rsi. */
277 mov rdi, qword [rsi + CPUMCTX.edi]
278 mov rsi, qword [rsi + CPUMCTX.esi]
279
280 vmlaunch
281 jmp .vmlaunch64_done; ;/* here if vmlaunch detected a failure. */
282
283ALIGNCODE(16)
284.vmlaunch64_done:
285 jc near .vmstart64_invalid_vmxon_ptr
286 jz near .vmstart64_start_failed
287
288 push rdi
289 mov rdi, [rsp + 8] ; pCtx
290
291 mov qword [rdi + CPUMCTX.eax], rax
292 mov qword [rdi + CPUMCTX.ebx], rbx
293 mov qword [rdi + CPUMCTX.ecx], rcx
294 mov qword [rdi + CPUMCTX.edx], rdx
295 mov qword [rdi + CPUMCTX.esi], rsi
296 mov qword [rdi + CPUMCTX.ebp], rbp
297 mov qword [rdi + CPUMCTX.r8], r8
298 mov qword [rdi + CPUMCTX.r9], r9
299 mov qword [rdi + CPUMCTX.r10], r10
300 mov qword [rdi + CPUMCTX.r11], r11
301 mov qword [rdi + CPUMCTX.r12], r12
302 mov qword [rdi + CPUMCTX.r13], r13
303 mov qword [rdi + CPUMCTX.r14], r14
304 mov qword [rdi + CPUMCTX.r15], r15
305
306 pop rax ; the guest edi we pushed above
307 mov qword [rdi + CPUMCTX.edi], rax
308
309 pop rsi ; pCtx (needed in rsi by the macros below)
310
311 ;; @todo use the automatic load feature for MSRs
312 SAVEGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
313%if 0 ; not supported on Intel CPUs
314 SAVEGUESTMSR MSR_K8_CSTAR, CPUMCTX.msrCSTAR
315%endif
316 SAVEGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
317 SAVEGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
318 SAVEGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
319
320%ifdef VMX_USE_CACHED_VMCS_ACCESSES
321 pop rdi ; saved pCache
322
323%ifdef VBOX_WITH_CRASHDUMP_MAGIC
324 mov dword [rdi + VMCSCACHE.uPos], 7
325%endif
326%ifdef DEBUG
327 mov [rdi + VMCSCACHE.TestOut.pCache], rdi
328 mov [rdi + VMCSCACHE.TestOut.pCtx], rsi
329 mov rax, cr8
330 mov [rdi + VMCSCACHE.TestOut.cr8], rax
331%endif
332
333 mov ecx, [rdi + VMCSCACHE.Read.cValidEntries]
334 cmp ecx, 0 ; can't happen
335 je .no_cached_reads
336 jmp .cached_read
337
338ALIGN(16)
339.cached_read:
340 dec rcx
341 mov eax, [rdi + VMCSCACHE.Read.aField + rcx*4]
342 vmread qword [rdi + VMCSCACHE.Read.aFieldVal + rcx*8], rax
343 cmp rcx, 0
344 jnz .cached_read
345.no_cached_reads:
346
347 ; Save CR2 for EPT
348 mov rax, cr2
349 mov [rdi + VMCSCACHE.cr2], rax
350%ifdef VBOX_WITH_CRASHDUMP_MAGIC
351 mov dword [rdi + VMCSCACHE.uPos], 8
352%endif
353%endif
354
355 ; Restore segment registers
356 MYPOPSEGS rax
357
358 mov eax, VINF_SUCCESS
359
360%ifdef VBOX_WITH_CRASHDUMP_MAGIC
361 mov dword [rdi + VMCSCACHE.uPos], 9
362%endif
363.vmstart64_end:
364
365%ifdef VMX_USE_CACHED_VMCS_ACCESSES
366%ifdef DEBUG
367 mov rdx, [rsp] ; pVMCSPhys
368 mov [rdi + VMCSCACHE.TestOut.pVMCSPhys], rdx
369%endif
370%endif
371
372 ; Write back the data and disable the VMCS
373 vmclear qword [rsp] ;Pushed pVMCS
374 add rsp, 8
375
376.vmstart64_vmxoff_end:
377 ; Disable VMX root mode
378 vmxoff
379.vmstart64_vmxon_failed:
380%ifdef VMX_USE_CACHED_VMCS_ACCESSES
381%ifdef DEBUG
382 cmp eax, VINF_SUCCESS
383 jne .skip_flags_save
384
385 pushf
386 pop rdx
387 mov [rdi + VMCSCACHE.TestOut.eflags], rdx
388%ifdef VBOX_WITH_CRASHDUMP_MAGIC
389 mov dword [rdi + VMCSCACHE.uPos], 12
390%endif
391.skip_flags_save:
392%endif
393%endif
394 pop rbp
395 ret
396
397
398.vmstart64_invalid_vmxon_ptr:
399 pop rsi ; pCtx (needed in rsi by the macros below)
400
401%ifdef VMX_USE_CACHED_VMCS_ACCESSES
402 pop rdi ; pCache
403%ifdef VBOX_WITH_CRASHDUMP_MAGIC
404 mov dword [rdi + VMCSCACHE.uPos], 10
405%endif
406
407%ifdef DEBUG
408 mov [rdi + VMCSCACHE.TestOut.pCache], rdi
409 mov [rdi + VMCSCACHE.TestOut.pCtx], rsi
410%endif
411
412%endif
413
414 ; Restore segment registers
415 MYPOPSEGS rax
416
417 ; Restore all general purpose host registers.
418 mov eax, VERR_VMX_INVALID_VMXON_PTR
419 jmp .vmstart64_end
420
421.vmstart64_start_failed:
422 pop rsi ; pCtx (needed in rsi by the macros below)
423
424%ifdef VMX_USE_CACHED_VMCS_ACCESSES
425 pop rdi ; pCache
426
427%ifdef DEBUG
428 mov [rdi + VMCSCACHE.TestOut.pCache], rdi
429 mov [rdi + VMCSCACHE.TestOut.pCtx], rsi
430%endif
431%ifdef VBOX_WITH_CRASHDUMP_MAGIC
432 mov dword [rdi + VMCSCACHE.uPos], 11
433%endif
434
435%endif
436
437 ; Restore segment registers
438 MYPOPSEGS rax
439
440 ; Restore all general purpose host registers.
441 mov eax, VERR_VMX_UNABLE_TO_START_VM
442 jmp .vmstart64_end
443ENDPROC VMXGCStartVM64
444
445
446;/**
447; * Prepares for and executes VMRUN (64 bits guests)
448; *
449; * @returns VBox status code
450; * @param HCPhysVMCB Physical address of host VMCB (rsp+8)
451; * @param HCPhysVMCB Physical address of guest VMCB (rsp+16)
452; * @param pCtx Guest context (rsi)
453; */
454BEGINPROC SVMGCVMRun64
455 push rbp
456 mov rbp, rsp
457 pushf
458
459 ;/* Manual save and restore:
460 ; * - General purpose registers except RIP, RSP, RAX
461 ; *
462 ; * Trashed:
463 ; * - CR2 (we don't care)
464 ; * - LDTR (reset to 0)
465 ; * - DRx (presumably not changed at all)
466 ; * - DR7 (reset to 0x400)
467 ; */
468
469 ;/* Save the Guest CPU context pointer. */
470 push rsi ; push for saving the state at the end
471
472 ; save host fs, gs, sysenter msr etc
473 mov rax, [rbp + 8 + 8] ; pVMCBHostPhys (64 bits physical address)
474 push rax ; save for the vmload after vmrun
475 vmsave
476
477 ; setup eax for VMLOAD
478 mov rax, [rbp + 8 + 8 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address)
479
480 ;/* Restore Guest's general purpose registers. */
481 ;/* RAX is loaded from the VMCB by VMRUN */
482 mov rbx, qword [rsi + CPUMCTX.ebx]
483 mov rcx, qword [rsi + CPUMCTX.ecx]
484 mov rdx, qword [rsi + CPUMCTX.edx]
485 mov rdi, qword [rsi + CPUMCTX.edi]
486 mov rbp, qword [rsi + CPUMCTX.ebp]
487 mov r8, qword [rsi + CPUMCTX.r8]
488 mov r9, qword [rsi + CPUMCTX.r9]
489 mov r10, qword [rsi + CPUMCTX.r10]
490 mov r11, qword [rsi + CPUMCTX.r11]
491 mov r12, qword [rsi + CPUMCTX.r12]
492 mov r13, qword [rsi + CPUMCTX.r13]
493 mov r14, qword [rsi + CPUMCTX.r14]
494 mov r15, qword [rsi + CPUMCTX.r15]
495 mov rsi, qword [rsi + CPUMCTX.esi]
496
497 ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch
498 clgi
499 sti
500
501 ; load guest fs, gs, sysenter msr etc
502 vmload
503 ; run the VM
504 vmrun
505
506 ;/* RAX is in the VMCB already; we can use it here. */
507
508 ; save guest fs, gs, sysenter msr etc
509 vmsave
510
511 ; load host fs, gs, sysenter msr etc
512 pop rax ; pushed above
513 vmload
514
515 ; Set the global interrupt flag again, but execute cli to make sure IF=0.
516 cli
517 stgi
518
519 pop rax ; pCtx
520
521 mov qword [rax + CPUMCTX.ebx], rbx
522 mov qword [rax + CPUMCTX.ecx], rcx
523 mov qword [rax + CPUMCTX.edx], rdx
524 mov qword [rax + CPUMCTX.esi], rsi
525 mov qword [rax + CPUMCTX.edi], rdi
526 mov qword [rax + CPUMCTX.ebp], rbp
527 mov qword [rax + CPUMCTX.r8], r8
528 mov qword [rax + CPUMCTX.r9], r9
529 mov qword [rax + CPUMCTX.r10], r10
530 mov qword [rax + CPUMCTX.r11], r11
531 mov qword [rax + CPUMCTX.r12], r12
532 mov qword [rax + CPUMCTX.r13], r13
533 mov qword [rax + CPUMCTX.r14], r14
534 mov qword [rax + CPUMCTX.r15], r15
535
536 mov eax, VINF_SUCCESS
537
538 popf
539 pop rbp
540 ret
541ENDPROC SVMGCVMRun64
542
543;/**
544; * Saves the guest FPU context
545; *
546; * @returns VBox status code
547; * @param pCtx Guest context [rsi]
548; */
549BEGINPROC HWACCMSaveGuestFPU64
550 mov rax, cr0
551 mov rcx, rax ; save old CR0
552 and rax, ~(X86_CR0_TS | X86_CR0_EM)
553 mov cr0, rax
554
555 fxsave [rsi + CPUMCTX.fpu]
556
557 mov cr0, rcx ; and restore old CR0 again
558
559 mov eax, VINF_SUCCESS
560 ret
561ENDPROC HWACCMSaveGuestFPU64
562
563;/**
564; * Saves the guest debug context (DR0-3, DR6)
565; *
566; * @returns VBox status code
567; * @param pCtx Guest context [rsi]
568; */
569BEGINPROC HWACCMSaveGuestDebug64
570 mov rax, dr0
571 mov qword [rsi + CPUMCTX.dr + 0*8], rax
572 mov rax, dr1
573 mov qword [rsi + CPUMCTX.dr + 1*8], rax
574 mov rax, dr2
575 mov qword [rsi + CPUMCTX.dr + 2*8], rax
576 mov rax, dr3
577 mov qword [rsi + CPUMCTX.dr + 3*8], rax
578 mov rax, dr6
579 mov qword [rsi + CPUMCTX.dr + 6*8], rax
580 mov eax, VINF_SUCCESS
581 ret
582ENDPROC HWACCMSaveGuestDebug64
583
584;/**
585; * Dummy callback handler
586; *
587; * @returns VBox status code
588; * @param param1 Parameter 1 [rsp+8]
589; * @param param2 Parameter 2 [rsp+12]
590; * @param param3 Parameter 3 [rsp+16]
591; * @param param4 Parameter 4 [rsp+20]
592; * @param param5 Parameter 5 [rsp+24]
593; * @param pCtx Guest context [rsi]
594; */
595BEGINPROC HWACCMTestSwitcher64
596 mov eax, [rsp+8]
597 ret
598ENDPROC HWACCMTestSwitcher64
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette