CPUMGCA.asm@ 2988

Last change on this file since 2988 was 2988, checked in by vboxsync, 17 years ago
InnoTek -> innotek part 4: more miscellaneous files.
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1	; $Id: CPUMGCA.asm 2988 2007-06-01 17:36:09Z vboxsync $
2	;; @file
3	;
4	; CPUM - Guest Context Assembly Routines.
5
6	; Copyright (C) 2006-2007 innotek GmbH
7	;
8	; This file is part of VirtualBox Open Source Edition (OSE), as
9	; available from http://www.virtualbox.org. This file is free software;
10	; you can redistribute it and/or modify it under the terms of the GNU
11	; General Public License as published by the Free Software Foundation,
12	; in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13	; distribution. VirtualBox OSE is distributed in the hope that it will
14	; be useful, but WITHOUT ANY WARRANTY of any kind.
15	;
16	; If you received this file as part of a commercial VirtualBox
17	; distribution, then only the terms of your commercial VirtualBox
18	; license agreement apply instead of the previous paragraph.
19
20	;*******************************************************************************
21	;* Header Files *
22	;*******************************************************************************
23	%include "VMMGC.mac"
24	%include "VBox/vm.mac"
25	%include "VBox/err.mac"
26	%include "VBox/stam.mac"
27	%include "CPUMInternal.mac"
28	%include "VBox/x86.mac"
29	%include "VBox/cpum.mac"
30
31
32	;*******************************************************************************
33	;* External Symbols *
34	;*******************************************************************************
35	extern IMPNAME(g_CPUM) ; VMM GC Builtin import
36	extern IMPNAME(g_VM) ; VMM GC Builtin import
37	extern NAME(cpumGCHandleNPAndGP) ; CPUMGC.cpp
38
39	;
40	; Enables write protection of Hypervisor memory pages.
41	; !note! Must be commented out for Trap8 debug handler.
42	;
43	%define ENABLE_WRITE_PROTECTION 1
44
45	BEGINCODE
46
47
48	;;
49	; Restores GC context before doing iret.
50	;
51	; @param [esp + 4] Pointer to interrupt stack frame, i.e. pointer
52	; to the a struct with this layout:
53	; 00h eip
54	; 04h cs
55	; 08h eflags
56	; 0ch esp
57	; 10h ss
58	; 14h es (V86 only)
59	; 18h ds (V86 only)
60	; 1Ch fs (V86 only)
61	; 20h gs (V86 only)
62	;
63	; @uses everything but cs, ss, esp, and eflags.
64	;
65	; @remark Assumes we're restoring in Ring-0 a context which is not Ring-0.
66	; Further assumes flat stack and valid ds.
67
68	BEGINPROC CPUMGCRestoreInt
69	;
70	; Update iret frame.
71	;
72	mov eax, [esp + 4] ; get argument
73	mov edx, IMP(g_CPUM)
74
75	mov ecx, [edx + CPUM.Guest.eip]
76	mov [eax + 0h], ecx
77	mov ecx, [edx + CPUM.Guest.cs]
78	mov [eax + 4h], ecx
79	mov ecx, [edx + CPUM.Guest.eflags]
80	mov [eax + 8h], ecx
81	mov ecx, [edx + CPUM.Guest.esp]
82	mov [eax + 0ch], ecx
83	mov ecx, [edx + CPUM.Guest.ss]
84	mov [eax + 10h], ecx
85
86	test dword [edx + CPUM.Guest.eflags], X86_EFL_VM
87	jnz short CPUMGCRestoreInt_V86
88
89	;
90	; Load registers.
91	;
92	; todo: potential trouble loading invalid es,fs,gs,ds because
93	; of a VMM imposed exception?
94	mov es, [edx + CPUM.Guest.es]
95	mov fs, [edx + CPUM.Guest.fs]
96	mov gs, [edx + CPUM.Guest.gs]
97	mov esi, [edx + CPUM.Guest.esi]
98	mov edi, [edx + CPUM.Guest.edi]
99	mov ebp, [edx + CPUM.Guest.ebp]
100	mov ebx, [edx + CPUM.Guest.ebx]
101	mov ecx, [edx + CPUM.Guest.ecx]
102	mov eax, [edx + CPUM.Guest.eax]
103	push dword [edx + CPUM.Guest.ds]
104	mov edx, [edx + CPUM.Guest.edx]
105	pop ds
106
107	ret
108
109	CPUMGCRestoreInt_V86:
110	; iret restores ds, es, fs & gs
111	mov ecx, [edx + CPUM.Guest.es]
112	mov [eax + 14h], ecx
113	mov ecx, [edx + CPUM.Guest.ds]
114	mov [eax + 18h], ecx
115	mov ecx, [edx + CPUM.Guest.fs]
116	mov [eax + 1Ch], ecx
117	mov ecx, [edx + CPUM.Guest.gs]
118	mov [eax + 20h], ecx
119	mov esi, [edx + CPUM.Guest.esi]
120	mov edi, [edx + CPUM.Guest.edi]
121	mov ebp, [edx + CPUM.Guest.ebp]
122	mov ebx, [edx + CPUM.Guest.ebx]
123	mov ecx, [edx + CPUM.Guest.ecx]
124	mov eax, [edx + CPUM.Guest.eax]
125	mov edx, [edx + CPUM.Guest.edx]
126	ret
127
128	ENDPROC CPUMGCRestoreInt
129
130
131	;;
132	; Calls a guest trap/interrupt handler directly
133	; Assumes a trap stack frame has already been setup on the guest's stack!
134	;
135	; @param pRegFrame [esp + 4] Original trap/interrupt context
136	; @param selCS [esp + 8] Code selector of handler
137	; @param pHandler [esp + 12] GC virtual address of handler
138	; @param eflags [esp + 16] Callee's EFLAGS
139	; @param selSS [esp + 20] Stack selector for handler
140	; @param pEsp [esp + 24] Stack address for handler
141	;
142	; @remark This call never returns!
143	;
144	; CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
145	align 16
146	BEGINPROC_EXPORTED CPUMGCCallGuestTrapHandler
147	mov ebp, esp
148
149	; construct iret stack frame
150	push dword [ebp + 20] ; SS
151	push dword [ebp + 24] ; ESP
152	push dword [ebp + 16] ; EFLAGS
153	push dword [ebp + 8] ; CS
154	push dword [ebp + 12] ; EIP
155
156	;
157	; enable WP
158	;
159	%ifdef ENABLE_WRITE_PROTECTION
160	mov eax, cr0
161	or eax, X86_CR0_WRITE_PROTECT
162	mov cr0, eax
163	%endif
164
165	; restore CPU context (all except cs, eip, ss, esp & eflags; which are restored or overwritten by iret)
166	mov ebp, [ebp + 4] ; pRegFrame
167	mov ebx, [ebp + CPUMCTXCORE.ebx]
168	mov ecx, [ebp + CPUMCTXCORE.ecx]
169	mov edx, [ebp + CPUMCTXCORE.edx]
170	mov esi, [ebp + CPUMCTXCORE.esi]
171	mov edi, [ebp + CPUMCTXCORE.edi]
172
173	;; @todo load segment registers before enabling WP.
174	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS \| CPUM_HANDLER_CTXCORE_IN_EBP
175	mov gs, [ebp + CPUMCTXCORE.gs]
176	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS \| CPUM_HANDLER_CTXCORE_IN_EBP
177	mov fs, [ebp + CPUMCTXCORE.fs]
178	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES \| CPUM_HANDLER_CTXCORE_IN_EBP
179	mov es, [ebp + CPUMCTXCORE.es]
180	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS \| CPUM_HANDLER_CTXCORE_IN_EBP
181	mov ds, [ebp + CPUMCTXCORE.ds]
182
183	mov eax, [ebp + CPUMCTXCORE.eax]
184	mov ebp, [ebp + CPUMCTXCORE.ebp]
185
186	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
187	iret
188
189	ENDPROC CPUMGCCallGuestTrapHandler
190
191	;;
192	; Performs an iret to V86 code
193	; Assumes a trap stack frame has already been setup on the guest's stack!
194	;
195	; @param pRegFrame Original trap/interrupt context
196	;
197	; This function does not return!
198	;
199	;CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
200	align 16
201	BEGINPROC CPUMGCCallV86Code
202	mov ebp, [esp + 4] ; pRegFrame
203
204	; construct iret stack frame
205	push dword [ebp + CPUMCTXCORE.gs]
206	push dword [ebp + CPUMCTXCORE.fs]
207	push dword [ebp + CPUMCTXCORE.ds]
208	push dword [ebp + CPUMCTXCORE.es]
209	push dword [ebp + CPUMCTXCORE.ss]
210	push dword [ebp + CPUMCTXCORE.esp]
211	push dword [ebp + CPUMCTXCORE.eflags]
212	push dword [ebp + CPUMCTXCORE.cs]
213	push dword [ebp + CPUMCTXCORE.eip]
214
215	;
216	; enable WP
217	;
218	%ifdef ENABLE_WRITE_PROTECTION
219	mov eax, cr0
220	or eax, X86_CR0_WRITE_PROTECT
221	mov cr0, eax
222	%endif
223
224	; restore CPU context (all except cs, eip, ss, esp, eflags, ds, es, fs & gs; which are restored or overwritten by iret)
225	mov eax, [ebp + CPUMCTXCORE.eax]
226	mov ebx, [ebp + CPUMCTXCORE.ebx]
227	mov ecx, [ebp + CPUMCTXCORE.ecx]
228	mov edx, [ebp + CPUMCTXCORE.edx]
229	mov esi, [ebp + CPUMCTXCORE.esi]
230	mov edi, [ebp + CPUMCTXCORE.edi]
231	mov ebp, [ebp + CPUMCTXCORE.ebp]
232
233	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
234	iret
235	ENDPROC CPUMGCCallV86Code
236
237	;;
238	; This is a main entry point for resuming (or starting) guest
239	; code execution.
240	;
241	; We get here directly from VMMSwitcher.asm (jmp at the end
242	; of VMMSwitcher_HostToGuest).
243	;
244	; This call never returns!
245	;
246	; @param edx Pointer to CPUM structure.
247	;
248	align 16
249	BEGINPROC_EXPORTED CPUMGCResumeGuest
250	;
251	; Setup iretd
252	;
253	push dword [edx + CPUM.Guest.ss]
254	push dword [edx + CPUM.Guest.esp]
255	push dword [edx + CPUM.Guest.eflags]
256	push dword [edx + CPUM.Guest.cs]
257	push dword [edx + CPUM.Guest.eip]
258
259	;
260	; Restore registers.
261	;
262	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_ES
263	mov es, [edx + CPUM.Guest.es]
264	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_FS
265	mov fs, [edx + CPUM.Guest.fs]
266	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_GS
267	mov gs, [edx + CPUM.Guest.gs]
268
269	%ifdef VBOX_WITH_STATISTICS
270	;
271	; Statistics.
272	;
273	push edx
274	mov edx, IMP(g_VM)
275	lea edx, [edx + VM.StatTotalQemuToGC]
276	STAM_PROFILE_ADV_STOP edx
277
278	mov edx, IMP(g_VM)
279	lea edx, [edx + VM.StatTotalInGC]
280	STAM_PROFILE_ADV_START edx
281	pop edx
282	%endif
283
284	;
285	; enable WP
286	;
287	%ifdef ENABLE_WRITE_PROTECTION
288	mov eax, cr0
289	or eax, X86_CR0_WRITE_PROTECT
290	mov cr0, eax
291	%endif
292
293	;
294	; Continue restore.
295	;
296	mov esi, [edx + CPUM.Guest.esi]
297	mov edi, [edx + CPUM.Guest.edi]
298	mov ebp, [edx + CPUM.Guest.ebp]
299	mov ebx, [edx + CPUM.Guest.ebx]
300	mov ecx, [edx + CPUM.Guest.ecx]
301	mov eax, [edx + CPUM.Guest.eax]
302	push dword [edx + CPUM.Guest.ds]
303	mov edx, [edx + CPUM.Guest.edx]
304	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_DS
305	pop ds
306
307	; restart execution.
308	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
309	iretd
310	ENDPROC CPUMGCResumeGuest
311
312
313	;;
314	; This is a main entry point for resuming (or starting) guest
315	; code execution for raw V86 mode
316	;
317	; We get here directly from VMMSwitcher.asm (jmp at the end
318	; of VMMSwitcher_HostToGuest).
319	;
320	; This call never returns!
321	;
322	; @param edx Pointer to CPUM structure.
323	;
324	align 16
325	BEGINPROC_EXPORTED CPUMGCResumeGuestV86
326	;
327	; Setup iretd
328	;
329	push dword [edx + CPUM.Guest.gs]
330	push dword [edx + CPUM.Guest.fs]
331	push dword [edx + CPUM.Guest.ds]
332	push dword [edx + CPUM.Guest.es]
333
334	push dword [edx + CPUM.Guest.ss]
335	push dword [edx + CPUM.Guest.esp]
336
337	push dword [edx + CPUM.Guest.eflags]
338	push dword [edx + CPUM.Guest.cs]
339	push dword [edx + CPUM.Guest.eip]
340
341	;
342	; Restore registers.
343	;
344
345	%ifdef VBOX_WITH_STATISTICS
346	;
347	; Statistics.
348	;
349	push edx
350	mov edx, IMP(g_VM)
351	lea edx, [edx + VM.StatTotalQemuToGC]
352	STAM_PROFILE_ADV_STOP edx
353
354	mov edx, IMP(g_VM)
355	lea edx, [edx + VM.StatTotalInGC]
356	STAM_PROFILE_ADV_START edx
357	pop edx
358	%endif
359
360	;
361	; enable WP
362	;
363	%ifdef ENABLE_WRITE_PROTECTION
364	mov eax, cr0
365	or eax, X86_CR0_WRITE_PROTECT
366	mov cr0, eax
367	%endif
368
369	;
370	; Continue restore.
371	;
372	mov esi, [edx + CPUM.Guest.esi]
373	mov edi, [edx + CPUM.Guest.edi]
374	mov ebp, [edx + CPUM.Guest.ebp]
375	mov ecx, [edx + CPUM.Guest.ecx]
376	mov ebx, [edx + CPUM.Guest.ebx]
377	mov eax, [edx + CPUM.Guest.eax]
378	mov edx, [edx + CPUM.Guest.edx]
379
380	; restart execution.
381	TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
382	iretd
383	ENDPROC CPUMGCResumeGuestV86
384
385
386	;;
387	; Set the Guest CPU CR2 register.
388	;
389	; @param eax cr2
390	; @uses edx
391	;
392	align 16
393	BEGINPROC CPUMGCSetGuestCR2Asm
394	mov edx, IMP(g_CPUM)
395	mov [edx + CPUM.Guest.cr2], eax
396	ret
397	ENDPROC CPUMGCSetGuestCR2Asm
398
399
400	;;
401	; Get the Guest CPU CR0 register.
402	;
403	; @returns cr0 in eax
404	; @uses eax
405	;
406	align 16
407	BEGINPROC CPUMGCGetGuestCR0
408	mov eax, IMP(g_CPUM)
409	mov eax, [eax + CPUM.Guest.cr0]
410	ret
411	ENDPROC CPUMGCGetGuestCR0
412
413
414

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source: vbox/trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm@ 2988

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