TRPMAll.cpp@ 42202

Last change on this file since 42202 was 42186, checked in by vboxsync, 12 years ago
SELM,DIS,CPUM,EM: Hidden selector register cleanups.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 32.6 KB

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1	/* $Id: TRPMAll.cpp 42186 2012-07-17 13:32:15Z vboxsync $ */
2	/** @file
3	* TRPM - Trap Monitor - Any Context.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_TRPM
23	#include <VBox/vmm/trpm.h>
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/patm.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/stam.h>
29	#include "TRPMInternal.h"
30	#include <VBox/vmm/vm.h>
31	#include <VBox/err.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include <iprt/asm-amd64-x86.h>
37	#include <iprt/param.h>
38	#include <iprt/x86.h>
39	#include "internal/pgm.h"
40
41
42
43	/**
44	* Query info about the current active trap/interrupt.
45	* If no trap is active active an error code is returned.
46	*
47	* @returns VBox status code.
48	* @param pVCpu Pointer to the VMCPU.
49	* @param pu8TrapNo Where to store the trap number.
50	* @param pEnmType Where to store the trap type
51	*/
52	VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t pu8TrapNo, TRPMEVENT pEnmType)
53	{
54	/*
55	* Check if we have a trap at present.
56	*/
57	if (pVCpu->trpm.s.uActiveVector != ~0U)
58	{
59	if (pu8TrapNo)
60	*pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
61	if (pEnmType)
62	*pEnmType = pVCpu->trpm.s.enmActiveType;
63	return VINF_SUCCESS;
64	}
65
66	return VERR_TRPM_NO_ACTIVE_TRAP;
67	}
68
69
70	/**
71	* Gets the trap number for the current trap.
72	*
73	* The caller is responsible for making sure there is an active trap which
74	* takes an error code when making this request.
75	*
76	* @returns The current trap number.
77	* @param pVCpu Pointer to the VMCPU.
78	*/
79	VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu)
80	{
81	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
82	return (uint8_t)pVCpu->trpm.s.uActiveVector;
83	}
84
85
86	/**
87	* Gets the error code for the current trap.
88	*
89	* The caller is responsible for making sure there is an active trap which
90	* takes an error code when making this request.
91	*
92	* @returns Error code.
93	* @param pVCpu Pointer to the VMCPU.
94	*/
95	VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu)
96	{
97	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
98	#ifdef VBOX_STRICT
99	switch (pVCpu->trpm.s.uActiveVector)
100	{
101	case 0x0a:
102	case 0x0b:
103	case 0x0c:
104	case 0x0d:
105	case 0x0e:
106	case 0x11:
107	case 0x08:
108	break;
109	default:
110	AssertMsgFailed(("This trap (%#x) doesn't have any error code\n", pVCpu->trpm.s.uActiveVector));
111	break;
112	}
113	#endif
114	return pVCpu->trpm.s.uActiveErrorCode;
115	}
116
117
118	/**
119	* Gets the fault address for the current trap.
120	*
121	* The caller is responsible for making sure there is an active trap 0x0e when
122	* making this request.
123	*
124	* @returns Fault address associated with the trap.
125	* @param pVCpu Pointer to the VMCPU.
126	*/
127	VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu)
128	{
129	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
130	AssertMsg(pVCpu->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n"));
131	return pVCpu->trpm.s.uActiveCR2;
132	}
133
134
135	/**
136	* Clears the current active trap/exception/interrupt.
137	*
138	* The caller is responsible for making sure there is an active trap
139	* when making this request.
140	*
141	* @returns VBox status code.
142	* @param pVCpu Pointer to the VMCPU.
143	*/
144	VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu)
145	{
146	/*
147	* Cannot reset non-existing trap!
148	*/
149	if (pVCpu->trpm.s.uActiveVector == ~0U)
150	{
151	AssertMsgFailed(("No active trap!\n"));
152	return VERR_TRPM_NO_ACTIVE_TRAP;
153	}
154
155	/*
156	* Reset it.
157	*/
158	pVCpu->trpm.s.uActiveVector = ~0U;
159	return VINF_SUCCESS;
160	}
161
162
163	/**
164	* Assert trap/exception/interrupt.
165	*
166	* The caller is responsible for making sure there is no active trap
167	* when making this request.
168	*
169	* @returns VBox status code.
170	* @param pVCpu Pointer to the VMCPU.
171	* @param u8TrapNo The trap vector to assert.
172	* @param enmType Trap type.
173	*/
174	VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType)
175	{
176	Log2(("TRPMAssertTrap: u8TrapNo=%02x type=%d\n", u8TrapNo, enmType));
177
178	/*
179	* Cannot assert a trap when one is already active.
180	*/
181	if (pVCpu->trpm.s.uActiveVector != ~0U)
182	{
183	AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
184	return VERR_TRPM_ACTIVE_TRAP;
185	}
186
187	pVCpu->trpm.s.uActiveVector = u8TrapNo;
188	pVCpu->trpm.s.enmActiveType = enmType;
189	pVCpu->trpm.s.uActiveErrorCode = ~(RTGCUINT)0;
190	pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
191	return VINF_SUCCESS;
192	}
193
194
195	/**
196	* Sets the error code of the current trap.
197	* (This function is for use in trap handlers and such.)
198	*
199	* The caller is responsible for making sure there is an active trap
200	* which takes an errorcode when making this request.
201	*
202	* @param pVCpu Pointer to the VMCPU.
203	* @param uErrorCode The new error code.
204	*/
205	VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode)
206	{
207	Log2(("TRPMSetErrorCode: uErrorCode=%RGv\n", uErrorCode)); /** @todo RTGCUINT mess! */
208	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
209	pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
210	#ifdef VBOX_STRICT
211	switch (pVCpu->trpm.s.uActiveVector)
212	{
213	case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e:
214	AssertMsg(uErrorCode != ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
215	break;
216	case 0x11: case 0x08:
217	AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
218	break;
219	default:
220	AssertMsg(uErrorCode == ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
221	break;
222	}
223	#endif
224	}
225
226
227	/**
228	* Sets the error code of the current trap.
229	* (This function is for use in trap handlers and such.)
230	*
231	* The caller is responsible for making sure there is an active trap 0e
232	* when making this request.
233	*
234	* @param pVCpu Pointer to the VMCPU.
235	* @param uCR2 The new fault address (cr2 register).
236	*/
237	VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPTR uCR2)
238	{
239	Log2(("TRPMSetFaultAddress: uCR2=%RGv\n", uCR2));
240	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
241	AssertMsg(pVCpu->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n"));
242	pVCpu->trpm.s.uActiveCR2 = uCR2;
243	}
244
245
246	/**
247	* Checks if the current active trap/interrupt/exception/fault/whatever is a software
248	* interrupt or not.
249	*
250	* The caller is responsible for making sure there is an active trap
251	* when making this request.
252	*
253	* @returns true if software interrupt, false if not.
254	*
255	* @param pVCpu Pointer to the VMCPU.
256	*/
257	VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu)
258	{
259	AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
260	return (pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT);
261	}
262
263
264	/**
265	* Check if there is an active trap.
266	*
267	* @returns true if trap active, false if not.
268	* @param pVCpu Pointer to the VMCPU.
269	*/
270	VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu)
271	{
272	return pVCpu->trpm.s.uActiveVector != ~0U;
273	}
274
275
276	/**
277	* Query all info about the current active trap/interrupt.
278	* If no trap is active active an error code is returned.
279	*
280	* @returns VBox status code.
281	* @param pVCpu Pointer to the VMCPU.
282	* @param pu8TrapNo Where to store the trap number.
283	* @param pEnmType Where to store the trap type
284	* @param puErrorCode Where to store the error code associated with some traps.
285	* ~0U is stored if the trap has no error code.
286	* @param puCR2 Where to store the CR2 associated with a trap 0E.
287	*/
288	VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t pu8TrapNo, TRPMEVENT pEnmType, PRTGCUINT puErrorCode, PRTGCUINTPTR puCR2)
289	{
290	/*
291	* Check if we have a trap at present.
292	*/
293	if (pVCpu->trpm.s.uActiveVector == ~0U)
294	return VERR_TRPM_NO_ACTIVE_TRAP;
295
296	if (pu8TrapNo)
297	*pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
298	if (pEnmType)
299	*pEnmType = pVCpu->trpm.s.enmActiveType;
300	if (puErrorCode)
301	*puErrorCode = pVCpu->trpm.s.uActiveErrorCode;
302	if (puCR2)
303	*puCR2 = pVCpu->trpm.s.uActiveCR2;
304
305	return VINF_SUCCESS;
306	}
307
308
309	/**
310	* Save the active trap.
311	*
312	* This routine useful when doing try/catch in the hypervisor.
313	* Any function which uses temporary trap handlers should
314	* probably also use this facility to save the original trap.
315	*
316	* @param pVM Pointer to the VM.
317	*/
318	VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu)
319	{
320	pVCpu->trpm.s.uSavedVector = pVCpu->trpm.s.uActiveVector;
321	pVCpu->trpm.s.enmSavedType = pVCpu->trpm.s.enmActiveType;
322	pVCpu->trpm.s.uSavedErrorCode = pVCpu->trpm.s.uActiveErrorCode;
323	pVCpu->trpm.s.uSavedCR2 = pVCpu->trpm.s.uActiveCR2;
324	}
325
326
327	/**
328	* Restore a saved trap.
329	*
330	* Multiple restores of a saved trap is possible.
331	*
332	* @param pVM Pointer to the VM.
333	*/
334	VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu)
335	{
336	pVCpu->trpm.s.uActiveVector = pVCpu->trpm.s.uSavedVector;
337	pVCpu->trpm.s.enmActiveType = pVCpu->trpm.s.enmSavedType;
338	pVCpu->trpm.s.uActiveErrorCode = pVCpu->trpm.s.uSavedErrorCode;
339	pVCpu->trpm.s.uActiveCR2 = pVCpu->trpm.s.uSavedCR2;
340	}
341
342
343	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
344	/**
345	* Forward trap or interrupt to the guest's handler
346	*
347	*
348	* @returns VBox status code.
349	* or does not return at all (when the trap is actually forwarded)
350	*
351	* @param pVM Pointer to the VM.
352	* @param pRegFrame Pointer to the register frame for the trap.
353	* @param iGate Trap or interrupt gate number
354	* @param cbInstr Instruction size (only relevant for software interrupts)
355	* @param enmError TRPM_TRAP_HAS_ERRORCODE or TRPM_TRAP_NO_ERRORCODE.
356	* @param enmType TRPM event type
357	* @param iOrgTrap The original trap.
358	* @internal
359	*/
360	VMMDECL(int) TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t cbInstr,
361	TRPMERRORCODE enmError, TRPMEVENT enmType, int32_t iOrgTrap)
362	{
363	#ifdef TRPM_FORWARD_TRAPS_IN_GC
364	PVM pVM = pVCpu->CTX_SUFF(pVM);
365	X86EFLAGS eflags;
366	Assert(pVM->cCpus == 1);
367
368	STAM_PROFILE_ADV_START(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
369
370	# if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
371	if (pRegFrame->eflags.Bits.u1VM)
372	Log(("TRPMForwardTrap-VM: eip=%04X:%04X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
373	else
374	Log(("TRPMForwardTrap: eip=%04X:%08X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
375
376	switch (iGate) {
377	case 14:
378	if (pRegFrame->eip == pVCpu->trpm.s.uActiveCR2)
379	{
380	int rc;
381	RTGCPTR pCallerGC;
382	# ifdef IN_RC
383	rc = MMGCRamRead(pVM, &pCallerGC, (void *)pRegFrame->esp, sizeof(pCallerGC));
384	# else
385	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pCallerGC, (RTGCPTR)pRegFrame->esp, sizeof(pCallerGC));
386	# endif
387	if (RT_SUCCESS(rc))
388	Log(("TRPMForwardTrap: caller=%RGv\n", pCallerGC));
389	}
390	/* no break */
391	case 8:
392	case 10:
393	case 11:
394	case 12:
395	case 13:
396	case 17:
397	Assert(enmError == TRPM_TRAP_HAS_ERRORCODE \|\| enmType == TRPM_SOFTWARE_INT);
398	break;
399
400	default:
401	Assert(enmError == TRPM_TRAP_NO_ERRORCODE);
402	break;
403	}
404	# endif /* VBOX_STRICT \|\| LOG_ENABLED */
405
406	/* Retrieve the eflags including the virtualized bits. */
407	/* Note: hackish as the cpumctxcore structure doesn't contain the right value */
408	eflags.u32 = CPUMRawGetEFlags(pVCpu);
409
410	/* VMCPU_FF_INHIBIT_INTERRUPTS should be cleared upfront or don't call this function at all for dispatching hardware interrupts. */
411	Assert(enmType != TRPM_HARDWARE_INT \|\| !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
412
413	/*
414	* If it's a real guest trap and the guest's page fault handler is marked as safe for GC execution, then we call it directly.
415	* Well, only if the IF flag is set.
416	*/
417	/** @todo if the trap handler was modified and marked invalid, then we should now go back to the host context and install a new patch. */
418	if ( pVM->trpm.s.aGuestTrapHandler[iGate]
419	&& (eflags.Bits.u1IF)
420	#ifndef VBOX_RAW_V86
421	&& !(eflags.Bits.u1VM) /** @todo implement when needed (illegal for same privilege level transfers). */
422	#endif
423	&& !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
424	)
425	{
426	uint16_t cbIDT;
427	RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
428	uint32_t cpl;
429	VBOXIDTE GuestIdte;
430	RTGCPTR pIDTEntry;
431	int rc;
432
433	Assert(PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame));
434	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
435
436	if (GCPtrIDT && iGate * sizeof(VBOXIDTE) >= cbIDT)
437	goto failure;
438
439	/* Get the current privilege level. */
440	cpl = CPUMGetGuestCPL(pVCpu);
441
442	/*
443	* BIG TODO: The checks are not complete. see trap and interrupt dispatching section in Intel docs for details
444	* All very obscure, but still necessary.
445	* Currently only some CS & TSS selector checks are missing.
446	*
447	*/
448	pIDTEntry = (RTGCPTR)((RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate);
449	#ifdef IN_RC
450	rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
451	#else
452	rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
453	#endif
454	if (RT_FAILURE(rc))
455	{
456	/* The page might be out of sync. / /* @todo might cross a page boundary) */
457	Log(("Page %RGv out of sync -> prefetch and try again\n", pIDTEntry));
458	rc = PGMPrefetchPage(pVCpu, pIDTEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
459	if (rc != VINF_SUCCESS)
460	{
461	Log(("TRPMForwardTrap: PGMPrefetchPage failed with rc=%Rrc\n", rc));
462	goto failure;
463	}
464	#ifdef IN_RC
465	rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
466	#else
467	rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
468	#endif
469	}
470	if ( RT_SUCCESS(rc)
471	&& GuestIdte.Gen.u1Present
472	&& (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32 \|\| GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
473	&& (GuestIdte.Gen.u2DPL == 3 \|\| GuestIdte.Gen.u2DPL == 0)
474	&& (GuestIdte.Gen.u16SegSel & 0xfffc) /* must not be zero */
475	&& (enmType == TRPM_TRAP \|\| enmType == TRPM_HARDWARE_INT \|\| cpl <= GuestIdte.Gen.u2DPL) /* CPL <= DPL if software int */
476	)
477	{
478	RTGCPTR pHandler, dummy;
479	RTGCPTR pTrapStackGC;
480
481	pHandler = (RTGCPTR)VBOXIDTE_OFFSET(GuestIdte);
482
483	/* Note: SELMValidateAndConvertCSAddr checks for code type, memory type, selector validity. */
484	/** @todo dpl <= cpl else GPF */
485
486	/* Note: don't use current eflags as we might be in V86 mode and the IDT always contains protected mode selectors */
487	X86EFLAGS fakeflags;
488	fakeflags.u32 = 0;
489
490	rc = SELMValidateAndConvertCSAddr(pVCpu, fakeflags, 0, GuestIdte.Gen.u16SegSel, NULL, pHandler, &dummy);
491	if (rc == VINF_SUCCESS)
492	{
493	VBOXGDTR gdtr = {0, 0};
494	bool fConforming = false;
495	int idx = 0;
496	uint32_t dpl;
497	uint32_t ss_r0;
498	uint32_t esp_r0;
499	X86DESC Desc;
500	RTGCPTR pGdtEntry;
501
502	CPUMGetGuestGDTR(pVCpu, &gdtr);
503	Assert(gdtr.pGdt && gdtr.cbGdt > GuestIdte.Gen.u16SegSel);
504
505	if (!gdtr.pGdt)
506	goto failure;
507
508	pGdtEntry = gdtr.pGdt + (GuestIdte.Gen.u16SegSel >> X86_SEL_SHIFT) * sizeof(X86DESC);
509	#ifdef IN_RC
510	rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
511	#else
512	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
513	#endif
514	if (RT_FAILURE(rc))
515	{
516	/* The page might be out of sync. / /* @todo might cross a page boundary) */
517	Log(("Page %RGv out of sync -> prefetch and try again\n", pGdtEntry));
518	rc = PGMPrefetchPage(pVCpu, pGdtEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
519	if (rc != VINF_SUCCESS)
520	{
521	Log(("PGMPrefetchPage failed with rc=%Rrc\n", rc));
522	goto failure;
523	}
524	#ifdef IN_RC
525	rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
526	#else
527	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
528	#endif
529	if (RT_FAILURE(rc))
530	{
531	Log(("MMGCRamRead failed with %Rrc\n", rc));
532	goto failure;
533	}
534	}
535
536	if (Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
537	{
538	Log(("Conforming code selector\n"));
539	fConforming = true;
540	}
541	/** @todo check descriptor type!! */
542
543	dpl = Desc.Gen.u2Dpl;
544
545	if (!fConforming && dpl < cpl) /* to inner privilege level */
546	{
547	rc = SELMGetRing1Stack(pVM, &ss_r0, &esp_r0);
548	if (RT_FAILURE(rc))
549	goto failure;
550
551	Assert((ss_r0 & X86_SEL_RPL) == 1);
552
553	if ( !esp_r0
554	\|\| !ss_r0
555	\|\| (ss_r0 & X86_SEL_RPL) != ((dpl == 0) ? 1 : dpl)
556	\|\| SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
557	(PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS
558	)
559	{
560	Log(("Invalid ring 0 stack %04X:%08RX32\n", ss_r0, esp_r0));
561	goto failure;
562	}
563	}
564	else
565	if (fConforming \|\| dpl == cpl) /* to the same privilege level */
566	{
567	ss_r0 = pRegFrame->ss.Sel;
568	esp_r0 = pRegFrame->esp;
569
570	if ( eflags.Bits.u1VM /* illegal */
571	\|\| SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
572	(PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS)
573	{
574	AssertMsgFailed(("Invalid stack %04X:%08RX32??? (VM=%d)\n", ss_r0, esp_r0, eflags.Bits.u1VM));
575	goto failure;
576	}
577	}
578	else
579	{
580	Log(("Invalid cpl-dpl combo %d vs %d\n", cpl, dpl));
581	goto failure;
582	}
583	/*
584	* Build trap stack frame on guest handler's stack
585	*/
586	uint32_t *pTrapStack;
587	#ifdef IN_RC
588	Assert(eflags.Bits.u1VM \|\| (pRegFrame->ss.Sel & X86_SEL_RPL) != 0);
589	/* Check maximum amount we need (10 when executing in V86 mode) */
590	rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)pTrapStackGC - 10sizeof(uint32_t), 10 sizeof(uint32_t), X86_PTE_RW);
591	pTrapStack = (uint32_t *)(uintptr_t)pTrapStackGC;
592	#else
593	Assert(eflags.Bits.u1VM \|\| (pRegFrame->ss.Sel & X86_SEL_RPL) == 0 \|\| (pRegFrame->ss.Sel & X86_SEL_RPL) == 3);
594	/* Check maximum amount we need (10 when executing in V86 mode) */
595	if ((pTrapStackGC >> PAGE_SHIFT) != ((pTrapStackGC - 10sizeof(uint32_t)) >> PAGE_SHIFT)) / fail if we cross a page boundary */
596	goto failure;
597	PGMPAGEMAPLOCK PageMappingLock;
598	rc = PGMPhysGCPtr2CCPtr(pVCpu, pTrapStackGC, (void **)&pTrapStack, &PageMappingLock);
599	if (RT_FAILURE(rc))
600	{
601	AssertRC(rc);
602	goto failure;
603	}
604	#endif
605	if (rc == VINF_SUCCESS)
606	{
607	/** if eflags.Bits.u1VM then push gs, fs, ds, es */
608	if (eflags.Bits.u1VM)
609	{
610	Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
611	pTrapStack[--idx] = pRegFrame->gs.Sel;
612	pTrapStack[--idx] = pRegFrame->fs.Sel;
613	pTrapStack[--idx] = pRegFrame->ds.Sel;
614	pTrapStack[--idx] = pRegFrame->es.Sel;
615
616	/* clear ds, es, fs & gs in current context */
617	pRegFrame->ds.Sel = pRegFrame->es.Sel = pRegFrame->fs.Sel = pRegFrame->gs.Sel = 0;
618	}
619	else
620	Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
621
622	if (!fConforming && dpl < cpl)
623	{
624	if ((pRegFrame->ss.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
625	pTrapStack[--idx] = pRegFrame->ss.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */
626	else
627	pTrapStack[--idx] = pRegFrame->ss.Sel;
628
629	pTrapStack[--idx] = pRegFrame->esp;
630	}
631
632	/* Note: We use the eflags copy, that includes the virtualized bits! */
633	/* Note: Not really necessary as we grab include those bits in the trap/irq handler trampoline */
634	pTrapStack[--idx] = eflags.u32;
635
636	if ((pRegFrame->cs.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
637	pTrapStack[--idx] = pRegFrame->cs.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */
638	else
639	pTrapStack[--idx] = pRegFrame->cs.Sel;
640
641	if (enmType == TRPM_SOFTWARE_INT)
642	{
643	Assert(cbInstr);
644	pTrapStack[--idx] = pRegFrame->eip + cbInstr; /* return address = next instruction */
645	}
646	else
647	pTrapStack[--idx] = pRegFrame->eip;
648
649	if (enmError == TRPM_TRAP_HAS_ERRORCODE)
650	{
651	pTrapStack[--idx] = pVCpu->trpm.s.uActiveErrorCode;
652	}
653
654	Assert(esp_r0 > -idx*sizeof(uint32_t));
655	/* Adjust ESP accordingly */
656	esp_r0 += idx*sizeof(uint32_t);
657
658	/* Mask away dangerous flags for the trap/interrupt handler. */
659	eflags.u32 &= ~(X86_EFL_TF \| X86_EFL_VM \| X86_EFL_RF \| X86_EFL_NT);
660	#ifdef DEBUG
661	for (int j = idx; j < 0; j++)
662	Log4(("Stack %RRv pos %02d: %08x\n", &pTrapStack[j], j, pTrapStack[j]));
663
664	Log4(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
665	"eip=%08x esp=%08x ebp=%08x iopl=%d\n"
666	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n",
667	pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx, pRegFrame->esi, pRegFrame->edi,
668	pRegFrame->eip, pRegFrame->esp, pRegFrame->ebp, eflags.Bits.u2IOPL,
669	pRegFrame->cs.Sel, pRegFrame->ds.Sel, pRegFrame->es.Sel,
670	pRegFrame->fs.Sel, pRegFrame->gs.Sel, eflags.u32));
671	#endif
672
673	Log(("PATM Handler %RRv Adjusted stack %08X new EFLAGS=%08X idx=%d dpl=%d cpl=%d\n", pVM->trpm.s.aGuestTrapHandler[iGate], esp_r0, eflags.u32, idx, dpl, cpl));
674
675	/* Make sure the internal guest context structure is up-to-date. */
676	CPUMSetGuestCR2(pVCpu, pVCpu->trpm.s.uActiveCR2);
677
678	#ifdef IN_RC
679	/* Note: shouldn't be necessary */
680	ASMSetCR2(pVCpu->trpm.s.uActiveCR2);
681
682	/* Turn off interrupts for interrupt gates. */
683	if (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
684	CPUMRawSetEFlags(pVCpu, eflags.u32 & ~X86_EFL_IF);
685
686	/* The virtualized bits must be removed again!! */
687	eflags.Bits.u1IF = 1;
688	eflags.Bits.u2IOPL = 0;
689
690	Assert(eflags.Bits.u1IF);
691	Assert(eflags.Bits.u2IOPL == 0);
692	STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF(paStatForwardedIRQ)[iGate]);
693	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
694	if (iOrgTrap >= 0 && iOrgTrap < (int)RT_ELEMENTS(pVM->trpm.s.aStatGCTraps))
695	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[iOrgTrap], o);
696
697	PGMRZDynMapReleaseAutoSet(pVCpu);
698	CPUMGCCallGuestTrapHandler(pRegFrame, GuestIdte.Gen.u16SegSel \| 1, pVM->trpm.s.aGuestTrapHandler[iGate],
699	eflags.u32, ss_r0, (RTRCPTR)esp_r0);
700	/* does not return */
701	#else
702	/* Turn off interrupts for interrupt gates. */
703	if (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
704	eflags.Bits.u1IF = 0;
705
706	pRegFrame->eflags.u32 = eflags.u32;
707
708	pRegFrame->eip = pVM->trpm.s.aGuestTrapHandler[iGate];
709	pRegFrame->cs.Sel = GuestIdte.Gen.u16SegSel;
710	pRegFrame->esp = esp_r0;
711	pRegFrame->ss.Sel = ss_r0 & ~X86_SEL_RPL; /* set rpl to ring 0 */
712	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
713	PGMPhysReleasePageMappingLock(pVM, &PageMappingLock);
714	NOREF(iOrgTrap);
715	return VINF_SUCCESS;
716	#endif
717	}
718	else
719	Log(("TRAP%02X: PGMVerifyAccess %RGv failed with %Rrc -> forward to REM\n", iGate, pTrapStackGC, rc));
720	}
721	else
722	Log(("SELMValidateAndConvertCSAddr failed with %Rrc\n", rc));
723	}
724	else
725	Log(("MMRamRead %RGv size %d failed with %Rrc\n", (RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate, sizeof(GuestIdte), rc));
726	}
727	else
728	{
729	Log(("Refused to forward trap: eflags=%08x IF=%d\n", eflags.u32, eflags.Bits.u1IF));
730	#ifdef VBOX_WITH_STATISTICS
731	if (pVM->trpm.s.aGuestTrapHandler[iGate] == TRPM_INVALID_HANDLER)
732	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
733	else if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
734	STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailPatchAddr);
735	#endif
736	}
737	failure:
738	STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF_Z(StatForwardFail));
739	STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
740
741	Log(("TRAP%02X: forwarding to REM (ss rpl=%d eflags=%08X VMIF=%d handler=%08X\n", iGate, pRegFrame->ss.Sel & X86_SEL_RPL, pRegFrame->eflags.u32, PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame), pVM->trpm.s.aGuestTrapHandler[iGate]));
742	#endif
743	return VINF_EM_RAW_GUEST_TRAP;
744	}
745	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
746
747
748	/**
749	* Raises a cpu exception which doesn't take an error code.
750	*
751	* This function may or may not dispatch the exception before returning.
752	*
753	* @returns VBox status code fit for scheduling.
754	* @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
755	* @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
756	* @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
757	*
758	* @param pVM Pointer to the VM.
759	* @param pCtxCore The CPU context core.
760	* @param enmXcpt The exception.
761	*/
762	VMMDECL(int) TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt)
763	{
764	LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt));
765	/** @todo dispatch the trap. */
766	pVCpu->trpm.s.uActiveVector = enmXcpt;
767	pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
768	pVCpu->trpm.s.uActiveErrorCode = 0xdeadbeef;
769	pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
770	return VINF_EM_RAW_GUEST_TRAP;
771	}
772
773
774	/**
775	* Raises a cpu exception with an errorcode.
776	*
777	* This function may or may not dispatch the exception before returning.
778	*
779	* @returns VBox status code fit for scheduling.
780	* @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
781	* @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
782	* @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
783	*
784	* @param pVM Pointer to the VM.
785	* @param pCtxCore The CPU context core.
786	* @param enmXcpt The exception.
787	* @param uErr The error code.
788	*/
789	VMMDECL(int) TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr)
790	{
791	LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr));
792	/** @todo dispatch the trap. */
793	pVCpu->trpm.s.uActiveVector = enmXcpt;
794	pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
795	pVCpu->trpm.s.uActiveErrorCode = uErr;
796	pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
797	return VINF_EM_RAW_GUEST_TRAP;
798	}
799
800
801	/**
802	* Raises a cpu exception with an errorcode and CR2.
803	*
804	* This function may or may not dispatch the exception before returning.
805	*
806	* @returns VBox status code fit for scheduling.
807	* @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
808	* @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
809	* @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
810	*
811	* @param pVM Pointer to the VM.
812	* @param pCtxCore The CPU context core.
813	* @param enmXcpt The exception.
814	* @param uErr The error code.
815	* @param uCR2 The CR2 value.
816	*/
817	VMMDECL(int) TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2)
818	{
819	LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr, uCR2));
820	/** @todo dispatch the trap. */
821	pVCpu->trpm.s.uActiveVector = enmXcpt;
822	pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
823	pVCpu->trpm.s.uActiveErrorCode = uErr;
824	pVCpu->trpm.s.uActiveCR2 = uCR2;
825	return VINF_EM_RAW_GUEST_TRAP;
826	}
827
828
829	/**
830	* Clear guest trap/interrupt gate handler
831	*
832	* @returns VBox status code.
833	* @param pVM Pointer to the VM.
834	* @param iTrap Interrupt/trap number.
835	*/
836	VMMDECL(int) trpmClearGuestTrapHandler(PVM pVM, unsigned iTrap)
837	{
838	/*
839	* Validate.
840	*/
841	if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
842	{
843	AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
844	return VERR_INVALID_PARAMETER;
845	}
846
847	if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
848	#ifdef IN_RING3
849	trpmR3ClearPassThroughHandler(pVM, iTrap);
850	#else
851	AssertFailed();
852	#endif
853
854	pVM->trpm.s.aGuestTrapHandler[iTrap] = TRPM_INVALID_HANDLER;
855	return VINF_SUCCESS;
856	}
857

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source: vbox/trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp@ 42202

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