VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp

Last change on this file was 106061, checked in by vboxsync, 2 months ago

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1/* $Id: TRPMAll.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * TRPM - Trap Monitor - Any Context.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_TRPM
33#include <VBox/vmm/trpm.h>
34#include <VBox/vmm/pgm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/selm.h>
38#include <VBox/vmm/stam.h>
39#include <VBox/vmm/dbgf.h>
40#include "TRPMInternal.h"
41#include <VBox/vmm/vmcc.h>
42#include <VBox/err.h>
43#include <VBox/vmm/em.h>
44#include <VBox/log.h>
45#include <iprt/assert.h>
46#include <iprt/asm.h>
47#include <iprt/param.h>
48#include <iprt/x86.h>
49
50
51
52/**
53 * Query info about the current active trap/interrupt.
54 * If no trap is active active an error code is returned.
55 *
56 * @returns VBox status code.
57 * @param pVCpu The cross context virtual CPU structure.
58 * @param pu8TrapNo Where to store the trap number.
59 * @param penmType Where to store the trap type
60 */
61VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *penmType)
62{
63 /*
64 * Check if we have a trap at present.
65 */
66 if (pVCpu->trpm.s.uActiveVector != ~0U)
67 {
68 if (pu8TrapNo)
69 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
70 if (penmType)
71 *penmType = pVCpu->trpm.s.enmActiveType;
72 return VINF_SUCCESS;
73 }
74
75 return VERR_TRPM_NO_ACTIVE_TRAP;
76}
77
78
79/**
80 * Gets the trap number for the current trap.
81 *
82 * The caller is responsible for making sure there is an active trap which
83 * takes an error code when making this request.
84 *
85 * @returns The current trap number.
86 * @param pVCpu The cross context virtual CPU structure.
87 */
88VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu)
89{
90 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
91 return (uint8_t)pVCpu->trpm.s.uActiveVector;
92}
93
94
95/**
96 * Gets the error code for the current trap.
97 *
98 * The caller is responsible for making sure there is an active trap which
99 * takes an error code when making this request.
100 *
101 * @returns Error code.
102 * @param pVCpu The cross context virtual CPU structure.
103 */
104VMMDECL(uint32_t) TRPMGetErrorCode(PVMCPU pVCpu)
105{
106 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
107#ifdef VBOX_STRICT
108 switch (pVCpu->trpm.s.uActiveVector)
109 {
110 case X86_XCPT_TS:
111 case X86_XCPT_NP:
112 case X86_XCPT_SS:
113 case X86_XCPT_GP:
114 case X86_XCPT_PF:
115 case X86_XCPT_AC:
116 case X86_XCPT_DF:
117 break;
118 default:
119 AssertMsgFailed(("This trap (%#x) doesn't have any error code\n", pVCpu->trpm.s.uActiveVector));
120 break;
121 }
122#endif
123 return pVCpu->trpm.s.uActiveErrorCode;
124}
125
126
127/**
128 * Gets the fault address for the current trap.
129 *
130 * The caller is responsible for making sure there is an active trap 0x0e when
131 * making this request.
132 *
133 * @returns Fault address associated with the trap.
134 * @param pVCpu The cross context virtual CPU structure.
135 */
136VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu)
137{
138 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
139 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_PF, ("Not page-fault trap!\n"));
140 return pVCpu->trpm.s.uActiveCR2;
141}
142
143
144/**
145 * Gets the instruction-length for the current trap (only relevant for software
146 * interrupts and software exceptions \#BP and \#OF).
147 *
148 * The caller is responsible for making sure there is an active trap 0x0e when
149 * making this request.
150 *
151 * @returns Fault address associated with the trap.
152 * @param pVCpu The cross context virtual CPU structure.
153 */
154VMMDECL(uint8_t) TRPMGetInstrLength(PVMCPU pVCpu)
155{
156 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
157 return pVCpu->trpm.s.cbInstr;
158}
159
160
161/**
162 * Checks if the current \#DB exception is due to an INT1/ICEBP instruction.
163 *
164 * The caller is responsible for making sure there is an active trap.
165 *
166 * @returns @c true if it's due to INT1/ICEBP, @c false if not.
167 *
168 * @param pVCpu The cross context virtual CPU structure.
169 */
170VMMDECL(bool) TRPMIsTrapDueToIcebp(PVMCPU pVCpu)
171{
172 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
173 return pVCpu->trpm.s.fIcebp;
174}
175
176
177/**
178 * Clears the current active trap/exception/interrupt.
179 *
180 * The caller is responsible for making sure there is an active trap
181 * when making this request.
182 *
183 * @returns VBox status code.
184 * @param pVCpu The cross context virtual CPU structure.
185 */
186VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu)
187{
188 /*
189 * Cannot reset non-existing trap!
190 */
191 if (pVCpu->trpm.s.uActiveVector == ~0U)
192 {
193 AssertMsgFailed(("No active trap!\n"));
194 return VERR_TRPM_NO_ACTIVE_TRAP;
195 }
196
197 /*
198 * Reset it.
199 */
200 pVCpu->trpm.s.uActiveVector = ~0U;
201 return VINF_SUCCESS;
202}
203
204
205/**
206 * Assert trap/exception/interrupt.
207 *
208 * The caller is responsible for making sure there is no active trap
209 * when making this request.
210 *
211 * @returns VBox status code.
212 * @param pVCpu The cross context virtual CPU structure.
213 * @param u8TrapNo The trap vector to assert.
214 * @param enmType Trap type.
215 */
216VMMDECL(int) TRPMAssertTrap(PVMCPUCC pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType)
217{
218 Log2(("TRPMAssertTrap: u8TrapNo=%02x type=%d\n", u8TrapNo, enmType));
219
220 /*
221 * Cannot assert a trap when one is already active.
222 */
223 if (pVCpu->trpm.s.uActiveVector != ~0U)
224 {
225 AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
226 return VERR_TRPM_ACTIVE_TRAP;
227 }
228
229 /* NMI TRPM type must specify the vector as 2 (NMI). */
230 Assert(enmType != TRPM_NMI || u8TrapNo == X86_XCPT_NMI);
231
232 pVCpu->trpm.s.uActiveVector = u8TrapNo;
233 pVCpu->trpm.s.enmActiveType = enmType;
234 pVCpu->trpm.s.uActiveErrorCode = ~0U;
235 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
236 pVCpu->trpm.s.cbInstr = UINT8_MAX;
237 pVCpu->trpm.s.fIcebp = false;
238 return VINF_SUCCESS;
239}
240
241
242/**
243 * Assert a page-fault exception.
244 *
245 * The caller is responsible for making sure there is no active trap
246 * when making this request.
247 *
248 * @returns VBox status code.
249 * @param pVCpu The cross context virtual CPU structure.
250 * @param uCR2 The new fault address.
251 * @param uErrorCode The error code for the page-fault.
252 */
253VMMDECL(int) TRPMAssertXcptPF(PVMCPUCC pVCpu, RTGCUINTPTR uCR2, uint32_t uErrorCode)
254{
255 Log2(("TRPMAssertXcptPF: uCR2=%RGv uErrorCode=%#RX32\n", uCR2, uErrorCode));
256
257 /*
258 * Cannot assert a trap when one is already active.
259 */
260 if (pVCpu->trpm.s.uActiveVector != ~0U)
261 {
262 AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
263 return VERR_TRPM_ACTIVE_TRAP;
264 }
265
266 pVCpu->trpm.s.uActiveVector = X86_XCPT_PF;
267 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
268 pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
269 pVCpu->trpm.s.uActiveCR2 = uCR2;
270 pVCpu->trpm.s.cbInstr = UINT8_MAX;
271 return VINF_SUCCESS;
272}
273
274
275/**
276 * Sets the error code of the current trap.
277 * (This function is for use in trap handlers and such.)
278 *
279 * The caller is responsible for making sure there is an active trap
280 * which takes an errorcode when making this request.
281 *
282 * @param pVCpu The cross context virtual CPU structure.
283 * @param uErrorCode The new error code.
284 */
285VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, uint32_t uErrorCode)
286{
287 Log2(("TRPMSetErrorCode: uErrorCode=%#RX32\n", uErrorCode));
288 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
289 AssertMsg( pVCpu->trpm.s.enmActiveType == TRPM_TRAP
290 || ( pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT && pVCpu->trpm.s.uActiveVector == X86_XCPT_DB),
291 ("Not hardware exception or privileged software exception (INT1/ICEBP)!\n"));
292 pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
293#ifdef VBOX_STRICT
294 if (pVCpu->trpm.s.enmActiveType == TRPM_TRAP)
295 {
296 switch (pVCpu->trpm.s.uActiveVector)
297 {
298 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP: case X86_XCPT_PF:
299 AssertMsg(uErrorCode != ~0U, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
300 break;
301 case X86_XCPT_AC: case X86_XCPT_DF:
302 AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
303 break;
304 default:
305 AssertMsg(uErrorCode == ~0U, ("Invalid uErrorCode=%#x u8TrapNo=%u\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
306 break;
307 }
308 }
309#endif
310}
311
312
313/**
314 * Sets the fault address of the current \#PF trap. (This function is for use in
315 * trap handlers and such.)
316 *
317 * The caller is responsible for making sure there is an active trap 0e
318 * when making this request.
319 *
320 * @param pVCpu The cross context virtual CPU structure.
321 * @param uCR2 The new fault address (cr2 register).
322 */
323VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPTR uCR2)
324{
325 Log2(("TRPMSetFaultAddress: uCR2=%RGv\n", uCR2));
326 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
327 AssertMsg(pVCpu->trpm.s.enmActiveType == TRPM_TRAP, ("Not hardware exception!\n"));
328 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_PF, ("Not trap 0e!\n"));
329 pVCpu->trpm.s.uActiveCR2 = uCR2;
330}
331
332
333/**
334 * Sets the instruction-length of the current trap (relevant for software
335 * interrupts and software exceptions like \#BP, \#OF).
336 *
337 * The caller is responsible for making sure there is an active trap when making
338 * this request.
339 *
340 * @param pVCpu The cross context virtual CPU structure.
341 * @param cbInstr The instruction length.
342 */
343VMMDECL(void) TRPMSetInstrLength(PVMCPU pVCpu, uint8_t cbInstr)
344{
345 Log2(("TRPMSetInstrLength: cbInstr=%u\n", cbInstr));
346 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
347 AssertMsg( pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT
348 || ( pVCpu->trpm.s.enmActiveType == TRPM_TRAP
349 && ( pVCpu->trpm.s.uActiveVector == X86_XCPT_BP
350 || pVCpu->trpm.s.uActiveVector == X86_XCPT_OF)),
351 ("Invalid trap type %#x\n", pVCpu->trpm.s.enmActiveType));
352 pVCpu->trpm.s.cbInstr = cbInstr;
353}
354
355
356/**
357 * Sets if the current \#DB exception is due to an INT1/ICEBP instruction.
358 *
359 * The caller is responsible for making sure there is an active trap and it's a
360 * \#DB.
361 *
362 * @param pVCpu The cross context virtual CPU structure.
363 */
364VMMDECL(void) TRPMSetTrapDueToIcebp(PVMCPU pVCpu)
365{
366 AssertMsg(pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT, ("Trap type for INT1/ICEBP invalid!"));
367 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_DB, ("INT1/ICEBP must be indicated by a #DB!\n"));
368 pVCpu->trpm.s.fIcebp = true;
369}
370
371
372/**
373 * Checks if the current active trap/interrupt/exception/fault/whatever is a software
374 * interrupt or not.
375 *
376 * The caller is responsible for making sure there is an active trap
377 * when making this request.
378 *
379 * @returns true if software interrupt, false if not.
380 *
381 * @param pVCpu The cross context virtual CPU structure.
382 */
383VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu)
384{
385 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
386 return (pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT);
387}
388
389
390/**
391 * Check if there is an active trap.
392 *
393 * @returns true if trap active, false if not.
394 * @param pVCpu The cross context virtual CPU structure.
395 */
396VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu)
397{
398 return pVCpu->trpm.s.uActiveVector != ~0U;
399}
400
401
402/**
403 * Query all info about the current active trap/interrupt.
404 * If no trap is active active an error code is returned.
405 *
406 * @returns VBox status code.
407 * @param pVCpu The cross context virtual CPU structure.
408 * @param pu8TrapNo Where to store the trap number.
409 * @param pEnmType Where to store the trap type.
410 * @param puErrorCode Where to store the error code associated with some
411 * traps. ~0U is stored if the trap has no error code.
412 * @param puCR2 Where to store the CR2 associated with a trap 0E.
413 * @param pcbInstr Where to store the instruction-length associated with
414 * some traps.
415 * @param pfIcebp Where to store whether the trap is a \#DB caused by an
416 * INT1/ICEBP instruction.
417 */
418VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, uint32_t *puErrorCode, PRTGCUINTPTR puCR2,
419 uint8_t *pcbInstr, bool *pfIcebp)
420{
421 /*
422 * Check if we have an active trap.
423 */
424 if (pVCpu->trpm.s.uActiveVector == ~0U)
425 return VERR_TRPM_NO_ACTIVE_TRAP;
426
427 if (pu8TrapNo)
428 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
429 if (pEnmType)
430 *pEnmType = pVCpu->trpm.s.enmActiveType;
431 if (puErrorCode)
432 *puErrorCode = pVCpu->trpm.s.uActiveErrorCode;
433 if (puCR2)
434 *puCR2 = pVCpu->trpm.s.uActiveCR2;
435 if (pcbInstr)
436 *pcbInstr = pVCpu->trpm.s.cbInstr;
437 if (pfIcebp)
438 *pfIcebp = pVCpu->trpm.s.fIcebp;
439 return VINF_SUCCESS;
440}
441
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