SELMAll.cpp@ 59710

Last change on this file since 59710 was 58126, checked in by vboxsync, 9 years ago
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1	/* $Id: SELMAll.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2	/** @file
3	* SELM All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_SELM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/hm.h>
30	#include "SELMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <VBox/vmm/vmm.h>
36	#include <iprt/x86.h>
37	#include <iprt/string.h>
38
39	#include "SELMInline.h"
40
41
42	/*********************************************************************************************************************************
43	* Global Variables *
44	*********************************************************************************************************************************/
45	#if defined(LOG_ENABLED) && defined(VBOX_WITH_RAW_MODE_NOT_R0)
46	/** Segment register names. */
47	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
48	#endif
49
50
51	#ifndef IN_RING0
52
53	# ifdef SELM_TRACK_GUEST_GDT_CHANGES
54	/**
55	* @callback_method_impl{FNPGMVIRTHANDLER}
56	*/
57	PGM_ALL_CB2_DECL(VBOXSTRICTRC)
58	selmGuestGDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
59	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
60	{
61	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
62	Log(("selmGuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
63	NOREF(pvPtr); NOREF(pvBuf); NOREF(enmOrigin); NOREF(pvUser);
64
65	# ifdef IN_RING3
66	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
67	return VINF_PGM_HANDLER_DO_DEFAULT;
68
69	# else /* IN_RC: */
70	/*
71	* Execute the write, doing necessary pre and post shadow GDT checks.
72	*/
73	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
74	uint32_t offGuestGdt = pCtx->gdtr.pGdt - GCPtr;
75	selmRCGuestGdtPreWriteCheck(pVM, pVCpu, offGuestGdt, cbBuf, pCtx);
76	memcpy(pvBuf, pvPtr, cbBuf);
77	VBOXSTRICTRC rcStrict = selmRCGuestGdtPostWriteCheck(pVM, pVCpu, offGuestGdt, cbBuf, pCtx);
78	if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
79	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTHandled);
80	else
81	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTUnhandled);
82	return rcStrict;
83	# endif
84	}
85	# endif
86
87
88	# ifdef SELM_TRACK_GUEST_LDT_CHANGES
89	/**
90	* @callback_method_impl{FNPGMVIRTHANDLER}
91	*/
92	PGM_ALL_CB2_DECL(VBOXSTRICTRC)
93	selmGuestLDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
94	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
95	{
96	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
97	Log(("selmGuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
98	NOREF(pvPtr); NOREF(pvBuf); NOREF(enmOrigin); NOREF(pvUser);
99
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
101	# ifdef IN_RING3
102	return VINF_PGM_HANDLER_DO_DEFAULT;
103	# else
104	STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestLDT);
105	return VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT;
106	# endif
107	}
108	# endif
109
110
111	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
112	/**
113	* @callback_method_impl{FNPGMVIRTHANDLER}
114	*/
115	PGM_ALL_CB2_DECL(VBOXSTRICTRC)
116	selmGuestTSSWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
117	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
118	{
119	Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
120	Log(("selmGuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
121	NOREF(pvBuf); NOREF(GCPtr); NOREF(cbBuf); NOREF(enmOrigin); NOREF(pvUser); NOREF(pvPtr);
122
123	# ifdef IN_RING3
124	/** @todo This can be optimized by checking for the ESP0 offset and tracking TR
125	* reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
126	* should probably also deregister the virtual handler if TR.base/size
127	* changes while we're in REM. May also share
128	* selmRCGuestTssPostWriteCheck code. */
129	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
130	return VINF_PGM_HANDLER_DO_DEFAULT;
131
132	# else /* IN_RC */
133	/*
134	* Do the write and check if anything relevant changed.
135	*/
136	Assert(pVM->selm.s.GCPtrGuestTss != (uintptr_t)RTRCPTR_MAX);
137	memcpy(pvPtr, pvBuf, cbBuf);
138	return selmRCGuestTssPostWriteCheck(pVM, pVCpu, GCPtr - pVM->selm.s.GCPtrGuestTss, cbBuf);
139	# endif
140	}
141	# endif
142
143	#endif /* IN_RING0 */
144
145
146	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
147	/**
148	* Converts a GC selector based address to a flat address.
149	*
150	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
151	* for that.
152	*
153	* @returns Flat address.
154	* @param pVM The cross context VM structure.
155	* @param Sel Selector part.
156	* @param Addr Address part.
157	* @remarks Don't use when in long mode.
158	*/
159	VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr)
160	{
161	Assert(pVM->cCpus == 1 && !CPUMIsGuestInLongMode(VMMGetCpu(pVM))); /* DON'T USE! */
162	Assert(!HMIsEnabled(pVM));
163
164	/** @todo check the limit. */
165	X86DESC Desc;
166	if (!(Sel & X86_SEL_LDT))
167	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
168	else
169	{
170	/** @todo handle LDT pages not present! */
171	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
172	Desc = paLDT[Sel >> X86_SEL_SHIFT];
173	}
174
175	return (RTGCPTR)(((RTGCUINTPTR)Addr + X86DESC_BASE(&Desc)) & 0xffffffff);
176	}
177	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
178
179
180	/**
181	* Converts a GC selector based address to a flat address.
182	*
183	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
184	* for that.
185	*
186	* @returns Flat address.
187	* @param pVM The cross context VM structure.
188	* @param SelReg Selector register
189	* @param pCtxCore CPU context
190	* @param Addr Address part.
191	*/
192	VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr)
193	{
194	PCPUMSELREG pSReg;
195	PVMCPU pVCpu = VMMGetCpu(pVM);
196
197	int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg); AssertRC(rc);
198
199	/*
200	* Deal with real & v86 mode first.
201	*/
202	if ( pCtxCore->eflags.Bits.u1VM
203	\|\| CPUMIsGuestInRealMode(pVCpu))
204	{
205	uint32_t uFlat = (uint32_t)Addr & 0xffff;
206	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
207	uFlat += (uint32_t)pSReg->u64Base;
208	else
209	uFlat += (uint32_t)pSReg->Sel << 4;
210	return (RTGCPTR)uFlat;
211	}
212
213	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
214	/** @todo when we're in 16 bits mode, we should cut off the address as well?? */
215	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
216	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSReg);
217	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs))
218	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtxCore->cs);
219	#else
220	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
221	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
222	#endif
223
224	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
225	(Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
226	if ( pCtxCore->cs.Attr.n.u1Long
227	&& CPUMIsGuestInLongMode(pVCpu))
228	{
229	switch (SelReg)
230	{
231	case DISSELREG_FS:
232	case DISSELREG_GS:
233	return (RTGCPTR)(pSReg->u64Base + Addr);
234
235	default:
236	return Addr; /* base 0 */
237	}
238	}
239
240	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
241	Assert(pSReg->u64Base <= 0xffffffff);
242	return (uint32_t)pSReg->u64Base + (uint32_t)Addr;
243	}
244
245
246	/**
247	* Converts a GC selector based address to a flat address.
248	*
249	* Some basic checking is done, but not all kinds yet.
250	*
251	* @returns VBox status
252	* @param pVCpu The cross context virtual CPU structure.
253	* @param SelReg Selector register.
254	* @param pCtxCore CPU context.
255	* @param Addr Address part.
256	* @param fFlags SELMTOFLAT_FLAGS_*
257	* GDT entires are valid.
258	* @param ppvGC Where to store the GC flat address.
259	*/
260	VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags, PRTGCPTR ppvGC)
261	{
262	/*
263	* Fetch the selector first.
264	*/
265	PCPUMSELREG pSReg;
266	int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg);
267	AssertRCReturn(rc, rc); AssertPtr(pSReg);
268
269	/*
270	* Deal with real & v86 mode first.
271	*/
272	if ( pCtxCore->eflags.Bits.u1VM
273	\|\| CPUMIsGuestInRealMode(pVCpu))
274	{
275	if (ppvGC)
276	{
277	uint32_t uFlat = (uint32_t)Addr & 0xffff;
278	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
279	*ppvGC = (uint32_t)pSReg->u64Base + uFlat;
280	else
281	*ppvGC = ((uint32_t)pSReg->Sel << 4) + uFlat;
282	}
283	return VINF_SUCCESS;
284	}
285
286	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
287	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
288	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSReg);
289	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs))
290	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtxCore->cs);
291	#else
292	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
293	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
294	#endif
295
296	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
297	(Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
298	RTGCPTR pvFlat;
299	bool fCheckLimit = true;
300	if ( pCtxCore->cs.Attr.n.u1Long
301	&& CPUMIsGuestInLongMode(pVCpu))
302	{
303	fCheckLimit = false;
304	switch (SelReg)
305	{
306	case DISSELREG_FS:
307	case DISSELREG_GS:
308	pvFlat = pSReg->u64Base + Addr;
309	break;
310
311	default:
312	pvFlat = Addr;
313	break;
314	}
315	}
316	else
317	{
318	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
319	Assert(pSReg->u64Base <= UINT32_C(0xffffffff));
320	pvFlat = (uint32_t)pSReg->u64Base + (uint32_t)Addr;
321	Assert(pvFlat <= UINT32_MAX);
322	}
323
324	/*
325	* Check type if present.
326	*/
327	if (pSReg->Attr.n.u1Present)
328	{
329	switch (pSReg->Attr.n.u4Type)
330	{
331	/* Read only selector type. */
332	case X86_SEL_TYPE_RO:
333	case X86_SEL_TYPE_RO_ACC:
334	case X86_SEL_TYPE_RW:
335	case X86_SEL_TYPE_RW_ACC:
336	case X86_SEL_TYPE_EO:
337	case X86_SEL_TYPE_EO_ACC:
338	case X86_SEL_TYPE_ER:
339	case X86_SEL_TYPE_ER_ACC:
340	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
341	{
342	/** @todo fix this mess */
343	}
344	/* check limit. */
345	if (fCheckLimit && Addr > pSReg->u32Limit)
346	return VERR_OUT_OF_SELECTOR_BOUNDS;
347	/* ok */
348	if (ppvGC)
349	*ppvGC = pvFlat;
350	return VINF_SUCCESS;
351
352	case X86_SEL_TYPE_EO_CONF:
353	case X86_SEL_TYPE_EO_CONF_ACC:
354	case X86_SEL_TYPE_ER_CONF:
355	case X86_SEL_TYPE_ER_CONF_ACC:
356	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
357	{
358	/** @todo fix this mess */
359	}
360	/* check limit. */
361	if (fCheckLimit && Addr > pSReg->u32Limit)
362	return VERR_OUT_OF_SELECTOR_BOUNDS;
363	/* ok */
364	if (ppvGC)
365	*ppvGC = pvFlat;
366	return VINF_SUCCESS;
367
368	case X86_SEL_TYPE_RO_DOWN:
369	case X86_SEL_TYPE_RO_DOWN_ACC:
370	case X86_SEL_TYPE_RW_DOWN:
371	case X86_SEL_TYPE_RW_DOWN_ACC:
372	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
373	{
374	/** @todo fix this mess */
375	}
376	/* check limit. */
377	if (fCheckLimit)
378	{
379	if (!pSReg->Attr.n.u1Granularity && Addr > UINT32_C(0xffff))
380	return VERR_OUT_OF_SELECTOR_BOUNDS;
381	if (Addr <= pSReg->u32Limit)
382	return VERR_OUT_OF_SELECTOR_BOUNDS;
383	}
384	/* ok */
385	if (ppvGC)
386	*ppvGC = pvFlat;
387	return VINF_SUCCESS;
388
389	default:
390	return VERR_INVALID_SELECTOR;
391
392	}
393	}
394	return VERR_SELECTOR_NOT_PRESENT;
395	}
396
397
398	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
399	/**
400	* Converts a GC selector based address to a flat address.
401	*
402	* Some basic checking is done, but not all kinds yet.
403	*
404	* @returns VBox status
405	* @param pVCpu The cross context virtual CPU structure.
406	* @param eflags Current eflags
407	* @param Sel Selector part.
408	* @param Addr Address part.
409	* @param fFlags SELMTOFLAT_FLAGS_*
410	* GDT entires are valid.
411	* @param ppvGC Where to store the GC flat address.
412	* @param pcb Where to store the bytes from *ppvGC which can be accessed according to
413	* the selector. NULL is allowed.
414	* @remarks Don't use when in long mode.
415	*/
416	VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr,
417	uint32_t fFlags, PRTGCPTR ppvGC, uint32_t *pcb)
418	{
419	Assert(!CPUMIsGuestInLongMode(pVCpu)); /* DON'T USE! (Accessing shadow GDT/LDT.) */
420	Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
421
422	/*
423	* Deal with real & v86 mode first.
424	*/
425	if ( eflags.Bits.u1VM
426	\|\| CPUMIsGuestInRealMode(pVCpu))
427	{
428	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
429	if (ppvGC)
430	*ppvGC = ((RTGCUINTPTR)Sel << 4) + uFlat;
431	if (pcb)
432	*pcb = 0x10000 - uFlat;
433	return VINF_SUCCESS;
434	}
435
436	/** @todo when we're in 16 bits mode, we should cut off the address as well?? */
437	X86DESC Desc;
438	PVM pVM = pVCpu->CTX_SUFF(pVM);
439	if (!(Sel & X86_SEL_LDT))
440	{
441	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
442	&& (Sel \| X86_SEL_RPL_LDT) > pVM->selm.s.GuestGdtr.cbGdt)
443	return VERR_INVALID_SELECTOR;
444	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
445	}
446	else
447	{
448	if ((Sel \| X86_SEL_RPL_LDT) > pVM->selm.s.cbLdtLimit)
449	return VERR_INVALID_SELECTOR;
450
451	/** @todo handle LDT page(s) not present! */
452	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
453	Desc = paLDT[Sel >> X86_SEL_SHIFT];
454	}
455
456	/* calc limit. */
457	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
458
459	/* calc address assuming straight stuff. */
460	RTGCPTR pvFlat = Addr + X86DESC_BASE(&Desc);
461
462	/* Cut the address to 32 bits. */
463	Assert(!CPUMIsGuestInLongMode(pVCpu));
464	pvFlat &= 0xffffffff;
465
466	uint8_t u1Present = Desc.Gen.u1Present;
467	uint8_t u1Granularity = Desc.Gen.u1Granularity;
468	uint8_t u1DescType = Desc.Gen.u1DescType;
469	uint8_t u4Type = Desc.Gen.u4Type;
470
471	/*
472	* Check if present.
473	*/
474	if (u1Present)
475	{
476	/*
477	* Type check.
478	*/
479	#define BOTH(a, b) ((a << 16) \| b)
480	switch (BOTH(u1DescType, u4Type))
481	{
482
483	/** Read only selector type. */
484	case BOTH(1,X86_SEL_TYPE_RO):
485	case BOTH(1,X86_SEL_TYPE_RO_ACC):
486	case BOTH(1,X86_SEL_TYPE_RW):
487	case BOTH(1,X86_SEL_TYPE_RW_ACC):
488	case BOTH(1,X86_SEL_TYPE_EO):
489	case BOTH(1,X86_SEL_TYPE_EO_ACC):
490	case BOTH(1,X86_SEL_TYPE_ER):
491	case BOTH(1,X86_SEL_TYPE_ER_ACC):
492	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
493	{
494	/** @todo fix this mess */
495	}
496	/* check limit. */
497	if ((RTGCUINTPTR)Addr > u32Limit)
498	return VERR_OUT_OF_SELECTOR_BOUNDS;
499	/* ok */
500	if (ppvGC)
501	*ppvGC = pvFlat;
502	if (pcb)
503	*pcb = u32Limit - (uint32_t)Addr + 1;
504	return VINF_SUCCESS;
505
506	case BOTH(1,X86_SEL_TYPE_EO_CONF):
507	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
508	case BOTH(1,X86_SEL_TYPE_ER_CONF):
509	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
510	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
511	{
512	/** @todo fix this mess */
513	}
514	/* check limit. */
515	if ((RTGCUINTPTR)Addr > u32Limit)
516	return VERR_OUT_OF_SELECTOR_BOUNDS;
517	/* ok */
518	if (ppvGC)
519	*ppvGC = pvFlat;
520	if (pcb)
521	*pcb = u32Limit - (uint32_t)Addr + 1;
522	return VINF_SUCCESS;
523
524	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
525	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
526	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
527	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
528	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
529	{
530	/** @todo fix this mess */
531	}
532	/* check limit. */
533	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
534	return VERR_OUT_OF_SELECTOR_BOUNDS;
535	if ((RTGCUINTPTR)Addr <= u32Limit)
536	return VERR_OUT_OF_SELECTOR_BOUNDS;
537
538	/* ok */
539	if (ppvGC)
540	*ppvGC = pvFlat;
541	if (pcb)
542	*pcb = (RTGCUINTPTR)(u1Granularity ? 0xffffffff : 0xffff) - (RTGCUINTPTR)Addr + 1;
543	return VINF_SUCCESS;
544
545	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
546	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
547	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
548	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
549	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
550	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
551	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
552	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
553	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
554	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
555	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
556	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
557	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
558	{
559	/** @todo fix this mess */
560	}
561	/* check limit. */
562	if ((RTGCUINTPTR)Addr > u32Limit)
563	return VERR_OUT_OF_SELECTOR_BOUNDS;
564	/* ok */
565	if (ppvGC)
566	*ppvGC = pvFlat;
567	if (pcb)
568	pcb = 0xffffffff - (RTGCUINTPTR)pvFlat + 1; / Depends on the type.. fixme if we care. */
569	return VINF_SUCCESS;
570
571	default:
572	return VERR_INVALID_SELECTOR;
573
574	}
575	#undef BOTH
576	}
577	return VERR_SELECTOR_NOT_PRESENT;
578	}
579	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
580
581
582	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
583
584	static void selLoadHiddenSelectorRegFromGuestTable(PVMCPU pVCpu, PCCPUMCTX pCtx, PCPUMSELREG pSReg,
585	RTGCPTR GCPtrDesc, RTSEL const Sel, uint32_t const iSReg)
586	{
587	Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
588
589	/*
590	* Try read the entry.
591	*/
592	X86DESC GstDesc;
593	VBOXSTRICTRC rcStrict = PGMPhysReadGCPtr(pVCpu, &GstDesc, GCPtrDesc, sizeof(GstDesc), PGMACCESSORIGIN_SELM);
594	if (rcStrict == VINF_SUCCESS)
595	{
596	/*
597	* Validate it and load it.
598	*/
599	if (selmIsGstDescGoodForSReg(pVCpu, pSReg, &GstDesc, iSReg, CPUMGetGuestCPL(pVCpu)))
600	{
601	selmLoadHiddenSRegFromGuestDesc(pVCpu, pSReg, &GstDesc);
602	Log(("SELMLoadHiddenSelectorReg: loaded %s=%#x:{b=%llx, l=%x, a=%x, vs=%x} (gst)\n",
603	g_aszSRegNms[iSReg], Sel, pSReg->u64Base, pSReg->u32Limit, pSReg->Attr.u, pSReg->ValidSel));
604	STAM_COUNTER_INC(&pVCpu->CTX_SUFF(pVM)->selm.s.StatLoadHidSelGst);
605	}
606	else
607	{
608	Log(("SELMLoadHiddenSelectorReg: Guest table entry is no good (%s=%#x): %.8Rhxs\n", g_aszSRegNms[iSReg], Sel, &GstDesc));
609	STAM_REL_COUNTER_INC(&pVCpu->CTX_SUFF(pVM)->selm.s.StatLoadHidSelGstNoGood);
610	}
611	}
612	else
613	{
614	AssertMsg(RT_FAILURE_NP(rcStrict), ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
615	Log(("SELMLoadHiddenSelectorReg: Error reading descriptor %s=%#x: %Rrc\n",
616	g_aszSRegNms[iSReg], Sel, VBOXSTRICTRC_VAL(rcStrict) ));
617	STAM_REL_COUNTER_INC(&pVCpu->CTX_SUFF(pVM)->selm.s.StatLoadHidSelReadErrors);
618	}
619	}
620
621
622	/**
623	* CPUM helper that loads the hidden selector register from the descriptor table
624	* when executing with raw-mode.
625	*
626	* @remarks This is only used when in legacy protected mode!
627	*
628	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
629	* @param pCtx The guest CPU context.
630	* @param pSReg The selector register.
631	*
632	* @todo Deal 100% correctly with stale selectors. What's more evil is
633	* invalid page table entries, which isn't impossible to imagine for
634	* LDT entries for instance, though unlikely. Currently, we turn a
635	* blind eye to these issues and return the old hidden registers,
636	* though we don't set the valid flag, so that we'll try loading them
637	* over and over again till we succeed loading something.
638	*/
639	VMM_INT_DECL(void) SELMLoadHiddenSelectorReg(PVMCPU pVCpu, PCCPUMCTX pCtx, PCPUMSELREG pSReg)
640	{
641	Assert(pCtx->cr0 & X86_CR0_PE);
642	Assert(!(pCtx->msrEFER & MSR_K6_EFER_LMA));
643
644	PVM pVM = pVCpu->CTX_SUFF(pVM);
645	Assert(pVM->cCpus == 1);
646	Assert(!HMIsEnabled(pVM));
647
648
649	/*
650	* Get the shadow descriptor table entry and validate it.
651	* Should something go amiss, try the guest table.
652	*/
653	RTSEL const Sel = pSReg->Sel;
654	uint32_t const iSReg = pSReg - CPUMCTX_FIRST_SREG(pCtx); Assert(iSReg < X86_SREG_COUNT);
655	PCX86DESC pShwDesc;
656	if (!(Sel & X86_SEL_LDT))
657	{
658	/** @todo this shall not happen, we shall check for these things when executing
659	* LGDT */
660	AssertReturnVoid((Sel \| X86_SEL_RPL \| X86_SEL_LDT) <= pCtx->gdtr.cbGdt);
661
662	pShwDesc = &pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
663	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT)
664	\|\| !selmIsShwDescGoodForSReg(pSReg, pShwDesc, iSReg, CPUMGetGuestCPL(pVCpu)))
665	{
666	selLoadHiddenSelectorRegFromGuestTable(pVCpu, pCtx, pSReg, pCtx->gdtr.pGdt + (Sel & X86_SEL_MASK), Sel, iSReg);
667	return;
668	}
669	}
670	else
671	{
672	/** @todo this shall not happen, we shall check for these things when executing
673	* LLDT */
674	AssertReturnVoid((Sel \| X86_SEL_RPL \| X86_SEL_LDT) <= pCtx->ldtr.u32Limit);
675
676	pShwDesc = (PCX86DESC)((uintptr_t)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper + (Sel & X86_SEL_MASK));
677	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT)
678	\|\| !selmIsShwDescGoodForSReg(pSReg, pShwDesc, iSReg, CPUMGetGuestCPL(pVCpu)))
679	{
680	selLoadHiddenSelectorRegFromGuestTable(pVCpu, pCtx, pSReg, pCtx->ldtr.u64Base + (Sel & X86_SEL_MASK), Sel, iSReg);
681	return;
682	}
683	}
684
685	/*
686	* All fine, load it.
687	*/
688	selmLoadHiddenSRegFromShadowDesc(pSReg, pShwDesc);
689	STAM_COUNTER_INC(&pVCpu->CTX_SUFF(pVM)->selm.s.StatLoadHidSelShw);
690	Log(("SELMLoadHiddenSelectorReg: loaded %s=%#x:{b=%llx, l=%x, a=%x, vs=%x} (shw)\n",
691	g_aszSRegNms[iSReg], Sel, pSReg->u64Base, pSReg->u32Limit, pSReg->Attr.u, pSReg->ValidSel));
692	}
693
694	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
695
696	/**
697	* Validates and converts a GC selector based code address to a flat
698	* address when in real or v8086 mode.
699	*
700	* @returns VINF_SUCCESS.
701	* @param pVCpu The cross context virtual CPU structure.
702	* @param SelCS Selector part.
703	* @param pSReg The hidden CS register part. Optional.
704	* @param Addr Address part.
705	* @param ppvFlat Where to store the flat address.
706	*/
707	DECLINLINE(int) selmValidateAndConvertCSAddrRealMode(PVMCPU pVCpu, RTSEL SelCS, PCCPUMSELREGHID pSReg, RTGCPTR Addr,
708	PRTGCPTR ppvFlat)
709	{
710	NOREF(pVCpu);
711	uint32_t uFlat = Addr & 0xffff;
712	if (!pSReg \|\| !CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
713	uFlat += (uint32_t)SelCS << 4;
714	else
715	uFlat += (uint32_t)pSReg->u64Base;
716	*ppvFlat = uFlat;
717	return VINF_SUCCESS;
718	}
719
720
721	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
722	/**
723	* Validates and converts a GC selector based code address to a flat address
724	* when in protected/long mode using the raw-mode algorithm.
725	*
726	* @returns VBox status code.
727	* @param pVM The cross context VM structure.
728	* @param pVCpu The cross context virtual CPU structure.
729	* @param SelCPL Current privilege level. Get this from SS - CS might be
730	* conforming! A full selector can be passed, we'll only
731	* use the RPL part.
732	* @param SelCS Selector part.
733	* @param Addr Address part.
734	* @param ppvFlat Where to store the flat address.
735	* @param pcBits Where to store the segment bitness (16/32/64). Optional.
736	*/
737	DECLINLINE(int) selmValidateAndConvertCSAddrRawMode(PVM pVM, PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr,
738	PRTGCPTR ppvFlat, uint32_t *pcBits)
739	{
740	NOREF(pVCpu);
741	Assert(!HMIsEnabled(pVM));
742
743	/** @todo validate limit! */
744	X86DESC Desc;
745	if (!(SelCS & X86_SEL_LDT))
746	Desc = pVM->selm.s.CTX_SUFF(paGdt)[SelCS >> X86_SEL_SHIFT];
747	else
748	{
749	/** @todo handle LDT page(s) not present! */
750	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
751	Desc = paLDT[SelCS >> X86_SEL_SHIFT];
752	}
753
754	/*
755	* Check if present.
756	*/
757	if (Desc.Gen.u1Present)
758	{
759	/*
760	* Type check.
761	*/
762	if ( Desc.Gen.u1DescType == 1
763	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
764	{
765	/*
766	* Check level.
767	*/
768	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
769	if ( !(Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
770	? uLevel <= Desc.Gen.u2Dpl
771	: uLevel >= Desc.Gen.u2Dpl /* hope I got this right now... */
772	)
773	{
774	/*
775	* Limit check.
776	*/
777	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
778	if ((RTGCUINTPTR)Addr <= u32Limit)
779	{
780	*ppvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(&Desc));
781	/* Cut the address to 32 bits. */
782	*ppvFlat &= 0xffffffff;
783
784	if (pcBits)
785	pcBits = Desc.Gen.u1DefBig ? 32 : 16; /* @todo GUEST64 */
786	return VINF_SUCCESS;
787	}
788	return VERR_OUT_OF_SELECTOR_BOUNDS;
789	}
790	return VERR_INVALID_RPL;
791	}
792	return VERR_NOT_CODE_SELECTOR;
793	}
794	return VERR_SELECTOR_NOT_PRESENT;
795	}
796	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
797
798
799	/**
800	* Validates and converts a GC selector based code address to a flat address
801	* when in protected/long mode using the standard hidden selector registers
802	*
803	* @returns VBox status code.
804	* @param pVCpu The cross context virtual CPU structure.
805	* @param SelCPL Current privilege level. Get this from SS - CS might be
806	* conforming! A full selector can be passed, we'll only
807	* use the RPL part.
808	* @param SelCS Selector part.
809	* @param pSRegCS The full CS selector register.
810	* @param Addr The address (think IP/EIP/RIP).
811	* @param ppvFlat Where to store the flat address upon successful return.
812	*/
813	DECLINLINE(int) selmValidateAndConvertCSAddrHidden(PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pSRegCS,
814	RTGCPTR Addr, PRTGCPTR ppvFlat)
815	{
816	NOREF(SelCPL); NOREF(SelCS);
817
818	/*
819	* Check if present.
820	*/
821	if (pSRegCS->Attr.n.u1Present)
822	{
823	/*
824	* Type check.
825	*/
826	if ( pSRegCS->Attr.n.u1DescType == 1
827	&& (pSRegCS->Attr.n.u4Type & X86_SEL_TYPE_CODE))
828	{
829	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
830	(Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
831	if ( pSRegCS->Attr.n.u1Long
832	&& CPUMIsGuestInLongMode(pVCpu))
833	{
834	*ppvFlat = Addr;
835	return VINF_SUCCESS;
836	}
837
838	/*
839	* Limit check. Note that the limit in the hidden register is the
840	* final value. The granularity bit was included in its calculation.
841	*/
842	uint32_t u32Limit = pSRegCS->u32Limit;
843	if ((uint32_t)Addr <= u32Limit)
844	{
845	*ppvFlat = (uint32_t)Addr + (uint32_t)pSRegCS->u64Base;
846	return VINF_SUCCESS;
847	}
848
849	return VERR_OUT_OF_SELECTOR_BOUNDS;
850	}
851	return VERR_NOT_CODE_SELECTOR;
852	}
853	return VERR_SELECTOR_NOT_PRESENT;
854	}
855
856
857	/**
858	* Validates and converts a GC selector based code address to a flat address.
859	*
860	* @returns VBox status code.
861	* @param pVCpu The cross context virtual CPU structure.
862	* @param Efl Current EFLAGS.
863	* @param SelCPL Current privilege level. Get this from SS - CS might be
864	* conforming! A full selector can be passed, we'll only
865	* use the RPL part.
866	* @param SelCS Selector part.
867	* @param pSRegCS The full CS selector register.
868	* @param Addr The address (think IP/EIP/RIP).
869	* @param ppvFlat Where to store the flat address upon successful return.
870	*/
871	VMMDECL(int) SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS Efl, RTSEL SelCPL, RTSEL SelCS, PCPUMSELREG pSRegCS,
872	RTGCPTR Addr, PRTGCPTR ppvFlat)
873	{
874	if ( Efl.Bits.u1VM
875	\|\| CPUMIsGuestInRealMode(pVCpu))
876	return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, pSRegCS, Addr, ppvFlat);
877
878	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
879	/* Use the hidden registers when possible, updating them if outdate. */
880	if (!pSRegCS)
881	return selmValidateAndConvertCSAddrRawMode(pVCpu->CTX_SUFF(pVM), pVCpu, SelCPL, SelCS, Addr, ppvFlat, NULL);
882
883	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
884	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSRegCS);
885
886	/* Undo ring compression. */
887	if ((SelCPL & X86_SEL_RPL) == 1 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
888	SelCPL &= ~X86_SEL_RPL;
889	Assert(pSRegCS->Sel == SelCS);
890	if ((SelCS & X86_SEL_RPL) == 1 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
891	SelCS &= ~X86_SEL_RPL;
892	#else
893	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS));
894	Assert(pSRegCS->Sel == SelCS);
895	#endif
896
897	return selmValidateAndConvertCSAddrHidden(pVCpu, SelCPL, SelCS, pSRegCS, Addr, ppvFlat);
898	}
899
900
901	/**
902	* Returns Hypervisor's Trap 08 (\#DF) selector.
903	*
904	* @returns Hypervisor's Trap 08 (\#DF) selector.
905	* @param pVM The cross context VM structure.
906	*/
907	VMMDECL(RTSEL) SELMGetTrap8Selector(PVM pVM)
908	{
909	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
910	}
911
912
913	/**
914	* Sets EIP of Hypervisor's Trap 08 (\#DF) TSS.
915	*
916	* @param pVM The cross context VM structure.
917	* @param u32EIP EIP of Trap 08 handler.
918	*/
919	VMMDECL(void) SELMSetTrap8EIP(PVM pVM, uint32_t u32EIP)
920	{
921	pVM->selm.s.TssTrap08.eip = u32EIP;
922	}
923
924
925	/**
926	* Sets ss:esp for ring1 in main Hypervisor's TSS.
927	*
928	* @param pVM The cross context VM structure.
929	* @param ss Ring1 SS register value. Pass 0 if invalid.
930	* @param esp Ring1 ESP register value.
931	*/
932	void selmSetRing1Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
933	{
934	Assert(!HMIsEnabled(pVM));
935	Assert((ss & 1) \|\| esp == 0);
936	pVM->selm.s.Tss.ss1 = ss;
937	pVM->selm.s.Tss.esp1 = (uint32_t)esp;
938	}
939
940
941	#ifdef VBOX_WITH_RAW_RING1
942	/**
943	* Sets ss:esp for ring1 in main Hypervisor's TSS.
944	*
945	* @param pVM The cross context VM structure.
946	* @param ss Ring2 SS register value. Pass 0 if invalid.
947	* @param esp Ring2 ESP register value.
948	*/
949	void selmSetRing2Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
950	{
951	Assert(!HMIsEnabled(pVM));
952	Assert((ss & 3) == 2 \|\| esp == 0);
953	pVM->selm.s.Tss.ss2 = ss;
954	pVM->selm.s.Tss.esp2 = (uint32_t)esp;
955	}
956	#endif
957
958
959	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
960	/**
961	* Gets ss:esp for ring1 in main Hypervisor's TSS.
962	*
963	* Returns SS=0 if the ring-1 stack isn't valid.
964	*
965	* @returns VBox status code.
966	* @param pVM The cross context VM structure.
967	* @param pSS Ring1 SS register value.
968	* @param pEsp Ring1 ESP register value.
969	*/
970	VMMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t *pSS, PRTGCPTR32 pEsp)
971	{
972	Assert(!HMIsEnabled(pVM));
973	Assert(pVM->cCpus == 1);
974	PVMCPU pVCpu = &pVM->aCpus[0];
975
976	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
977	if (pVM->selm.s.fSyncTSSRing0Stack)
978	{
979	#endif
980	RTGCPTR GCPtrTss = pVM->selm.s.GCPtrGuestTss;
981	int rc;
982	VBOXTSS tss;
983
984	Assert(pVM->selm.s.GCPtrGuestTss && pVM->selm.s.cbMonitoredGuestTss);
985
986	# ifdef IN_RC
987	bool fTriedAlready = false;
988
989	l_tryagain:
990	PVBOXTSS pTss = (PVBOXTSS)(uintptr_t)GCPtrTss;
991	rc = MMGCRamRead(pVM, &tss.ss0, &pTss->ss0, sizeof(tss.ss0));
992	rc \|= MMGCRamRead(pVM, &tss.esp0, &pTss->esp0, sizeof(tss.esp0));
993	# ifdef DEBUG
994	rc \|= MMGCRamRead(pVM, &tss.offIoBitmap, &pTss->offIoBitmap, sizeof(tss.offIoBitmap));
995	# endif
996
997	if (RT_FAILURE(rc))
998	{
999	if (!fTriedAlready)
1000	{
1001	/* Shadow page might be out of sync. Sync and try again */
1002	/** @todo might cross page boundary */
1003	fTriedAlready = true;
1004	rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPtrTss);
1005	if (rc != VINF_SUCCESS)
1006	return rc;
1007	goto l_tryagain;
1008	}
1009	AssertMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1010	return rc;
1011	}
1012
1013	# else /* !IN_RC */
1014	/* Reading too much. Could be cheaper than two separate calls though. */
1015	rc = PGMPhysSimpleReadGCPtr(pVCpu, &tss, GCPtrTss, sizeof(VBOXTSS));
1016	if (RT_FAILURE(rc))
1017	{
1018	AssertReleaseMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1019	return rc;
1020	}
1021	# endif /* !IN_RC */
1022
1023	# ifdef LOG_ENABLED
1024	uint32_t ssr0 = pVM->selm.s.Tss.ss1;
1025	uint32_t espr0 = pVM->selm.s.Tss.esp1;
1026	ssr0 &= ~1;
1027
1028	if (ssr0 != tss.ss0 \|\| espr0 != tss.esp0)
1029	Log(("SELMGetRing1Stack: Updating TSS ring 0 stack to %04X:%08X\n", tss.ss0, tss.esp0));
1030
1031	Log(("offIoBitmap=%#x\n", tss.offIoBitmap));
1032	# endif
1033	/* Update our TSS structure for the guest's ring 1 stack */
1034	selmSetRing1Stack(pVM, tss.ss0 \| 1, (RTGCPTR32)tss.esp0);
1035	pVM->selm.s.fSyncTSSRing0Stack = false;
1036	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
1037	}
1038	#endif
1039
1040	*pSS = pVM->selm.s.Tss.ss1;
1041	*pEsp = (RTGCPTR32)pVM->selm.s.Tss.esp1;
1042
1043	return VINF_SUCCESS;
1044	}
1045	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
1046
1047
1048	#if defined(VBOX_WITH_RAW_MODE) \|\| (HC_ARCH_BITS != 64 && defined(VBOX_WITH_64_BITS_GUESTS))
1049
1050	/**
1051	* Gets the hypervisor code selector (CS).
1052	* @returns CS selector.
1053	* @param pVM The cross context VM structure.
1054	*/
1055	VMMDECL(RTSEL) SELMGetHyperCS(PVM pVM)
1056	{
1057	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
1058	}
1059
1060
1061	/**
1062	* Gets the 64-mode hypervisor code selector (CS64).
1063	* @returns CS selector.
1064	* @param pVM The cross context VM structure.
1065	*/
1066	VMMDECL(RTSEL) SELMGetHyperCS64(PVM pVM)
1067	{
1068	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64];
1069	}
1070
1071
1072	/**
1073	* Gets the hypervisor data selector (DS).
1074	* @returns DS selector.
1075	* @param pVM The cross context VM structure.
1076	*/
1077	VMMDECL(RTSEL) SELMGetHyperDS(PVM pVM)
1078	{
1079	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
1080	}
1081
1082
1083	/**
1084	* Gets the hypervisor TSS selector.
1085	* @returns TSS selector.
1086	* @param pVM The cross context VM structure.
1087	*/
1088	VMMDECL(RTSEL) SELMGetHyperTSS(PVM pVM)
1089	{
1090	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS];
1091	}
1092
1093
1094	/**
1095	* Gets the hypervisor TSS Trap 8 selector.
1096	* @returns TSS Trap 8 selector.
1097	* @param pVM The cross context VM structure.
1098	*/
1099	VMMDECL(RTSEL) SELMGetHyperTSSTrap08(PVM pVM)
1100	{
1101	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1102	}
1103
1104	/**
1105	* Gets the address for the hypervisor GDT.
1106	*
1107	* @returns The GDT address.
1108	* @param pVM The cross context VM structure.
1109	* @remark This is intended only for very special use, like in the world
1110	* switchers. Don't exploit this API!
1111	*/
1112	VMMDECL(RTRCPTR) SELMGetHyperGDT(PVM pVM)
1113	{
1114	/*
1115	* Always convert this from the HC pointer since we can be
1116	* called before the first relocation and have to work correctly
1117	* without having dependencies on the relocation order.
1118	*/
1119	return (RTRCPTR)MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3);
1120	}
1121
1122	#endif /* defined(VBOX_WITH_RAW_MODE) \|\| (HC_ARCH_BITS != 64 && defined(VBOX_WITH_64_BITS_GUESTS)) */
1123
1124	/**
1125	* Gets info about the current TSS.
1126	*
1127	* @returns VBox status code.
1128	* @retval VINF_SUCCESS if we've got a TSS loaded.
1129	* @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
1130	*
1131	* @param pVM The cross context VM structure.
1132	* @param pVCpu The cross context virtual CPU structure.
1133	* @param pGCPtrTss Where to store the TSS address.
1134	* @param pcbTss Where to store the TSS size limit.
1135	* @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
1136	*/
1137	VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
1138	{
1139	NOREF(pVM);
1140
1141	/*
1142	* The TR hidden register is always valid.
1143	*/
1144	CPUMSELREGHID trHid;
1145	RTSEL tr = CPUMGetGuestTR(pVCpu, &trHid);
1146	if (!(tr & X86_SEL_MASK_OFF_RPL))
1147	return VERR_SELM_NO_TSS;
1148
1149	*pGCPtrTss = trHid.u64Base;
1150	pcbTss = trHid.u32Limit + (trHid.u32Limit != UINT32_MAX); / be careful. */
1151	if (pfCanHaveIOBitmap)
1152	*pfCanHaveIOBitmap = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1153	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1154	return VINF_SUCCESS;
1155	}
1156
1157
1158
1159	/**
1160	* Notification callback which is called whenever there is a chance that a CR3
1161	* value might have changed.
1162	* This is called by PGM.
1163	*
1164	* @param pVM The cross context VM structure.
1165	* @param pVCpu The cross context virtual CPU structure.
1166	*/
1167	VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu)
1168	{
1169	/** @todo SMP support!! (64-bit guest scenario, primarily) */
1170	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
1171	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu);
1172	}
1173

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source: vbox/trunk/src/VBox/VMM/VMMAll/SELMAll.cpp@ 59710

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