SELMAll.cpp@ 3696

Last change on this file since 3696 was 2981, checked in by vboxsync, 17 years ago
InnoTek -> innotek: all the headers and comments.
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1	/* $Id: SELMAll.cpp 2981 2007-06-01 16:01:28Z vboxsync $ */
2	/** @file
3	* SELM All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_SELM
27	#include <VBox/selm.h>
28	#include <VBox/stam.h>
29	#include <VBox/mm.h>
30	#include <VBox/pgm.h>
31	#include "SELMInternal.h"
32	#include <VBox/vm.h>
33	#include <VBox/x86.h>
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36	#include <iprt/assert.h>
37	#include <VBox/log.h>
38
39
40
41	/**
42	* Converts a GC selector based address to a flat address.
43	*
44	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
45	* for that.
46	*
47	* @returns Flat address.
48	* @param pVM VM Handle.
49	* @param Sel Selector part.
50	* @param Addr Address part.
51	*/
52	static RTGCPTR selmToFlat(PVM pVM, RTSEL Sel, RTGCPTR Addr)
53	{
54	Assert(!CPUMAreHiddenSelRegsValid(pVM));
55
56	/** @todo check the limit. */
57	VBOXDESC Desc;
58	if (!(Sel & X86_SEL_LDT))
59	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
60	else
61	{
62	/** @todo handle LDT pages not present! */
63	#ifdef IN_GC
64	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
65	#else
66	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
67	#endif
68	Desc = paLDT[Sel >> X86_SEL_SHIFT];
69	}
70
71	return (RTGCPTR)( (RTGCUINTPTR)Addr
72	+ ( (Desc.Gen.u8BaseHigh2 << 24)
73	\| (Desc.Gen.u8BaseHigh1 << 16)
74	\| Desc.Gen.u16BaseLow));
75	}
76
77
78	/**
79	* Converts a GC selector based address to a flat address.
80	*
81	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
82	* for that.
83	*
84	* @returns Flat address.
85	* @param pVM VM Handle.
86	* @param eflags Current eflags
87	* @param Sel Selector part.
88	* @param pHiddenSel Hidden selector register
89	* @param Addr Address part.
90	*/
91	SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, X86EFLAGS eflags, RTSEL Sel, CPUMSELREGHID *pHiddenSel, RTGCPTR Addr)
92	{
93	Assert(pHiddenSel \|\| !CPUMAreHiddenSelRegsValid(pVM));
94
95	/*
96	* Deal with real & v86 mode first.
97	*/
98	if ( CPUMIsGuestInRealMode(pVM)
99	\|\| eflags.Bits.u1VM)
100	{
101	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
102
103	if (CPUMAreHiddenSelRegsValid(pVM))
104	uFlat += pHiddenSel->u32Base;
105	else
106	uFlat += ((RTGCUINTPTR)Sel << 4);
107	return (RTGCPTR)uFlat;
108	}
109
110	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
111	if (!CPUMAreHiddenSelRegsValid(pVM))
112	return selmToFlat(pVM, Sel, Addr);
113	return (RTGCPTR)(pHiddenSel->u32Base + (RTGCUINTPTR)Addr);
114	}
115
116
117	/**
118	* Converts a GC selector based address to a flat address.
119	*
120	* Some basic checking is done, but not all kinds yet.
121	*
122	* @returns VBox status
123	* @param pVM VM Handle.
124	* @param eflags Current eflags
125	* @param Sel Selector part.
126	* @param Addr Address part.
127	* @param pHiddenSel Hidden selector register (can be NULL)
128	* @param fFlags SELMTOFLAT_FLAGS_*
129	* GDT entires are valid.
130	* @param ppvGC Where to store the GC flat address.
131	* @param pcb Where to store the bytes from *ppvGC which can be accessed according to
132	* the selector. NULL is allowed.
133	*/
134	SELMDECL(int) SELMToFlatEx(PVM pVM, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, CPUMSELREGHID pHiddenSel, unsigned fFlags, PRTGCPTR ppvGC, uint32_t pcb)
135	{
136	/*
137	* Deal with real & v86 mode first.
138	*/
139	if ( CPUMIsGuestInRealMode(pVM)
140	\|\| eflags.Bits.u1VM)
141	{
142	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
143	if (ppvGC)
144	{
145	if ( pHiddenSel
146	&& CPUMAreHiddenSelRegsValid(pVM))
147	*ppvGC = (RTGCPTR)(pHiddenSel->u32Base + uFlat);
148	else
149	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
150	}
151	if (pcb)
152	*pcb = 0x10000 - uFlat;
153	return VINF_SUCCESS;
154	}
155
156
157	uint32_t u32Limit;
158	RTGCPTR pvFlat;
159	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
160
161	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
162	if ( pHiddenSel
163	&& CPUMAreHiddenSelRegsValid(pVM))
164	{
165	u1Present = pHiddenSel->Attr.n.u1Present;
166	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
167	u1DescType = pHiddenSel->Attr.n.u1DescType;
168	u4Type = pHiddenSel->Attr.n.u4Type;
169
170	u32Limit = pHiddenSel->u32Limit;
171	pvFlat = (RTGCPTR)(pHiddenSel->u32Base + (RTGCUINTPTR)Addr);
172	}
173	else
174	{
175	VBOXDESC Desc;
176
177	if (!(Sel & X86_SEL_LDT))
178	{
179	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
180	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
181	return VERR_INVALID_SELECTOR;
182	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
183	}
184	else
185	{
186	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
187	return VERR_INVALID_SELECTOR;
188
189	/** @todo handle LDT page(s) not present! */
190	#ifdef IN_GC
191	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
192	#else
193	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
194	#endif
195	Desc = paLDT[Sel >> X86_SEL_SHIFT];
196	}
197
198	/* calc limit. */
199	u32Limit = Desc.Gen.u4LimitHigh << 16 \| Desc.Gen.u16LimitLow;
200	if (Desc.Gen.u1Granularity)
201	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
202
203	/* calc address assuming straight stuff. */
204	pvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr
205	+ ( (Desc.Gen.u8BaseHigh2 << 24)
206	\| (Desc.Gen.u8BaseHigh1 << 16)
207	\| Desc.Gen.u16BaseLow )
208	);
209
210	u1Present = Desc.Gen.u1Present;
211	u1Granularity = Desc.Gen.u1Granularity;
212	u1DescType = Desc.Gen.u1DescType;
213	u4Type = Desc.Gen.u4Type;
214	}
215
216	/*
217	* Check if present.
218	*/
219	if (u1Present)
220	{
221	/*
222	* Type check.
223	*/
224	#define BOTH(a, b) ((a << 16) \| b)
225	switch (BOTH(u1DescType, u4Type))
226	{
227
228	/** Read only selector type. */
229	case BOTH(1,X86_SEL_TYPE_RO):
230	case BOTH(1,X86_SEL_TYPE_RO_ACC):
231	case BOTH(1,X86_SEL_TYPE_RW):
232	case BOTH(1,X86_SEL_TYPE_RW_ACC):
233	case BOTH(1,X86_SEL_TYPE_EO):
234	case BOTH(1,X86_SEL_TYPE_EO_ACC):
235	case BOTH(1,X86_SEL_TYPE_ER):
236	case BOTH(1,X86_SEL_TYPE_ER_ACC):
237	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
238	{
239	/** @todo fix this mess */
240	}
241	/* check limit. */
242	if ((RTGCUINTPTR)Addr > u32Limit)
243	return VERR_OUT_OF_SELECTOR_BOUNDS;
244	/* ok */
245	if (ppvGC)
246	*ppvGC = pvFlat;
247	if (pcb)
248	*pcb = u32Limit - (uint32_t)Addr + 1;
249	return VINF_SUCCESS;
250
251	case BOTH(1,X86_SEL_TYPE_EO_CONF):
252	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
253	case BOTH(1,X86_SEL_TYPE_ER_CONF):
254	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
255	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
256	{
257	/** @todo fix this mess */
258	}
259	/* check limit. */
260	if ((RTGCUINTPTR)Addr > u32Limit)
261	return VERR_OUT_OF_SELECTOR_BOUNDS;
262	/* ok */
263	if (ppvGC)
264	*ppvGC = pvFlat;
265	if (pcb)
266	*pcb = u32Limit - (uint32_t)Addr + 1;
267	return VINF_SUCCESS;
268
269	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
270	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
271	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
272	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
273	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
274	{
275	/** @todo fix this mess */
276	}
277	/* check limit. */
278	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
279	return VERR_OUT_OF_SELECTOR_BOUNDS;
280	if ((RTGCUINTPTR)Addr <= u32Limit)
281	return VERR_OUT_OF_SELECTOR_BOUNDS;
282
283	/* ok */
284	if (ppvGC)
285	*ppvGC = pvFlat;
286	if (pcb)
287	*pcb = (u1Granularity ? 0xffffffff : 0xffff) - (RTGCUINTPTR)Addr + 1;
288	return VINF_SUCCESS;
289
290	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
291	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
292	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
293	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
294	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
295	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
296	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
297	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
298	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
299	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
300	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
301	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
302	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
303	{
304	/** @todo fix this mess */
305	}
306	/* check limit. */
307	if ((RTGCUINTPTR)Addr > u32Limit)
308	return VERR_OUT_OF_SELECTOR_BOUNDS;
309	/* ok */
310	if (ppvGC)
311	*ppvGC = pvFlat;
312	if (pcb)
313	pcb = 0xffffffff - (RTGCUINTPTR)pvFlat + 1; / Depends on the type.. fixme if we care. */
314	return VINF_SUCCESS;
315
316	default:
317	return VERR_INVALID_SELECTOR;
318
319	}
320	#undef BOTH
321	}
322	return VERR_SELECTOR_NOT_PRESENT;
323	}
324
325
326	/**
327	* Validates and converts a GC selector based code address to a flat address.
328	*
329	* @returns Flat address.
330	* @param pVM VM Handle.
331	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
332	* A full selector can be passed, we'll only use the RPL part.
333	* @param SelCS Selector part.
334	* @param Addr Address part.
335	* @param ppvFlat Where to store the flat address.
336	*/
337	static int selmValidateAndConvertCSAddr(PVM pVM, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr, PRTGCPTR ppvFlat)
338	{
339	Assert(!CPUMAreHiddenSelRegsValid(pVM));
340
341	/** @todo validate limit! */
342	VBOXDESC Desc;
343	if (!(SelCS & X86_SEL_LDT))
344	Desc = pVM->selm.s.CTXSUFF(paGdt)[SelCS >> X86_SEL_SHIFT];
345	else
346	{
347	/** @todo handle LDT page(s) not present! */
348	#ifdef IN_GC
349	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
350	#else
351	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
352	#endif
353	Desc = paLDT[SelCS >> X86_SEL_SHIFT];
354	}
355
356	/*
357	* Check if present.
358	*/
359	if (Desc.Gen.u1Present)
360	{
361	/*
362	* Type check.
363	*/
364	if ( Desc.Gen.u1DescType == 1
365	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
366	{
367	/*
368	* Check level.
369	*/
370	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
371	if ( !(Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
372	? uLevel <= Desc.Gen.u2Dpl
373	: uLevel >= Desc.Gen.u2Dpl /* hope I got this right now... */
374	)
375	{
376	/*
377	* Limit check.
378	*/
379	uint32_t u32Limit = Desc.Gen.u4LimitHigh << 16 \| Desc.Gen.u16LimitLow;
380	if (Desc.Gen.u1Granularity)
381	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
382	if ((RTGCUINTPTR)Addr <= u32Limit)
383	{
384	if (ppvFlat)
385	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr
386	+ ( (Desc.Gen.u8BaseHigh2 << 24)
387	\| (Desc.Gen.u8BaseHigh1 << 16)
388	\| Desc.Gen.u16BaseLow)
389	);
390	return VINF_SUCCESS;
391	}
392	return VERR_OUT_OF_SELECTOR_BOUNDS;
393	}
394	return VERR_INVALID_RPL;
395	}
396	return VERR_NOT_CODE_SELECTOR;
397	}
398	return VERR_SELECTOR_NOT_PRESENT;
399	}
400
401
402	/**
403	* Validates and converts a GC selector based code address to a flat address.
404	*
405	* @returns Flat address.
406	* @param pVM VM Handle.
407	* @param eflags Current eflags
408	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
409	* A full selector can be passed, we'll only use the RPL part.
410	* @param SelCS Selector part.
411	* @param pHiddenSel The hidden CS selector register.
412	* @param Addr Address part.
413	* @param ppvFlat Where to store the flat address.
414	*/
415	SELMDECL(int) SELMValidateAndConvertCSAddr(PVM pVM, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, CPUMSELREGHID *pHiddenCSSel, RTGCPTR Addr, PRTGCPTR ppvFlat)
416	{
417	/*
418	* Deal with real & v86 mode first.
419	*/
420	if ( CPUMIsGuestInRealMode(pVM)
421	\|\| eflags.Bits.u1VM)
422	{
423	if (ppvFlat)
424	{
425	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
426
427	if (!CPUMAreHiddenSelRegsValid(pVM))
428	uFlat += ((RTGCUINTPTR)SelCS << 4);
429	else
430	uFlat += pHiddenCSSel->u32Base;
431
432	*ppvFlat = (RTGCPTR)uFlat;
433	}
434	return VINF_SUCCESS;
435	}
436
437	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
438
439	if (!CPUMAreHiddenSelRegsValid(pVM))
440	return selmValidateAndConvertCSAddr(pVM, SelCPL, SelCS, Addr, ppvFlat);
441
442	/*
443	* Check if present.
444	*/
445	if (pHiddenCSSel->Attr.n.u1Present)
446	{
447	/*
448	* Type check.
449	*/
450	if ( pHiddenCSSel->Attr.n.u1DescType == 1
451	&& (pHiddenCSSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
452	{
453	/*
454	* Check level.
455	*/
456	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
457	if ( !(pHiddenCSSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
458	? uLevel <= pHiddenCSSel->Attr.n.u2Dpl
459	: uLevel >= pHiddenCSSel->Attr.n.u2Dpl /* hope I got this right now... */
460	)
461	{
462	/*
463	* Limit check.
464	*/
465	uint32_t u32Limit = pHiddenCSSel->u32Limit;
466	/** @todo correct with hidden limit value?? */
467	if (pHiddenCSSel->Attr.n.u1Granularity)
468	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
469	if ((RTGCUINTPTR)Addr <= u32Limit)
470	{
471	if (ppvFlat)
472	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr + pHiddenCSSel->u32Base );
473
474	return VINF_SUCCESS;
475	}
476	return VERR_OUT_OF_SELECTOR_BOUNDS;
477	}
478	return VERR_INVALID_RPL;
479	}
480	return VERR_NOT_CODE_SELECTOR;
481	}
482	return VERR_SELECTOR_NOT_PRESENT;
483	}
484
485
486	/**
487	* Checks if a selector is 32-bit or 16-bit.
488	*
489	* @returns True if it is 32-bit.
490	* @returns False if it is 16-bit.
491	* @param pVM VM Handle.
492	* @param Sel The selector.
493	*/
494	static bool selmIsSelector32Bit(PVM pVM, RTSEL Sel)
495	{
496	Assert(!CPUMAreHiddenSelRegsValid(pVM));
497
498	/** @todo validate limit! */
499	VBOXDESC Desc;
500	if (!(Sel & X86_SEL_LDT))
501	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
502	else
503	{
504	/** @todo handle LDT page(s) not present! */
505	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.CTXMID(,PtrLdt) + pVM->selm.s.offLdtHyper);
506	Desc = paLDT[Sel >> X86_SEL_SHIFT];
507	}
508	return Desc.Gen.u1DefBig;
509	}
510
511
512	/**
513	* Checks if a selector is 32-bit or 16-bit.
514	*
515	* @returns True if it is 32-bit.
516	* @returns False if it is 16-bit.
517	* @param pVM VM Handle.
518	* @param eflags Current eflags register
519	* @param Sel The selector.
520	* @param pHiddenSel The hidden selector register.
521	*/
522	SELMDECL(bool) SELMIsSelector32Bit(PVM pVM, X86EFLAGS eflags, RTSEL Sel, CPUMSELREGHID *pHiddenSel)
523	{
524	if (!CPUMAreHiddenSelRegsValid(pVM))
525	{
526	/*
527	* Deal with real & v86 mode first.
528	*/
529	if ( CPUMIsGuestInRealMode(pVM)
530	\|\| eflags.Bits.u1VM)
531	return false;
532
533	return selmIsSelector32Bit(pVM, Sel);
534	}
535	return pHiddenSel->Attr.n.u1DefBig;
536	}
537
538
539	/**
540	* Returns Hypervisor's Trap 08 (\#DF) selector.
541	*
542	* @returns Hypervisor's Trap 08 (\#DF) selector.
543	* @param pVM VM Handle.
544	*/
545	SELMDECL(RTSEL) SELMGetTrap8Selector(PVM pVM)
546	{
547	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
548	}
549
550
551	/**
552	* Sets EIP of Hypervisor's Trap 08 (\#DF) TSS.
553	*
554	* @param pVM VM Handle.
555	* @param u32EIP EIP of Trap 08 handler.
556	*/
557	SELMDECL(void) SELMSetTrap8EIP(PVM pVM, uint32_t u32EIP)
558	{
559	pVM->selm.s.TssTrap08.eip = u32EIP;
560	}
561
562
563	/**
564	* Sets ss:esp for ring1 in main Hypervisor's TSS.
565	*
566	* @param pVM VM Handle.
567	* @param ss Ring1 SS register value.
568	* @param esp Ring1 ESP register value.
569	*/
570	SELMDECL(void) SELMSetRing1Stack(PVM pVM, uint32_t ss, uint32_t esp)
571	{
572	pVM->selm.s.Tss.ss1 = ss;
573	pVM->selm.s.Tss.esp1 = esp;
574	}
575
576
577	/**
578	* Gets ss:esp for ring1 in main Hypervisor's TSS.
579	*
580	* @returns VBox status code.
581	* @param pVM VM Handle.
582	* @param pSS Ring1 SS register value.
583	* @param pEsp Ring1 ESP register value.
584	*/
585	SELMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t pSS, uint32_t pEsp)
586	{
587	if (pVM->selm.s.fSyncTSSRing0Stack)
588	{
589	GCPTRTYPE(uint8_t ) GCPtrTss = (GCPTRTYPE(uint8_t ))pVM->selm.s.GCPtrGuestTss;
590	int rc;
591	VBOXTSS tss;
592
593	Assert(pVM->selm.s.GCPtrGuestTss && pVM->selm.s.cbMonitoredGuestTss);
594
595	#ifdef IN_GC
596	bool fTriedAlready = false;
597
598	l_tryagain:
599	rc = MMGCRamRead(pVM, &tss.ss0, GCPtrTss + RT_OFFSETOF(VBOXTSS, ss0), sizeof(tss.ss0));
600	rc \|= MMGCRamRead(pVM, &tss.esp0, GCPtrTss + RT_OFFSETOF(VBOXTSS, esp0), sizeof(tss.esp0));
601	#ifdef DEBUG
602	rc \|= MMGCRamRead(pVM, &tss.offIoBitmap, GCPtrTss + RT_OFFSETOF(VBOXTSS, offIoBitmap), sizeof(tss.offIoBitmap));
603	#endif
604
605	if (VBOX_FAILURE(rc))
606	{
607	if (!fTriedAlready)
608	{
609	/* Shadow page might be out of sync. Sync and try again */
610	/** @todo might cross page boundary */
611	fTriedAlready = true;
612	rc = PGMPrefetchPage(pVM, GCPtrTss);
613	if (rc != VINF_SUCCESS)
614	return rc;
615	goto l_tryagain;
616	}
617	AssertMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
618	return rc;
619	}
620
621	#else /* !IN_GC */
622	/* Reading too much. Could be cheaper than two seperate calls though. */
623	rc = PGMPhysReadGCPtr(pVM, &tss, GCPtrTss, sizeof(VBOXTSS));
624	if (VBOX_FAILURE(rc))
625	{
626	AssertReleaseMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
627	return rc;
628	}
629	#endif /* !IN_GC */
630
631	#ifdef LOG_ENABLED
632	uint32_t ssr0 = pVM->selm.s.Tss.ss1;
633	uint32_t espr0 = pVM->selm.s.Tss.esp1;
634	ssr0 &= ~1;
635
636	if (ssr0 != tss.ss0 \|\| espr0 != tss.esp0)
637	Log(("SELMGetRing1Stack: Updating TSS ring 0 stack to %04X:%08X\n", tss.ss0, tss.esp0));
638
639	Log(("offIoBitmap=%#x\n", tss.offIoBitmap));
640	#endif
641	/* Update our TSS structure for the guest's ring 1 stack */
642	SELMSetRing1Stack(pVM, tss.ss0 \| 1, tss.esp0);
643	pVM->selm.s.fSyncTSSRing0Stack = false;
644	}
645
646	*pSS = pVM->selm.s.Tss.ss1;
647	*pEsp = pVM->selm.s.Tss.esp1;
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Returns Guest TSS pointer
655	*
656	* @param pVM VM Handle.
657	*/
658	SELMDECL(RTGCPTR) SELMGetGuestTSS(PVM pVM)
659	{
660	return (RTGCPTR)pVM->selm.s.GCPtrGuestTss;
661	}
662
663
664	/**
665	* Validates a CS selector.
666	*
667	* @returns VBox status code.
668	* @param pSelInfo Pointer to the selector information for the CS selector.
669	* @param SelCPL The selector defining the CPL (SS).
670	*/
671	SELMDECL(int) SELMSelInfoValidateCS(PCSELMSELINFO pSelInfo, RTSEL SelCPL)
672	{
673	/*
674	* Check if present.
675	*/
676	if (pSelInfo->Raw.Gen.u1Present)
677	{
678	/*
679	* Type check.
680	*/
681	if ( pSelInfo->Raw.Gen.u1DescType == 1
682	&& (pSelInfo->Raw.Gen.u4Type & X86_SEL_TYPE_CODE))
683	{
684	/*
685	* Check level.
686	*/
687	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, pSelInfo->Sel & X86_SEL_RPL);
688	if ( !(pSelInfo->Raw.Gen.u4Type & X86_SEL_TYPE_CONF)
689	? uLevel <= pSelInfo->Raw.Gen.u2Dpl
690	: uLevel >= pSelInfo->Raw.Gen.u2Dpl /* hope I got this right now... */
691	)
692	return VINF_SUCCESS;
693	return VERR_INVALID_RPL;
694	}
695	return VERR_NOT_CODE_SELECTOR;
696	}
697	return VERR_SELECTOR_NOT_PRESENT;
698	}
699
700
701	/**
702	* Gets the hypervisor code selector (CS).
703	* @returns CS selector.
704	* @param pVM The VM handle.
705	*/
706	SELMDECL(RTSEL) SELMGetHyperCS(PVM pVM)
707	{
708	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
709	}
710
711
712	/**
713	* Gets the 64-mode hypervisor code selector (CS64).
714	* @returns CS selector.
715	* @param pVM The VM handle.
716	*/
717	SELMDECL(RTSEL) SELMGetHyperCS64(PVM pVM)
718	{
719	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64];
720	}
721
722
723	/**
724	* Gets the hypervisor data selector (DS).
725	* @returns DS selector.
726	* @param pVM The VM handle.
727	*/
728	SELMDECL(RTSEL) SELMGetHyperDS(PVM pVM)
729	{
730	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
731	}
732
733
734	/**
735	* Gets the hypervisor TSS selector.
736	* @returns TSS selector.
737	* @param pVM The VM handle.
738	*/
739	SELMDECL(RTSEL) SELMGetHyperTSS(PVM pVM)
740	{
741	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS];
742	}
743
744
745	/**
746	* Gets the hypervisor TSS Trap 8 selector.
747	* @returns TSS Trap 8 selector.
748	* @param pVM The VM handle.
749	*/
750	SELMDECL(RTSEL) SELMGetHyperTSSTrap08(PVM pVM)
751	{
752	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
753	}
754
755
756	/**
757	* Gets the address for the hypervisor GDT.
758	*
759	* @returns The GDT address.
760	* @param pVM The VM handle.
761	* @remark This is intended only for very special use, like in the world
762	* switchers. Don't exploit this API!
763	*/
764	SELMDECL(RTGCPTR) SELMGetHyperGDT(PVM pVM)
765	{
766	/*
767	* Always convert this from the HC pointer since. We're can be
768	* called before the first relocation and have to work correctly
769	* without having dependencies on the relocation order.
770	*/
771	return MMHyperHC2GC(pVM, pVM->selm.s.paGdtHC);
772	}
773
774
775	/**
776	* Gets info about the current TSS.
777	*
778	* @returns VBox status code.
779	* @retval VINF_SUCCESS if we've got a TSS loaded.
780	* @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
781	*
782	* @param pVM The VM handle.
783	* @param pGCPtrTss Where to store the TSS address.
784	* @param pcbTss Where to store the TSS size limit.
785	* @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
786	*/
787	SELMDECL(int) SELMGetTSSInfo(PVM pVM, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
788	{
789	if (!CPUMAreHiddenSelRegsValid(pVM))
790	{
791	/*
792	* Do we have a valid TSS?
793	*/
794	if ( pVM->selm.s.GCSelTss == (RTSEL)~0
795	\|\| !pVM->selm.s.fGuestTss32Bit)
796	return VERR_SELM_NO_TSS;
797
798	/*
799	* Fill in return values.
800	*/
801	*pGCPtrTss = (RTGCUINTPTR)pVM->selm.s.GCPtrGuestTss;
802	*pcbTss = pVM->selm.s.cbGuestTss;
803	if (pfCanHaveIOBitmap)
804	*pfCanHaveIOBitmap = pVM->selm.s.fGuestTss32Bit;
805	}
806	else
807	{
808	CPUMSELREGHID *pHiddenTRReg;
809
810	pHiddenTRReg = CPUMGetGuestTRHid(pVM);
811
812	*pGCPtrTss = pHiddenTRReg->u32Base;
813	*pcbTss = pHiddenTRReg->u32Limit;
814
815	if (pfCanHaveIOBitmap)
816	*pfCanHaveIOBitmap = pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
817	\|\| pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
818	}
819	return VINF_SUCCESS;
820	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/SELMAll.cpp@ 3696

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