PGMAllShw.h@ 8170

Last change on this file since 8170 was 8155, checked in by vboxsync, 17 years ago
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1	/* $Id: PGMAllShw.h 8155 2008-04-18 15:16:47Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_POOL_ROOT_IDX
43
44	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
45	# define SHWPT X86PT
46	# define PSHWPT PX86PT
47	# define SHWPTE X86PTE
48	# define PSHWPTE PX86PTE
49	# define SHWPD X86PD
50	# define PSHWPD PX86PD
51	# define SHWPDE X86PDE
52	# define PSHWPDE PX86PDE
53	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
54	# define SHW_PD_SHIFT X86_PD_SHIFT
55	# define SHW_PD_MASK X86_PD_MASK
56	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
57	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
58	# define SHW_PT_SHIFT X86_PT_SHIFT
59	# define SHW_PT_MASK X86_PT_MASK
60	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
61	#else
62	# define SHWPT X86PTPAE
63	# define PSHWPT PX86PTPAE
64	# define SHWPTE X86PTEPAE
65	# define PSHWPTE PX86PTEPAE
66	# define SHWPD X86PDPAE
67	# define PSHWPD PX86PDPAE
68	# define SHWPDE X86PDEPAE
69	# define PSHWPDE PX86PDEPAE
70	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
71	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
72	# define SHW_PD_MASK X86_PD_PAE_MASK
73	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
74	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
75	# define SHW_PT_MASK X86_PT_PAE_MASK
76	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
77	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
78	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
79	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
80	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PML4
81	#else /* 32 bits PAE mode */
82	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
83	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
84	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
85	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
86	#endif
87	#endif
88
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	__BEGIN_DECLS
95	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
96	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
97	PGM_SHW_DECL(int, GetPDEByIndex)(PVM pVM, uint32_t iPD, PX86PDEPAE pPde);
98	PGM_SHW_DECL(int, SetPDEByIndex)(PVM pVM, uint32_t iPD, X86PDEPAE Pde);
99	PGM_SHW_DECL(int, ModifyPDEByIndex)(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask);
100	__END_DECLS
101
102
103
104	/**
105	* Gets effective page information (from the VMM page directory).
106	*
107	* @returns VBox status.
108	* @param pVM VM Handle.
109	* @param GCPtr Guest Context virtual address of the page.
110	* @param pfFlags Where to store the flags. These are X86_PTE_*.
111	* @param pHCPhys Where to store the HC physical address of the page.
112	* This is page aligned.
113	* @remark You should use PGMMapGetPage() for pages in a mapping.
114	*/
115	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
116	{
117	/*
118	* Get the PDE.
119	*/
120	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
121	/*
122	* For the first 4G we have preallocated page directories.
123	* Since the two upper levels contains only fixed flags, we skip those when possible.
124	*/
125	X86PDEPAE Pde;
126	#if GC_ARCH_BITS == 64
127	if (GCPtr < _4G)
128	#endif
129	{
130	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
131	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
132	Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
133	}
134	#if GC_ARCH_BITS == 64
135	else
136	{
137	/* PML4 */
138	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
139	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
140	if (!Pml4e.n.u1Present)
141	return VERR_PAGE_TABLE_NOT_PRESENT;
142
143	/* PDPT */
144	PX86PDPT pPDPT;
145	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
146	if (VBOX_FAILURE(rc))
147	return rc;
148	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
149	X86PDPE Pdpe = pPDPT->a[iPDPT];
150	if (!Pdpe.n.u1Present)
151	return VERR_PAGE_TABLE_NOT_PRESENT;
152
153	/* PD */
154	PX86PDPAE pPd;
155	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
156	if (VBOX_FAILURE(rc))
157	return rc;
158	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
159	Pdpe = pPDPT->a[iPd];
160	}
161	#endif /* GC_ARCH_BITS == 64 */
162
163	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
164	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
165	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
166	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
167
168	#else /* PGM_TYPE_32BIT */
169	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
170	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
171	#endif
172	if (!Pde.n.u1Present)
173	return VERR_PAGE_TABLE_NOT_PRESENT;
174
175	/*
176	* Get PT entry.
177	*/
178	PSHWPT pPT;
179	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
180	{
181	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
182	if (VBOX_FAILURE(rc))
183	return rc;
184	}
185	else /* mapping: */
186	{
187	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
188
189	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
190	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
191	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
192	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(pPT);
193	#else /* PAE and AMD64: */
194	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(paPaePTs);
195	#endif
196	}
197	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
198	SHWPTE Pte = pPT->a[iPt];
199	if (!Pte.n.u1Present)
200	return VERR_PAGE_NOT_PRESENT;
201
202	/*
203	* Store the results.
204	* RW and US flags depend on the entire page transation hierarchy - except for
205	* legacy PAE which has a simplified PDPE.
206	*/
207	if (pfFlags)
208	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
209	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
210	if (pHCPhys)
211	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
212
213	return VINF_SUCCESS;
214	}
215
216
217	/**
218	* Modify page flags for a range of pages in the shadow context.
219	*
220	* The existing flags are ANDed with the fMask and ORed with the fFlags.
221	*
222	* @returns VBox status code.
223	* @param pVM VM handle.
224	* @param GCPtr Virtual address of the first page in the range. Page aligned!
225	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
226	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
227	* @param fMask The AND mask - page flags X86_PTE_*.
228	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
229	* @remark You must use PGMMapModifyPage() for pages in a mapping.
230	*/
231	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
232	{
233	/*
234	* Walk page tables and pages till we're done.
235	*/
236	for (;;)
237	{
238	/*
239	* Get the PDE.
240	*/
241	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
242	/*
243	* For the first 4G we have preallocated page directories.
244	* Since the two upper levels contains only fixed flags, we skip those when possible.
245	*/
246	X86PDEPAE Pde;
247	#if GC_ARCH_BITS == 64
248	if (GCPtr < _4G)
249	#endif
250	{
251	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
252	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
253	Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
254	}
255	#if GC_ARCH_BITS == 64
256	else
257	{
258	/* PML4 */
259	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
260	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
261	if (!Pml4e.n.u1Present)
262	return VERR_PAGE_TABLE_NOT_PRESENT;
263
264	/* PDPT */
265	PX86PDPT pPDPT;
266	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
267	if (VBOX_FAILURE(rc))
268	return rc;
269	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
270	X86PDPE Pdpe = pPDPT->a[iPDPT];
271	if (!Pdpe.n.u1Present)
272	return VERR_PAGE_TABLE_NOT_PRESENT;
273
274	/* PD */
275	PX86PDPAE pPd;
276	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
277	if (VBOX_FAILURE(rc))
278	return rc;
279	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
280	Pdpe = pPDPT->a[iPd];
281	}
282	#endif /* GC_ARCH_BITS == 64 */
283
284	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
285	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
286	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
287	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
288
289	#else /* PGM_TYPE_32BIT */
290	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
291	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
292	#endif
293	if (!Pde.n.u1Present)
294	return VERR_PAGE_TABLE_NOT_PRESENT;
295
296
297	/*
298	* Map the page table.
299	*/
300	PSHWPT pPT;
301	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
302	if (VBOX_FAILURE(rc))
303	return rc;
304
305	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
306	while (iPTE < ELEMENTS(pPT->a))
307	{
308	if (pPT->a[iPTE].n.u1Present)
309	{
310	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
311	Assert(pPT->a[iPTE].n.u1Present);
312	PGM_INVL_PG(GCPtr);
313	}
314
315	/* next page */
316	cb -= PAGE_SIZE;
317	if (!cb)
318	return VINF_SUCCESS;
319	GCPtr += PAGE_SIZE;
320	iPTE++;
321	}
322	}
323	}
324
325	/**
326	* Retrieve shadow PDE
327	*
328	* @returns VBox status code.
329	* @param pVM The virtual machine.
330	* @param iPD Shadow PDE index.
331	* @param pPde Where to store the shadow PDE entry.
332	*/
333	PGM_SHW_DECL(int, GetPDEByIndex)(PVM pVM, unsigned iPD, PX86PDEPAE pPde)
334	{
335	#if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
336	/*
337	* Get page directory addresses.
338	*/
339	Assert(iPD < SHW_TOTAL_PD_ENTRIES);
340	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
341	PX86PDE pPdeSrc = &CTXMID(pVM->pgm.s.p,32BitPD)->a[iPD];
342	# else
343	PX86PDEPAE pPdeSrc = &CTXMID(pVM->pgm.s.ap,PaePDs)[0]->a[iPD]; /* We treat this as a PD with 2048 entries. */
344	# endif
345
346	pPde->u = (X86PGPAEUINT)pPdeSrc->u;
347	return VINF_SUCCESS;
348
349	#else
350	AssertFailed();
351	return VERR_NOT_IMPLEMENTED;
352	#endif
353	}
354
355	/**
356	* Set shadow PDE
357	*
358	* @returns VBox status code.
359	* @param pVM The virtual machine.
360	* @param iPD Shadow PDE index.
361	* @param Pde Shadow PDE.
362	*/
363	PGM_SHW_DECL(int, SetPDEByIndex)(PVM pVM, unsigned iPD, X86PDEPAE Pde)
364	{
365	#if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
366	/*
367	* Get page directory addresses and update the specified entry.
368	*/
369	Assert(iPD < SHW_TOTAL_PD_ENTRIES);
370	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
371	Assert(Pde.au32[1] == 0); /* First uint32_t is backwards compatible. */
372	Assert(Pde.n.u1Size == 0);
373	PX86PDE pPdeDst = &CTXMID(pVM->pgm.s.p,32BitPD)->a[iPD];
374	pPdeDst->u = Pde.au32[0];
375	# else
376	PX86PDEPAE pPdeDst = &CTXMID(pVM->pgm.s.ap,PaePDs)[0]->a[iPD]; /* We treat this as a PD with 2048 entries. */
377	pPdeDst->u = Pde.u;
378	# endif
379	Assert(pPdeDst->n.u1Present);
380
381	return VINF_SUCCESS;
382	#else
383	AssertFailed();
384	return VERR_NOT_IMPLEMENTED;
385	#endif
386	}
387
388	/**
389	* Modify shadow PDE
390	*
391	* @returns VBox status code.
392	* @param pVM The virtual machine.
393	* @param iPD Shadow PDE index.
394	* @param fFlags The OR mask - page flags X86_PDE_*, excluding the page mask of course.
395	* @param fMask The AND mask - page flags X86_PDE_*.
396	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
397	*/
398	PGM_SHW_DECL(int, ModifyPDEByIndex)(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask)
399	{
400	#if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
401	/*
402	* Get page directory addresses and update the specified entry.
403	*/
404	Assert(iPD < SHW_TOTAL_PD_ENTRIES);
405	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
406	PX86PDE pPdeDst = &CTXMID(pVM->pgm.s.p,32BitPD)->a[iPD];
407
408	pPdeDst->u = ((pPdeDst->u & ((X86PGUINT)fMask \| SHW_PDE_PG_MASK)) \| ((X86PGUINT)fFlags & ~SHW_PDE_PG_MASK));
409	Assert(!pPdeDst->n.u1Size);
410	# else
411	PX86PDEPAE pPdeDst = &CTXMID(pVM->pgm.s.ap,PaePDs)[0]->a[iPD]; /* We treat this as a PD with 2048 entries. */
412
413	pPdeDst->u = (pPdeDst->u & (fMask \| SHW_PDE_PG_MASK)) \| (fFlags & ~SHW_PDE_PG_MASK);
414	# endif
415	Assert(pPdeDst->n.u1Present);
416
417	return VINF_SUCCESS;
418	#else
419	AssertFailed();
420	return VERR_NOT_IMPLEMENTED;
421	#endif
422	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 8170

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