PGMAllShw.h@ 73268

Last change on this file since 73268 was 73268, checked in by vboxsync, 7 years ago
PGM: Working on consolidating templated code... bugref:9044
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1	/* $Id: PGMAllShw.h 73268 2018-07-20 14:49:05Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Defined Constants And Macros *
20	*******************************************************************************/
21	#undef SHWPT
22	#undef PSHWPT
23	#undef SHWPTE
24	#undef PSHWPTE
25	#undef SHWPD
26	#undef PSHWPD
27	#undef SHWPDE
28	#undef PSHWPDE
29	#undef SHW_PDE_PG_MASK
30	#undef SHW_PD_SHIFT
31	#undef SHW_PD_MASK
32	#undef SHW_PTE_PG_MASK
33	#undef SHW_PTE_IS_P
34	#undef SHW_PTE_IS_RW
35	#undef SHW_PTE_IS_US
36	#undef SHW_PTE_IS_A
37	#undef SHW_PTE_IS_D
38	#undef SHW_PTE_IS_P_RW
39	#undef SHW_PTE_IS_TRACK_DIRTY
40	#undef SHW_PTE_GET_HCPHYS
41	#undef SHW_PTE_GET_U
42	#undef SHW_PTE_LOG64
43	#undef SHW_PTE_SET
44	#undef SHW_PTE_ATOMIC_SET
45	#undef SHW_PTE_ATOMIC_SET2
46	#undef SHW_PTE_SET_RO
47	#undef SHW_PTE_SET_RW
48	#undef SHW_PT_SHIFT
49	#undef SHW_PT_MASK
50	#undef SHW_TOTAL_PD_ENTRIES
51	#undef SHW_PDPT_SHIFT
52	#undef SHW_PDPT_MASK
53	#undef SHW_PDPE_PG_MASK
54
55	#if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
56	# define SHWPT X86PT
57	# define PSHWPT PX86PT
58	# define SHWPTE X86PTE
59	# define PSHWPTE PX86PTE
60	# define SHWPD X86PD
61	# define PSHWPD PX86PD
62	# define SHWPDE X86PDE
63	# define PSHWPDE PX86PDE
64	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
65	# define SHW_PD_SHIFT X86_PD_SHIFT
66	# define SHW_PD_MASK X86_PD_MASK
67	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
68	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
69	# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present )
70	# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
71	# define SHW_PTE_IS_US(Pte) ( (Pte).n.u1User )
72	# define SHW_PTE_IS_A(Pte) ( (Pte).n.u1Accessed )
73	# define SHW_PTE_IS_D(Pte) ( (Pte).n.u1Dirty )
74	# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
75	# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
76	# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
77	# define SHW_PTE_LOG64(Pte) ( (uint64_t)(Pte).u )
78	# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
79	# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
80	# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU32(&(Pte).u, (uNew)); } while (0)
81	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU32(&(Pte).u, (Pte2).u); } while (0)
82	# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
83	# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
84	# define SHW_PT_SHIFT X86_PT_SHIFT
85	# define SHW_PT_MASK X86_PT_MASK
86
87	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
88	# define SHWPT EPTPT
89	# define PSHWPT PEPTPT
90	# define SHWPTE EPTPTE
91	# define PSHWPTE PEPTPTE
92	# define SHWPD EPTPD
93	# define PSHWPD PEPTPD
94	# define SHWPDE EPTPDE
95	# define PSHWPDE PEPTPDE
96	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
97	# define SHW_PD_SHIFT EPT_PD_SHIFT
98	# define SHW_PD_MASK EPT_PD_MASK
99	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
100	# define SHW_PTE_IS_P(Pte) ( (Pte).n.u1Present ) /* Approximation, works for us. */
101	# define SHW_PTE_IS_RW(Pte) ( (Pte).n.u1Write )
102	# define SHW_PTE_IS_US(Pte) ( true )
103	# define SHW_PTE_IS_A(Pte) ( true )
104	# define SHW_PTE_IS_D(Pte) ( true )
105	# define SHW_PTE_IS_P_RW(Pte) ( (Pte).n.u1Present && (Pte).n.u1Write )
106	# define SHW_PTE_IS_TRACK_DIRTY(Pte) ( false )
107	# define SHW_PTE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PG_MASK )
108	# define SHW_PTE_LOG64(Pte) ( (Pte).u )
109	# define SHW_PTE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
110	# define SHW_PTE_SET(Pte, uNew) do { (Pte).u = (uNew); } while (0)
111	# define SHW_PTE_ATOMIC_SET(Pte, uNew) do { ASMAtomicWriteU64(&(Pte).u, (uNew)); } while (0)
112	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
113	# define SHW_PTE_SET_RO(Pte) do { (Pte).n.u1Write = 0; } while (0)
114	# define SHW_PTE_SET_RW(Pte) do { (Pte).n.u1Write = 1; } while (0)
115	# define SHW_PT_SHIFT EPT_PT_SHIFT
116	# define SHW_PT_MASK EPT_PT_MASK
117	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
118	# define SHW_PDPT_MASK EPT_PDPT_MASK
119	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
120	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
121
122	#else
123	# define SHWPT PGMSHWPTPAE
124	# define PSHWPT PPGMSHWPTPAE
125	# define SHWPTE PGMSHWPTEPAE
126	# define PSHWPTE PPGMSHWPTEPAE
127	# define SHWPD X86PDPAE
128	# define PSHWPD PX86PDPAE
129	# define SHWPDE X86PDEPAE
130	# define PSHWPDE PX86PDEPAE
131	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
132	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
133	# define SHW_PD_MASK X86_PD_PAE_MASK
134	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
135	# define SHW_PTE_IS_P(Pte) PGMSHWPTEPAE_IS_P(Pte)
136	# define SHW_PTE_IS_RW(Pte) PGMSHWPTEPAE_IS_RW(Pte)
137	# define SHW_PTE_IS_US(Pte) PGMSHWPTEPAE_IS_US(Pte)
138	# define SHW_PTE_IS_A(Pte) PGMSHWPTEPAE_IS_A(Pte)
139	# define SHW_PTE_IS_D(Pte) PGMSHWPTEPAE_IS_D(Pte)
140	# define SHW_PTE_IS_P_RW(Pte) PGMSHWPTEPAE_IS_P_RW(Pte)
141	# define SHW_PTE_IS_TRACK_DIRTY(Pte) PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte)
142	# define SHW_PTE_GET_HCPHYS(Pte) PGMSHWPTEPAE_GET_HCPHYS(Pte)
143	# define SHW_PTE_LOG64(Pte) PGMSHWPTEPAE_GET_LOG(Pte)
144	# define SHW_PTE_GET_U(Pte) PGMSHWPTEPAE_GET_U(Pte) /*< Use with care. /
145	# define SHW_PTE_SET(Pte, uNew) PGMSHWPTEPAE_SET(Pte, uNew)
146	# define SHW_PTE_ATOMIC_SET(Pte, uNew) PGMSHWPTEPAE_ATOMIC_SET(Pte, uNew)
147	# define SHW_PTE_ATOMIC_SET2(Pte, Pte2) PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2)
148	# define SHW_PTE_SET_RO(Pte) PGMSHWPTEPAE_SET_RO(Pte)
149	# define SHW_PTE_SET_RW(Pte) PGMSHWPTEPAE_SET_RW(Pte)
150	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
151	# define SHW_PT_MASK X86_PT_PAE_MASK
152
153	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
154	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
155	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
156	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
157	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
158
159	# elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
160	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
161	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
162	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
163	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
164
165	# else
166	# error "Misconfigured PGM_SHW_TYPE or something..."
167	# endif
168	#endif
169
170
171
172	/*******************************************************************************
173	* Internal Functions *
174	*******************************************************************************/
175	RT_C_DECLS_BEGIN
176	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
177	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
178	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
179	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
180	#ifdef IN_RING3
181	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
182	#endif
183	RT_C_DECLS_END
184
185
186	/**
187	* Enters the shadow mode.
188	*
189	* @returns VBox status code.
190	* @param pVCpu The cross context virtual CPU structure.
191	* @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
192	*/
193	PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
194	{
195	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
196
197	# if PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && HC_ARCH_BITS == 32
198	/* Must distinguish between 32 and 64 bits guest paging modes as we'll use
199	a different shadow paging root/mode in both cases. */
200	RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
201	# else
202	RTGCPHYS GCPhysCR3 = RT_BIT_64(63); NOREF(fIs64BitsPagingMode);
203	# endif
204	PPGMPOOLPAGE pNewShwPageCR3;
205	PVM pVM = pVCpu->CTX_SUFF(pVM);
206
207	Assert((HMIsNestedPagingActive(pVM) \|\| VM_IS_NEM_ENABLED(pVM)) == pVM->pgm.s.fNestedPaging);
208	Assert(pVM->pgm.s.fNestedPaging);
209	Assert(!pVCpu->pgm.s.pShwPageCR3R3);
210
211	pgmLock(pVM);
212
213	int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
214	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
215	&pNewShwPageCR3);
216	AssertLogRelRCReturnStmt(rc, pgmUnlock(pVM), rc);
217
218	pVCpu->pgm.s.pShwPageCR3R3 = (R3PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR3(pVM, pNewShwPageCR3);
219	pVCpu->pgm.s.pShwPageCR3RC = (RCPTRTYPE(PPGMPOOLPAGE))MMHyperCCToRC(pVM, pNewShwPageCR3);
220	pVCpu->pgm.s.pShwPageCR3R0 = (R0PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR0(pVM, pNewShwPageCR3);
221
222	pgmUnlock(pVM);
223
224	Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
225	#else
226	NOREF(pVCpu); NOREF(fIs64BitsPagingMode);
227	#endif
228	return VINF_SUCCESS;
229	}
230
231
232	/**
233	* Exits the shadow mode.
234	*
235	* @returns VBox status code.
236	* @param pVCpu The cross context virtual CPU structure.
237	*/
238	PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
239	{
240	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
241	PVM pVM = pVCpu->CTX_SUFF(pVM);
242	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
243	{
244	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
245
246	pgmLock(pVM);
247
248	/* Do not unlock this page as we have two of them floating around in the 32-bit host & 64-bit guest case.
249	* We currently assert when you try to free one of them; don't bother to really allow this.
250	*
251	* Note that this is two nested paging root pages max. This isn't a leak. They are reused.
252	*/
253	/* pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)); */
254
255	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
256	pVCpu->pgm.s.pShwPageCR3R3 = 0;
257	pVCpu->pgm.s.pShwPageCR3R0 = 0;
258	pVCpu->pgm.s.pShwPageCR3RC = 0;
259
260	pgmUnlock(pVM);
261
262	Log(("Leave nested shadow paging mode\n"));
263	}
264	#else
265	RT_NOREF_PV(pVCpu);
266	#endif
267	return VINF_SUCCESS;
268	}
269
270
271	/**
272	* Gets effective page information (from the VMM page directory).
273	*
274	* @returns VBox status code.
275	* @param pVCpu The cross context virtual CPU structure.
276	* @param GCPtr Guest Context virtual address of the page.
277	* @param pfFlags Where to store the flags. These are X86_PTE_*.
278	* @param pHCPhys Where to store the HC physical address of the page.
279	* This is page aligned.
280	* @remark You should use PGMMapGetPage() for pages in a mapping.
281	*/
282	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
283	{
284	PVM pVM = pVCpu->CTX_SUFF(pVM);
285
286	PGM_LOCK_ASSERT_OWNER(pVM);
287
288	/*
289	* Get the PDE.
290	*/
291	#if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
292	X86PDEPAE Pde;
293
294	/* PML4 */
295	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
296	if (!Pml4e.n.u1Present)
297	return VERR_PAGE_TABLE_NOT_PRESENT;
298
299	/* PDPT */
300	PX86PDPT pPDPT;
301	int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
302	if (RT_FAILURE(rc))
303	return rc;
304	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
305	X86PDPE Pdpe = pPDPT->a[iPDPT];
306	if (!Pdpe.n.u1Present)
307	return VERR_PAGE_TABLE_NOT_PRESENT;
308
309	/* PD */
310	PX86PDPAE pPd;
311	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
312	if (RT_FAILURE(rc))
313	return rc;
314	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
315	Pde = pPd->a[iPd];
316
317	/* Merge accessed, write, user and no-execute bits into the PDE. */
318	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
319	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
320	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
321	Pde.n.u1NoExecute \|= Pml4e.n.u1NoExecute \| Pdpe.lm.u1NoExecute;
322
323	#elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
324	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
325
326	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
327	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
328	PEPTPD pPDDst;
329	EPTPDE Pde;
330
331	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
332	if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
333	{
334	AssertRC(rc);
335	return rc;
336	}
337	Assert(pPDDst);
338	Pde = pPDDst->a[iPd];
339
340	#elif PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
341	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
342	#else
343	# error "Misconfigured PGM_SHW_TYPE or something..."
344	#endif
345	if (!Pde.n.u1Present)
346	return VERR_PAGE_TABLE_NOT_PRESENT;
347
348	/* Deal with large pages. */
349	if (Pde.b.u1Size)
350	{
351	/*
352	* Store the results.
353	* RW and US flags depend on the entire page translation hierarchy - except for
354	* legacy PAE which has a simplified PDPE.
355	*/
356	if (pfFlags)
357	{
358	*pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
359	#if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
360	if ( (Pde.u & X86_PTE_PAE_NX)
361	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
362	&& CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
363	# endif
364	)
365	*pfFlags \|= X86_PTE_PAE_NX;
366	#endif
367	}
368
369	if (pHCPhys)
370	*pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
371
372	return VINF_SUCCESS;
373	}
374
375	/*
376	* Get PT entry.
377	*/
378	PSHWPT pPT;
379	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
380	{
381	int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
382	if (RT_FAILURE(rc2))
383	return rc2;
384	}
385	else /* mapping: */
386	{
387	#if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
388	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT \
389	\|\| defined(PGM_WITHOUT_MAPPINGS)
390	AssertFailed(); /* can't happen */
391	pPT = NULL; /* shut up MSC */
392	#else
393	Assert(pgmMapAreMappingsEnabled(pVM));
394
395	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
396	AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_PGM_MAPPING_IPE);
397	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
398	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
399	# else /* PAE */
400	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
401	# endif
402	#endif
403	}
404	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
405	SHWPTE Pte = pPT->a[iPt];
406	if (!SHW_PTE_IS_P(Pte))
407	return VERR_PAGE_NOT_PRESENT;
408
409	/*
410	* Store the results.
411	* RW and US flags depend on the entire page translation hierarchy - except for
412	* legacy PAE which has a simplified PDPE.
413	*/
414	if (pfFlags)
415	{
416	*pfFlags = (SHW_PTE_GET_U(Pte) & ~SHW_PTE_PG_MASK)
417	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
418
419	#if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
420	/* The NX bit is determined by a bitwise OR between the PT and PD */
421	if ( ((SHW_PTE_GET_U(Pte) \| Pde.u) & X86_PTE_PAE_NX)
422	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
423	&& CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
424	# endif
425	)
426	*pfFlags \|= X86_PTE_PAE_NX;
427	#endif
428	}
429
430	if (pHCPhys)
431	*pHCPhys = SHW_PTE_GET_HCPHYS(Pte);
432
433	return VINF_SUCCESS;
434	}
435
436
437	/**
438	* Modify page flags for a range of pages in the shadow context.
439	*
440	* The existing flags are ANDed with the fMask and ORed with the fFlags.
441	*
442	* @returns VBox status code.
443	* @param pVCpu The cross context virtual CPU structure.
444	* @param GCPtr Virtual address of the first page in the range. Page aligned!
445	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
446	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
447	* @param fMask The AND mask - page flags X86_PTE_*.
448	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
449	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
450	* @remark You must use PGMMapModifyPage() for pages in a mapping.
451	*/
452	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
453	{
454	PVM pVM = pVCpu->CTX_SUFF(pVM);
455	int rc;
456
457	PGM_LOCK_ASSERT_OWNER(pVM);
458
459	/*
460	* Walk page tables and pages till we're done.
461	*/
462	for (;;)
463	{
464	/*
465	* Get the PDE.
466	*/
467	#if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
468	X86PDEPAE Pde;
469	/* PML4 */
470	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
471	if (!Pml4e.n.u1Present)
472	return VERR_PAGE_TABLE_NOT_PRESENT;
473
474	/* PDPT */
475	PX86PDPT pPDPT;
476	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
477	if (RT_FAILURE(rc))
478	return rc;
479	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
480	X86PDPE Pdpe = pPDPT->a[iPDPT];
481	if (!Pdpe.n.u1Present)
482	return VERR_PAGE_TABLE_NOT_PRESENT;
483
484	/* PD */
485	PX86PDPAE pPd;
486	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
487	if (RT_FAILURE(rc))
488	return rc;
489	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
490	Pde = pPd->a[iPd];
491
492	#elif PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
493	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
494
495	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
496	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
497	PEPTPD pPDDst;
498	EPTPDE Pde;
499
500	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
501	if (rc != VINF_SUCCESS)
502	{
503	AssertRC(rc);
504	return rc;
505	}
506	Assert(pPDDst);
507	Pde = pPDDst->a[iPd];
508
509	#else /* PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
510	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
511	#endif
512	if (!Pde.n.u1Present)
513	return VERR_PAGE_TABLE_NOT_PRESENT;
514
515	AssertFatal(!Pde.b.u1Size);
516
517	/*
518	* Map the page table.
519	*/
520	PSHWPT pPT;
521	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
522	if (RT_FAILURE(rc))
523	return rc;
524
525	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
526	while (iPTE < RT_ELEMENTS(pPT->a))
527	{
528	if (SHW_PTE_IS_P(pPT->a[iPTE]))
529	{
530	SHWPTE const OrgPte = pPT->a[iPTE];
531	SHWPTE NewPte;
532
533	SHW_PTE_SET(NewPte, (SHW_PTE_GET_U(OrgPte) & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK));
534	if (!SHW_PTE_IS_P(NewPte))
535	{
536	/** @todo Some CSAM code path might end up here and upset
537	* the page pool. */
538	AssertFailed();
539	}
540	else if ( SHW_PTE_IS_RW(NewPte)
541	&& !SHW_PTE_IS_RW(OrgPte)
542	&& !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
543	{
544	/** @todo Optimize \#PF handling by caching data. We can
545	* then use this when PGM_MK_PG_IS_WRITE_FAULT is
546	* set instead of resolving the guest physical
547	* address yet again. */
548	RTGCPHYS GCPhys;
549	uint64_t fGstPte;
550	rc = PGMGstGetPage(pVCpu, GCPtr, &fGstPte, &GCPhys);
551	AssertRC(rc);
552	if (RT_SUCCESS(rc))
553	{
554	Assert((fGstPte & X86_PTE_RW) \|\| !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP /* allow netware hack */));
555	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
556	Assert(pPage);
557	if (pPage)
558	{
559	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
560	AssertRCReturn(rc, rc);
561	Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GCPhys, pPage));
562	}
563	}
564	}
565
566	SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
567	#if PGM_SHW_TYPE == PGM_TYPE_EPT
568	HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
569	#else
570	PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
571	#endif
572	}
573
574	/* next page */
575	cb -= PAGE_SIZE;
576	if (!cb)
577	return VINF_SUCCESS;
578	GCPtr += PAGE_SIZE;
579	iPTE++;
580	}
581	}
582	}
583
584
585	#ifdef IN_RING3
586	/**
587	* Relocate any GC pointers related to shadow mode paging.
588	*
589	* @returns VBox status code.
590	* @param pVCpu The cross context virtual CPU structure.
591	* @param offDelta The relocation offset.
592	*/
593	PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
594	{
595	pVCpu->pgm.s.pShwPageCR3RC += offDelta;
596	return VINF_SUCCESS;
597	}
598	#endif
599

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 73268

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