PGMAllShw.h@ 24125

Last change on this file since 24125 was 22600, checked in by vboxsync, 15 years ago
Removed unnecessary EPT invlpg calls. Invalidate the page who's R/W attribute was changed.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 12.9 KB

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1	/* $Id: PGMAllShw.h 22600 2009-08-31 12:19:56Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_PDPE_PG_MASK
43	#undef SHW_POOL_ROOT_IDX
44
45	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46	# define SHWPT X86PT
47	# define PSHWPT PX86PT
48	# define SHWPTE X86PTE
49	# define PSHWPTE PX86PTE
50	# define SHWPD X86PD
51	# define PSHWPD PX86PD
52	# define SHWPDE X86PDE
53	# define PSHWPDE PX86PDE
54	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55	# define SHW_PD_SHIFT X86_PD_SHIFT
56	# define SHW_PD_MASK X86_PD_MASK
57	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59	# define SHW_PT_SHIFT X86_PT_SHIFT
60	# define SHW_PT_MASK X86_PT_MASK
61	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62
63	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
64	# define SHWPT EPTPT
65	# define PSHWPT PEPTPT
66	# define SHWPTE EPTPTE
67	# define PSHWPTE PEPTPTE
68	# define SHWPD EPTPD
69	# define PSHWPD PEPTPD
70	# define SHWPDE EPTPDE
71	# define PSHWPDE PEPTPDE
72	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
73	# define SHW_PD_SHIFT EPT_PD_SHIFT
74	# define SHW_PD_MASK EPT_PD_MASK
75	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
76	# define SHW_PT_SHIFT EPT_PT_SHIFT
77	# define SHW_PT_MASK EPT_PT_MASK
78	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
79	# define SHW_PDPT_MASK EPT_PDPT_MASK
80	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
81	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
82	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
83
84	#else
85	# define SHWPT X86PTPAE
86	# define PSHWPT PX86PTPAE
87	# define SHWPTE X86PTEPAE
88	# define PSHWPTE PX86PTEPAE
89	# define SHWPD X86PDPAE
90	# define PSHWPD PX86PDPAE
91	# define SHWPDE X86PDEPAE
92	# define PSHWPDE PX86PDEPAE
93	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
94	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
95	# define SHW_PD_MASK X86_PD_PAE_MASK
96	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
97	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
98	# define SHW_PT_MASK X86_PT_PAE_MASK
99
100	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
101	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
102	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
103	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
104	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
105	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
106
107	# else /* 32 bits PAE mode */
108	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
109	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
110	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
111	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
112	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
113
114	# endif
115	#endif
116
117
118
119	/*******************************************************************************
120	* Internal Functions *
121	*******************************************************************************/
122	RT_C_DECLS_BEGIN
123	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
124	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
125	RT_C_DECLS_END
126
127
128
129	/**
130	* Gets effective page information (from the VMM page directory).
131	*
132	* @returns VBox status.
133	* @param pVCpu The VMCPU handle.
134	* @param GCPtr Guest Context virtual address of the page.
135	* @param pfFlags Where to store the flags. These are X86_PTE_*.
136	* @param pHCPhys Where to store the HC physical address of the page.
137	* This is page aligned.
138	* @remark You should use PGMMapGetPage() for pages in a mapping.
139	*/
140	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
141	{
142	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
143	return VERR_PAGE_TABLE_NOT_PRESENT;
144
145	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
146	PVM pVM = pVCpu->CTX_SUFF(pVM);
147
148	Assert(PGMIsLockOwner(pVM));
149
150	/*
151	* Get the PDE.
152	*/
153	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
154	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
155	X86PDEPAE Pde;
156
157	/* PML4 */
158	X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
159	if (!Pml4e.n.u1Present)
160	return VERR_PAGE_TABLE_NOT_PRESENT;
161
162	/* PDPT */
163	PX86PDPT pPDPT;
164	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
165	if (RT_FAILURE(rc))
166	return rc;
167	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
168	X86PDPE Pdpe = pPDPT->a[iPDPT];
169	if (!Pdpe.n.u1Present)
170	return VERR_PAGE_TABLE_NOT_PRESENT;
171
172	/* PD */
173	PX86PDPAE pPd;
174	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
175	if (RT_FAILURE(rc))
176	return rc;
177	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
178	Pde = pPd->a[iPd];
179
180	/* Merge accessed, write, user and no-execute bits into the PDE. */
181	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
182	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
183	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
184	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
185
186	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
187	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
188	X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
189
190	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
191	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
192	PEPTPD pPDDst;
193	EPTPDE Pde;
194
195	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
196	if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
197	{
198	AssertRC(rc);
199	return rc;
200	}
201	Assert(pPDDst);
202	Pde = pPDDst->a[iPd];
203
204	# else /* PGM_TYPE_32BIT */
205	X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
206	# endif
207	if (!Pde.n.u1Present)
208	return VERR_PAGE_TABLE_NOT_PRESENT;
209
210	Assert(!Pde.b.u1Size);
211
212	/*
213	* Get PT entry.
214	*/
215	PSHWPT pPT;
216	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
217	{
218	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
219	if (RT_FAILURE(rc))
220	return rc;
221	}
222	else /* mapping: */
223	{
224	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
225	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT
226	AssertFailed(); /* can't happen */
227	# else
228	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
229
230	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
231	AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_INTERNAL_ERROR);
232	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
233	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
234	# else /* PAE */
235	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
236	# endif
237	# endif
238	}
239	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
240	SHWPTE Pte = pPT->a[iPt];
241	if (!Pte.n.u1Present)
242	return VERR_PAGE_NOT_PRESENT;
243
244	/*
245	* Store the results.
246	* RW and US flags depend on the entire page translation hierarchy - except for
247	* legacy PAE which has a simplified PDPE.
248	*/
249	if (pfFlags)
250	{
251	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
252	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
253	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
254	/* The NX bit is determined by a bitwise OR between the PT and PD */
255	if (fNoExecuteBitValid)
256	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
257	# endif
258	}
259
260	if (pHCPhys)
261	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
262
263	return VINF_SUCCESS;
264	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
265	}
266
267
268	/**
269	* Modify page flags for a range of pages in the shadow context.
270	*
271	* The existing flags are ANDed with the fMask and ORed with the fFlags.
272	*
273	* @returns VBox status code.
274	* @param pVCpu The VMCPU handle.
275	* @param GCPtr Virtual address of the first page in the range. Page aligned!
276	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
277	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
278	* @param fMask The AND mask - page flags X86_PTE_*.
279	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
280	* @remark You must use PGMMapModifyPage() for pages in a mapping.
281	*/
282	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
283	{
284	# if PGM_SHW_TYPE == PGM_TYPE_NESTED
285	return VERR_PAGE_TABLE_NOT_PRESENT;
286
287	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
288	PVM pVM = pVCpu->CTX_SUFF(pVM);
289	int rc;
290
291	Assert(PGMIsLockOwner(pVM));
292	/*
293	* Walk page tables and pages till we're done.
294	*/
295	for (;;)
296	{
297	/*
298	* Get the PDE.
299	*/
300	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
301	X86PDEPAE Pde;
302	/* PML4 */
303	X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
304	if (!Pml4e.n.u1Present)
305	return VERR_PAGE_TABLE_NOT_PRESENT;
306
307	/* PDPT */
308	PX86PDPT pPDPT;
309	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
310	if (RT_FAILURE(rc))
311	return rc;
312	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
313	X86PDPE Pdpe = pPDPT->a[iPDPT];
314	if (!Pdpe.n.u1Present)
315	return VERR_PAGE_TABLE_NOT_PRESENT;
316
317	/* PD */
318	PX86PDPAE pPd;
319	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
320	if (RT_FAILURE(rc))
321	return rc;
322	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
323	Pde = pPd->a[iPd];
324
325	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
326	X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
327
328	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
329	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
330	PEPTPD pPDDst;
331	EPTPDE Pde;
332
333	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
334	if (rc != VINF_SUCCESS)
335	{
336	AssertRC(rc);
337	return rc;
338	}
339	Assert(pPDDst);
340	Pde = pPDDst->a[iPd];
341
342	# else /* PGM_TYPE_32BIT */
343	X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
344	# endif
345	if (!Pde.n.u1Present)
346	return VERR_PAGE_TABLE_NOT_PRESENT;
347
348	/*
349	* Map the page table.
350	*/
351	PSHWPT pPT;
352	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
353	if (RT_FAILURE(rc))
354	return rc;
355
356	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
357	while (iPTE < RT_ELEMENTS(pPT->a))
358	{
359	if (pPT->a[iPTE].n.u1Present)
360	{
361	SHWPTE Pte;
362
363	Pte.u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
364	ASMAtomicWriteSize(&pPT->a[iPTE], Pte.u);
365	Assert(pPT->a[iPTE].n.u1Present);
366	# if PGM_SHW_TYPE == PGM_TYPE_EPT
367	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
368	# else
369	PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
370	# endif
371	}
372
373	/* next page */
374	cb -= PAGE_SIZE;
375	if (!cb)
376	return VINF_SUCCESS;
377	GCPtr += PAGE_SIZE;
378	iPTE++;
379	}
380	}
381	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
382	}
383

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 24125

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