PGMAllShw.h@ 13203

Last change on this file since 13203 was 13203, checked in by vboxsync, 16 years ago
Missing shadow cases for EPT.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 13.1 KB

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1	/* $Id: PGMAllShw.h 13203 2008-10-13 10:02:04Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_PDPE_PG_MASK
43	#undef SHW_POOL_ROOT_IDX
44
45	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46	# define SHWPT X86PT
47	# define PSHWPT PX86PT
48	# define SHWPTE X86PTE
49	# define PSHWPTE PX86PTE
50	# define SHWPD X86PD
51	# define PSHWPD PX86PD
52	# define SHWPDE X86PDE
53	# define PSHWPDE PX86PDE
54	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55	# define SHW_PD_SHIFT X86_PD_SHIFT
56	# define SHW_PD_MASK X86_PD_MASK
57	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59	# define SHW_PT_SHIFT X86_PT_SHIFT
60	# define SHW_PT_MASK X86_PT_MASK
61	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
63	# define SHWPT EPTPT
64	# define PSHWPT PEPTPT
65	# define SHWPTE EPTPTE
66	# define PSHWPTE PEPTPTE
67	# define SHWPD EPTPD
68	# define PSHWPD PEPTPD
69	# define SHWPDE EPTPDE
70	# define PSHWPDE PEPTPDE
71	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
72	# define SHW_PD_SHIFT EPT_PD_SHIFT
73	# define SHW_PD_MASK EPT_PD_MASK
74	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
75	# define SHW_PT_SHIFT EPT_PT_SHIFT
76	# define SHW_PT_MASK EPT_PT_MASK
77	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
78	# define SHW_PDPT_MASK EPT_PDPT_MASK
79	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
80	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
81	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
82	#else
83	# define SHWPT X86PTPAE
84	# define PSHWPT PX86PTPAE
85	# define SHWPTE X86PTEPAE
86	# define PSHWPTE PX86PTEPAE
87	# define SHWPD X86PDPAE
88	# define PSHWPD PX86PDPAE
89	# define SHWPDE X86PDEPAE
90	# define PSHWPDE PX86PDEPAE
91	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
92	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
93	# define SHW_PD_MASK X86_PD_PAE_MASK
94	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
95	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
96	# define SHW_PT_MASK X86_PT_PAE_MASK
97	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
98	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
99	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
100	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
101	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
102	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD /* do not use! exception is real mode & protected mode without paging. */
103	#else /* 32 bits PAE mode */
104	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
105	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
106	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
107	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
108	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
109	#endif
110	#endif
111
112
113
114	/*******************************************************************************
115	* Internal Functions *
116	*******************************************************************************/
117	__BEGIN_DECLS
118	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
119	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
120	__END_DECLS
121
122
123
124	/**
125	* Gets effective page information (from the VMM page directory).
126	*
127	* @returns VBox status.
128	* @param pVM VM Handle.
129	* @param GCPtr Guest Context virtual address of the page.
130	* @param pfFlags Where to store the flags. These are X86_PTE_*.
131	* @param pHCPhys Where to store the HC physical address of the page.
132	* This is page aligned.
133	* @remark You should use PGMMapGetPage() for pages in a mapping.
134	*/
135	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
136	{
137	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
138	return VERR_PAGE_TABLE_NOT_PRESENT;
139
140	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
141	/*
142	* Get the PDE.
143	*/
144	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
145	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
146	X86PDEPAE Pde;
147
148	/* PML4 */
149	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
150	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
151	if (!Pml4e.n.u1Present)
152	return VERR_PAGE_TABLE_NOT_PRESENT;
153
154	/* PDPT */
155	PX86PDPT pPDPT;
156	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
157	if (VBOX_FAILURE(rc))
158	return rc;
159	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
160	X86PDPE Pdpe = pPDPT->a[iPDPT];
161	if (!Pdpe.n.u1Present)
162	return VERR_PAGE_TABLE_NOT_PRESENT;
163
164	/* PD */
165	PX86PDPAE pPd;
166	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
167	if (VBOX_FAILURE(rc))
168	return rc;
169	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
170	Pde = pPd->a[iPd];
171
172	/* Merge accessed, write, user and no-execute bits into the PDE. */
173	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
174	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
175	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
176	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
177
178	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
179	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
180	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
181	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
182	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
183	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
184	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
185	PEPTPD pPDDst;
186	EPTPDE Pde;
187
188	int rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
189	if (rc != VINF_SUCCESS)
190	{
191	AssertRC(rc);
192	return rc;
193	}
194	Assert(pPDDst);
195	Pde = pPDDst->a[iPd];
196	# else /* PGM_TYPE_32BIT */
197	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
198	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
199	# endif
200	if (!Pde.n.u1Present)
201	return VERR_PAGE_TABLE_NOT_PRESENT;
202
203	Assert(!Pde.b.u1Size);
204
205	/*
206	* Get PT entry.
207	*/
208	PSHWPT pPT;
209	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
210	{
211	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
212	if (VBOX_FAILURE(rc))
213	return rc;
214	}
215	else /* mapping: */
216	{
217	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
218	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT
219	AssertFailed(); /* can't happen */
220	# else
221	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
222
223	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
224	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
225	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
226	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
227	# else /* PAE */
228	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
229	# endif
230	# endif
231	}
232	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
233	SHWPTE Pte = pPT->a[iPt];
234	if (!Pte.n.u1Present)
235	return VERR_PAGE_NOT_PRESENT;
236
237	/*
238	* Store the results.
239	* RW and US flags depend on the entire page translation hierarchy - except for
240	* legacy PAE which has a simplified PDPE.
241	*/
242	if (pfFlags)
243	{
244	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
245	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
246	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
247	/* The NX bit is determined by a bitwise OR between the PT and PD */
248	if (fNoExecuteBitValid)
249	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
250	# endif
251	}
252
253	if (pHCPhys)
254	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
255
256	return VINF_SUCCESS;
257	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
258	}
259
260
261	/**
262	* Modify page flags for a range of pages in the shadow context.
263	*
264	* The existing flags are ANDed with the fMask and ORed with the fFlags.
265	*
266	* @returns VBox status code.
267	* @param pVM VM handle.
268	* @param GCPtr Virtual address of the first page in the range. Page aligned!
269	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
270	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
271	* @param fMask The AND mask - page flags X86_PTE_*.
272	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
273	* @remark You must use PGMMapModifyPage() for pages in a mapping.
274	*/
275	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
276	{
277	# if PGM_SHW_TYPE == PGM_TYPE_NESTED
278	return VERR_PAGE_TABLE_NOT_PRESENT;
279
280	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
281	int rc;
282
283	/*
284	* Walk page tables and pages till we're done.
285	*/
286	for (;;)
287	{
288	/*
289	* Get the PDE.
290	*/
291	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
292	X86PDEPAE Pde;
293	/* PML4 */
294	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
295	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
296	if (!Pml4e.n.u1Present)
297	return VERR_PAGE_TABLE_NOT_PRESENT;
298
299	/* PDPT */
300	PX86PDPT pPDPT;
301	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
302	if (VBOX_FAILURE(rc))
303	return rc;
304	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
305	X86PDPE Pdpe = pPDPT->a[iPDPT];
306	if (!Pdpe.n.u1Present)
307	return VERR_PAGE_TABLE_NOT_PRESENT;
308
309	/* PD */
310	PX86PDPAE pPd;
311	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
312	if (VBOX_FAILURE(rc))
313	return rc;
314	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
315	Pde = pPd->a[iPd];
316
317	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
318	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
319	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
320	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
321
322	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
323	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
324	PEPTPD pPDDst;
325	EPTPDE Pde;
326
327	rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
328	if (rc != VINF_SUCCESS)
329	{
330	AssertRC(rc);
331	return rc;
332	}
333	Assert(pPDDst);
334	Pde = pPDDst->a[iPd];
335	# else /* PGM_TYPE_32BIT */
336	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
337	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
338	# endif
339	if (!Pde.n.u1Present)
340	return VERR_PAGE_TABLE_NOT_PRESENT;
341
342	/*
343	* Map the page table.
344	*/
345	PSHWPT pPT;
346	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
347	if (VBOX_FAILURE(rc))
348	return rc;
349
350	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
351	while (iPTE < RT_ELEMENTS(pPT->a))
352	{
353	if (pPT->a[iPTE].n.u1Present)
354	{
355	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
356	Assert(pPT->a[iPTE].n.u1Present);
357	# if PGM_SHW_TYPE == PGM_TYPE_EPT
358	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
359	# else
360	PGM_INVL_PG(GCPtr);
361	# endif
362	}
363
364	/* next page */
365	cb -= PAGE_SIZE;
366	if (!cb)
367	return VINF_SUCCESS;
368	GCPtr += PAGE_SIZE;
369	iPTE++;
370	}
371	}
372	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
373	}
374

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 13203

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