PGMAllShw.h@ 31631

Last change on this file since 31631 was 31178, checked in by vboxsync, 14 years ago
PGM: Some more preparatory cleanup.
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File size: 15.1 KB

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1	/* $Id: PGMAllShw.h 31178 2010-07-28 17:21:13Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Defined Constants And Macros *
20	*******************************************************************************/
21	#undef SHWPT
22	#undef PSHWPT
23	#undef SHWPTE
24	#undef PSHWPTE
25	#undef SHWPD
26	#undef PSHWPD
27	#undef SHWPDE
28	#undef PSHWPDE
29	#undef SHW_PDE_PG_MASK
30	#undef SHW_PD_SHIFT
31	#undef SHW_PD_MASK
32	#undef SHW_PTE_PG_MASK
33	#undef SHW_PT_SHIFT
34	#undef SHW_PT_MASK
35	#undef SHW_TOTAL_PD_ENTRIES
36	#undef SHW_PDPT_SHIFT
37	#undef SHW_PDPT_MASK
38	#undef SHW_PDPE_PG_MASK
39	#undef SHW_POOL_ROOT_IDX
40
41	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
42	# define SHWPT X86PT
43	# define PSHWPT PX86PT
44	# define SHWPTE X86PTE
45	# define PSHWPTE PX86PTE
46	# define SHWPD X86PD
47	# define PSHWPD PX86PD
48	# define SHWPDE X86PDE
49	# define PSHWPDE PX86PDE
50	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
51	# define SHW_PD_SHIFT X86_PD_SHIFT
52	# define SHW_PD_MASK X86_PD_MASK
53	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
54	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
55	# define SHW_PT_SHIFT X86_PT_SHIFT
56	# define SHW_PT_MASK X86_PT_MASK
57	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
58
59	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
60	# define SHWPT EPTPT
61	# define PSHWPT PEPTPT
62	# define SHWPTE EPTPTE
63	# define PSHWPTE PEPTPTE
64	# define SHWPD EPTPD
65	# define PSHWPD PEPTPD
66	# define SHWPDE EPTPDE
67	# define PSHWPDE PEPTPDE
68	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
69	# define SHW_PD_SHIFT EPT_PD_SHIFT
70	# define SHW_PD_MASK EPT_PD_MASK
71	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
72	# define SHW_PT_SHIFT EPT_PT_SHIFT
73	# define SHW_PT_MASK EPT_PT_MASK
74	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
75	# define SHW_PDPT_MASK EPT_PDPT_MASK
76	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
77	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
78	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
79
80	#else
81	# define SHWPT X86PTPAE
82	# define PSHWPT PX86PTPAE
83	# define SHWPTE X86PTEPAE
84	# define PSHWPTE PX86PTEPAE
85	# define SHWPD X86PDPAE
86	# define PSHWPD PX86PDPAE
87	# define SHWPDE X86PDEPAE
88	# define PSHWPDE PX86PDEPAE
89	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
90	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
91	# define SHW_PD_MASK X86_PD_PAE_MASK
92	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
93	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
94	# define SHW_PT_MASK X86_PT_PAE_MASK
95
96	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
97	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
98	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
99	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
100	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
101	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
102
103	# else /* 32 bits PAE mode */
104	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
105	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
106	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
107	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
108	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
109
110	# endif
111	#endif
112
113
114
115	/*******************************************************************************
116	* Internal Functions *
117	*******************************************************************************/
118	RT_C_DECLS_BEGIN
119	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags);
121	RT_C_DECLS_END
122
123
124
125	/**
126	* Gets effective page information (from the VMM page directory).
127	*
128	* @returns VBox status.
129	* @param pVCpu The VMCPU handle.
130	* @param GCPtr Guest Context virtual address of the page.
131	* @param pfFlags Where to store the flags. These are X86_PTE_*.
132	* @param pHCPhys Where to store the HC physical address of the page.
133	* This is page aligned.
134	* @remark You should use PGMMapGetPage() for pages in a mapping.
135	*/
136	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
137	{
138	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
139	return VERR_PAGE_TABLE_NOT_PRESENT;
140
141	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
142	PVM pVM = pVCpu->CTX_SUFF(pVM);
143
144	Assert(PGMIsLockOwner(pVM));
145
146	/*
147	* Get the PDE.
148	*/
149	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
150	X86PDEPAE Pde;
151
152	/* PML4 */
153	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
154	if (!Pml4e.n.u1Present)
155	return VERR_PAGE_TABLE_NOT_PRESENT;
156
157	/* PDPT */
158	PX86PDPT pPDPT;
159	int rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
160	if (RT_FAILURE(rc))
161	return rc;
162	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
163	X86PDPE Pdpe = pPDPT->a[iPDPT];
164	if (!Pdpe.n.u1Present)
165	return VERR_PAGE_TABLE_NOT_PRESENT;
166
167	/* PD */
168	PX86PDPAE pPd;
169	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
170	if (RT_FAILURE(rc))
171	return rc;
172	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
173	Pde = pPd->a[iPd];
174
175	/* Merge accessed, write, user and no-execute bits into the PDE. */
176	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
177	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
178	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
179	Pde.n.u1NoExecute \|= Pml4e.n.u1NoExecute \| Pdpe.lm.u1NoExecute;
180
181	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
182	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
183
184	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
185	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
186	PEPTPD pPDDst;
187	EPTPDE Pde;
188
189	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
190	if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
191	{
192	AssertRC(rc);
193	return rc;
194	}
195	Assert(pPDDst);
196	Pde = pPDDst->a[iPd];
197
198	# else /* PGM_TYPE_32BIT */
199	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
200	# endif
201	if (!Pde.n.u1Present)
202	return VERR_PAGE_TABLE_NOT_PRESENT;
203
204	/** Deal with large pages. */
205	if (Pde.b.u1Size)
206	{
207	/*
208	* Store the results.
209	* RW and US flags depend on the entire page translation hierarchy - except for
210	* legacy PAE which has a simplified PDPE.
211	*/
212	if (pfFlags)
213	{
214	*pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
215	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */
216	if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
217	*pfFlags \|= X86_PTE_PAE_NX;
218	# endif
219	}
220
221	if (pHCPhys)
222	*pHCPhys = (Pde.u & SHW_PDE_PG_MASK) + (GCPtr & (RT_BIT(SHW_PD_SHIFT) - 1) & X86_PAGE_4K_BASE_MASK);
223
224	return VINF_SUCCESS;
225	}
226
227	/*
228	* Get PT entry.
229	*/
230	PSHWPT pPT;
231	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
232	{
233	int rc2 = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
234	if (RT_FAILURE(rc2))
235	return rc2;
236	}
237	else /* mapping: */
238	{
239	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
240	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT
241	AssertFailed(); /* can't happen */
242	# else
243	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
244
245	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
246	AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_INTERNAL_ERROR);
247	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
248	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
249	# else /* PAE */
250	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
251	# endif
252	# endif
253	}
254	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
255	SHWPTE Pte = pPT->a[iPt];
256	if (!Pte.n.u1Present)
257	return VERR_PAGE_NOT_PRESENT;
258
259	/*
260	* Store the results.
261	* RW and US flags depend on the entire page translation hierarchy - except for
262	* legacy PAE which has a simplified PDPE.
263	*/
264	if (pfFlags)
265	{
266	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
267	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
268	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) /** @todo why do we have to check the guest state here? */
269	/* The NX bit is determined by a bitwise OR between the PT and PD */
270	if (((Pte.u \| Pde.u) & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
271	*pfFlags \|= X86_PTE_PAE_NX;
272	# endif
273	}
274
275	if (pHCPhys)
276	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
277
278	return VINF_SUCCESS;
279	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
280	}
281
282
283	/**
284	* Modify page flags for a range of pages in the shadow context.
285	*
286	* The existing flags are ANDed with the fMask and ORed with the fFlags.
287	*
288	* @returns VBox status code.
289	* @param pVCpu The VMCPU handle.
290	* @param GCPtr Virtual address of the first page in the range. Page aligned!
291	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
292	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
293	* @param fMask The AND mask - page flags X86_PTE_*.
294	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
295	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
296	* @remark You must use PGMMapModifyPage() for pages in a mapping.
297	*/
298	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
299	{
300	# if PGM_SHW_TYPE == PGM_TYPE_NESTED
301	return VERR_PAGE_TABLE_NOT_PRESENT;
302
303	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
304	PVM pVM = pVCpu->CTX_SUFF(pVM);
305	int rc;
306
307	Assert(PGMIsLockOwner(pVM));
308	/*
309	* Walk page tables and pages till we're done.
310	*/
311	for (;;)
312	{
313	/*
314	* Get the PDE.
315	*/
316	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
317	X86PDEPAE Pde;
318	/* PML4 */
319	X86PML4E Pml4e = pgmShwGetLongModePML4E(pVCpu, GCPtr);
320	if (!Pml4e.n.u1Present)
321	return VERR_PAGE_TABLE_NOT_PRESENT;
322
323	/* PDPT */
324	PX86PDPT pPDPT;
325	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
326	if (RT_FAILURE(rc))
327	return rc;
328	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
329	X86PDPE Pdpe = pPDPT->a[iPDPT];
330	if (!Pdpe.n.u1Present)
331	return VERR_PAGE_TABLE_NOT_PRESENT;
332
333	/* PD */
334	PX86PDPAE pPd;
335	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
336	if (RT_FAILURE(rc))
337	return rc;
338	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
339	Pde = pPd->a[iPd];
340
341	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
342	X86PDEPAE Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
343
344	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
345	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
346	PEPTPD pPDDst;
347	EPTPDE Pde;
348
349	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
350	if (rc != VINF_SUCCESS)
351	{
352	AssertRC(rc);
353	return rc;
354	}
355	Assert(pPDDst);
356	Pde = pPDDst->a[iPd];
357
358	# else /* PGM_TYPE_32BIT */
359	X86PDE Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
360	# endif
361	if (!Pde.n.u1Present)
362	return VERR_PAGE_TABLE_NOT_PRESENT;
363
364	AssertFatal(!Pde.b.u1Size);
365
366	/*
367	* Map the page table.
368	*/
369	PSHWPT pPT;
370	rc = PGM_HCPHYS_2_PTR(pVM, pVCpu, Pde.u & SHW_PDE_PG_MASK, &pPT);
371	if (RT_FAILURE(rc))
372	return rc;
373
374	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
375	while (iPTE < RT_ELEMENTS(pPT->a))
376	{
377	if (pPT->a[iPTE].n.u1Present)
378	{
379	SHWPTE const OrgPte = pPT->a[iPTE];
380	SHWPTE NewPte;
381
382	NewPte.u = (OrgPte.u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
383	Assert(NewPte.n.u1Present);
384	if (!NewPte.n.u1Present)
385	{
386	/** @todo Some CSAM code path might end up here and upset
387	* the page pool. */
388	AssertFailed();
389	}
390	else if ( NewPte.n.u1Write
391	&& !OrgPte.n.u1Write
392	&& !(fOpFlags & PGM_MK_PG_IS_MMIO2) )
393	{
394	/** @todo Optimize \#PF handling by caching data. We can
395	* then use this when PGM_MK_PG_IS_WRITE_FAULT is
396	* set instead of resolving the guest physical
397	* address yet again. */
398	RTGCPHYS GCPhys;
399	uint64_t fGstPte;
400	rc = PGMGstGetPage(pVCpu, GCPtr, &fGstPte, &GCPhys);
401	AssertRC(rc);
402	if (RT_SUCCESS(rc))
403	{
404	Assert(fGstPte & X86_PTE_RW);
405	PPGMPAGE pPage = pgmPhysGetPage(&pVCpu->CTX_SUFF(pVM)->pgm.s, GCPhys);
406	Assert(pPage);
407	if (pPage)
408	{
409	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
410	AssertRCReturn(rc, rc);
411	Log(("%s: pgmPhysPageMakeWritable on %RGv / %RGp %R[pgmpage]\n", __PRETTY_FUNCTION__, GCPtr, GCPhys, pPage));
412	}
413	}
414	}
415
416	ASMAtomicWriteSize(&pPT->a[iPTE], NewPte.u);
417	# if PGM_SHW_TYPE == PGM_TYPE_EPT
418	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
419	# else
420	PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
421	# endif
422	}
423
424	/* next page */
425	cb -= PAGE_SIZE;
426	if (!cb)
427	return VINF_SUCCESS;
428	GCPtr += PAGE_SIZE;
429	iPTE++;
430	}
431	}
432	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
433	}
434

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 31631

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