PGMAllPool.cpp@ 19807

Last change on this file since 19807 was 19795, checked in by vboxsync, 16 years ago
Extra assertion
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1	/* $Id: PGMAllPool.cpp 19795 2009-05-18 15:18:12Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pCpu The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pCpu->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pCpu->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pCpu->param1.flags & USE_REG_GEN32)
881	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pCpu The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pCpu->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_GUEST_TLBS();
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pCpu The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	Assert(pCpu->mode == CPUMODE_32BIT);
964
965	Log3(("pgmPoolAccessHandlerSTOSD\n"));
966
967	/*
968	* Increment the modification counter and insert it into the list
969	* of modified pages the first time.
970	*/
971	if (!pPage->cModifications++)
972	pgmPoolMonitorModifiedInsert(pPool, pPage);
973
974	/*
975	* Execute REP STOSD.
976	*
977	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
978	* write situation, meaning that it's safe to write here.
979	*/
980	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
981	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
982	while (pRegFrame->ecx)
983	{
984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
987	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
988	#else
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	#endif
991	#ifdef IN_RC
992	(uint32_t )pu32 = pRegFrame->eax;
993	#else
994	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
995	#endif
996	pu32 += 4;
997	GCPhysFault += 4;
998	pRegFrame->edi += 4;
999	pRegFrame->ecx--;
1000	}
1001	pRegFrame->rip += pCpu->opsize;
1002
1003	#ifdef IN_RC
1004	/* See use in pgmPoolAccessHandlerSimple(). */
1005	PGM_INVL_GUEST_TLBS();
1006	#endif
1007
1008	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Handles the simple write accesses.
1015	*
1016	* @returns VBox status code suitable for scheduling.
1017	* @param pVM The VM handle.
1018	* @param pVCpu The VMCPU handle.
1019	* @param pPool The pool.
1020	* @param pPage The pool page (head).
1021	* @param pCpu The disassembly of the write instruction.
1022	* @param pRegFrame The trap register frame.
1023	* @param GCPhysFault The fault address as guest physical address.
1024	* @param pvFault The fault address.
1025	*/
1026	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1027	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1028	{
1029	Log3(("pgmPoolAccessHandlerSimple\n"));
1030	/*
1031	* Increment the modification counter and insert it into the list
1032	* of modified pages the first time.
1033	*/
1034	if (!pPage->cModifications++)
1035	pgmPoolMonitorModifiedInsert(pPool, pPage);
1036
1037	/*
1038	* Clear all the pages. ASSUMES that pvFault is readable.
1039	*/
1040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1041	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1042	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1043	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1044	#else
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	#endif
1047
1048	/*
1049	* Interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc))
1054	pRegFrame->rip += pCpu->opsize;
1055	else if (rc == VERR_EM_INTERPRETER)
1056	{
1057	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1058	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1059	rc = VINF_EM_RAW_EMULATE_INSTR;
1060	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1061	}
1062
1063	#ifdef IN_RC
1064	/*
1065	* Quick hack, with logging enabled we're getting stale
1066	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1067	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1068	* have to be fixed to support this. But that'll have to wait till next week.
1069	*
1070	* An alternative is to keep track of the changed PTEs together with the
1071	* GCPhys from the guest PT. This may proove expensive though.
1072	*
1073	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1074	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1075	*/
1076	PGM_INVL_GUEST_TLBS();
1077	#endif
1078
1079	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1080	return rc;
1081	}
1082
1083	/**
1084	* \#PF Handler callback for PT write accesses.
1085	*
1086	* @returns VBox status code (appropriate for GC return).
1087	* @param pVM VM Handle.
1088	* @param uErrorCode CPU Error code.
1089	* @param pRegFrame Trap register frame.
1090	* NULL on DMA and other non CPU access.
1091	* @param pvFault The fault address (cr2).
1092	* @param GCPhysFault The GC physical address corresponding to pvFault.
1093	* @param pvUser User argument.
1094	*/
1095	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1096	{
1097	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1098	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1099	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1100	PVMCPU pVCpu = VMMGetCpu(pVM);
1101
1102	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1103
1104	/*
1105	* We should ALWAYS have the list head as user parameter. This
1106	* is because we use that page to record the changes.
1107	*/
1108	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1109
1110	/*
1111	* Disassemble the faulting instruction.
1112	*/
1113	DISCPUSTATE Cpu;
1114	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1115	AssertRCReturn(rc, rc);
1116
1117	pgmLock(pVM);
1118	AssertMsg(PHYS_PAGE_ADDRESS(GCPhysFault) == PHYS_PAGE_ADDRESS(pPage->GCPhys), ("%RGp vs %RGp\n", PHYS_PAGE_ADDRESS(GCPhysFault), pPage->GCPhys));
1119
1120	/*
1121	* Check if it's worth dealing with.
1122	*/
1123	bool fReused = false;
1124	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1125	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1126	)
1127	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
1128	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1129	{
1130	/*
1131	* Simple instructions, no REP prefix.
1132	*/
1133	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1134	{
1135	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1136	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1137	pgmUnlock(pVM);
1138	return rc;
1139	}
1140
1141	/*
1142	* Windows is frequently doing small memset() operations (netio test 4k+).
1143	* We have to deal with these or we'll kill the cache and performance.
1144	*/
1145	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1146	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1147	&& pRegFrame->ecx <= 0x20
1148	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1149	&& !((uintptr_t)pvFault & 3)
1150	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1151	&& Cpu.mode == CPUMODE_32BIT
1152	&& Cpu.opmode == CPUMODE_32BIT
1153	&& Cpu.addrmode == CPUMODE_32BIT
1154	&& Cpu.prefix == PREFIX_REP
1155	&& !pRegFrame->eflags.Bits.u1DF
1156	)
1157	{
1158	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1159	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1160	pgmUnlock(pVM);
1161	return rc;
1162	}
1163
1164	/* REP prefix, don't bother. */
1165	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1166	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1167	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1168	}
1169
1170	/*
1171	* Not worth it, so flush it.
1172	*
1173	* If we considered it to be reused, don't go back to ring-3
1174	* to emulate failed instructions since we usually cannot
1175	* interpret then. This may be a bit risky, in which case
1176	* the reuse detection must be fixed.
1177	*/
1178	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1179	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1180	rc = VINF_SUCCESS;
1181	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1182	pgmUnlock(pVM);
1183	return rc;
1184	}
1185
1186	# endif /* !IN_RING3 */
1187	#endif /* PGMPOOL_WITH_MONITORING */
1188
1189	#ifdef PGMPOOL_WITH_CACHE
1190
1191	/**
1192	* Inserts a page into the GCPhys hash table.
1193	*
1194	* @param pPool The pool.
1195	* @param pPage The page.
1196	*/
1197	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1198	{
1199	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1200	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1201	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1202	pPage->iNext = pPool->aiHash[iHash];
1203	pPool->aiHash[iHash] = pPage->idx;
1204	}
1205
1206
1207	/**
1208	* Removes a page from the GCPhys hash table.
1209	*
1210	* @param pPool The pool.
1211	* @param pPage The page.
1212	*/
1213	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1214	{
1215	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1216	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1217	if (pPool->aiHash[iHash] == pPage->idx)
1218	pPool->aiHash[iHash] = pPage->iNext;
1219	else
1220	{
1221	uint16_t iPrev = pPool->aiHash[iHash];
1222	for (;;)
1223	{
1224	const int16_t i = pPool->aPages[iPrev].iNext;
1225	if (i == pPage->idx)
1226	{
1227	pPool->aPages[iPrev].iNext = pPage->iNext;
1228	break;
1229	}
1230	if (i == NIL_PGMPOOL_IDX)
1231	{
1232	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1233	break;
1234	}
1235	iPrev = i;
1236	}
1237	}
1238	pPage->iNext = NIL_PGMPOOL_IDX;
1239	}
1240
1241
1242	/**
1243	* Frees up one cache page.
1244	*
1245	* @returns VBox status code.
1246	* @retval VINF_SUCCESS on success.
1247	* @param pPool The pool.
1248	* @param iUser The user index.
1249	*/
1250	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1251	{
1252	#ifndef IN_RC
1253	const PVM pVM = pPool->CTX_SUFF(pVM);
1254	#endif
1255	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1256	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1257
1258	/*
1259	* Select one page from the tail of the age list.
1260	*/
1261	PPGMPOOLPAGE pPage;
1262	for (unsigned iLoop = 0; ; iLoop++)
1263	{
1264	uint16_t iToFree = pPool->iAgeTail;
1265	if (iToFree == iUser)
1266	iToFree = pPool->aPages[iToFree].iAgePrev;
1267	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1268	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1269	{
1270	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1271	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1272	{
1273	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1274	continue;
1275	iToFree = i;
1276	break;
1277	}
1278	}
1279	*/
1280	Assert(iToFree != iUser);
1281	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1282	pPage = &pPool->aPages[iToFree];
1283
1284	/*
1285	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1286	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1287	*/
1288	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1289	break;
1290	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1291	pgmPoolCacheUsed(pPool, pPage);
1292	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1293	}
1294
1295	/*
1296	* Found a usable page, flush it and return.
1297	*/
1298	int rc = pgmPoolFlushPage(pPool, pPage);
1299	if (rc == VINF_SUCCESS)
1300	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1301	return rc;
1302	}
1303
1304
1305	/**
1306	* Checks if a kind mismatch is really a page being reused
1307	* or if it's just normal remappings.
1308	*
1309	* @returns true if reused and the cached page (enmKind1) should be flushed
1310	* @returns false if not reused.
1311	* @param enmKind1 The kind of the cached page.
1312	* @param enmKind2 The kind of the requested page.
1313	*/
1314	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1315	{
1316	switch (enmKind1)
1317	{
1318	/*
1319	* Never reuse them. There is no remapping in non-paging mode.
1320	*/
1321	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1322	case PGMPOOLKIND_32BIT_PD_PHYS:
1323	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1324	case PGMPOOLKIND_PAE_PD_PHYS:
1325	case PGMPOOLKIND_PAE_PDPT_PHYS:
1326	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1327	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1328	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1329	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1330	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1331	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1332	return false;
1333
1334	/*
1335	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1336	*/
1337	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1338	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1339	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1340	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1341	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1342	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1343	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1344	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1345	case PGMPOOLKIND_32BIT_PD:
1346	case PGMPOOLKIND_PAE_PDPT:
1347	switch (enmKind2)
1348	{
1349	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1350	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1351	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1352	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1353	case PGMPOOLKIND_64BIT_PML4:
1354	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1355	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1356	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1357	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1358	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1359	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1360	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1361	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1362	return true;
1363	default:
1364	return false;
1365	}
1366
1367	/*
1368	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1369	*/
1370	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1371	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1372	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1373	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1374	case PGMPOOLKIND_64BIT_PML4:
1375	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1376	switch (enmKind2)
1377	{
1378	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1379	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1380	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1381	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1382	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1383	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1384	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1386	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1387	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1388	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1389	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1390	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1391	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1392	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1393	return true;
1394	default:
1395	return false;
1396	}
1397
1398	/*
1399	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1400	*/
1401	case PGMPOOLKIND_ROOT_NESTED:
1402	return false;
1403
1404	default:
1405	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1406	}
1407	}
1408
1409
1410	/**
1411	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1412	*
1413	* @returns VBox status code.
1414	* @retval VINF_PGM_CACHED_PAGE on success.
1415	* @retval VERR_FILE_NOT_FOUND if not found.
1416	* @param pPool The pool.
1417	* @param GCPhys The GC physical address of the page we're gonna shadow.
1418	* @param enmKind The kind of mapping.
1419	* @param iUser The shadow page pool index of the user table.
1420	* @param iUserTable The index into the user table (shadowed).
1421	* @param ppPage Where to store the pointer to the page.
1422	*/
1423	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1424	{
1425	#ifndef IN_RC
1426	const PVM pVM = pPool->CTX_SUFF(pVM);
1427	#endif
1428	/*
1429	* Look up the GCPhys in the hash.
1430	*/
1431	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1432	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1433	if (i != NIL_PGMPOOL_IDX)
1434	{
1435	do
1436	{
1437	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1438	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1439	if (pPage->GCPhys == GCPhys)
1440	{
1441	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1442	{
1443	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1444	* doesn't flush it in case there are no more free use records.
1445	*/
1446	pgmPoolCacheUsed(pPool, pPage);
1447
1448	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1449	if (RT_SUCCESS(rc))
1450	{
1451	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1452	*ppPage = pPage;
1453	STAM_COUNTER_INC(&pPool->StatCacheHits);
1454	return VINF_PGM_CACHED_PAGE;
1455	}
1456	return rc;
1457	}
1458
1459	/*
1460	* The kind is different. In some cases we should now flush the page
1461	* as it has been reused, but in most cases this is normal remapping
1462	* of PDs as PT or big pages using the GCPhys field in a slightly
1463	* different way than the other kinds.
1464	*/
1465	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1466	{
1467	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1468	pgmPoolFlushPage(pPool, pPage);
1469	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1470	break;
1471	}
1472	}
1473
1474	/* next */
1475	i = pPage->iNext;
1476	} while (i != NIL_PGMPOOL_IDX);
1477	}
1478
1479	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1480	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1481	return VERR_FILE_NOT_FOUND;
1482	}
1483
1484
1485	/**
1486	* Inserts a page into the cache.
1487	*
1488	* @param pPool The pool.
1489	* @param pPage The cached page.
1490	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1491	*/
1492	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1493	{
1494	/*
1495	* Insert into the GCPhys hash if the page is fit for that.
1496	*/
1497	Assert(!pPage->fCached);
1498	if (fCanBeCached)
1499	{
1500	pPage->fCached = true;
1501	pgmPoolHashInsert(pPool, pPage);
1502	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1503	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1504	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1505	}
1506	else
1507	{
1508	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1509	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1510	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1511	}
1512
1513	/*
1514	* Insert at the head of the age list.
1515	*/
1516	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1517	pPage->iAgeNext = pPool->iAgeHead;
1518	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1519	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1520	else
1521	pPool->iAgeTail = pPage->idx;
1522	pPool->iAgeHead = pPage->idx;
1523	}
1524
1525
1526	/**
1527	* Flushes a cached page.
1528	*
1529	* @param pPool The pool.
1530	* @param pPage The cached page.
1531	*/
1532	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1533	{
1534	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1535
1536	/*
1537	* Remove the page from the hash.
1538	*/
1539	if (pPage->fCached)
1540	{
1541	pPage->fCached = false;
1542	pgmPoolHashRemove(pPool, pPage);
1543	}
1544	else
1545	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1546
1547	/*
1548	* Remove it from the age list.
1549	*/
1550	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1551	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1552	else
1553	pPool->iAgeTail = pPage->iAgePrev;
1554	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1555	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1556	else
1557	pPool->iAgeHead = pPage->iAgeNext;
1558	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1559	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1560	}
1561
1562	#endif /* PGMPOOL_WITH_CACHE */
1563	#ifdef PGMPOOL_WITH_MONITORING
1564
1565	/**
1566	* Looks for pages sharing the monitor.
1567	*
1568	* @returns Pointer to the head page.
1569	* @returns NULL if not found.
1570	* @param pPool The Pool
1571	* @param pNewPage The page which is going to be monitored.
1572	*/
1573	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1574	{
1575	#ifdef PGMPOOL_WITH_CACHE
1576	/*
1577	* Look up the GCPhys in the hash.
1578	*/
1579	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1580	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1581	if (i == NIL_PGMPOOL_IDX)
1582	return NULL;
1583	do
1584	{
1585	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1586	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1587	&& pPage != pNewPage)
1588	{
1589	switch (pPage->enmKind)
1590	{
1591	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1592	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1593	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1594	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1595	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1596	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1597	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1598	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1599	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1600	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1601	case PGMPOOLKIND_64BIT_PML4:
1602	case PGMPOOLKIND_32BIT_PD:
1603	case PGMPOOLKIND_PAE_PDPT:
1604	{
1605	/* find the head */
1606	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1607	{
1608	Assert(pPage->iMonitoredPrev != pPage->idx);
1609	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1610	}
1611	return pPage;
1612	}
1613
1614	/* ignore, no monitoring. */
1615	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1616	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1617	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1618	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1619	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1620	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1621	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1622	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1623	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1624	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1625	case PGMPOOLKIND_ROOT_NESTED:
1626	case PGMPOOLKIND_PAE_PD_PHYS:
1627	case PGMPOOLKIND_PAE_PDPT_PHYS:
1628	case PGMPOOLKIND_32BIT_PD_PHYS:
1629	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1630	break;
1631	default:
1632	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1633	}
1634	}
1635
1636	/* next */
1637	i = pPage->iNext;
1638	} while (i != NIL_PGMPOOL_IDX);
1639	#endif
1640	return NULL;
1641	}
1642
1643
1644	/**
1645	* Enabled write monitoring of a guest page.
1646	*
1647	* @returns VBox status code.
1648	* @retval VINF_SUCCESS on success.
1649	* @param pPool The pool.
1650	* @param pPage The cached page.
1651	*/
1652	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1653	{
1654	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1655
1656	/*
1657	* Filter out the relevant kinds.
1658	*/
1659	switch (pPage->enmKind)
1660	{
1661	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1662	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1663	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1664	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1665	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1666	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1667	case PGMPOOLKIND_64BIT_PML4:
1668	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1669	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1670	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1671	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1672	case PGMPOOLKIND_32BIT_PD:
1673	case PGMPOOLKIND_PAE_PDPT:
1674	break;
1675
1676	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1677	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1678	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1679	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1680	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1681	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1682	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1683	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1684	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1685	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1686	case PGMPOOLKIND_ROOT_NESTED:
1687	/* Nothing to monitor here. */
1688	return VINF_SUCCESS;
1689
1690	case PGMPOOLKIND_32BIT_PD_PHYS:
1691	case PGMPOOLKIND_PAE_PDPT_PHYS:
1692	case PGMPOOLKIND_PAE_PD_PHYS:
1693	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1694	/* Nothing to monitor here. */
1695	return VINF_SUCCESS;
1696	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1697	break;
1698	#else
1699	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1700	#endif
1701	default:
1702	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1703	}
1704
1705	/*
1706	* Install handler.
1707	*/
1708	int rc;
1709	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1710	if (pPageHead)
1711	{
1712	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1713	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1714	pPage->iMonitoredPrev = pPageHead->idx;
1715	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1716	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1717	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1718	pPageHead->iMonitoredNext = pPage->idx;
1719	rc = VINF_SUCCESS;
1720	}
1721	else
1722	{
1723	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1724	PVM pVM = pPool->CTX_SUFF(pVM);
1725	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1726	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1727	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1728	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1729	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1730	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1731	pPool->pszAccessHandler);
1732	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1733	* the heap size should suffice. */
1734	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1735	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1736	}
1737	pPage->fMonitored = true;
1738	return rc;
1739	}
1740
1741
1742	/**
1743	* Disables write monitoring of a guest page.
1744	*
1745	* @returns VBox status code.
1746	* @retval VINF_SUCCESS on success.
1747	* @param pPool The pool.
1748	* @param pPage The cached page.
1749	*/
1750	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1751	{
1752	/*
1753	* Filter out the relevant kinds.
1754	*/
1755	switch (pPage->enmKind)
1756	{
1757	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1758	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1759	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1760	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1761	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1762	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1763	case PGMPOOLKIND_64BIT_PML4:
1764	case PGMPOOLKIND_32BIT_PD:
1765	case PGMPOOLKIND_PAE_PDPT:
1766	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1767	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1768	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1769	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1770	break;
1771
1772	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1773	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1774	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1775	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1776	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1777	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1778	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1779	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1780	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1781	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1782	case PGMPOOLKIND_ROOT_NESTED:
1783	case PGMPOOLKIND_PAE_PD_PHYS:
1784	case PGMPOOLKIND_PAE_PDPT_PHYS:
1785	case PGMPOOLKIND_32BIT_PD_PHYS:
1786	/* Nothing to monitor here. */
1787	return VINF_SUCCESS;
1788
1789	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1790	break;
1791	#endif
1792	default:
1793	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1794	}
1795
1796	/*
1797	* Remove the page from the monitored list or uninstall it if last.
1798	*/
1799	const PVM pVM = pPool->CTX_SUFF(pVM);
1800	int rc;
1801	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1802	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1803	{
1804	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1805	{
1806	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1807	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1808	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1809	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1810	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1811	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1812	pPool->pszAccessHandler);
1813	AssertFatalRCSuccess(rc);
1814	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1815	}
1816	else
1817	{
1818	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1819	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1820	{
1821	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1822	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1823	}
1824	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1825	rc = VINF_SUCCESS;
1826	}
1827	}
1828	else
1829	{
1830	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1831	AssertFatalRC(rc);
1832	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1833	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1834	}
1835	pPage->fMonitored = false;
1836
1837	/*
1838	* Remove it from the list of modified pages (if in it).
1839	*/
1840	pgmPoolMonitorModifiedRemove(pPool, pPage);
1841
1842	return rc;
1843	}
1844
1845
1846	/**
1847	* Inserts the page into the list of modified pages.
1848	*
1849	* @param pPool The pool.
1850	* @param pPage The page.
1851	*/
1852	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1853	{
1854	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1855	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1856	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1857	&& pPool->iModifiedHead != pPage->idx,
1858	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1859	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1860	pPool->iModifiedHead, pPool->cModifiedPages));
1861
1862	pPage->iModifiedNext = pPool->iModifiedHead;
1863	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1864	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1865	pPool->iModifiedHead = pPage->idx;
1866	pPool->cModifiedPages++;
1867	#ifdef VBOX_WITH_STATISTICS
1868	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1869	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1870	#endif
1871	}
1872
1873
1874	/**
1875	* Removes the page from the list of modified pages and resets the
1876	* moficiation counter.
1877	*
1878	* @param pPool The pool.
1879	* @param pPage The page which is believed to be in the list of modified pages.
1880	*/
1881	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1882	{
1883	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1884	if (pPool->iModifiedHead == pPage->idx)
1885	{
1886	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1887	pPool->iModifiedHead = pPage->iModifiedNext;
1888	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1889	{
1890	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1891	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1892	}
1893	pPool->cModifiedPages--;
1894	}
1895	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1896	{
1897	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1898	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1899	{
1900	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1901	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1902	}
1903	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1904	pPool->cModifiedPages--;
1905	}
1906	else
1907	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1908	pPage->cModifications = 0;
1909	}
1910
1911
1912	/**
1913	* Zaps the list of modified pages, resetting their modification counters in the process.
1914	*
1915	* @param pVM The VM handle.
1916	*/
1917	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1918	{
1919	pgmLock(pVM);
1920	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1921	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1922
1923	unsigned cPages = 0; NOREF(cPages);
1924	uint16_t idx = pPool->iModifiedHead;
1925	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1926	while (idx != NIL_PGMPOOL_IDX)
1927	{
1928	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1929	idx = pPage->iModifiedNext;
1930	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1931	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1932	pPage->cModifications = 0;
1933	Assert(++cPages);
1934	}
1935	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1936	pPool->cModifiedPages = 0;
1937	pgmUnlock(pVM);
1938	}
1939
1940
1941	#ifdef IN_RING3
1942	/**
1943	* Callback to clear all shadow pages and clear all modification counters.
1944	*
1945	* @returns VBox status code.
1946	* @param pVM The VM handle.
1947	* @param pvUser Unused parameter
1948	* @remark Should only be used when monitoring is available, thus placed in
1949	* the PGMPOOL_WITH_MONITORING #ifdef.
1950	*/
1951	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1952	{
1953	NOREF(pvUser);
1954	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1955	STAM_PROFILE_START(&pPool->StatClearAll, c);
1956	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1957
1958	pgmLock(pVM);
1959
1960	/*
1961	* Iterate all the pages until we've encountered all that in use.
1962	* This is simple but not quite optimal solution.
1963	*/
1964	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1965	unsigned cLeft = pPool->cUsedPages;
1966	unsigned iPage = pPool->cCurPages;
1967	while (--iPage >= PGMPOOL_IDX_FIRST)
1968	{
1969	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1970	if (pPage->GCPhys != NIL_RTGCPHYS)
1971	{
1972	switch (pPage->enmKind)
1973	{
1974	/*
1975	* We only care about shadow page tables.
1976	*/
1977	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1978	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1979	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1980	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1981	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1982	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1983	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1984	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1985	{
1986	#ifdef PGMPOOL_WITH_USER_TRACKING
1987	if (pPage->cPresent)
1988	#endif
1989	{
1990	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1991	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1992	ASMMemZeroPage(pvShw);
1993	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1994	#ifdef PGMPOOL_WITH_USER_TRACKING
1995	pPage->cPresent = 0;
1996	pPage->iFirstPresent = ~0;
1997	#endif
1998	}
1999	}
2000	/* fall thru */
2001
2002	default:
2003	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2004	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2005	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2006	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2007	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2008	pPage->cModifications = 0;
2009	break;
2010
2011	}
2012	if (!--cLeft)
2013	break;
2014	}
2015	}
2016
2017	/* swipe the special pages too. */
2018	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2019	{
2020	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2021	if (pPage->GCPhys != NIL_RTGCPHYS)
2022	{
2023	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2024	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2025	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2026	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2027	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2028	pPage->cModifications = 0;
2029	}
2030	}
2031
2032	#ifndef DEBUG_michael
2033	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2034	#endif
2035	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2036	pPool->cModifiedPages = 0;
2037
2038	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2039	/*
2040	* Clear all the GCPhys links and rebuild the phys ext free list.
2041	*/
2042	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2043	pRam;
2044	pRam = pRam->CTX_SUFF(pNext))
2045	{
2046	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2047	while (iPage-- > 0)
2048	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2049	}
2050
2051	pPool->iPhysExtFreeHead = 0;
2052	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2053	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2054	for (unsigned i = 0; i < cMaxPhysExts; i++)
2055	{
2056	paPhysExts[i].iNext = i + 1;
2057	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2058	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2059	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2060	}
2061	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2062	#endif
2063
2064	pPool->cPresent = 0;
2065	pgmUnlock(pVM);
2066	PGM_INVL_GUEST_TLBS();
2067	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2068	return VINF_SUCCESS;
2069	}
2070	#endif /* IN_RING3 */
2071
2072
2073	/**
2074	* Handle SyncCR3 pool tasks
2075	*
2076	* @returns VBox status code.
2077	* @retval VINF_SUCCESS if successfully added.
2078	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2079	* @param pVM The VM handle.
2080	* @remark Should only be used when monitoring is available, thus placed in
2081	* the PGMPOOL_WITH_MONITORING #ifdef.
2082	*/
2083	int pgmPoolSyncCR3(PVM pVM)
2084	{
2085	LogFlow(("pgmPoolSyncCR3\n"));
2086	/*
2087	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2088	* Occasionally we will have to clear all the shadow page tables because we wanted
2089	* to monitor a page which was mapped by too many shadowed page tables. This operation
2090	* sometimes refered to as a 'lightweight flush'.
2091	*/
2092	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2093	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2094	{
2095	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2096	# else /* !IN_RING3 */
2097	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2098	{
2099	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2100	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2101	return VINF_PGM_SYNC_CR3;
2102	# endif /* !IN_RING3 */
2103	}
2104	else
2105	pgmPoolMonitorModifiedClearAll(pVM);
2106
2107	return VINF_SUCCESS;
2108	}
2109
2110	#endif /* PGMPOOL_WITH_MONITORING */
2111	#ifdef PGMPOOL_WITH_USER_TRACKING
2112
2113	/**
2114	* Frees up at least one user entry.
2115	*
2116	* @returns VBox status code.
2117	* @retval VINF_SUCCESS if successfully added.
2118	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2119	* @param pPool The pool.
2120	* @param iUser The user index.
2121	*/
2122	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2123	{
2124	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2125	#ifdef PGMPOOL_WITH_CACHE
2126	/*
2127	* Just free cached pages in a braindead fashion.
2128	*/
2129	/** @todo walk the age list backwards and free the first with usage. */
2130	int rc = VINF_SUCCESS;
2131	do
2132	{
2133	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2134	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2135	rc = rc2;
2136	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2137	return rc;
2138	#else
2139	/*
2140	* Lazy approach.
2141	*/
2142	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2143	AssertCompileFailed();
2144	Assert(!CPUMIsGuestInLongMode(pVM));
2145	pgmPoolFlushAllInt(pPool);
2146	return VERR_PGM_POOL_FLUSHED;
2147	#endif
2148	}
2149
2150
2151	/**
2152	* Inserts a page into the cache.
2153	*
2154	* This will create user node for the page, insert it into the GCPhys
2155	* hash, and insert it into the age list.
2156	*
2157	* @returns VBox status code.
2158	* @retval VINF_SUCCESS if successfully added.
2159	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2160	* @param pPool The pool.
2161	* @param pPage The cached page.
2162	* @param GCPhys The GC physical address of the page we're gonna shadow.
2163	* @param iUser The user index.
2164	* @param iUserTable The user table index.
2165	*/
2166	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2167	{
2168	int rc = VINF_SUCCESS;
2169	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2170
2171	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2172
2173	#ifdef VBOX_STRICT
2174	/*
2175	* Check that the entry doesn't already exists.
2176	*/
2177	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2178	{
2179	uint16_t i = pPage->iUserHead;
2180	do
2181	{
2182	Assert(i < pPool->cMaxUsers);
2183	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2184	i = paUsers[i].iNext;
2185	} while (i != NIL_PGMPOOL_USER_INDEX);
2186	}
2187	#endif
2188
2189	/*
2190	* Find free a user node.
2191	*/
2192	uint16_t i = pPool->iUserFreeHead;
2193	if (i == NIL_PGMPOOL_USER_INDEX)
2194	{
2195	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2196	if (RT_FAILURE(rc))
2197	return rc;
2198	i = pPool->iUserFreeHead;
2199	}
2200
2201	/*
2202	* Unlink the user node from the free list,
2203	* initialize and insert it into the user list.
2204	*/
2205	pPool->iUserFreeHead = paUsers[i].iNext;
2206	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2207	paUsers[i].iUser = iUser;
2208	paUsers[i].iUserTable = iUserTable;
2209	pPage->iUserHead = i;
2210
2211	/*
2212	* Insert into cache and enable monitoring of the guest page if enabled.
2213	*
2214	* Until we implement caching of all levels, including the CR3 one, we'll
2215	* have to make sure we don't try monitor & cache any recursive reuse of
2216	* a monitored CR3 page. Because all windows versions are doing this we'll
2217	* have to be able to do combined access monitoring, CR3 + PT and
2218	* PD + PT (guest PAE).
2219	*
2220	* Update:
2221	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2222	*/
2223	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2224	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2225	const bool fCanBeMonitored = true;
2226	# else
2227	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2228	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2229	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2230	# endif
2231	# ifdef PGMPOOL_WITH_CACHE
2232	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2233	# endif
2234	if (fCanBeMonitored)
2235	{
2236	# ifdef PGMPOOL_WITH_MONITORING
2237	rc = pgmPoolMonitorInsert(pPool, pPage);
2238	AssertRC(rc);
2239	}
2240	# endif
2241	#endif /* PGMPOOL_WITH_MONITORING */
2242	return rc;
2243	}
2244
2245
2246	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2247	/**
2248	* Adds a user reference to a page.
2249	*
2250	* This will move the page to the head of the
2251	*
2252	* @returns VBox status code.
2253	* @retval VINF_SUCCESS if successfully added.
2254	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2255	* @param pPool The pool.
2256	* @param pPage The cached page.
2257	* @param iUser The user index.
2258	* @param iUserTable The user table.
2259	*/
2260	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2261	{
2262	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2263
2264	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2265
2266	# ifdef VBOX_STRICT
2267	/*
2268	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2269	*/
2270	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2271	{
2272	uint16_t i = pPage->iUserHead;
2273	do
2274	{
2275	Assert(i < pPool->cMaxUsers);
2276	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2277	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2278	i = paUsers[i].iNext;
2279	} while (i != NIL_PGMPOOL_USER_INDEX);
2280	}
2281	# endif
2282
2283	/*
2284	* Allocate a user node.
2285	*/
2286	uint16_t i = pPool->iUserFreeHead;
2287	if (i == NIL_PGMPOOL_USER_INDEX)
2288	{
2289	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2290	if (RT_FAILURE(rc))
2291	return rc;
2292	i = pPool->iUserFreeHead;
2293	}
2294	pPool->iUserFreeHead = paUsers[i].iNext;
2295
2296	/*
2297	* Initialize the user node and insert it.
2298	*/
2299	paUsers[i].iNext = pPage->iUserHead;
2300	paUsers[i].iUser = iUser;
2301	paUsers[i].iUserTable = iUserTable;
2302	pPage->iUserHead = i;
2303
2304	# ifdef PGMPOOL_WITH_CACHE
2305	/*
2306	* Tell the cache to update its replacement stats for this page.
2307	*/
2308	pgmPoolCacheUsed(pPool, pPage);
2309	# endif
2310	return VINF_SUCCESS;
2311	}
2312	# endif /* PGMPOOL_WITH_CACHE */
2313
2314
2315	/**
2316	* Frees a user record associated with a page.
2317	*
2318	* This does not clear the entry in the user table, it simply replaces the
2319	* user record to the chain of free records.
2320	*
2321	* @param pPool The pool.
2322	* @param HCPhys The HC physical address of the shadow page.
2323	* @param iUser The shadow page pool index of the user table.
2324	* @param iUserTable The index into the user table (shadowed).
2325	*/
2326	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2327	{
2328	/*
2329	* Unlink and free the specified user entry.
2330	*/
2331	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2332
2333	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2334	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2335	uint16_t i = pPage->iUserHead;
2336	if ( i != NIL_PGMPOOL_USER_INDEX
2337	&& paUsers[i].iUser == iUser
2338	&& paUsers[i].iUserTable == iUserTable)
2339	{
2340	pPage->iUserHead = paUsers[i].iNext;
2341
2342	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2343	paUsers[i].iNext = pPool->iUserFreeHead;
2344	pPool->iUserFreeHead = i;
2345	return;
2346	}
2347
2348	/* General: Linear search. */
2349	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2350	while (i != NIL_PGMPOOL_USER_INDEX)
2351	{
2352	if ( paUsers[i].iUser == iUser
2353	&& paUsers[i].iUserTable == iUserTable)
2354	{
2355	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2356	paUsers[iPrev].iNext = paUsers[i].iNext;
2357	else
2358	pPage->iUserHead = paUsers[i].iNext;
2359
2360	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2361	paUsers[i].iNext = pPool->iUserFreeHead;
2362	pPool->iUserFreeHead = i;
2363	return;
2364	}
2365	iPrev = i;
2366	i = paUsers[i].iNext;
2367	}
2368
2369	/* Fatal: didn't find it */
2370	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2371	iUser, iUserTable, pPage->GCPhys));
2372	}
2373
2374
2375	/**
2376	* Gets the entry size of a shadow table.
2377	*
2378	* @param enmKind The kind of page.
2379	*
2380	* @returns The size of the entry in bytes. That is, 4 or 8.
2381	* @returns If the kind is not for a table, an assertion is raised and 0 is
2382	* returned.
2383	*/
2384	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2385	{
2386	switch (enmKind)
2387	{
2388	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2389	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2390	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2391	case PGMPOOLKIND_32BIT_PD:
2392	case PGMPOOLKIND_32BIT_PD_PHYS:
2393	return 4;
2394
2395	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2396	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2397	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2398	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2399	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2400	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2401	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2402	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2403	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2404	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2405	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2406	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2407	case PGMPOOLKIND_64BIT_PML4:
2408	case PGMPOOLKIND_PAE_PDPT:
2409	case PGMPOOLKIND_ROOT_NESTED:
2410	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2411	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2412	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2413	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2414	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2415	case PGMPOOLKIND_PAE_PD_PHYS:
2416	case PGMPOOLKIND_PAE_PDPT_PHYS:
2417	return 8;
2418
2419	default:
2420	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2421	}
2422	}
2423
2424
2425	/**
2426	* Gets the entry size of a guest table.
2427	*
2428	* @param enmKind The kind of page.
2429	*
2430	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2431	* @returns If the kind is not for a table, an assertion is raised and 0 is
2432	* returned.
2433	*/
2434	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2435	{
2436	switch (enmKind)
2437	{
2438	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2439	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2440	case PGMPOOLKIND_32BIT_PD:
2441	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2442	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2443	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2444	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2445	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2447	return 4;
2448
2449	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2450	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2451	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2452	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2453	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2454	case PGMPOOLKIND_64BIT_PML4:
2455	case PGMPOOLKIND_PAE_PDPT:
2456	return 8;
2457
2458	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2459	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2460	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2461	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2462	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2463	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2464	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2465	case PGMPOOLKIND_ROOT_NESTED:
2466	case PGMPOOLKIND_PAE_PD_PHYS:
2467	case PGMPOOLKIND_PAE_PDPT_PHYS:
2468	case PGMPOOLKIND_32BIT_PD_PHYS:
2469	/** @todo can we return 0? (nobody is calling this...) */
2470	AssertFailed();
2471	return 0;
2472
2473	default:
2474	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2475	}
2476	}
2477
2478	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2479
2480	/**
2481	* Scans one shadow page table for mappings of a physical page.
2482	*
2483	* @param pVM The VM handle.
2484	* @param pPhysPage The guest page in question.
2485	* @param iShw The shadow page table.
2486	* @param cRefs The number of references made in that PT.
2487	*/
2488	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2489	{
2490	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2491	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2492
2493	/*
2494	* Assert sanity.
2495	*/
2496	Assert(cRefs == 1);
2497	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2498	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2499
2500	/*
2501	* Then, clear the actual mappings to the page in the shadow PT.
2502	*/
2503	switch (pPage->enmKind)
2504	{
2505	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2506	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2507	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2508	{
2509	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2510	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2511	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2512	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2513	{
2514	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2515	pPT->a[i].u = 0;
2516	cRefs--;
2517	if (!cRefs)
2518	return;
2519	}
2520	#ifdef LOG_ENABLED
2521	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2522	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2523	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2524	{
2525	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2526	pPT->a[i].u = 0;
2527	}
2528	#endif
2529	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2530	break;
2531	}
2532
2533	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2534	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2535	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2536	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2537	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2538	{
2539	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2540	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2541	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2542	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2543	{
2544	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2545	pPT->a[i].u = 0;
2546	cRefs--;
2547	if (!cRefs)
2548	return;
2549	}
2550	#ifdef LOG_ENABLED
2551	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2552	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2553	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2554	{
2555	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2556	pPT->a[i].u = 0;
2557	}
2558	#endif
2559	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2560	break;
2561	}
2562
2563	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2564	{
2565	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2566	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2567	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2568	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2569	{
2570	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2571	pPT->a[i].u = 0;
2572	cRefs--;
2573	if (!cRefs)
2574	return;
2575	}
2576	#ifdef LOG_ENABLED
2577	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2578	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2579	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2580	{
2581	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2582	pPT->a[i].u = 0;
2583	}
2584	#endif
2585	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2586	break;
2587	}
2588
2589	default:
2590	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2591	}
2592	}
2593
2594
2595	/**
2596	* Scans one shadow page table for mappings of a physical page.
2597	*
2598	* @param pVM The VM handle.
2599	* @param pPhysPage The guest page in question.
2600	* @param iShw The shadow page table.
2601	* @param cRefs The number of references made in that PT.
2602	*/
2603	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2604	{
2605	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2606	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2607	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2608	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2609	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2610	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2611	}
2612
2613
2614	/**
2615	* Flushes a list of shadow page tables mapping the same physical page.
2616	*
2617	* @param pVM The VM handle.
2618	* @param pPhysPage The guest page in question.
2619	* @param iPhysExt The physical cross reference extent list to flush.
2620	*/
2621	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2622	{
2623	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2624	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2625	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2626
2627	const uint16_t iPhysExtStart = iPhysExt;
2628	PPGMPOOLPHYSEXT pPhysExt;
2629	do
2630	{
2631	Assert(iPhysExt < pPool->cMaxPhysExts);
2632	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2633	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2634	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2635	{
2636	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2637	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2638	}
2639
2640	/* next */
2641	iPhysExt = pPhysExt->iNext;
2642	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2643
2644	/* insert the list into the free list and clear the ram range entry. */
2645	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2646	pPool->iPhysExtFreeHead = iPhysExtStart;
2647	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2648
2649	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2650	}
2651
2652	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2653
2654	/**
2655	* Flushes all shadow page table mappings of the given guest page.
2656	*
2657	* This is typically called when the host page backing the guest one has been
2658	* replaced or when the page protection was changed due to an access handler.
2659	*
2660	* @returns VBox status code.
2661	* @retval VINF_SUCCESS if all references has been successfully cleared.
2662	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2663	* pool cleaning. FF and sync flags are set.
2664	*
2665	* @param pVM The VM handle.
2666	* @param pPhysPage The guest page in question.
2667	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2668	* flushed, it is NOT touched if this isn't necessary.
2669	* The caller MUST initialized this to @a false.
2670	*/
2671	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2672	{
2673	pgmLock(pVM);
2674	int rc = VINF_SUCCESS;
2675	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2676	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2677	if (u16)
2678	{
2679	/*
2680	* The zero page is currently screwing up the tracking and we'll
2681	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2682	* is defined, zero pages won't normally be mapped. Some kind of solution
2683	* will be needed for this problem of course, but it will have to wait...
2684	*/
2685	if (PGM_PAGE_IS_ZERO(pPhysPage))
2686	rc = VINF_PGM_GCPHYS_ALIASED;
2687	else
2688	{
2689	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2690	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2691	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2692	PVMCPU pVCpu = VMMGetCpu(pVM);
2693	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2694	# endif
2695
2696	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2697	pgmPoolTrackFlushGCPhysPT(pVM,
2698	pPhysPage,
2699	PGMPOOL_TD_GET_IDX(u16),
2700	PGMPOOL_TD_GET_CREFS(u16));
2701	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2702	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2703	else
2704	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2705	*pfFlushTLBs = true;
2706
2707	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2708	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2709	# endif
2710	}
2711	}
2712
2713	#elif defined(PGMPOOL_WITH_CACHE)
2714	if (PGM_PAGE_IS_ZERO(pPhysPage))
2715	rc = VINF_PGM_GCPHYS_ALIASED;
2716	else
2717	{
2718	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2719	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2720	PVMCPU pVCpu = VMMGetCpu(pVM);
2721	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2722	# endif
2723	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2724	if (rc == VINF_SUCCESS)
2725	*pfFlushTLBs = true;
2726	}
2727
2728	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2729	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2730	# endif
2731
2732	#else
2733	rc = VINF_PGM_GCPHYS_ALIASED;
2734	#endif
2735
2736	if (rc == VINF_PGM_GCPHYS_ALIASED)
2737	{
2738	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2739	for (unsigned i=0;i<pVM->cCPUs;i++)
2740	{
2741	PVMCPU pVCpu = &pVM->aCpus[i];
2742	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2743	}
2744	rc = VINF_PGM_SYNC_CR3;
2745	}
2746	pgmUnlock(pVM);
2747	return rc;
2748	}
2749
2750
2751	/**
2752	* Scans all shadow page tables for mappings of a physical page.
2753	*
2754	* This may be slow, but it's most likely more efficient than cleaning
2755	* out the entire page pool / cache.
2756	*
2757	* @returns VBox status code.
2758	* @retval VINF_SUCCESS if all references has been successfully cleared.
2759	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2760	* a page pool cleaning.
2761	*
2762	* @param pVM The VM handle.
2763	* @param pPhysPage The guest page in question.
2764	*/
2765	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2766	{
2767	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2768	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2769	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2770	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2771
2772	#if 1
2773	/*
2774	* There is a limit to what makes sense.
2775	*/
2776	if (pPool->cPresent > 1024)
2777	{
2778	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2779	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2780	return VINF_PGM_GCPHYS_ALIASED;
2781	}
2782	#endif
2783
2784	/*
2785	* Iterate all the pages until we've encountered all that in use.
2786	* This is simple but not quite optimal solution.
2787	*/
2788	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2789	const uint32_t u32 = u64;
2790	unsigned cLeft = pPool->cUsedPages;
2791	unsigned iPage = pPool->cCurPages;
2792	while (--iPage >= PGMPOOL_IDX_FIRST)
2793	{
2794	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2795	if (pPage->GCPhys != NIL_RTGCPHYS)
2796	{
2797	switch (pPage->enmKind)
2798	{
2799	/*
2800	* We only care about shadow page tables.
2801	*/
2802	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2803	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2804	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2805	{
2806	unsigned cPresent = pPage->cPresent;
2807	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2808	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2809	if (pPT->a[i].n.u1Present)
2810	{
2811	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2812	{
2813	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2814	pPT->a[i].u = 0;
2815	}
2816	if (!--cPresent)
2817	break;
2818	}
2819	break;
2820	}
2821
2822	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2823	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2824	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2825	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2826	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2827	{
2828	unsigned cPresent = pPage->cPresent;
2829	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2830	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2831	if (pPT->a[i].n.u1Present)
2832	{
2833	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2834	{
2835	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2836	pPT->a[i].u = 0;
2837	}
2838	if (!--cPresent)
2839	break;
2840	}
2841	break;
2842	}
2843	}
2844	if (!--cLeft)
2845	break;
2846	}
2847	}
2848
2849	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2850	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2851	return VINF_SUCCESS;
2852	}
2853
2854
2855	/**
2856	* Clears the user entry in a user table.
2857	*
2858	* This is used to remove all references to a page when flushing it.
2859	*/
2860	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2861	{
2862	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2863	Assert(pUser->iUser < pPool->cCurPages);
2864	uint32_t iUserTable = pUser->iUserTable;
2865
2866	/*
2867	* Map the user page.
2868	*/
2869	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2870	union
2871	{
2872	uint64_t *pau64;
2873	uint32_t *pau32;
2874	} u;
2875	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2876
2877	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2878
2879	/* Safety precaution in case we change the paging for other modes too in the future. */
2880	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2881
2882	#ifdef VBOX_STRICT
2883	/*
2884	* Some sanity checks.
2885	*/
2886	switch (pUserPage->enmKind)
2887	{
2888	case PGMPOOLKIND_32BIT_PD:
2889	case PGMPOOLKIND_32BIT_PD_PHYS:
2890	Assert(iUserTable < X86_PG_ENTRIES);
2891	break;
2892	case PGMPOOLKIND_PAE_PDPT:
2893	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2894	case PGMPOOLKIND_PAE_PDPT_PHYS:
2895	Assert(iUserTable < 4);
2896	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2897	break;
2898	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2899	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2900	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2901	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2902	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2903	case PGMPOOLKIND_PAE_PD_PHYS:
2904	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2905	break;
2906	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2907	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2908	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2909	break;
2910	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2911	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2912	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2913	break;
2914	case PGMPOOLKIND_64BIT_PML4:
2915	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2916	/* GCPhys >> PAGE_SHIFT is the index here */
2917	break;
2918	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2919	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2920	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2921	break;
2922
2923	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2924	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2925	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2926	break;
2927
2928	case PGMPOOLKIND_ROOT_NESTED:
2929	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2930	break;
2931
2932	default:
2933	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2934	break;
2935	}
2936	#endif /* VBOX_STRICT */
2937
2938	/*
2939	* Clear the entry in the user page.
2940	*/
2941	switch (pUserPage->enmKind)
2942	{
2943	/* 32-bit entries */
2944	case PGMPOOLKIND_32BIT_PD:
2945	case PGMPOOLKIND_32BIT_PD_PHYS:
2946	u.pau32[iUserTable] = 0;
2947	break;
2948
2949	/* 64-bit entries */
2950	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2951	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2952	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2954	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2955	#if defined(IN_RC)
2956	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2957	* non-present PDPT will continue to cause page faults.
2958	*/
2959	ASMReloadCR3();
2960	#endif
2961	/* no break */
2962	case PGMPOOLKIND_PAE_PD_PHYS:
2963	case PGMPOOLKIND_PAE_PDPT_PHYS:
2964	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2965	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2966	case PGMPOOLKIND_64BIT_PML4:
2967	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2968	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2969	case PGMPOOLKIND_PAE_PDPT:
2970	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2971	case PGMPOOLKIND_ROOT_NESTED:
2972	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2973	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2974	u.pau64[iUserTable] = 0;
2975	break;
2976
2977	default:
2978	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2979	}
2980	}
2981
2982
2983	/**
2984	* Clears all users of a page.
2985	*/
2986	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2987	{
2988	/*
2989	* Free all the user records.
2990	*/
2991	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2992
2993	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2994	uint16_t i = pPage->iUserHead;
2995	while (i != NIL_PGMPOOL_USER_INDEX)
2996	{
2997	/* Clear enter in user table. */
2998	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
2999
3000	/* Free it. */
3001	const uint16_t iNext = paUsers[i].iNext;
3002	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3003	paUsers[i].iNext = pPool->iUserFreeHead;
3004	pPool->iUserFreeHead = i;
3005
3006	/* Next. */
3007	i = iNext;
3008	}
3009	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3010	}
3011
3012	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3013
3014	/**
3015	* Allocates a new physical cross reference extent.
3016	*
3017	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3018	* @param pVM The VM handle.
3019	* @param piPhysExt Where to store the phys ext index.
3020	*/
3021	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3022	{
3023	Assert(PGMIsLockOwner(pVM));
3024	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3025	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3026	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3027	{
3028	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3029	return NULL;
3030	}
3031	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3032	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3033	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3034	*piPhysExt = iPhysExt;
3035	return pPhysExt;
3036	}
3037
3038
3039	/**
3040	* Frees a physical cross reference extent.
3041	*
3042	* @param pVM The VM handle.
3043	* @param iPhysExt The extent to free.
3044	*/
3045	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3046	{
3047	Assert(PGMIsLockOwner(pVM));
3048	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3049	Assert(iPhysExt < pPool->cMaxPhysExts);
3050	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3051	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3052	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3053	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3054	pPool->iPhysExtFreeHead = iPhysExt;
3055	}
3056
3057
3058	/**
3059	* Frees a physical cross reference extent.
3060	*
3061	* @param pVM The VM handle.
3062	* @param iPhysExt The extent to free.
3063	*/
3064	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3065	{
3066	Assert(PGMIsLockOwner(pVM));
3067	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3068
3069	const uint16_t iPhysExtStart = iPhysExt;
3070	PPGMPOOLPHYSEXT pPhysExt;
3071	do
3072	{
3073	Assert(iPhysExt < pPool->cMaxPhysExts);
3074	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3075	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3076	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3077
3078	/* next */
3079	iPhysExt = pPhysExt->iNext;
3080	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3081
3082	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3083	pPool->iPhysExtFreeHead = iPhysExtStart;
3084	}
3085
3086
3087	/**
3088	* Insert a reference into a list of physical cross reference extents.
3089	*
3090	* @returns The new tracking data for PGMPAGE.
3091	*
3092	* @param pVM The VM handle.
3093	* @param iPhysExt The physical extent index of the list head.
3094	* @param iShwPT The shadow page table index.
3095	*
3096	*/
3097	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3098	{
3099	Assert(PGMIsLockOwner(pVM));
3100	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3101	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3102
3103	/* special common case. */
3104	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3105	{
3106	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3107	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3108	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3109	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3110	}
3111
3112	/* general treatment. */
3113	const uint16_t iPhysExtStart = iPhysExt;
3114	unsigned cMax = 15;
3115	for (;;)
3116	{
3117	Assert(iPhysExt < pPool->cMaxPhysExts);
3118	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3119	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3120	{
3121	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3122	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3123	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3124	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3125	}
3126	if (!--cMax)
3127	{
3128	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3129	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3130	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3131	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3132	}
3133	}
3134
3135	/* add another extent to the list. */
3136	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3137	if (!pNew)
3138	{
3139	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3140	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3141	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3142	}
3143	pNew->iNext = iPhysExtStart;
3144	pNew->aidx[0] = iShwPT;
3145	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3146	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3147	}
3148
3149
3150	/**
3151	* Add a reference to guest physical page where extents are in use.
3152	*
3153	* @returns The new tracking data for PGMPAGE.
3154	*
3155	* @param pVM The VM handle.
3156	* @param u16 The ram range flags (top 16-bits).
3157	* @param iShwPT The shadow page table index.
3158	*/
3159	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3160	{
3161	pgmLock(pVM);
3162	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3163	{
3164	/*
3165	* Convert to extent list.
3166	*/
3167	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3168	uint16_t iPhysExt;
3169	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3170	if (pPhysExt)
3171	{
3172	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3173	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3174	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3175	pPhysExt->aidx[1] = iShwPT;
3176	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3177	}
3178	else
3179	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3180	}
3181	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3182	{
3183	/*
3184	* Insert into the extent list.
3185	*/
3186	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3187	}
3188	else
3189	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3190	pgmUnlock(pVM);
3191	return u16;
3192	}
3193
3194
3195	/**
3196	* Clear references to guest physical memory.
3197	*
3198	* @param pPool The pool.
3199	* @param pPage The page.
3200	* @param pPhysPage Pointer to the aPages entry in the ram range.
3201	*/
3202	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3203	{
3204	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3205	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3206
3207	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3208	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3209	{
3210	PVM pVM = pPool->CTX_SUFF(pVM);
3211	pgmLock(pVM);
3212
3213	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3214	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3215	do
3216	{
3217	Assert(iPhysExt < pPool->cMaxPhysExts);
3218
3219	/*
3220	* Look for the shadow page and check if it's all freed.
3221	*/
3222	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3223	{
3224	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3225	{
3226	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3227
3228	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3229	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3230	{
3231	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3232	pgmUnlock(pVM);
3233	return;
3234	}
3235
3236	/* we can free the node. */
3237	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3238	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3239	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3240	{
3241	/* lonely node */
3242	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3243	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3244	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3245	}
3246	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3247	{
3248	/* head */
3249	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3250	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3251	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3252	}
3253	else
3254	{
3255	/* in list */
3256	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3257	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3258	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3259	}
3260	iPhysExt = iPhysExtNext;
3261	pgmUnlock(pVM);
3262	return;
3263	}
3264	}
3265
3266	/* next */
3267	iPhysExtPrev = iPhysExt;
3268	iPhysExt = paPhysExts[iPhysExt].iNext;
3269	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3270
3271	pgmUnlock(pVM);
3272	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3273	}
3274	else /* nothing to do */
3275	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3276	}
3277
3278
3279	/**
3280	* Clear references to guest physical memory.
3281	*
3282	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3283	* is assumed to be correct, so the linear search can be skipped and we can assert
3284	* at an earlier point.
3285	*
3286	* @param pPool The pool.
3287	* @param pPage The page.
3288	* @param HCPhys The host physical address corresponding to the guest page.
3289	* @param GCPhys The guest physical address corresponding to HCPhys.
3290	*/
3291	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3292	{
3293	/*
3294	* Walk range list.
3295	*/
3296	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3297	while (pRam)
3298	{
3299	RTGCPHYS off = GCPhys - pRam->GCPhys;
3300	if (off < pRam->cb)
3301	{
3302	/* does it match? */
3303	const unsigned iPage = off >> PAGE_SHIFT;
3304	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3305	#ifdef LOG_ENABLED
3306	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3307	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3308	#endif
3309	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3310	{
3311	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3312	return;
3313	}
3314	break;
3315	}
3316	pRam = pRam->CTX_SUFF(pNext);
3317	}
3318	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3319	}
3320
3321
3322	/**
3323	* Clear references to guest physical memory.
3324	*
3325	* @param pPool The pool.
3326	* @param pPage The page.
3327	* @param HCPhys The host physical address corresponding to the guest page.
3328	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3329	*/
3330	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3331	{
3332	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3333
3334	/*
3335	* Walk range list.
3336	*/
3337	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3338	while (pRam)
3339	{
3340	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3341	if (off < pRam->cb)
3342	{
3343	/* does it match? */
3344	const unsigned iPage = off >> PAGE_SHIFT;
3345	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3346	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3347	{
3348	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3349	return;
3350	}
3351	break;
3352	}
3353	pRam = pRam->CTX_SUFF(pNext);
3354	}
3355
3356	/*
3357	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3358	*/
3359	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3360	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3361	while (pRam)
3362	{
3363	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3364	while (iPage-- > 0)
3365	{
3366	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3367	{
3368	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3369	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3370	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3371	return;
3372	}
3373	}
3374	pRam = pRam->CTX_SUFF(pNext);
3375	}
3376
3377	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3378	}
3379
3380
3381	/**
3382	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3383	*
3384	* @param pPool The pool.
3385	* @param pPage The page.
3386	* @param pShwPT The shadow page table (mapping of the page).
3387	* @param pGstPT The guest page table.
3388	*/
3389	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3390	{
3391	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3392	if (pShwPT->a[i].n.u1Present)
3393	{
3394	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3395	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3396	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3397	if (!--pPage->cPresent)
3398	break;
3399	}
3400	}
3401
3402
3403	/**
3404	* Clear references to guest physical memory in a PAE / 32-bit page table.
3405	*
3406	* @param pPool The pool.
3407	* @param pPage The page.
3408	* @param pShwPT The shadow page table (mapping of the page).
3409	* @param pGstPT The guest page table (just a half one).
3410	*/
3411	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3412	{
3413	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3414	if (pShwPT->a[i].n.u1Present)
3415	{
3416	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3417	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3418	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3419	}
3420	}
3421
3422
3423	/**
3424	* Clear references to guest physical memory in a PAE / PAE page table.
3425	*
3426	* @param pPool The pool.
3427	* @param pPage The page.
3428	* @param pShwPT The shadow page table (mapping of the page).
3429	* @param pGstPT The guest page table.
3430	*/
3431	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3432	{
3433	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3434	if (pShwPT->a[i].n.u1Present)
3435	{
3436	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3437	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3438	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3439	}
3440	}
3441
3442
3443	/**
3444	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3445	*
3446	* @param pPool The pool.
3447	* @param pPage The page.
3448	* @param pShwPT The shadow page table (mapping of the page).
3449	*/
3450	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3451	{
3452	RTGCPHYS GCPhys = pPage->GCPhys;
3453	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3454	if (pShwPT->a[i].n.u1Present)
3455	{
3456	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3457	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3458	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3459	}
3460	}
3461
3462
3463	/**
3464	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3465	*
3466	* @param pPool The pool.
3467	* @param pPage The page.
3468	* @param pShwPT The shadow page table (mapping of the page).
3469	*/
3470	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3471	{
3472	RTGCPHYS GCPhys = pPage->GCPhys;
3473	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3474	if (pShwPT->a[i].n.u1Present)
3475	{
3476	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3477	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3478	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3479	}
3480	}
3481
3482	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3483
3484
3485	/**
3486	* Clear references to shadowed pages in a 32 bits page directory.
3487	*
3488	* @param pPool The pool.
3489	* @param pPage The page.
3490	* @param pShwPD The shadow page directory (mapping of the page).
3491	*/
3492	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3493	{
3494	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3495	{
3496	if ( pShwPD->a[i].n.u1Present
3497	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3498	)
3499	{
3500	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3501	if (pSubPage)
3502	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3503	else
3504	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3505	}
3506	}
3507	}
3508
3509	/**
3510	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3511	*
3512	* @param pPool The pool.
3513	* @param pPage The page.
3514	* @param pShwPD The shadow page directory (mapping of the page).
3515	*/
3516	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3517	{
3518	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3519	{
3520	if ( pShwPD->a[i].n.u1Present
3521	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3522	)
3523	{
3524	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3525	if (pSubPage)
3526	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3527	else
3528	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3529	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3530	}
3531	}
3532	}
3533
3534	/**
3535	* Clear references to shadowed pages in a PAE page directory pointer table.
3536	*
3537	* @param pPool The pool.
3538	* @param pPage The page.
3539	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3540	*/
3541	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3542	{
3543	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3544	{
3545	if ( pShwPDPT->a[i].n.u1Present
3546	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3547	)
3548	{
3549	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3550	if (pSubPage)
3551	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3552	else
3553	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3554	}
3555	}
3556	}
3557
3558
3559	/**
3560	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3561	*
3562	* @param pPool The pool.
3563	* @param pPage The page.
3564	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3565	*/
3566	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3567	{
3568	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3569	{
3570	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3571	if (pShwPDPT->a[i].n.u1Present)
3572	{
3573	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3574	if (pSubPage)
3575	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3576	else
3577	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3578	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3579	}
3580	}
3581	}
3582
3583
3584	/**
3585	* Clear references to shadowed pages in a 64-bit level 4 page table.
3586	*
3587	* @param pPool The pool.
3588	* @param pPage The page.
3589	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3590	*/
3591	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3592	{
3593	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3594	{
3595	if (pShwPML4->a[i].n.u1Present)
3596	{
3597	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3598	if (pSubPage)
3599	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3600	else
3601	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3602	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3603	}
3604	}
3605	}
3606
3607
3608	/**
3609	* Clear references to shadowed pages in an EPT page table.
3610	*
3611	* @param pPool The pool.
3612	* @param pPage The page.
3613	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3614	*/
3615	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3616	{
3617	RTGCPHYS GCPhys = pPage->GCPhys;
3618	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3619	if (pShwPT->a[i].n.u1Present)
3620	{
3621	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3622	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3623	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3624	}
3625	}
3626
3627
3628	/**
3629	* Clear references to shadowed pages in an EPT page directory.
3630	*
3631	* @param pPool The pool.
3632	* @param pPage The page.
3633	* @param pShwPD The shadow page directory (mapping of the page).
3634	*/
3635	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3636	{
3637	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3638	{
3639	if (pShwPD->a[i].n.u1Present)
3640	{
3641	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3642	if (pSubPage)
3643	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3644	else
3645	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3646	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3647	}
3648	}
3649	}
3650
3651
3652	/**
3653	* Clear references to shadowed pages in an EPT page directory pointer table.
3654	*
3655	* @param pPool The pool.
3656	* @param pPage The page.
3657	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3658	*/
3659	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3660	{
3661	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3662	{
3663	if (pShwPDPT->a[i].n.u1Present)
3664	{
3665	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3666	if (pSubPage)
3667	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3668	else
3669	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3670	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3671	}
3672	}
3673	}
3674
3675
3676	/**
3677	* Clears all references made by this page.
3678	*
3679	* This includes other shadow pages and GC physical addresses.
3680	*
3681	* @param pPool The pool.
3682	* @param pPage The page.
3683	*/
3684	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3685	{
3686	/*
3687	* Map the shadow page and take action according to the page kind.
3688	*/
3689	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3690	switch (pPage->enmKind)
3691	{
3692	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3693	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3694	{
3695	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3696	void *pvGst;
3697	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3698	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3699	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3700	break;
3701	}
3702
3703	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3704	{
3705	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3706	void *pvGst;
3707	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3708	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3709	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3710	break;
3711	}
3712
3713	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3714	{
3715	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3716	void *pvGst;
3717	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3718	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3719	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3720	break;
3721	}
3722
3723	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3724	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3725	{
3726	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3727	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3728	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3729	break;
3730	}
3731
3732	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3733	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3734	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3735	{
3736	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3737	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3738	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3739	break;
3740	}
3741
3742	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3743	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3744	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3745	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3746	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3747	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3748	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3749	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3750	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3751	break;
3752	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3753
3754	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3755	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3756	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3757	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3758	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3759	case PGMPOOLKIND_PAE_PD_PHYS:
3760	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3761	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3762	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3763	break;
3764
3765	case PGMPOOLKIND_32BIT_PD_PHYS:
3766	case PGMPOOLKIND_32BIT_PD:
3767	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3768	break;
3769
3770	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3771	case PGMPOOLKIND_PAE_PDPT:
3772	case PGMPOOLKIND_PAE_PDPT_PHYS:
3773	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3774	break;
3775
3776	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3777	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3778	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3779	break;
3780
3781	case PGMPOOLKIND_64BIT_PML4:
3782	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3783	break;
3784
3785	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3786	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3787	break;
3788
3789	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3790	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3791	break;
3792
3793	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3794	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3795	break;
3796
3797	default:
3798	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3799	}
3800
3801	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3802	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3803	ASMMemZeroPage(pvShw);
3804	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3805	pPage->fZeroed = true;
3806	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3807	}
3808
3809	#endif /* PGMPOOL_WITH_USER_TRACKING */
3810	#ifdef IN_RING3
3811	/**
3812	* Flushes the entire cache.
3813	*
3814	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
3815	* and execute this CR3 flush.
3816	*
3817	* @param pPool The pool.
3818	*
3819	* @remark Only used during reset now, we might want to rename and/or move it.
3820	*/
3821	static void pgmPoolFlushAllInt(PPGMPOOL pPool)
3822	{
3823	PVM pVM = pPool->CTX_SUFF(pVM);
3824
3825	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
3826	LogFlow(("pgmPoolFlushAllInt:\n"));
3827
3828	/*
3829	* If there are no pages in the pool, there is nothing to do.
3830	*/
3831	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
3832	{
3833	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3834	return;
3835	}
3836
3837	/*
3838	* Exit the shadow mode since we're going to clear everything,
3839	* including the root page.
3840	*/
3841	/** @todo Need to synchronize this across all VCPUs! */
3842	Assert(pVM->cCPUs == 1);
3843	for (unsigned i=0;i<pVM->cCPUs;i++)
3844	{
3845	PVMCPU pVCpu = &pVM->aCpus[i];
3846	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
3847	}
3848
3849	/*
3850	* Nuke the free list and reinsert all pages into it.
3851	*/
3852	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
3853	{
3854	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3855
3856	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
3857	#ifdef PGMPOOL_WITH_MONITORING
3858	if (pPage->fMonitored)
3859	pgmPoolMonitorFlush(pPool, pPage);
3860	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3861	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3862	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3863	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3864	pPage->cModifications = 0;
3865	#endif
3866	pPage->GCPhys = NIL_RTGCPHYS;
3867	pPage->enmKind = PGMPOOLKIND_FREE;
3868	Assert(pPage->idx == i);
3869	pPage->iNext = i + 1;
3870	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
3871	pPage->fSeenNonGlobal = false;
3872	pPage->fMonitored= false;
3873	pPage->fCached = false;
3874	pPage->fReusedFlushPending = false;
3875	#ifdef PGMPOOL_WITH_USER_TRACKING
3876	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3877	#else
3878	pPage->fCR3Mix = false;
3879	#endif
3880	#ifdef PGMPOOL_WITH_CACHE
3881	pPage->iAgeNext = NIL_PGMPOOL_IDX;
3882	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3883	#endif
3884	pPage->cLocked = 0;
3885	}
3886	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
3887	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
3888	pPool->cUsedPages = 0;
3889
3890	#ifdef PGMPOOL_WITH_USER_TRACKING
3891	/*
3892	* Zap and reinitialize the user records.
3893	*/
3894	pPool->cPresent = 0;
3895	pPool->iUserFreeHead = 0;
3896	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3897	const unsigned cMaxUsers = pPool->cMaxUsers;
3898	for (unsigned i = 0; i < cMaxUsers; i++)
3899	{
3900	paUsers[i].iNext = i + 1;
3901	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3902	paUsers[i].iUserTable = 0xfffffffe;
3903	}
3904	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
3905	#endif
3906
3907	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3908	/*
3909	* Clear all the GCPhys links and rebuild the phys ext free list.
3910	*/
3911	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3912	pRam;
3913	pRam = pRam->CTX_SUFF(pNext))
3914	{
3915	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3916	while (iPage-- > 0)
3917	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
3918	}
3919
3920	pPool->iPhysExtFreeHead = 0;
3921	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3922	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
3923	for (unsigned i = 0; i < cMaxPhysExts; i++)
3924	{
3925	paPhysExts[i].iNext = i + 1;
3926	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
3927	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
3928	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
3929	}
3930	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3931	#endif
3932
3933	#ifdef PGMPOOL_WITH_MONITORING
3934	/*
3935	* Just zap the modified list.
3936	*/
3937	pPool->cModifiedPages = 0;
3938	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
3939	#endif
3940
3941	#ifdef PGMPOOL_WITH_CACHE
3942	/*
3943	* Clear the GCPhys hash and the age list.
3944	*/
3945	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
3946	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
3947	pPool->iAgeHead = NIL_PGMPOOL_IDX;
3948	pPool->iAgeTail = NIL_PGMPOOL_IDX;
3949	#endif
3950
3951	/*
3952	* Reinsert active pages into the hash and ensure monitoring chains are correct.
3953	*/
3954	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
3955	{
3956	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3957	pPage->iNext = NIL_PGMPOOL_IDX;
3958	#ifdef PGMPOOL_WITH_MONITORING
3959	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3960	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3961	pPage->cModifications = 0;
3962	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
3963	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3964	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3965	if (pPage->fMonitored)
3966	{
3967	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
3968	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
3969	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
3970	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
3971	pPool->pszAccessHandler);
3972	AssertFatalRCSuccess(rc);
3973	# ifdef PGMPOOL_WITH_CACHE
3974	pgmPoolHashInsert(pPool, pPage);
3975	# endif
3976	}
3977	#endif
3978	#ifdef PGMPOOL_WITH_USER_TRACKING
3979	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
3980	#endif
3981	#ifdef PGMPOOL_WITH_CACHE
3982	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
3983	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
3984	#endif
3985	}
3986
3987	for (unsigned i=0;i<pVM->cCPUs;i++)
3988	{
3989	PVMCPU pVCpu = &pVM->aCpus[i];
3990	/*
3991	* Re-enter the shadowing mode and assert Sync CR3 FF.
3992	*/
3993	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
3994	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3995	}
3996
3997	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3998	}
3999
4000	#endif /* IN_RING3 */
4001
4002	/**
4003	* Flushes a pool page.
4004	*
4005	* This moves the page to the free list after removing all user references to it.
4006	* In GC this will cause a CR3 reload if the page is traced back to an active root page.
4007	*
4008	* @returns VBox status code.
4009	* @retval VINF_SUCCESS on success.
4010	* @param pPool The pool.
4011	* @param HCPhys The HC physical address of the shadow page.
4012	*/
4013	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4014	{
4015	PVM pVM = pPool->CTX_SUFF(pVM);
4016
4017	int rc = VINF_SUCCESS;
4018	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4019	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4020	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4021
4022	/*
4023	* Quietly reject any attempts at flushing any of the special root pages.
4024	*/
4025	if (pPage->idx < PGMPOOL_IDX_FIRST)
4026	{
4027	AssertFailed(); /* can no longer happen */
4028	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4029	return VINF_SUCCESS;
4030	}
4031
4032	pgmLock(pVM);
4033
4034	/*
4035	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4036	*/
4037	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4038	{
4039	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4040	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4041	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4042	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4043	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4044	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4045	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4046	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4047	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4048	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4049	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4050	pgmUnlock(pVM);
4051	return VINF_SUCCESS;
4052	}
4053
4054	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4055	/* Start a subset so we won't run out of mapping space. */
4056	PVMCPU pVCpu = VMMGetCpu(pVM);
4057	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4058	#endif
4059
4060	/*
4061	* Mark the page as being in need of a ASMMemZeroPage().
4062	*/
4063	pPage->fZeroed = false;
4064
4065	#ifdef PGMPOOL_WITH_USER_TRACKING
4066	/*
4067	* Clear the page.
4068	*/
4069	pgmPoolTrackClearPageUsers(pPool, pPage);
4070	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4071	pgmPoolTrackDeref(pPool, pPage);
4072	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4073	#endif
4074
4075	#ifdef PGMPOOL_WITH_CACHE
4076	/*
4077	* Flush it from the cache.
4078	*/
4079	pgmPoolCacheFlushPage(pPool, pPage);
4080	#endif /* PGMPOOL_WITH_CACHE */
4081
4082	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4083	/* Heavy stuff done. */
4084	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4085	#endif
4086
4087	#ifdef PGMPOOL_WITH_MONITORING
4088	/*
4089	* Deregistering the monitoring.
4090	*/
4091	if (pPage->fMonitored)
4092	rc = pgmPoolMonitorFlush(pPool, pPage);
4093	#endif
4094
4095	/*
4096	* Free the page.
4097	*/
4098	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4099	pPage->iNext = pPool->iFreeHead;
4100	pPool->iFreeHead = pPage->idx;
4101	pPage->enmKind = PGMPOOLKIND_FREE;
4102	pPage->GCPhys = NIL_RTGCPHYS;
4103	pPage->fReusedFlushPending = false;
4104
4105	pPool->cUsedPages--;
4106	pgmUnlock(pVM);
4107	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4108	return rc;
4109	}
4110
4111
4112	/**
4113	* Frees a usage of a pool page.
4114	*
4115	* The caller is responsible to updating the user table so that it no longer
4116	* references the shadow page.
4117	*
4118	* @param pPool The pool.
4119	* @param HCPhys The HC physical address of the shadow page.
4120	* @param iUser The shadow page pool index of the user table.
4121	* @param iUserTable The index into the user table (shadowed).
4122	*/
4123	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4124	{
4125	PVM pVM = pPool->CTX_SUFF(pVM);
4126
4127	STAM_PROFILE_START(&pPool->StatFree, a);
4128	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4129	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4130	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4131	pgmLock(pVM);
4132	#ifdef PGMPOOL_WITH_USER_TRACKING
4133	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4134	#endif
4135	#ifdef PGMPOOL_WITH_CACHE
4136	if (!pPage->fCached)
4137	#endif
4138	pgmPoolFlushPage(pPool, pPage);
4139	pgmUnlock(pVM);
4140	STAM_PROFILE_STOP(&pPool->StatFree, a);
4141	}
4142
4143
4144	/**
4145	* Makes one or more free page free.
4146	*
4147	* @returns VBox status code.
4148	* @retval VINF_SUCCESS on success.
4149	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4150	*
4151	* @param pPool The pool.
4152	* @param enmKind Page table kind
4153	* @param iUser The user of the page.
4154	*/
4155	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4156	{
4157	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4158
4159	/*
4160	* If the pool isn't full grown yet, expand it.
4161	*/
4162	if ( pPool->cCurPages < pPool->cMaxPages
4163	#if defined(IN_RC)
4164	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4165	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4166	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4167	#endif
4168	)
4169	{
4170	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4171	#ifdef IN_RING3
4172	int rc = PGMR3PoolGrow(pPool->pVMR3);
4173	#else
4174	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
4175	#endif
4176	if (RT_FAILURE(rc))
4177	return rc;
4178	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4179	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4180	return VINF_SUCCESS;
4181	}
4182
4183	#ifdef PGMPOOL_WITH_CACHE
4184	/*
4185	* Free one cached page.
4186	*/
4187	return pgmPoolCacheFreeOne(pPool, iUser);
4188	#else
4189	/*
4190	* Flush the pool.
4191	*
4192	* If we have tracking enabled, it should be possible to come up with
4193	* a cheap replacement strategy...
4194	*/
4195	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4196	AssertCompileFailed();
4197	Assert(!CPUMIsGuestInLongMode(pVM));
4198	pgmPoolFlushAllInt(pPool);
4199	return VERR_PGM_POOL_FLUSHED;
4200	#endif
4201	}
4202
4203
4204	/**
4205	* Allocates a page from the pool.
4206	*
4207	* This page may actually be a cached page and not in need of any processing
4208	* on the callers part.
4209	*
4210	* @returns VBox status code.
4211	* @retval VINF_SUCCESS if a NEW page was allocated.
4212	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4213	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4214	* @param pVM The VM handle.
4215	* @param GCPhys The GC physical address of the page we're gonna shadow.
4216	* For 4MB and 2MB PD entries, it's the first address the
4217	* shadow PT is covering.
4218	* @param enmKind The kind of mapping.
4219	* @param iUser The shadow page pool index of the user table.
4220	* @param iUserTable The index into the user table (shadowed).
4221	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4222	*/
4223	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4224	{
4225	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4226	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4227	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4228	*ppPage = NULL;
4229	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4230	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4231	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4232
4233	pgmLock(pVM);
4234
4235	#ifdef PGMPOOL_WITH_CACHE
4236	if (pPool->fCacheEnabled)
4237	{
4238	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4239	if (RT_SUCCESS(rc2))
4240	{
4241	pgmUnlock(pVM);
4242	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4243	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4244	return rc2;
4245	}
4246	}
4247	#endif
4248
4249	/*
4250	* Allocate a new one.
4251	*/
4252	int rc = VINF_SUCCESS;
4253	uint16_t iNew = pPool->iFreeHead;
4254	if (iNew == NIL_PGMPOOL_IDX)
4255	{
4256	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4257	if (RT_FAILURE(rc))
4258	{
4259	pgmUnlock(pVM);
4260	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4261	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4262	return rc;
4263	}
4264	iNew = pPool->iFreeHead;
4265	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4266	}
4267
4268	/* unlink the free head */
4269	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4270	pPool->iFreeHead = pPage->iNext;
4271	pPage->iNext = NIL_PGMPOOL_IDX;
4272
4273	/*
4274	* Initialize it.
4275	*/
4276	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4277	pPage->enmKind = enmKind;
4278	pPage->GCPhys = GCPhys;
4279	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4280	pPage->fMonitored = false;
4281	pPage->fCached = false;
4282	pPage->fReusedFlushPending = false;
4283	#ifdef PGMPOOL_WITH_MONITORING
4284	pPage->cModifications = 0;
4285	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4286	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4287	#else
4288	pPage->fCR3Mix = false;
4289	#endif
4290	#ifdef PGMPOOL_WITH_USER_TRACKING
4291	pPage->cPresent = 0;
4292	pPage->iFirstPresent = ~0;
4293
4294	/*
4295	* Insert into the tracking and cache. If this fails, free the page.
4296	*/
4297	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4298	if (RT_FAILURE(rc3))
4299	{
4300	pPool->cUsedPages--;
4301	pPage->enmKind = PGMPOOLKIND_FREE;
4302	pPage->GCPhys = NIL_RTGCPHYS;
4303	pPage->iNext = pPool->iFreeHead;
4304	pPool->iFreeHead = pPage->idx;
4305	pgmUnlock(pVM);
4306	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4307	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4308	return rc3;
4309	}
4310	#endif /* PGMPOOL_WITH_USER_TRACKING */
4311
4312	/*
4313	* Commit the allocation, clear the page and return.
4314	*/
4315	#ifdef VBOX_WITH_STATISTICS
4316	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4317	pPool->cUsedPagesHigh = pPool->cUsedPages;
4318	#endif
4319
4320	if (!pPage->fZeroed)
4321	{
4322	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4323	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4324	ASMMemZeroPage(pv);
4325	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4326	}
4327
4328	*ppPage = pPage;
4329	pgmUnlock(pVM);
4330	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4331	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4332	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4333	return rc;
4334	}
4335
4336
4337	/**
4338	* Frees a usage of a pool page.
4339	*
4340	* @param pVM The VM handle.
4341	* @param HCPhys The HC physical address of the shadow page.
4342	* @param iUser The shadow page pool index of the user table.
4343	* @param iUserTable The index into the user table (shadowed).
4344	*/
4345	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4346	{
4347	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4348	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4349	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4350	}
4351
4352	/**
4353	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4354	*
4355	* @returns Pointer to the shadow page structure.
4356	* @param pPool The pool.
4357	* @param HCPhys The HC physical address of the shadow page.
4358	*/
4359	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4360	{
4361	PVM pVM = pPool->CTX_SUFF(pVM);
4362
4363	/*
4364	* Look up the page.
4365	*/
4366	pgmLock(pVM);
4367	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4368	pgmUnlock(pVM);
4369
4370	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4371	return pPage;
4372	}
4373
4374
4375	#ifdef IN_RING3
4376	/**
4377	* Flushes the entire cache.
4378	*
4379	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4380	* and execute this CR3 flush.
4381	*
4382	* @param pPool The pool.
4383	*/
4384	void pgmPoolFlushAll(PVM pVM)
4385	{
4386	LogFlow(("pgmPoolFlushAll:\n"));
4387	pgmPoolFlushAllInt(pVM->pgm.s.CTX_SUFF(pPool));
4388	}
4389	#endif /* IN_RING3 */
4390
4391	#ifdef LOG_ENABLED
4392	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4393	{
4394	switch(enmKind)
4395	{
4396	case PGMPOOLKIND_INVALID:
4397	return "PGMPOOLKIND_INVALID";
4398	case PGMPOOLKIND_FREE:
4399	return "PGMPOOLKIND_FREE";
4400	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4401	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4402	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4403	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4404	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4405	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4406	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4407	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4408	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4409	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4410	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4411	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4412	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4413	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4414	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4415	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4416	case PGMPOOLKIND_32BIT_PD:
4417	return "PGMPOOLKIND_32BIT_PD";
4418	case PGMPOOLKIND_32BIT_PD_PHYS:
4419	return "PGMPOOLKIND_32BIT_PD_PHYS";
4420	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4421	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4422	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4423	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4424	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4425	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4426	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4427	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4428	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4429	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4430	case PGMPOOLKIND_PAE_PD_PHYS:
4431	return "PGMPOOLKIND_PAE_PD_PHYS";
4432	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4433	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4434	case PGMPOOLKIND_PAE_PDPT:
4435	return "PGMPOOLKIND_PAE_PDPT";
4436	case PGMPOOLKIND_PAE_PDPT_PHYS:
4437	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4438	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4439	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4440	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4441	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4442	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4443	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4444	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4445	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4446	case PGMPOOLKIND_64BIT_PML4:
4447	return "PGMPOOLKIND_64BIT_PML4";
4448	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4449	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4450	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4451	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4452	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4453	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4454	case PGMPOOLKIND_ROOT_NESTED:
4455	return "PGMPOOLKIND_ROOT_NESTED";
4456	}
4457	return "Unknown kind!";
4458	}
4459	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 19807

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