VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 25046

Last change on this file since 25046 was 24962, checked in by vboxsync, 15 years ago

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1/* $Id: PGMAllPool.cpp 24962 2009-11-25 16:21:46Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_POOL
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include <VBox/em.h>
30#include <VBox/cpum.h>
31#ifdef IN_RC
32# include <VBox/patm.h>
33#endif
34#include "PGMInternal.h"
35#include <VBox/vm.h>
36#include <VBox/disopcode.h>
37#include <VBox/hwacc_vmx.h>
38
39#include <VBox/log.h>
40#include <VBox/err.h>
41#include <iprt/asm.h>
42#include <iprt/string.h>
43
44
45/*******************************************************************************
46* Internal Functions *
47*******************************************************************************/
48RT_C_DECLS_BEGIN
49static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50#ifdef PGMPOOL_WITH_USER_TRACKING
51DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54#endif
55#ifdef PGMPOOL_WITH_CACHE
56static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
57#endif
58#ifdef PGMPOOL_WITH_MONITORING
59static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
60#endif
61#ifndef IN_RING3
62DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
63#endif
64#ifdef LOG_ENABLED
65static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
66#endif
67#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
68static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
69#endif
70
71int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
72PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
73void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
74void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
75
76RT_C_DECLS_END
77
78
79/**
80 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
81 *
82 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
83 * @param enmKind The page kind.
84 */
85DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
86{
87 switch (enmKind)
88 {
89 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
90 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
91 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
92 return true;
93 default:
94 return false;
95 }
96}
97
98/** @def PGMPOOL_PAGE_2_LOCKED_PTR
99 * Maps a pool page pool into the current context and lock it (RC only).
100 *
101 * @returns VBox status code.
102 * @param pVM The VM handle.
103 * @param pPage The pool page.
104 *
105 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
106 * small page window employeed by that function. Be careful.
107 * @remark There is no need to assert on the result.
108 */
109#if defined(IN_RC)
110DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
111{
112 void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
113
114 /* Make sure the dynamic mapping will not be reused. */
115 if (pv)
116 PGMDynLockHCPage(pVM, (uint8_t *)pv);
117
118 return pv;
119}
120#else
121# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
122#endif
123
124/** @def PGMPOOL_UNLOCK_PTR
125 * Unlock a previously locked dynamic caching (RC only).
126 *
127 * @returns VBox status code.
128 * @param pVM The VM handle.
129 * @param pPage The pool page.
130 *
131 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
132 * small page window employeed by that function. Be careful.
133 * @remark There is no need to assert on the result.
134 */
135#if defined(IN_RC)
136DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
137{
138 if (pvPage)
139 PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
140}
141#else
142# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
143#endif
144
145
146#ifdef PGMPOOL_WITH_MONITORING
147/**
148 * Determin the size of a write instruction.
149 * @returns number of bytes written.
150 * @param pDis The disassembler state.
151 */
152static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
153{
154 /*
155 * This is very crude and possibly wrong for some opcodes,
156 * but since it's not really supposed to be called we can
157 * probably live with that.
158 */
159 return DISGetParamSize(pDis, &pDis->param1);
160}
161
162
163/**
164 * Flushes a chain of pages sharing the same access monitor.
165 *
166 * @returns VBox status code suitable for scheduling.
167 * @param pPool The pool.
168 * @param pPage A page in the chain.
169 */
170int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
171{
172 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
173
174 /*
175 * Find the list head.
176 */
177 uint16_t idx = pPage->idx;
178 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
179 {
180 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181 {
182 idx = pPage->iMonitoredPrev;
183 Assert(idx != pPage->idx);
184 pPage = &pPool->aPages[idx];
185 }
186 }
187
188 /*
189 * Iterate the list flushing each shadow page.
190 */
191 int rc = VINF_SUCCESS;
192 for (;;)
193 {
194 idx = pPage->iMonitoredNext;
195 Assert(idx != pPage->idx);
196 if (pPage->idx >= PGMPOOL_IDX_FIRST)
197 {
198 int rc2 = pgmPoolFlushPage(pPool, pPage);
199 AssertRC(rc2);
200 }
201 /* next */
202 if (idx == NIL_PGMPOOL_IDX)
203 break;
204 pPage = &pPool->aPages[idx];
205 }
206 return rc;
207}
208
209
210/**
211 * Wrapper for getting the current context pointer to the entry being modified.
212 *
213 * @returns VBox status code suitable for scheduling.
214 * @param pVM VM Handle.
215 * @param pvDst Destination address
216 * @param pvSrc Source guest virtual address.
217 * @param GCPhysSrc The source guest physical address.
218 * @param cb Size of data to read
219 */
220DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
221{
222#if defined(IN_RING3)
223 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
224 return VINF_SUCCESS;
225#else
226 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
227 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
228#endif
229}
230
231/**
232 * Process shadow entries before they are changed by the guest.
233 *
234 * For PT entries we will clear them. For PD entries, we'll simply check
235 * for mapping conflicts and set the SyncCR3 FF if found.
236 *
237 * @param pVCpu VMCPU handle
238 * @param pPool The pool.
239 * @param pPage The head page.
240 * @param GCPhysFault The guest physical fault address.
241 * @param uAddress In R0 and GC this is the guest context fault address (flat).
242 * In R3 this is the host context 'fault' address.
243 * @param pDis The disassembler state for figuring out the write size.
244 * This need not be specified if the caller knows we won't do cross entry accesses.
245 */
246void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
247{
248 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
249 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
250 const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
251 PVM pVM = pPool->CTX_SUFF(pVM);
252
253 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, cbWrite));
254
255 for (;;)
256 {
257 union
258 {
259 void *pv;
260 PX86PT pPT;
261 PX86PTPAE pPTPae;
262 PX86PD pPD;
263 PX86PDPAE pPDPae;
264 PX86PDPT pPDPT;
265 PX86PML4 pPML4;
266 } uShw;
267
268 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
269
270 uShw.pv = NULL;
271 switch (pPage->enmKind)
272 {
273 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
274 {
275 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
276 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
277 const unsigned iShw = off / sizeof(X86PTE);
278 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
279 if (uShw.pPT->a[iShw].n.u1Present)
280 {
281# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
282 X86PTE GstPte;
283
284 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
285 AssertRC(rc);
286 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
287 pgmPoolTracDerefGCPhysHint(pPool, pPage,
288 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
289 GstPte.u & X86_PTE_PG_MASK);
290# endif
291 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
292 }
293 break;
294 }
295
296 /* page/2 sized */
297 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
298 {
299 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
300 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
301 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
302 {
303 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
304 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
305 if (uShw.pPTPae->a[iShw].n.u1Present)
306 {
307# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
308 X86PTE GstPte;
309 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
310 AssertRC(rc);
311
312 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
313 pgmPoolTracDerefGCPhysHint(pPool, pPage,
314 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
315 GstPte.u & X86_PTE_PG_MASK);
316# endif
317 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
318 }
319 }
320 break;
321 }
322
323 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
324 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
325 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
326 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
327 {
328 unsigned iGst = off / sizeof(X86PDE);
329 unsigned iShwPdpt = iGst / 256;
330 unsigned iShw = (iGst % 256) * 2;
331 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
332
333 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
334 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
335 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
336 {
337 for (unsigned i = 0; i < 2; i++)
338 {
339# ifndef IN_RING0
340 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
341 {
342 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
343 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
344 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
345 break;
346 }
347 else
348# endif /* !IN_RING0 */
349 if (uShw.pPDPae->a[iShw+i].n.u1Present)
350 {
351 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
352 pgmPoolFree(pVM,
353 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
354 pPage->idx,
355 iShw + i);
356 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
357 }
358
359 /* paranoia / a bit assumptive. */
360 if ( pDis
361 && (off & 3)
362 && (off & 3) + cbWrite > 4)
363 {
364 const unsigned iShw2 = iShw + 2 + i;
365 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
366 {
367# ifndef IN_RING0
368 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
369 {
370 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
371 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
372 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
373 break;
374 }
375 else
376# endif /* !IN_RING0 */
377 if (uShw.pPDPae->a[iShw2].n.u1Present)
378 {
379 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
380 pgmPoolFree(pVM,
381 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
382 pPage->idx,
383 iShw2);
384 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
385 }
386 }
387 }
388 }
389 }
390 break;
391 }
392
393 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
394 {
395 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
396 const unsigned iShw = off / sizeof(X86PTEPAE);
397 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
398 if (uShw.pPTPae->a[iShw].n.u1Present)
399 {
400# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
401 X86PTEPAE GstPte;
402 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
403 AssertRC(rc);
404
405 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
406 pgmPoolTracDerefGCPhysHint(pPool, pPage,
407 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
408 GstPte.u & X86_PTE_PAE_PG_MASK);
409# endif
410 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
411 }
412
413 /* paranoia / a bit assumptive. */
414 if ( pDis
415 && (off & 7)
416 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
417 {
418 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
419 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
420
421 if (uShw.pPTPae->a[iShw2].n.u1Present)
422 {
423# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
424 X86PTEPAE GstPte;
425# ifdef IN_RING3
426 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
427# else
428 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
429# endif
430 AssertRC(rc);
431 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
432 pgmPoolTracDerefGCPhysHint(pPool, pPage,
433 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
434 GstPte.u & X86_PTE_PAE_PG_MASK);
435# endif
436 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
437 }
438 }
439 break;
440 }
441
442 case PGMPOOLKIND_32BIT_PD:
443 {
444 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
445 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
446
447 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
448 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
449# ifndef IN_RING0
450 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
451 {
452 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
453 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
454 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
455 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
456 break;
457 }
458# endif /* !IN_RING0 */
459# ifndef IN_RING0
460 else
461# endif /* !IN_RING0 */
462 {
463 if (uShw.pPD->a[iShw].n.u1Present)
464 {
465 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
466 pgmPoolFree(pVM,
467 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
468 pPage->idx,
469 iShw);
470 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
471 }
472 }
473 /* paranoia / a bit assumptive. */
474 if ( pDis
475 && (off & 3)
476 && (off & 3) + cbWrite > sizeof(X86PTE))
477 {
478 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
479 if ( iShw2 != iShw
480 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
481 {
482# ifndef IN_RING0
483 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
484 {
485 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
486 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
487 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
488 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
489 break;
490 }
491# endif /* !IN_RING0 */
492# ifndef IN_RING0
493 else
494# endif /* !IN_RING0 */
495 {
496 if (uShw.pPD->a[iShw2].n.u1Present)
497 {
498 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
499 pgmPoolFree(pVM,
500 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
501 pPage->idx,
502 iShw2);
503 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
504 }
505 }
506 }
507 }
508#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
509 if ( uShw.pPD->a[iShw].n.u1Present
510 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
511 {
512 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
513# ifdef IN_RC /* TLB load - we're pushing things a bit... */
514 ASMProbeReadByte(pvAddress);
515# endif
516 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
517 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
518 }
519#endif
520 break;
521 }
522
523 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
524 {
525 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
526 const unsigned iShw = off / sizeof(X86PDEPAE);
527 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
528#ifndef IN_RING0
529 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
530 {
531 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
532 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
533 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
534 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
535 break;
536 }
537#endif /* !IN_RING0 */
538 /*
539 * Causes trouble when the guest uses a PDE to refer to the whole page table level
540 * structure. (Invalidate here; faults later on when it tries to change the page
541 * table entries -> recheck; probably only applies to the RC case.)
542 */
543# ifndef IN_RING0
544 else
545# endif /* !IN_RING0 */
546 {
547 if (uShw.pPDPae->a[iShw].n.u1Present)
548 {
549 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
550 pgmPoolFree(pVM,
551 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
552 pPage->idx,
553 iShw);
554 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
555 }
556 }
557 /* paranoia / a bit assumptive. */
558 if ( pDis
559 && (off & 7)
560 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
561 {
562 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
563 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
564
565#ifndef IN_RING0
566 if ( iShw2 != iShw
567 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
568 {
569 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
570 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
571 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
572 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
573 break;
574 }
575#endif /* !IN_RING0 */
576# ifndef IN_RING0
577 else
578# endif /* !IN_RING0 */
579 if (uShw.pPDPae->a[iShw2].n.u1Present)
580 {
581 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
582 pgmPoolFree(pVM,
583 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
584 pPage->idx,
585 iShw2);
586 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
587 }
588 }
589 break;
590 }
591
592 case PGMPOOLKIND_PAE_PDPT:
593 {
594 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
595 /*
596 * Hopefully this doesn't happen very often:
597 * - touching unused parts of the page
598 * - messing with the bits of pd pointers without changing the physical address
599 */
600 /* PDPT roots are not page aligned; 32 byte only! */
601 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
602
603 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
604 const unsigned iShw = offPdpt / sizeof(X86PDPE);
605 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
606 {
607# ifndef IN_RING0
608 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
609 {
610 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
611 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
612 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
613 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
614 break;
615 }
616# endif /* !IN_RING0 */
617# ifndef IN_RING0
618 else
619# endif /* !IN_RING0 */
620 if (uShw.pPDPT->a[iShw].n.u1Present)
621 {
622 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
623 pgmPoolFree(pVM,
624 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
625 pPage->idx,
626 iShw);
627 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
628 }
629
630 /* paranoia / a bit assumptive. */
631 if ( pDis
632 && (offPdpt & 7)
633 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
634 {
635 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
636 if ( iShw2 != iShw
637 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
638 {
639# ifndef IN_RING0
640 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
641 {
642 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
643 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
644 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
645 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
646 break;
647 }
648# endif /* !IN_RING0 */
649# ifndef IN_RING0
650 else
651# endif /* !IN_RING0 */
652 if (uShw.pPDPT->a[iShw2].n.u1Present)
653 {
654 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
655 pgmPoolFree(pVM,
656 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
657 pPage->idx,
658 iShw2);
659 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
660 }
661 }
662 }
663 }
664 break;
665 }
666
667#ifndef IN_RC
668 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
669 {
670 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
671 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
672 const unsigned iShw = off / sizeof(X86PDEPAE);
673 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
674 if (uShw.pPDPae->a[iShw].n.u1Present)
675 {
676 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
677 pgmPoolFree(pVM,
678 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
679 pPage->idx,
680 iShw);
681 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
682 }
683 /* paranoia / a bit assumptive. */
684 if ( pDis
685 && (off & 7)
686 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
687 {
688 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
689 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
690
691 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
692 if (uShw.pPDPae->a[iShw2].n.u1Present)
693 {
694 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
695 pgmPoolFree(pVM,
696 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
697 pPage->idx,
698 iShw2);
699 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
700 }
701 }
702 break;
703 }
704
705 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
706 {
707 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
708 /*
709 * Hopefully this doesn't happen very often:
710 * - messing with the bits of pd pointers without changing the physical address
711 */
712 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
713 {
714 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
715 const unsigned iShw = off / sizeof(X86PDPE);
716 if (uShw.pPDPT->a[iShw].n.u1Present)
717 {
718 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
719 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
720 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
721 }
722 /* paranoia / a bit assumptive. */
723 if ( pDis
724 && (off & 7)
725 && (off & 7) + cbWrite > sizeof(X86PDPE))
726 {
727 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
728 if (uShw.pPDPT->a[iShw2].n.u1Present)
729 {
730 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
731 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
732 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
733 }
734 }
735 }
736 break;
737 }
738
739 case PGMPOOLKIND_64BIT_PML4:
740 {
741 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
742 /*
743 * Hopefully this doesn't happen very often:
744 * - messing with the bits of pd pointers without changing the physical address
745 */
746 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
747 {
748 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
749 const unsigned iShw = off / sizeof(X86PDPE);
750 if (uShw.pPML4->a[iShw].n.u1Present)
751 {
752 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
753 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
754 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
755 }
756 /* paranoia / a bit assumptive. */
757 if ( pDis
758 && (off & 7)
759 && (off & 7) + cbWrite > sizeof(X86PDPE))
760 {
761 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
762 if (uShw.pPML4->a[iShw2].n.u1Present)
763 {
764 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
765 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
766 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
767 }
768 }
769 }
770 break;
771 }
772#endif /* IN_RING0 */
773
774 default:
775 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
776 }
777 PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
778
779 /* next */
780 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
781 return;
782 pPage = &pPool->aPages[pPage->iMonitoredNext];
783 }
784}
785
786# ifndef IN_RING3
787/**
788 * Checks if a access could be a fork operation in progress.
789 *
790 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
791 *
792 * @returns true if it's likly that we're forking, otherwise false.
793 * @param pPool The pool.
794 * @param pDis The disassembled instruction.
795 * @param offFault The access offset.
796 */
797DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
798{
799 /*
800 * i386 linux is using btr to clear X86_PTE_RW.
801 * The functions involved are (2.6.16 source inspection):
802 * clear_bit
803 * ptep_set_wrprotect
804 * copy_one_pte
805 * copy_pte_range
806 * copy_pmd_range
807 * copy_pud_range
808 * copy_page_range
809 * dup_mmap
810 * dup_mm
811 * copy_mm
812 * copy_process
813 * do_fork
814 */
815 if ( pDis->pCurInstr->opcode == OP_BTR
816 && !(offFault & 4)
817 /** @todo Validate that the bit index is X86_PTE_RW. */
818 )
819 {
820 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
821 return true;
822 }
823 return false;
824}
825
826
827/**
828 * Determine whether the page is likely to have been reused.
829 *
830 * @returns true if we consider the page as being reused for a different purpose.
831 * @returns false if we consider it to still be a paging page.
832 * @param pVM VM Handle.
833 * @param pVCpu VMCPU Handle.
834 * @param pRegFrame Trap register frame.
835 * @param pDis The disassembly info for the faulting instruction.
836 * @param pvFault The fault address.
837 *
838 * @remark The REP prefix check is left to the caller because of STOSD/W.
839 */
840DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
841{
842#ifndef IN_RC
843 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
844 if ( HWACCMHasPendingIrq(pVM)
845 && (pRegFrame->rsp - pvFault) < 32)
846 {
847 /* Fault caused by stack writes while trying to inject an interrupt event. */
848 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
849 return true;
850 }
851#else
852 NOREF(pVM); NOREF(pvFault);
853#endif
854
855 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
856
857 /* Non-supervisor mode write means it's used for something else. */
858 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
859 return true;
860
861 switch (pDis->pCurInstr->opcode)
862 {
863 /* call implies the actual push of the return address faulted */
864 case OP_CALL:
865 Log4(("pgmPoolMonitorIsReused: CALL\n"));
866 return true;
867 case OP_PUSH:
868 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
869 return true;
870 case OP_PUSHF:
871 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
872 return true;
873 case OP_PUSHA:
874 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
875 return true;
876 case OP_FXSAVE:
877 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
878 return true;
879 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
880 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
881 return true;
882 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
883 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
884 return true;
885 case OP_MOVSWD:
886 case OP_STOSWD:
887 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
888 && pRegFrame->rcx >= 0x40
889 )
890 {
891 Assert(pDis->mode == CPUMODE_64BIT);
892
893 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
894 return true;
895 }
896 return false;
897 }
898 if ( ( (pDis->param1.flags & USE_REG_GEN32)
899 || (pDis->param1.flags & USE_REG_GEN64))
900 && (pDis->param1.base.reg_gen == USE_REG_ESP))
901 {
902 Log4(("pgmPoolMonitorIsReused: ESP\n"));
903 return true;
904 }
905
906 return false;
907}
908
909/**
910 * Flushes the page being accessed.
911 *
912 * @returns VBox status code suitable for scheduling.
913 * @param pVM The VM handle.
914 * @param pVCpu The VMCPU handle.
915 * @param pPool The pool.
916 * @param pPage The pool page (head).
917 * @param pDis The disassembly of the write instruction.
918 * @param pRegFrame The trap register frame.
919 * @param GCPhysFault The fault address as guest physical address.
920 * @param pvFault The fault address.
921 */
922static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
923 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
924{
925 /*
926 * First, do the flushing.
927 */
928 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
929
930 /*
931 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
932 */
933 uint32_t cbWritten;
934 int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten);
935 if (RT_SUCCESS(rc2))
936 pRegFrame->rip += pDis->opsize;
937 else if (rc2 == VERR_EM_INTERPRETER)
938 {
939#ifdef IN_RC
940 if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
941 {
942 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
943 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
944 rc = VINF_SUCCESS;
945 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
946 }
947 else
948#endif
949 {
950 rc = VINF_EM_RAW_EMULATE_INSTR;
951 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
952 }
953 }
954 else
955 rc = rc2;
956
957 /* See use in pgmPoolAccessHandlerSimple(). */
958 PGM_INVL_VCPU_TLBS(pVCpu);
959 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
960 return rc;
961}
962
963/**
964 * Handles the STOSD write accesses.
965 *
966 * @returns VBox status code suitable for scheduling.
967 * @param pVM The VM handle.
968 * @param pPool The pool.
969 * @param pPage The pool page (head).
970 * @param pDis The disassembly of the write instruction.
971 * @param pRegFrame The trap register frame.
972 * @param GCPhysFault The fault address as guest physical address.
973 * @param pvFault The fault address.
974 */
975DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
976 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
977{
978 unsigned uIncrement = pDis->param1.size;
979
980 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
981 Assert(pRegFrame->rcx <= 0x20);
982
983#ifdef VBOX_STRICT
984 if (pDis->opmode == CPUMODE_32BIT)
985 Assert(uIncrement == 4);
986 else
987 Assert(uIncrement == 8);
988#endif
989
990 Log3(("pgmPoolAccessHandlerSTOSD\n"));
991
992 /*
993 * Increment the modification counter and insert it into the list
994 * of modified pages the first time.
995 */
996 if (!pPage->cModifications++)
997 pgmPoolMonitorModifiedInsert(pPool, pPage);
998
999 /*
1000 * Execute REP STOSD.
1001 *
1002 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
1003 * write situation, meaning that it's safe to write here.
1004 */
1005 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
1006 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
1007 while (pRegFrame->rcx)
1008 {
1009#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1010 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1011 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1012 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1013#else
1014 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1015#endif
1016#ifdef IN_RC
1017 *(uint32_t *)pu32 = pRegFrame->eax;
1018#else
1019 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
1020#endif
1021 pu32 += uIncrement;
1022 GCPhysFault += uIncrement;
1023 pRegFrame->rdi += uIncrement;
1024 pRegFrame->rcx--;
1025 }
1026 pRegFrame->rip += pDis->opsize;
1027
1028#ifdef IN_RC
1029 /* See use in pgmPoolAccessHandlerSimple(). */
1030 PGM_INVL_VCPU_TLBS(pVCpu);
1031#endif
1032
1033 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1034 return VINF_SUCCESS;
1035}
1036
1037
1038/**
1039 * Handles the simple write accesses.
1040 *
1041 * @returns VBox status code suitable for scheduling.
1042 * @param pVM The VM handle.
1043 * @param pVCpu The VMCPU handle.
1044 * @param pPool The pool.
1045 * @param pPage The pool page (head).
1046 * @param pDis The disassembly of the write instruction.
1047 * @param pRegFrame The trap register frame.
1048 * @param GCPhysFault The fault address as guest physical address.
1049 * @param pvFault The fault address.
1050 * @param pfReused Reused state (out)
1051 */
1052DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
1053 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
1054{
1055 Log3(("pgmPoolAccessHandlerSimple\n"));
1056 /*
1057 * Increment the modification counter and insert it into the list
1058 * of modified pages the first time.
1059 */
1060 if (!pPage->cModifications++)
1061 pgmPoolMonitorModifiedInsert(pPool, pPage);
1062
1063 /*
1064 * Clear all the pages. ASSUMES that pvFault is readable.
1065 */
1066#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1067 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1068 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1069 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1070#else
1071 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1072#endif
1073
1074 /*
1075 * Interpret the instruction.
1076 */
1077 uint32_t cb;
1078 int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
1079 if (RT_SUCCESS(rc))
1080 pRegFrame->rip += pDis->opsize;
1081 else if (rc == VERR_EM_INTERPRETER)
1082 {
1083 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1084 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1085 rc = VINF_EM_RAW_EMULATE_INSTR;
1086 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1087 }
1088
1089#if 0 /* experimental code */
1090 if (rc == VINF_SUCCESS)
1091 {
1092 switch (pPage->enmKind)
1093 {
1094 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1095 {
1096 X86PTEPAE GstPte;
1097 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1098 AssertRC(rc);
1099
1100 /* Check the new value written by the guest. If present and with a bogus physical address, then
1101 * it's fairly safe to assume the guest is reusing the PT.
1102 */
1103 if (GstPte.n.u1Present)
1104 {
1105 RTHCPHYS HCPhys = -1;
1106 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1107 if (rc != VINF_SUCCESS)
1108 {
1109 *pfReused = true;
1110 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1111 }
1112 }
1113 break;
1114 }
1115 }
1116 }
1117#endif
1118
1119#ifdef IN_RC
1120 /*
1121 * Quick hack, with logging enabled we're getting stale
1122 * code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1123 * Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1124 * have to be fixed to support this. But that'll have to wait till next week.
1125 *
1126 * An alternative is to keep track of the changed PTEs together with the
1127 * GCPhys from the guest PT. This may proove expensive though.
1128 *
1129 * At the moment, it's VITAL that it's done AFTER the instruction interpreting
1130 * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1131 */
1132 PGM_INVL_VCPU_TLBS(pVCpu);
1133#endif
1134
1135 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1136 return rc;
1137}
1138
1139/**
1140 * \#PF Handler callback for PT write accesses.
1141 *
1142 * @returns VBox status code (appropriate for GC return).
1143 * @param pVM VM Handle.
1144 * @param uErrorCode CPU Error code.
1145 * @param pRegFrame Trap register frame.
1146 * NULL on DMA and other non CPU access.
1147 * @param pvFault The fault address (cr2).
1148 * @param GCPhysFault The GC physical address corresponding to pvFault.
1149 * @param pvUser User argument.
1150 */
1151DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1152{
1153 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1154 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1155 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1156 PVMCPU pVCpu = VMMGetCpu(pVM);
1157 unsigned cMaxModifications;
1158 bool fForcedFlush = false;
1159
1160 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1161
1162 pgmLock(pVM);
1163 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1164 {
1165 /* Pool page changed while we were waiting for the lock; ignore. */
1166 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1167 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1168 pgmUnlock(pVM);
1169 return VINF_SUCCESS;
1170 }
1171#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1172 if (pPage->fDirty)
1173 {
1174 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1175 return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1176 }
1177#endif
1178
1179#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1180 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1181 {
1182 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1183 void *pvGst;
1184 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1185 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1186 }
1187#endif
1188
1189 /*
1190 * Disassemble the faulting instruction.
1191 */
1192 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1193 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1194 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1195 {
1196 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1197 pgmUnlock(pVM);
1198 return rc;
1199 }
1200
1201 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1202
1203 /*
1204 * We should ALWAYS have the list head as user parameter. This
1205 * is because we use that page to record the changes.
1206 */
1207 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1208
1209#ifdef IN_RING0
1210 /* Maximum nr of modifications depends on the page type. */
1211 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1212 cMaxModifications = 4;
1213 else
1214 cMaxModifications = 24;
1215#else
1216 cMaxModifications = 48;
1217#endif
1218
1219 /*
1220 * Incremental page table updates should weight more than random ones.
1221 * (Only applies when started from offset 0)
1222 */
1223 pVCpu->pgm.s.cPoolAccessHandler++;
1224 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1225 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1226 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1227 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1228 {
1229 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1230 pPage->cModifications = pPage->cModifications * 2;
1231 pPage->pvLastAccessHandlerFault = pvFault;
1232 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1233 if (pPage->cModifications >= cMaxModifications)
1234 {
1235 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1236 fForcedFlush = true;
1237 }
1238 }
1239
1240 if (pPage->cModifications >= cMaxModifications)
1241 Log(("Mod overflow %VGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1242
1243 /*
1244 * Check if it's worth dealing with.
1245 */
1246 bool fReused = false;
1247 bool fNotReusedNotForking = false;
1248 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1249 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1250 )
1251 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1252 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1253 {
1254 /*
1255 * Simple instructions, no REP prefix.
1256 */
1257 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1258 {
1259 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1260 if (fReused)
1261 goto flushPage;
1262
1263 /* A mov instruction to change the first page table entry will be remembered so we can detect
1264 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1265 */
1266 if ( rc == VINF_SUCCESS
1267 && pDis->pCurInstr->opcode == OP_MOV
1268 && (pvFault & PAGE_OFFSET_MASK) == 0)
1269 {
1270 pPage->pvLastAccessHandlerFault = pvFault;
1271 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1272 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1273 /* Make sure we don't kick out a page too quickly. */
1274 if (pPage->cModifications > 8)
1275 pPage->cModifications = 2;
1276 }
1277 else
1278 if (pPage->pvLastAccessHandlerFault == pvFault)
1279 {
1280 /* ignore the 2nd write to this page table entry. */
1281 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1282 }
1283 else
1284 {
1285 pPage->pvLastAccessHandlerFault = 0;
1286 pPage->pvLastAccessHandlerRip = 0;
1287 }
1288
1289 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1290 pgmUnlock(pVM);
1291 return rc;
1292 }
1293
1294 /*
1295 * Windows is frequently doing small memset() operations (netio test 4k+).
1296 * We have to deal with these or we'll kill the cache and performance.
1297 */
1298 if ( pDis->pCurInstr->opcode == OP_STOSWD
1299 && !pRegFrame->eflags.Bits.u1DF
1300 && pDis->opmode == pDis->mode
1301 && pDis->addrmode == pDis->mode)
1302 {
1303 bool fValidStosd = false;
1304
1305 if ( pDis->mode == CPUMODE_32BIT
1306 && pDis->prefix == PREFIX_REP
1307 && pRegFrame->ecx <= 0x20
1308 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1309 && !((uintptr_t)pvFault & 3)
1310 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1311 )
1312 {
1313 fValidStosd = true;
1314 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1315 }
1316 else
1317 if ( pDis->mode == CPUMODE_64BIT
1318 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1319 && pRegFrame->rcx <= 0x20
1320 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1321 && !((uintptr_t)pvFault & 7)
1322 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1323 )
1324 {
1325 fValidStosd = true;
1326 }
1327
1328 if (fValidStosd)
1329 {
1330 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1331 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1332 pgmUnlock(pVM);
1333 return rc;
1334 }
1335 }
1336
1337 /* REP prefix, don't bother. */
1338 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1339 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1340 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1341 fNotReusedNotForking = true;
1342 }
1343
1344#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1345 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1346 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1347 */
1348 if ( pPage->cModifications >= cMaxModifications
1349 && !fForcedFlush
1350 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1351 && ( fNotReusedNotForking
1352 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1353 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1354 )
1355 )
1356 {
1357 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1358 Assert(pPage->fDirty == false);
1359
1360 /* Flush any monitored duplicates as we will disable write protection. */
1361 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1362 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1363 {
1364 PPGMPOOLPAGE pPageHead = pPage;
1365
1366 /* Find the monitor head. */
1367 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1368 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1369
1370 while (pPageHead)
1371 {
1372 unsigned idxNext = pPageHead->iMonitoredNext;
1373
1374 if (pPageHead != pPage)
1375 {
1376 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1377 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1378 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1379 AssertRC(rc2);
1380 }
1381
1382 if (idxNext == NIL_PGMPOOL_IDX)
1383 break;
1384
1385 pPageHead = &pPool->aPages[idxNext];
1386 }
1387 }
1388
1389 /* The flushing above might fail for locked pages, so double check. */
1390 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1391 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1392 {
1393 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1394
1395 /* Temporarily allow write access to the page table again. */
1396 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1397 if (rc == VINF_SUCCESS)
1398 {
1399 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
1400 AssertMsg(rc == VINF_SUCCESS
1401 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1402 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1403 || rc == VERR_PAGE_NOT_PRESENT,
1404 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1405
1406 pPage->pvDirtyFault = pvFault;
1407
1408 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1409 pgmUnlock(pVM);
1410 return rc;
1411 }
1412 }
1413 }
1414#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1415
1416 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1417flushPage:
1418 /*
1419 * Not worth it, so flush it.
1420 *
1421 * If we considered it to be reused, don't go back to ring-3
1422 * to emulate failed instructions since we usually cannot
1423 * interpret then. This may be a bit risky, in which case
1424 * the reuse detection must be fixed.
1425 */
1426 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1427 if ( rc == VINF_EM_RAW_EMULATE_INSTR
1428 && fReused)
1429 {
1430 /* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1431 if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1432 rc = VINF_SUCCESS; /* safe to restart the instruction. */
1433 }
1434 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1435 pgmUnlock(pVM);
1436 return rc;
1437}
1438
1439# endif /* !IN_RING3 */
1440
1441# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1442
1443# ifdef VBOX_STRICT
1444/**
1445 * Check references to guest physical memory in a PAE / PAE page table.
1446 *
1447 * @param pPool The pool.
1448 * @param pPage The page.
1449 * @param pShwPT The shadow page table (mapping of the page).
1450 * @param pGstPT The guest page table.
1451 */
1452static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1453{
1454 unsigned cErrors = 0;
1455 int LastRc = -1; /* initialized to shut up gcc */
1456 unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1457 RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1458
1459#ifdef VBOX_STRICT
1460 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1461 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1462#endif
1463 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1464 {
1465 if (pShwPT->a[i].n.u1Present)
1466 {
1467 RTHCPHYS HCPhys = -1;
1468 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1469 if ( rc != VINF_SUCCESS
1470 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1471 {
1472 RTHCPHYS HCPhysPT = -1;
1473 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1474 LastPTE = i;
1475 LastRc = rc;
1476 LastHCPhys = HCPhys;
1477 cErrors++;
1478
1479 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
1480 AssertRC(rc);
1481
1482 for (unsigned i = 0; i < pPool->cCurPages; i++)
1483 {
1484 PPGMPOOLPAGE pTempPage = &pPool->aPages[i];
1485
1486 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1487 {
1488 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pTempPage);
1489
1490 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1491 {
1492 if ( pShwPT2->a[j].n.u1Present
1493 && pShwPT2->a[j].n.u1Write
1494 && ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1495 {
1496 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1497 }
1498 }
1499 }
1500 }
1501 }
1502 }
1503 }
1504 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1505}
1506# endif /* VBOX_STRICT */
1507
1508/**
1509 * Clear references to guest physical memory in a PAE / PAE page table.
1510 *
1511 * @returns nr of changed PTEs
1512 * @param pPool The pool.
1513 * @param pPage The page.
1514 * @param pShwPT The shadow page table (mapping of the page).
1515 * @param pGstPT The guest page table.
1516 * @param pOldGstPT The old cached guest page table.
1517 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1518 * @param pfFlush Flush reused page table (out)
1519 */
1520DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT, PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1521{
1522 unsigned cChanged = 0;
1523
1524#ifdef VBOX_STRICT
1525 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1526 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1527#endif
1528 *pfFlush = false;
1529
1530 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1531 {
1532 /* Check the new value written by the guest. If present and with a bogus physical address, then
1533 * it's fairly safe to assume the guest is reusing the PT.
1534 */
1535 if ( fAllowRemoval
1536 && pGstPT->a[i].n.u1Present)
1537 {
1538 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1539 {
1540 *pfFlush = true;
1541 return ++cChanged;
1542 }
1543 }
1544 if (pShwPT->a[i].n.u1Present)
1545 {
1546 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1547 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1548 {
1549#ifdef VBOX_STRICT
1550 RTHCPHYS HCPhys = -1;
1551 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1552 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1553#endif
1554 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1555 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1556 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1557 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1558
1559 if ( uHostAttr == uGuestAttr
1560 && fHostRW <= fGuestRW)
1561 continue;
1562 }
1563 cChanged++;
1564 /* Something was changed, so flush it. */
1565 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1566 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1567 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
1568 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1569 }
1570 }
1571 return cChanged;
1572}
1573
1574
1575/**
1576 * Flush a dirty page
1577 *
1578 * @param pVM VM Handle.
1579 * @param pPool The pool.
1580 * @param idxSlot Dirty array slot index
1581 * @param fAllowRemoval Allow a reused page table to be removed
1582 */
1583static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1584{
1585 PPGMPOOLPAGE pPage;
1586 unsigned idxPage;
1587
1588 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1589 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1590 return;
1591
1592 idxPage = pPool->aIdxDirtyPages[idxSlot];
1593 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1594 pPage = &pPool->aPages[idxPage];
1595 Assert(pPage->idx == idxPage);
1596 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1597
1598 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1599 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1600
1601 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1602 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1603 Assert(rc == VINF_SUCCESS);
1604 pPage->fDirty = false;
1605
1606#ifdef VBOX_STRICT
1607 uint64_t fFlags = 0;
1608 RTHCPHYS HCPhys;
1609 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1610 AssertMsg( ( rc == VINF_SUCCESS
1611 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1612 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1613 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1614 || rc == VERR_PAGE_NOT_PRESENT,
1615 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1616#endif
1617
1618 /* Flush those PTEs that have changed. */
1619 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1620 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1621 void *pvGst;
1622 bool fFlush;
1623 rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1624 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst, (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1625 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1626 /** Note: we might want to consider keeping the dirty page active in case there were many changes. */
1627
1628 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1629 Assert(pPage->cModifications);
1630 if (cChanges < 4)
1631 pPage->cModifications = 1; /* must use > 0 here */
1632 else
1633 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1634
1635 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1636 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1637 pPool->idxFreeDirtyPage = idxSlot;
1638
1639 pPool->cDirtyPages--;
1640 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1641 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1642 if (fFlush)
1643 {
1644 Assert(fAllowRemoval);
1645 Log(("Flush reused page table!\n"));
1646 pgmPoolFlushPage(pPool, pPage);
1647 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1648 }
1649 else
1650 Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1651}
1652
1653# ifndef IN_RING3
1654/**
1655 * Add a new dirty page
1656 *
1657 * @param pVM VM Handle.
1658 * @param pPool The pool.
1659 * @param pPage The page.
1660 */
1661void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1662{
1663 unsigned idxFree;
1664
1665 Assert(PGMIsLocked(pVM));
1666 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1667 Assert(!pPage->fDirty);
1668
1669 idxFree = pPool->idxFreeDirtyPage;
1670 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1671 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1672
1673 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1674 {
1675 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1676 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1677 }
1678 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1679 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1680
1681 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1682
1683 /* Make a copy of the guest page table as we require valid GCPhys addresses when removing
1684 * references to physical pages. (the HCPhys linear lookup is *extremely* expensive!)
1685 */
1686 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1687 void *pvGst;
1688 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1689 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1690#ifdef VBOX_STRICT
1691 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1692#endif
1693
1694 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1695 pPage->fDirty = true;
1696 pPage->idxDirty = idxFree;
1697 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1698 pPool->cDirtyPages++;
1699
1700 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1701 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1702 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1703 {
1704 unsigned i;
1705 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1706 {
1707 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1708 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1709 {
1710 pPool->idxFreeDirtyPage = idxFree;
1711 break;
1712 }
1713 }
1714 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1715 }
1716
1717 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1718 return;
1719}
1720# endif /* !IN_RING3 */
1721
1722/**
1723 * Check if the specified page is dirty (not write monitored)
1724 *
1725 * @return dirty or not
1726 * @param pVM VM Handle.
1727 * @param GCPhys Guest physical address
1728 */
1729bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1730{
1731 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1732 Assert(PGMIsLocked(pVM));
1733 if (!pPool->cDirtyPages)
1734 return false;
1735
1736 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1737
1738 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1739 {
1740 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1741 {
1742 PPGMPOOLPAGE pPage;
1743 unsigned idxPage = pPool->aIdxDirtyPages[i];
1744
1745 pPage = &pPool->aPages[idxPage];
1746 if (pPage->GCPhys == GCPhys)
1747 return true;
1748 }
1749 }
1750 return false;
1751}
1752
1753/**
1754 * Reset all dirty pages by reinstating page monitoring.
1755 *
1756 * @param pVM VM Handle.
1757 */
1758void pgmPoolResetDirtyPages(PVM pVM)
1759{
1760 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1761 Assert(PGMIsLocked(pVM));
1762 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1763
1764 if (!pPool->cDirtyPages)
1765 return;
1766
1767 Log(("pgmPoolResetDirtyPages\n"));
1768 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1769 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1770
1771 pPool->idxFreeDirtyPage = 0;
1772 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1773 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1774 {
1775 unsigned i;
1776 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1777 {
1778 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1779 {
1780 pPool->idxFreeDirtyPage = i;
1781 break;
1782 }
1783 }
1784 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1785 }
1786
1787 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1788 return;
1789}
1790
1791/**
1792 * Reset all dirty pages by reinstating page monitoring.
1793 *
1794 * @param pVM VM Handle.
1795 * @param GCPhysPT Physical address of the page table
1796 */
1797void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1798{
1799 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1800 Assert(PGMIsLocked(pVM));
1801 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1802 unsigned idxDirtyPage = RT_ELEMENTS(pPool->aIdxDirtyPages);
1803
1804 if (!pPool->cDirtyPages)
1805 return;
1806
1807 GCPhysPT = GCPhysPT & ~(RTGCPHYS)(PAGE_SIZE - 1);
1808
1809 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1810 {
1811 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1812 {
1813 unsigned idxPage = pPool->aIdxDirtyPages[i];
1814
1815 PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1816 if (pPage->GCPhys == GCPhysPT)
1817 {
1818 idxDirtyPage = i;
1819 break;
1820 }
1821 }
1822 }
1823
1824 if (idxDirtyPage != RT_ELEMENTS(pPool->aIdxDirtyPages))
1825 {
1826 pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1827 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1828 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1829 {
1830 unsigned i;
1831 for (i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1832 {
1833 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1834 {
1835 pPool->idxFreeDirtyPage = i;
1836 break;
1837 }
1838 }
1839 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1840 }
1841 }
1842}
1843
1844# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1845#endif /* PGMPOOL_WITH_MONITORING */
1846
1847#ifdef PGMPOOL_WITH_CACHE
1848
1849/**
1850 * Inserts a page into the GCPhys hash table.
1851 *
1852 * @param pPool The pool.
1853 * @param pPage The page.
1854 */
1855DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1856{
1857 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1858 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1859 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1860 pPage->iNext = pPool->aiHash[iHash];
1861 pPool->aiHash[iHash] = pPage->idx;
1862}
1863
1864
1865/**
1866 * Removes a page from the GCPhys hash table.
1867 *
1868 * @param pPool The pool.
1869 * @param pPage The page.
1870 */
1871DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1872{
1873 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1874 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1875 if (pPool->aiHash[iHash] == pPage->idx)
1876 pPool->aiHash[iHash] = pPage->iNext;
1877 else
1878 {
1879 uint16_t iPrev = pPool->aiHash[iHash];
1880 for (;;)
1881 {
1882 const int16_t i = pPool->aPages[iPrev].iNext;
1883 if (i == pPage->idx)
1884 {
1885 pPool->aPages[iPrev].iNext = pPage->iNext;
1886 break;
1887 }
1888 if (i == NIL_PGMPOOL_IDX)
1889 {
1890 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1891 break;
1892 }
1893 iPrev = i;
1894 }
1895 }
1896 pPage->iNext = NIL_PGMPOOL_IDX;
1897}
1898
1899
1900/**
1901 * Frees up one cache page.
1902 *
1903 * @returns VBox status code.
1904 * @retval VINF_SUCCESS on success.
1905 * @param pPool The pool.
1906 * @param iUser The user index.
1907 */
1908static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1909{
1910#ifndef IN_RC
1911 const PVM pVM = pPool->CTX_SUFF(pVM);
1912#endif
1913 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1914 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1915
1916 /*
1917 * Select one page from the tail of the age list.
1918 */
1919 PPGMPOOLPAGE pPage;
1920 for (unsigned iLoop = 0; ; iLoop++)
1921 {
1922 uint16_t iToFree = pPool->iAgeTail;
1923 if (iToFree == iUser)
1924 iToFree = pPool->aPages[iToFree].iAgePrev;
1925/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1926 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1927 {
1928 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1929 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1930 {
1931 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1932 continue;
1933 iToFree = i;
1934 break;
1935 }
1936 }
1937*/
1938 Assert(iToFree != iUser);
1939 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1940 pPage = &pPool->aPages[iToFree];
1941
1942 /*
1943 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1944 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1945 */
1946 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1947 break;
1948 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1949 pgmPoolCacheUsed(pPool, pPage);
1950 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1951 }
1952
1953 /*
1954 * Found a usable page, flush it and return.
1955 */
1956 return pgmPoolFlushPage(pPool, pPage);
1957}
1958
1959
1960/**
1961 * Checks if a kind mismatch is really a page being reused
1962 * or if it's just normal remappings.
1963 *
1964 * @returns true if reused and the cached page (enmKind1) should be flushed
1965 * @returns false if not reused.
1966 * @param enmKind1 The kind of the cached page.
1967 * @param enmKind2 The kind of the requested page.
1968 */
1969static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1970{
1971 switch (enmKind1)
1972 {
1973 /*
1974 * Never reuse them. There is no remapping in non-paging mode.
1975 */
1976 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1977 case PGMPOOLKIND_32BIT_PD_PHYS:
1978 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1979 case PGMPOOLKIND_PAE_PD_PHYS:
1980 case PGMPOOLKIND_PAE_PDPT_PHYS:
1981 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1982 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1983 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1984 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1985 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1986 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1987 return false;
1988
1989 /*
1990 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1991 */
1992 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1993 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1994 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1995 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1996 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1997 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1998 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1999 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2000 case PGMPOOLKIND_32BIT_PD:
2001 case PGMPOOLKIND_PAE_PDPT:
2002 switch (enmKind2)
2003 {
2004 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2005 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2006 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2007 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2008 case PGMPOOLKIND_64BIT_PML4:
2009 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2010 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2011 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2012 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2013 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2014 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2015 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2016 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2017 return true;
2018 default:
2019 return false;
2020 }
2021
2022 /*
2023 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2024 */
2025 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2026 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2027 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2028 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2029 case PGMPOOLKIND_64BIT_PML4:
2030 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2031 switch (enmKind2)
2032 {
2033 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2034 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2035 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2036 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2037 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2038 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2039 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2040 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2041 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2042 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2043 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2044 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2045 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2046 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2047 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2048 return true;
2049 default:
2050 return false;
2051 }
2052
2053 /*
2054 * These cannot be flushed, and it's common to reuse the PDs as PTs.
2055 */
2056 case PGMPOOLKIND_ROOT_NESTED:
2057 return false;
2058
2059 default:
2060 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2061 }
2062}
2063
2064
2065/**
2066 * Attempts to satisfy a pgmPoolAlloc request from the cache.
2067 *
2068 * @returns VBox status code.
2069 * @retval VINF_PGM_CACHED_PAGE on success.
2070 * @retval VERR_FILE_NOT_FOUND if not found.
2071 * @param pPool The pool.
2072 * @param GCPhys The GC physical address of the page we're gonna shadow.
2073 * @param enmKind The kind of mapping.
2074 * @param enmAccess Access type for the mapping (only relevant for big pages)
2075 * @param iUser The shadow page pool index of the user table.
2076 * @param iUserTable The index into the user table (shadowed).
2077 * @param ppPage Where to store the pointer to the page.
2078 */
2079static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2080{
2081#ifndef IN_RC
2082 const PVM pVM = pPool->CTX_SUFF(pVM);
2083#endif
2084 /*
2085 * Look up the GCPhys in the hash.
2086 */
2087 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2088 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2089 if (i != NIL_PGMPOOL_IDX)
2090 {
2091 do
2092 {
2093 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2094 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2095 if (pPage->GCPhys == GCPhys)
2096 {
2097 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2098 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2099 {
2100 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2101 * doesn't flush it in case there are no more free use records.
2102 */
2103 pgmPoolCacheUsed(pPool, pPage);
2104
2105 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2106 if (RT_SUCCESS(rc))
2107 {
2108 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2109 *ppPage = pPage;
2110 if (pPage->cModifications)
2111 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2112 STAM_COUNTER_INC(&pPool->StatCacheHits);
2113 return VINF_PGM_CACHED_PAGE;
2114 }
2115 return rc;
2116 }
2117
2118 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2119 {
2120 /*
2121 * The kind is different. In some cases we should now flush the page
2122 * as it has been reused, but in most cases this is normal remapping
2123 * of PDs as PT or big pages using the GCPhys field in a slightly
2124 * different way than the other kinds.
2125 */
2126 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2127 {
2128 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2129 pgmPoolFlushPage(pPool, pPage);
2130 break;
2131 }
2132 }
2133 }
2134
2135 /* next */
2136 i = pPage->iNext;
2137 } while (i != NIL_PGMPOOL_IDX);
2138 }
2139
2140 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2141 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2142 return VERR_FILE_NOT_FOUND;
2143}
2144
2145
2146/**
2147 * Inserts a page into the cache.
2148 *
2149 * @param pPool The pool.
2150 * @param pPage The cached page.
2151 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2152 */
2153static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2154{
2155 /*
2156 * Insert into the GCPhys hash if the page is fit for that.
2157 */
2158 Assert(!pPage->fCached);
2159 if (fCanBeCached)
2160 {
2161 pPage->fCached = true;
2162 pgmPoolHashInsert(pPool, pPage);
2163 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2164 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2165 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2166 }
2167 else
2168 {
2169 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2170 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2171 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2172 }
2173
2174 /*
2175 * Insert at the head of the age list.
2176 */
2177 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2178 pPage->iAgeNext = pPool->iAgeHead;
2179 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2180 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2181 else
2182 pPool->iAgeTail = pPage->idx;
2183 pPool->iAgeHead = pPage->idx;
2184}
2185
2186
2187/**
2188 * Flushes a cached page.
2189 *
2190 * @param pPool The pool.
2191 * @param pPage The cached page.
2192 */
2193static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2194{
2195 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2196
2197 /*
2198 * Remove the page from the hash.
2199 */
2200 if (pPage->fCached)
2201 {
2202 pPage->fCached = false;
2203 pgmPoolHashRemove(pPool, pPage);
2204 }
2205 else
2206 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2207
2208 /*
2209 * Remove it from the age list.
2210 */
2211 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2212 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2213 else
2214 pPool->iAgeTail = pPage->iAgePrev;
2215 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2216 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2217 else
2218 pPool->iAgeHead = pPage->iAgeNext;
2219 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2220 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2221}
2222
2223#endif /* PGMPOOL_WITH_CACHE */
2224#ifdef PGMPOOL_WITH_MONITORING
2225
2226/**
2227 * Looks for pages sharing the monitor.
2228 *
2229 * @returns Pointer to the head page.
2230 * @returns NULL if not found.
2231 * @param pPool The Pool
2232 * @param pNewPage The page which is going to be monitored.
2233 */
2234static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2235{
2236#ifdef PGMPOOL_WITH_CACHE
2237 /*
2238 * Look up the GCPhys in the hash.
2239 */
2240 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2241 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2242 if (i == NIL_PGMPOOL_IDX)
2243 return NULL;
2244 do
2245 {
2246 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2247 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2248 && pPage != pNewPage)
2249 {
2250 switch (pPage->enmKind)
2251 {
2252 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2253 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2254 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2255 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2256 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2257 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2258 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2259 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2260 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2261 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2262 case PGMPOOLKIND_64BIT_PML4:
2263 case PGMPOOLKIND_32BIT_PD:
2264 case PGMPOOLKIND_PAE_PDPT:
2265 {
2266 /* find the head */
2267 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2268 {
2269 Assert(pPage->iMonitoredPrev != pPage->idx);
2270 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2271 }
2272 return pPage;
2273 }
2274
2275 /* ignore, no monitoring. */
2276 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2277 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2278 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2279 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2280 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2281 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2282 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2283 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2284 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2285 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2286 case PGMPOOLKIND_ROOT_NESTED:
2287 case PGMPOOLKIND_PAE_PD_PHYS:
2288 case PGMPOOLKIND_PAE_PDPT_PHYS:
2289 case PGMPOOLKIND_32BIT_PD_PHYS:
2290 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2291 break;
2292 default:
2293 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2294 }
2295 }
2296
2297 /* next */
2298 i = pPage->iNext;
2299 } while (i != NIL_PGMPOOL_IDX);
2300#endif
2301 return NULL;
2302}
2303
2304
2305/**
2306 * Enabled write monitoring of a guest page.
2307 *
2308 * @returns VBox status code.
2309 * @retval VINF_SUCCESS on success.
2310 * @param pPool The pool.
2311 * @param pPage The cached page.
2312 */
2313static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2314{
2315 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2316
2317 /*
2318 * Filter out the relevant kinds.
2319 */
2320 switch (pPage->enmKind)
2321 {
2322 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2323 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2324 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2325 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2326 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2327 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2328 case PGMPOOLKIND_64BIT_PML4:
2329 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2330 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2331 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2332 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2333 case PGMPOOLKIND_32BIT_PD:
2334 case PGMPOOLKIND_PAE_PDPT:
2335 break;
2336
2337 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2338 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2339 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2340 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2341 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2342 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2343 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2344 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2345 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2346 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2347 case PGMPOOLKIND_ROOT_NESTED:
2348 /* Nothing to monitor here. */
2349 return VINF_SUCCESS;
2350
2351 case PGMPOOLKIND_32BIT_PD_PHYS:
2352 case PGMPOOLKIND_PAE_PDPT_PHYS:
2353 case PGMPOOLKIND_PAE_PD_PHYS:
2354 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2355 /* Nothing to monitor here. */
2356 return VINF_SUCCESS;
2357#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2358 break;
2359#else
2360 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2361#endif
2362 default:
2363 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2364 }
2365
2366 /*
2367 * Install handler.
2368 */
2369 int rc;
2370 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2371 if (pPageHead)
2372 {
2373 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2374 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2375
2376#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2377 if (pPageHead->fDirty)
2378 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2379#endif
2380
2381 pPage->iMonitoredPrev = pPageHead->idx;
2382 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2383 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2384 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2385 pPageHead->iMonitoredNext = pPage->idx;
2386 rc = VINF_SUCCESS;
2387 }
2388 else
2389 {
2390 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2391 PVM pVM = pPool->CTX_SUFF(pVM);
2392 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2393 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2394 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2395 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2396 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2397 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2398 pPool->pszAccessHandler);
2399 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2400 * the heap size should suffice. */
2401 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2402 Assert(!(VMMGetCpu(pVM)->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
2403 }
2404 pPage->fMonitored = true;
2405 return rc;
2406}
2407
2408
2409/**
2410 * Disables write monitoring of a guest page.
2411 *
2412 * @returns VBox status code.
2413 * @retval VINF_SUCCESS on success.
2414 * @param pPool The pool.
2415 * @param pPage The cached page.
2416 */
2417static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2418{
2419 /*
2420 * Filter out the relevant kinds.
2421 */
2422 switch (pPage->enmKind)
2423 {
2424 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2425 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2426 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2427 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2428 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2429 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2430 case PGMPOOLKIND_64BIT_PML4:
2431 case PGMPOOLKIND_32BIT_PD:
2432 case PGMPOOLKIND_PAE_PDPT:
2433 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2434 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2435 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2436 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2437 break;
2438
2439 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2440 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2441 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2442 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2443 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2444 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2445 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2446 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2447 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2448 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2449 case PGMPOOLKIND_ROOT_NESTED:
2450 case PGMPOOLKIND_PAE_PD_PHYS:
2451 case PGMPOOLKIND_PAE_PDPT_PHYS:
2452 case PGMPOOLKIND_32BIT_PD_PHYS:
2453 /* Nothing to monitor here. */
2454 return VINF_SUCCESS;
2455
2456#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2457 break;
2458#endif
2459 default:
2460 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2461 }
2462
2463 /*
2464 * Remove the page from the monitored list or uninstall it if last.
2465 */
2466 const PVM pVM = pPool->CTX_SUFF(pVM);
2467 int rc;
2468 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2469 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2470 {
2471 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2472 {
2473 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2474 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2475 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2476 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2477 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2478 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2479 pPool->pszAccessHandler);
2480 AssertFatalRCSuccess(rc);
2481 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2482 }
2483 else
2484 {
2485 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2486 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2487 {
2488 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2489 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2490 }
2491 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2492 rc = VINF_SUCCESS;
2493 }
2494 }
2495 else
2496 {
2497 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2498 AssertFatalRC(rc);
2499#ifdef VBOX_STRICT
2500 PVMCPU pVCpu = VMMGetCpu(pVM);
2501#endif
2502 AssertMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2503 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2504 }
2505 pPage->fMonitored = false;
2506
2507 /*
2508 * Remove it from the list of modified pages (if in it).
2509 */
2510 pgmPoolMonitorModifiedRemove(pPool, pPage);
2511
2512 return rc;
2513}
2514
2515
2516/**
2517 * Inserts the page into the list of modified pages.
2518 *
2519 * @param pPool The pool.
2520 * @param pPage The page.
2521 */
2522void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2523{
2524 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2525 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2526 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2527 && pPool->iModifiedHead != pPage->idx,
2528 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2529 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2530 pPool->iModifiedHead, pPool->cModifiedPages));
2531
2532 pPage->iModifiedNext = pPool->iModifiedHead;
2533 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2534 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2535 pPool->iModifiedHead = pPage->idx;
2536 pPool->cModifiedPages++;
2537#ifdef VBOX_WITH_STATISTICS
2538 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2539 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2540#endif
2541}
2542
2543
2544/**
2545 * Removes the page from the list of modified pages and resets the
2546 * moficiation counter.
2547 *
2548 * @param pPool The pool.
2549 * @param pPage The page which is believed to be in the list of modified pages.
2550 */
2551static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2552{
2553 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2554 if (pPool->iModifiedHead == pPage->idx)
2555 {
2556 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2557 pPool->iModifiedHead = pPage->iModifiedNext;
2558 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2559 {
2560 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2561 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2562 }
2563 pPool->cModifiedPages--;
2564 }
2565 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2566 {
2567 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2568 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2569 {
2570 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2571 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2572 }
2573 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2574 pPool->cModifiedPages--;
2575 }
2576 else
2577 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2578 pPage->cModifications = 0;
2579}
2580
2581
2582/**
2583 * Zaps the list of modified pages, resetting their modification counters in the process.
2584 *
2585 * @param pVM The VM handle.
2586 */
2587static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2588{
2589 pgmLock(pVM);
2590 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2591 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2592
2593 unsigned cPages = 0; NOREF(cPages);
2594
2595#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2596 pgmPoolResetDirtyPages(pVM);
2597#endif
2598
2599 uint16_t idx = pPool->iModifiedHead;
2600 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2601 while (idx != NIL_PGMPOOL_IDX)
2602 {
2603 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2604 idx = pPage->iModifiedNext;
2605 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2606 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2607 pPage->cModifications = 0;
2608 Assert(++cPages);
2609 }
2610 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2611 pPool->cModifiedPages = 0;
2612 pgmUnlock(pVM);
2613}
2614
2615
2616/**
2617 * Handle SyncCR3 pool tasks
2618 *
2619 * @returns VBox status code.
2620 * @retval VINF_SUCCESS if successfully added.
2621 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2622 * @param pVCpu The VMCPU handle.
2623 * @remark Should only be used when monitoring is available, thus placed in
2624 * the PGMPOOL_WITH_MONITORING #ifdef.
2625 */
2626int pgmPoolSyncCR3(PVMCPU pVCpu)
2627{
2628 PVM pVM = pVCpu->CTX_SUFF(pVM);
2629 LogFlow(("pgmPoolSyncCR3\n"));
2630
2631 /*
2632 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2633 * Occasionally we will have to clear all the shadow page tables because we wanted
2634 * to monitor a page which was mapped by too many shadowed page tables. This operation
2635 * sometimes refered to as a 'lightweight flush'.
2636 */
2637# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2638 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2639 pgmR3PoolClearAll(pVM);
2640# else /* !IN_RING3 */
2641 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2642 {
2643 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2644 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2645 return VINF_PGM_SYNC_CR3;
2646 }
2647# endif /* !IN_RING3 */
2648 else
2649 pgmPoolMonitorModifiedClearAll(pVM);
2650
2651 return VINF_SUCCESS;
2652}
2653
2654#endif /* PGMPOOL_WITH_MONITORING */
2655#ifdef PGMPOOL_WITH_USER_TRACKING
2656
2657/**
2658 * Frees up at least one user entry.
2659 *
2660 * @returns VBox status code.
2661 * @retval VINF_SUCCESS if successfully added.
2662 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2663 * @param pPool The pool.
2664 * @param iUser The user index.
2665 */
2666static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2667{
2668 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2669#ifdef PGMPOOL_WITH_CACHE
2670 /*
2671 * Just free cached pages in a braindead fashion.
2672 */
2673 /** @todo walk the age list backwards and free the first with usage. */
2674 int rc = VINF_SUCCESS;
2675 do
2676 {
2677 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2678 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2679 rc = rc2;
2680 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2681 return rc;
2682#else
2683 /*
2684 * Lazy approach.
2685 */
2686 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
2687 AssertCompileFailed();
2688 Assert(!CPUMIsGuestInLongMode(pVM));
2689 pgmPoolFlushAllInt(pPool);
2690 return VERR_PGM_POOL_FLUSHED;
2691#endif
2692}
2693
2694
2695/**
2696 * Inserts a page into the cache.
2697 *
2698 * This will create user node for the page, insert it into the GCPhys
2699 * hash, and insert it into the age list.
2700 *
2701 * @returns VBox status code.
2702 * @retval VINF_SUCCESS if successfully added.
2703 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2704 * @param pPool The pool.
2705 * @param pPage The cached page.
2706 * @param GCPhys The GC physical address of the page we're gonna shadow.
2707 * @param iUser The user index.
2708 * @param iUserTable The user table index.
2709 */
2710DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2711{
2712 int rc = VINF_SUCCESS;
2713 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2714
2715 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2716
2717#ifdef VBOX_STRICT
2718 /*
2719 * Check that the entry doesn't already exists.
2720 */
2721 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2722 {
2723 uint16_t i = pPage->iUserHead;
2724 do
2725 {
2726 Assert(i < pPool->cMaxUsers);
2727 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2728 i = paUsers[i].iNext;
2729 } while (i != NIL_PGMPOOL_USER_INDEX);
2730 }
2731#endif
2732
2733 /*
2734 * Find free a user node.
2735 */
2736 uint16_t i = pPool->iUserFreeHead;
2737 if (i == NIL_PGMPOOL_USER_INDEX)
2738 {
2739 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2740 if (RT_FAILURE(rc))
2741 return rc;
2742 i = pPool->iUserFreeHead;
2743 }
2744
2745 /*
2746 * Unlink the user node from the free list,
2747 * initialize and insert it into the user list.
2748 */
2749 pPool->iUserFreeHead = paUsers[i].iNext;
2750 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2751 paUsers[i].iUser = iUser;
2752 paUsers[i].iUserTable = iUserTable;
2753 pPage->iUserHead = i;
2754
2755 /*
2756 * Insert into cache and enable monitoring of the guest page if enabled.
2757 *
2758 * Until we implement caching of all levels, including the CR3 one, we'll
2759 * have to make sure we don't try monitor & cache any recursive reuse of
2760 * a monitored CR3 page. Because all windows versions are doing this we'll
2761 * have to be able to do combined access monitoring, CR3 + PT and
2762 * PD + PT (guest PAE).
2763 *
2764 * Update:
2765 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2766 */
2767#if defined(PGMPOOL_WITH_MONITORING) || defined(PGMPOOL_WITH_CACHE)
2768# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2769 const bool fCanBeMonitored = true;
2770# else
2771 bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2772 || (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2773 || pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2774# endif
2775# ifdef PGMPOOL_WITH_CACHE
2776 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2777# endif
2778 if (fCanBeMonitored)
2779 {
2780# ifdef PGMPOOL_WITH_MONITORING
2781 rc = pgmPoolMonitorInsert(pPool, pPage);
2782 AssertRC(rc);
2783 }
2784# endif
2785#endif /* PGMPOOL_WITH_MONITORING */
2786 return rc;
2787}
2788
2789
2790# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2791/**
2792 * Adds a user reference to a page.
2793 *
2794 * This will move the page to the head of the
2795 *
2796 * @returns VBox status code.
2797 * @retval VINF_SUCCESS if successfully added.
2798 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2799 * @param pPool The pool.
2800 * @param pPage The cached page.
2801 * @param iUser The user index.
2802 * @param iUserTable The user table.
2803 */
2804static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2805{
2806 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2807
2808 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2809
2810# ifdef VBOX_STRICT
2811 /*
2812 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2813 */
2814 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2815 {
2816 uint16_t i = pPage->iUserHead;
2817 do
2818 {
2819 Assert(i < pPool->cMaxUsers);
2820 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2821 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2822 i = paUsers[i].iNext;
2823 } while (i != NIL_PGMPOOL_USER_INDEX);
2824 }
2825# endif
2826
2827 /*
2828 * Allocate a user node.
2829 */
2830 uint16_t i = pPool->iUserFreeHead;
2831 if (i == NIL_PGMPOOL_USER_INDEX)
2832 {
2833 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2834 if (RT_FAILURE(rc))
2835 return rc;
2836 i = pPool->iUserFreeHead;
2837 }
2838 pPool->iUserFreeHead = paUsers[i].iNext;
2839
2840 /*
2841 * Initialize the user node and insert it.
2842 */
2843 paUsers[i].iNext = pPage->iUserHead;
2844 paUsers[i].iUser = iUser;
2845 paUsers[i].iUserTable = iUserTable;
2846 pPage->iUserHead = i;
2847
2848# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2849 if (pPage->fDirty)
2850 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2851# endif
2852
2853# ifdef PGMPOOL_WITH_CACHE
2854 /*
2855 * Tell the cache to update its replacement stats for this page.
2856 */
2857 pgmPoolCacheUsed(pPool, pPage);
2858# endif
2859 return VINF_SUCCESS;
2860}
2861# endif /* PGMPOOL_WITH_CACHE */
2862
2863
2864/**
2865 * Frees a user record associated with a page.
2866 *
2867 * This does not clear the entry in the user table, it simply replaces the
2868 * user record to the chain of free records.
2869 *
2870 * @param pPool The pool.
2871 * @param HCPhys The HC physical address of the shadow page.
2872 * @param iUser The shadow page pool index of the user table.
2873 * @param iUserTable The index into the user table (shadowed).
2874 */
2875static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2876{
2877 /*
2878 * Unlink and free the specified user entry.
2879 */
2880 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2881
2882 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2883 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2884 uint16_t i = pPage->iUserHead;
2885 if ( i != NIL_PGMPOOL_USER_INDEX
2886 && paUsers[i].iUser == iUser
2887 && paUsers[i].iUserTable == iUserTable)
2888 {
2889 pPage->iUserHead = paUsers[i].iNext;
2890
2891 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2892 paUsers[i].iNext = pPool->iUserFreeHead;
2893 pPool->iUserFreeHead = i;
2894 return;
2895 }
2896
2897 /* General: Linear search. */
2898 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2899 while (i != NIL_PGMPOOL_USER_INDEX)
2900 {
2901 if ( paUsers[i].iUser == iUser
2902 && paUsers[i].iUserTable == iUserTable)
2903 {
2904 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2905 paUsers[iPrev].iNext = paUsers[i].iNext;
2906 else
2907 pPage->iUserHead = paUsers[i].iNext;
2908
2909 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2910 paUsers[i].iNext = pPool->iUserFreeHead;
2911 pPool->iUserFreeHead = i;
2912 return;
2913 }
2914 iPrev = i;
2915 i = paUsers[i].iNext;
2916 }
2917
2918 /* Fatal: didn't find it */
2919 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2920 iUser, iUserTable, pPage->GCPhys));
2921}
2922
2923
2924/**
2925 * Gets the entry size of a shadow table.
2926 *
2927 * @param enmKind The kind of page.
2928 *
2929 * @returns The size of the entry in bytes. That is, 4 or 8.
2930 * @returns If the kind is not for a table, an assertion is raised and 0 is
2931 * returned.
2932 */
2933DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2934{
2935 switch (enmKind)
2936 {
2937 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2938 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2939 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2940 case PGMPOOLKIND_32BIT_PD:
2941 case PGMPOOLKIND_32BIT_PD_PHYS:
2942 return 4;
2943
2944 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2945 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2946 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2947 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2948 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2949 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2950 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2951 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2952 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2953 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2954 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2955 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2956 case PGMPOOLKIND_64BIT_PML4:
2957 case PGMPOOLKIND_PAE_PDPT:
2958 case PGMPOOLKIND_ROOT_NESTED:
2959 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2960 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2961 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2962 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2963 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2964 case PGMPOOLKIND_PAE_PD_PHYS:
2965 case PGMPOOLKIND_PAE_PDPT_PHYS:
2966 return 8;
2967
2968 default:
2969 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2970 }
2971}
2972
2973
2974/**
2975 * Gets the entry size of a guest table.
2976 *
2977 * @param enmKind The kind of page.
2978 *
2979 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2980 * @returns If the kind is not for a table, an assertion is raised and 0 is
2981 * returned.
2982 */
2983DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2984{
2985 switch (enmKind)
2986 {
2987 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2988 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2989 case PGMPOOLKIND_32BIT_PD:
2990 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2991 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2992 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2993 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2994 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2995 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2996 return 4;
2997
2998 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2999 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3000 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3001 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3002 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3003 case PGMPOOLKIND_64BIT_PML4:
3004 case PGMPOOLKIND_PAE_PDPT:
3005 return 8;
3006
3007 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3008 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3009 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3010 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3011 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3012 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3013 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3014 case PGMPOOLKIND_ROOT_NESTED:
3015 case PGMPOOLKIND_PAE_PD_PHYS:
3016 case PGMPOOLKIND_PAE_PDPT_PHYS:
3017 case PGMPOOLKIND_32BIT_PD_PHYS:
3018 /** @todo can we return 0? (nobody is calling this...) */
3019 AssertFailed();
3020 return 0;
3021
3022 default:
3023 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3024 }
3025}
3026
3027#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3028
3029/**
3030 * Scans one shadow page table for mappings of a physical page.
3031 *
3032 * @returns true/false indicating removal of all relevant PTEs
3033 * @param pVM The VM handle.
3034 * @param pPhysPage The guest page in question.
3035 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3036 * @param iShw The shadow page table.
3037 * @param cRefs The number of references made in that PT.
3038 * @param pfKeptPTEs Flag indicating removal of all relevant PTEs (out)
3039 */
3040static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3041{
3042 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3043 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3044 bool bRet = false;
3045
3046 /*
3047 * Assert sanity.
3048 */
3049 Assert(cRefs == 1);
3050 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3051 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3052
3053 /*
3054 * Then, clear the actual mappings to the page in the shadow PT.
3055 */
3056 switch (pPage->enmKind)
3057 {
3058 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3059 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3060 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3061 {
3062 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3063 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3064 uint32_t u32AndMask, u32OrMask;
3065
3066 u32AndMask = 0;
3067 u32OrMask = 0;
3068
3069 if (!fFlushPTEs)
3070 {
3071 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3072 {
3073 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3074 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3075 u32OrMask = X86_PTE_RW;
3076 u32AndMask = UINT32_MAX;
3077 bRet = true;
3078 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3079 break;
3080
3081 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3082 u32OrMask = 0;
3083 u32AndMask = ~X86_PTE_RW;
3084 bRet = true;
3085 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3086 break;
3087 default:
3088 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3089 break;
3090 }
3091 }
3092 else
3093 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3094
3095 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3096 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3097 {
3098 X86PTE Pte;
3099
3100 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
3101 Pte.u = (pPT->a[i].u & u32AndMask) | u32OrMask;
3102 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3103 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3104
3105 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3106 cRefs--;
3107 if (!cRefs)
3108 return bRet;
3109 }
3110#ifdef LOG_ENABLED
3111 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3112 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3113 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3114 {
3115 Log(("i=%d cRefs=%d\n", i, cRefs--));
3116 }
3117#endif
3118 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3119 break;
3120 }
3121
3122 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3123 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3124 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3125 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3126 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3127 {
3128 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3129 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3130 uint64_t u64AndMask, u64OrMask;
3131
3132 u64OrMask = 0;
3133 u64AndMask = 0;
3134 if (!fFlushPTEs)
3135 {
3136 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3137 {
3138 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3139 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3140 u64OrMask = X86_PTE_RW;
3141 u64AndMask = UINT64_MAX;
3142 bRet = true;
3143 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3144 break;
3145
3146 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3147 u64OrMask = 0;
3148 u64AndMask = ~((uint64_t)X86_PTE_RW);
3149 bRet = true;
3150 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3151 break;
3152
3153 default:
3154 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3155 break;
3156 }
3157 }
3158 else
3159 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3160
3161 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3162 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3163 {
3164 X86PTEPAE Pte;
3165
3166 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3167 Pte.u = (pPT->a[i].u & u64AndMask) | u64OrMask;
3168 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3169 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3170
3171 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3172 cRefs--;
3173 if (!cRefs)
3174 return bRet;
3175 }
3176#ifdef LOG_ENABLED
3177 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3178 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3179 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3180 {
3181 Log(("i=%d cRefs=%d\n", i, cRefs--));
3182 }
3183#endif
3184 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
3185 break;
3186 }
3187
3188 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3189 {
3190 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3191 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3192 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3193 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3194 {
3195 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3196 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3197 pPT->a[i].u = 0;
3198 cRefs--;
3199 if (!cRefs)
3200 return bRet;
3201 }
3202#ifdef LOG_ENABLED
3203 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3204 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3205 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3206 {
3207 Log(("i=%d cRefs=%d\n", i, cRefs--));
3208 }
3209#endif
3210 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3211 break;
3212 }
3213
3214 default:
3215 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3216 }
3217 return bRet;
3218}
3219
3220
3221/**
3222 * Scans one shadow page table for mappings of a physical page.
3223 *
3224 * @param pVM The VM handle.
3225 * @param pPhysPage The guest page in question.
3226 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3227 * @param iShw The shadow page table.
3228 * @param cRefs The number of references made in that PT.
3229 */
3230static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3231{
3232 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3233
3234 Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3235 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3236 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, cRefs);
3237 if (!fKeptPTEs)
3238 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3239 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3240}
3241
3242
3243/**
3244 * Flushes a list of shadow page tables mapping the same physical page.
3245 *
3246 * @param pVM The VM handle.
3247 * @param pPhysPage The guest page in question.
3248 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3249 * @param iPhysExt The physical cross reference extent list to flush.
3250 */
3251static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3252{
3253 Assert(PGMIsLockOwner(pVM));
3254 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3255 bool fKeepList = false;
3256
3257 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3258 Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3259
3260 const uint16_t iPhysExtStart = iPhysExt;
3261 PPGMPOOLPHYSEXT pPhysExt;
3262 do
3263 {
3264 Assert(iPhysExt < pPool->cMaxPhysExts);
3265 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3266 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3267 {
3268 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3269 {
3270 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], 1);
3271 if (!fKeptPTEs)
3272 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3273 else
3274 fKeepList = true;
3275 }
3276 }
3277 /* next */
3278 iPhysExt = pPhysExt->iNext;
3279 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3280
3281 if (!fKeepList)
3282 {
3283 /* insert the list into the free list and clear the ram range entry. */
3284 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3285 pPool->iPhysExtFreeHead = iPhysExtStart;
3286 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3287 }
3288
3289 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3290}
3291
3292#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3293
3294/**
3295 * Flushes all shadow page table mappings of the given guest page.
3296 *
3297 * This is typically called when the host page backing the guest one has been
3298 * replaced or when the page protection was changed due to an access handler.
3299 *
3300 * @returns VBox status code.
3301 * @retval VINF_SUCCESS if all references has been successfully cleared.
3302 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3303 * pool cleaning. FF and sync flags are set.
3304 *
3305 * @param pVM The VM handle.
3306 * @param pPhysPage The guest page in question.
3307 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3308 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3309 * flushed, it is NOT touched if this isn't necessary.
3310 * The caller MUST initialized this to @a false.
3311 */
3312int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3313{
3314 PVMCPU pVCpu = VMMGetCpu(pVM);
3315 pgmLock(pVM);
3316 int rc = VINF_SUCCESS;
3317#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3318 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3319 if (u16)
3320 {
3321 /*
3322 * The zero page is currently screwing up the tracking and we'll
3323 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3324 * is defined, zero pages won't normally be mapped. Some kind of solution
3325 * will be needed for this problem of course, but it will have to wait...
3326 */
3327 if (PGM_PAGE_IS_ZERO(pPhysPage))
3328 rc = VINF_PGM_GCPHYS_ALIASED;
3329 else
3330 {
3331# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3332 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3333 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3334 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3335# endif
3336
3337 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3338 pgmPoolTrackFlushGCPhysPT(pVM,
3339 pPhysPage,
3340 fFlushPTEs,
3341 PGMPOOL_TD_GET_IDX(u16),
3342 PGMPOOL_TD_GET_CREFS(u16));
3343 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3344 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3345 else
3346 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3347 *pfFlushTLBs = true;
3348
3349# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3350 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3351# endif
3352 }
3353 }
3354
3355#elif defined(PGMPOOL_WITH_CACHE)
3356 if (PGM_PAGE_IS_ZERO(pPhysPage))
3357 rc = VINF_PGM_GCPHYS_ALIASED;
3358 else
3359 {
3360# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3361 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kills the pool otherwise. */
3362 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3363# endif
3364 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3365 if (rc == VINF_SUCCESS)
3366 *pfFlushTLBs = true;
3367 }
3368
3369# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3370 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3371# endif
3372
3373#else
3374 rc = VINF_PGM_GCPHYS_ALIASED;
3375#endif
3376
3377 if (rc == VINF_PGM_GCPHYS_ALIASED)
3378 {
3379 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3380 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3381 rc = VINF_PGM_SYNC_CR3;
3382 }
3383 pgmUnlock(pVM);
3384 return rc;
3385}
3386
3387
3388/**
3389 * Scans all shadow page tables for mappings of a physical page.
3390 *
3391 * This may be slow, but it's most likely more efficient than cleaning
3392 * out the entire page pool / cache.
3393 *
3394 * @returns VBox status code.
3395 * @retval VINF_SUCCESS if all references has been successfully cleared.
3396 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3397 * a page pool cleaning.
3398 *
3399 * @param pVM The VM handle.
3400 * @param pPhysPage The guest page in question.
3401 */
3402int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3403{
3404 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3405 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3406 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3407 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3408
3409#if 1
3410 /*
3411 * There is a limit to what makes sense.
3412 */
3413 if (pPool->cPresent > 1024)
3414 {
3415 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3416 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3417 return VINF_PGM_GCPHYS_ALIASED;
3418 }
3419#endif
3420
3421 /*
3422 * Iterate all the pages until we've encountered all that in use.
3423 * This is simple but not quite optimal solution.
3424 */
3425 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3426 const uint32_t u32 = u64;
3427 unsigned cLeft = pPool->cUsedPages;
3428 unsigned iPage = pPool->cCurPages;
3429 while (--iPage >= PGMPOOL_IDX_FIRST)
3430 {
3431 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3432 if (pPage->GCPhys != NIL_RTGCPHYS)
3433 {
3434 switch (pPage->enmKind)
3435 {
3436 /*
3437 * We only care about shadow page tables.
3438 */
3439 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3440 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3441 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3442 {
3443 unsigned cPresent = pPage->cPresent;
3444 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3445 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3446 if (pPT->a[i].n.u1Present)
3447 {
3448 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3449 {
3450 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3451 pPT->a[i].u = 0;
3452 }
3453 if (!--cPresent)
3454 break;
3455 }
3456 break;
3457 }
3458
3459 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3460 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3461 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3462 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3463 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3464 {
3465 unsigned cPresent = pPage->cPresent;
3466 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3467 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3468 if (pPT->a[i].n.u1Present)
3469 {
3470 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3471 {
3472 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3473 pPT->a[i].u = 0;
3474 }
3475 if (!--cPresent)
3476 break;
3477 }
3478 break;
3479 }
3480 }
3481 if (!--cLeft)
3482 break;
3483 }
3484 }
3485
3486 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3487 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3488 return VINF_SUCCESS;
3489}
3490
3491
3492/**
3493 * Clears the user entry in a user table.
3494 *
3495 * This is used to remove all references to a page when flushing it.
3496 */
3497static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3498{
3499 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3500 Assert(pUser->iUser < pPool->cCurPages);
3501 uint32_t iUserTable = pUser->iUserTable;
3502
3503 /*
3504 * Map the user page.
3505 */
3506 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3507 union
3508 {
3509 uint64_t *pau64;
3510 uint32_t *pau32;
3511 } u;
3512 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3513
3514 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3515
3516 /* Safety precaution in case we change the paging for other modes too in the future. */
3517 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3518
3519#ifdef VBOX_STRICT
3520 /*
3521 * Some sanity checks.
3522 */
3523 switch (pUserPage->enmKind)
3524 {
3525 case PGMPOOLKIND_32BIT_PD:
3526 case PGMPOOLKIND_32BIT_PD_PHYS:
3527 Assert(iUserTable < X86_PG_ENTRIES);
3528 break;
3529 case PGMPOOLKIND_PAE_PDPT:
3530 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3531 case PGMPOOLKIND_PAE_PDPT_PHYS:
3532 Assert(iUserTable < 4);
3533 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3534 break;
3535 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3536 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3537 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3538 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3539 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3540 case PGMPOOLKIND_PAE_PD_PHYS:
3541 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3542 break;
3543 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3544 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3545 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3546 break;
3547 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3548 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3549 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3550 break;
3551 case PGMPOOLKIND_64BIT_PML4:
3552 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3553 /* GCPhys >> PAGE_SHIFT is the index here */
3554 break;
3555 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3556 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3557 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3558 break;
3559
3560 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3561 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3562 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3563 break;
3564
3565 case PGMPOOLKIND_ROOT_NESTED:
3566 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3567 break;
3568
3569 default:
3570 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3571 break;
3572 }
3573#endif /* VBOX_STRICT */
3574
3575 /*
3576 * Clear the entry in the user page.
3577 */
3578 switch (pUserPage->enmKind)
3579 {
3580 /* 32-bit entries */
3581 case PGMPOOLKIND_32BIT_PD:
3582 case PGMPOOLKIND_32BIT_PD_PHYS:
3583 u.pau32[iUserTable] = 0;
3584 break;
3585
3586 /* 64-bit entries */
3587 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3588 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3589 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3590 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3591 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3592#if defined(IN_RC)
3593 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3594 * non-present PDPT will continue to cause page faults.
3595 */
3596 ASMReloadCR3();
3597#endif
3598 /* no break */
3599 case PGMPOOLKIND_PAE_PD_PHYS:
3600 case PGMPOOLKIND_PAE_PDPT_PHYS:
3601 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3602 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3603 case PGMPOOLKIND_64BIT_PML4:
3604 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3605 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3606 case PGMPOOLKIND_PAE_PDPT:
3607 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3608 case PGMPOOLKIND_ROOT_NESTED:
3609 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3610 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3611 u.pau64[iUserTable] = 0;
3612 break;
3613
3614 default:
3615 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3616 }
3617}
3618
3619
3620/**
3621 * Clears all users of a page.
3622 */
3623static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3624{
3625 /*
3626 * Free all the user records.
3627 */
3628 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3629
3630 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3631 uint16_t i = pPage->iUserHead;
3632 while (i != NIL_PGMPOOL_USER_INDEX)
3633 {
3634 /* Clear enter in user table. */
3635 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3636
3637 /* Free it. */
3638 const uint16_t iNext = paUsers[i].iNext;
3639 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3640 paUsers[i].iNext = pPool->iUserFreeHead;
3641 pPool->iUserFreeHead = i;
3642
3643 /* Next. */
3644 i = iNext;
3645 }
3646 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3647}
3648
3649#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3650
3651/**
3652 * Allocates a new physical cross reference extent.
3653 *
3654 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3655 * @param pVM The VM handle.
3656 * @param piPhysExt Where to store the phys ext index.
3657 */
3658PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3659{
3660 Assert(PGMIsLockOwner(pVM));
3661 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3662 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3663 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3664 {
3665 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3666 return NULL;
3667 }
3668 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3669 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3670 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3671 *piPhysExt = iPhysExt;
3672 return pPhysExt;
3673}
3674
3675
3676/**
3677 * Frees a physical cross reference extent.
3678 *
3679 * @param pVM The VM handle.
3680 * @param iPhysExt The extent to free.
3681 */
3682void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3683{
3684 Assert(PGMIsLockOwner(pVM));
3685 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3686 Assert(iPhysExt < pPool->cMaxPhysExts);
3687 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3688 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3689 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3690 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3691 pPool->iPhysExtFreeHead = iPhysExt;
3692}
3693
3694
3695/**
3696 * Frees a physical cross reference extent.
3697 *
3698 * @param pVM The VM handle.
3699 * @param iPhysExt The extent to free.
3700 */
3701void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3702{
3703 Assert(PGMIsLockOwner(pVM));
3704 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3705
3706 const uint16_t iPhysExtStart = iPhysExt;
3707 PPGMPOOLPHYSEXT pPhysExt;
3708 do
3709 {
3710 Assert(iPhysExt < pPool->cMaxPhysExts);
3711 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3712 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3713 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3714
3715 /* next */
3716 iPhysExt = pPhysExt->iNext;
3717 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3718
3719 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3720 pPool->iPhysExtFreeHead = iPhysExtStart;
3721}
3722
3723
3724/**
3725 * Insert a reference into a list of physical cross reference extents.
3726 *
3727 * @returns The new tracking data for PGMPAGE.
3728 *
3729 * @param pVM The VM handle.
3730 * @param iPhysExt The physical extent index of the list head.
3731 * @param iShwPT The shadow page table index.
3732 *
3733 */
3734static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3735{
3736 Assert(PGMIsLockOwner(pVM));
3737 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3738 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3739
3740 /* special common case. */
3741 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3742 {
3743 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3744 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3745 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3746 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3747 }
3748
3749 /* general treatment. */
3750 const uint16_t iPhysExtStart = iPhysExt;
3751 unsigned cMax = 15;
3752 for (;;)
3753 {
3754 Assert(iPhysExt < pPool->cMaxPhysExts);
3755 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3756 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3757 {
3758 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3759 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3760 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3761 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3762 }
3763 if (!--cMax)
3764 {
3765 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3766 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3767 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3768 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3769 }
3770 }
3771
3772 /* add another extent to the list. */
3773 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3774 if (!pNew)
3775 {
3776 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3777 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3778 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3779 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3780 }
3781 pNew->iNext = iPhysExtStart;
3782 pNew->aidx[0] = iShwPT;
3783 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3784 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3785}
3786
3787
3788/**
3789 * Add a reference to guest physical page where extents are in use.
3790 *
3791 * @returns The new tracking data for PGMPAGE.
3792 *
3793 * @param pVM The VM handle.
3794 * @param u16 The ram range flags (top 16-bits).
3795 * @param iShwPT The shadow page table index.
3796 */
3797uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3798{
3799 pgmLock(pVM);
3800 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3801 {
3802 /*
3803 * Convert to extent list.
3804 */
3805 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3806 uint16_t iPhysExt;
3807 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3808 if (pPhysExt)
3809 {
3810 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3811 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3812 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3813 pPhysExt->aidx[1] = iShwPT;
3814 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3815 }
3816 else
3817 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3818 }
3819 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3820 {
3821 /*
3822 * Insert into the extent list.
3823 */
3824 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3825 }
3826 else
3827 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3828 pgmUnlock(pVM);
3829 return u16;
3830}
3831
3832
3833/**
3834 * Clear references to guest physical memory.
3835 *
3836 * @param pPool The pool.
3837 * @param pPage The page.
3838 * @param pPhysPage Pointer to the aPages entry in the ram range.
3839 */
3840void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3841{
3842 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3843 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3844
3845 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3846 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3847 {
3848 PVM pVM = pPool->CTX_SUFF(pVM);
3849 pgmLock(pVM);
3850
3851 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3852 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3853 do
3854 {
3855 Assert(iPhysExt < pPool->cMaxPhysExts);
3856
3857 /*
3858 * Look for the shadow page and check if it's all freed.
3859 */
3860 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3861 {
3862 if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3863 {
3864 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3865
3866 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3867 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3868 {
3869 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3870 pgmUnlock(pVM);
3871 return;
3872 }
3873
3874 /* we can free the node. */
3875 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3876 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3877 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3878 {
3879 /* lonely node */
3880 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3881 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3882 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3883 }
3884 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3885 {
3886 /* head */
3887 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3888 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3889 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3890 }
3891 else
3892 {
3893 /* in list */
3894 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3895 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3896 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3897 }
3898 iPhysExt = iPhysExtNext;
3899 pgmUnlock(pVM);
3900 return;
3901 }
3902 }
3903
3904 /* next */
3905 iPhysExtPrev = iPhysExt;
3906 iPhysExt = paPhysExts[iPhysExt].iNext;
3907 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3908
3909 pgmUnlock(pVM);
3910 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3911 }
3912 else /* nothing to do */
3913 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3914}
3915
3916
3917/**
3918 * Clear references to guest physical memory.
3919 *
3920 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3921 * is assumed to be correct, so the linear search can be skipped and we can assert
3922 * at an earlier point.
3923 *
3924 * @param pPool The pool.
3925 * @param pPage The page.
3926 * @param HCPhys The host physical address corresponding to the guest page.
3927 * @param GCPhys The guest physical address corresponding to HCPhys.
3928 */
3929static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3930{
3931 /*
3932 * Walk range list.
3933 */
3934 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3935 while (pRam)
3936 {
3937 RTGCPHYS off = GCPhys - pRam->GCPhys;
3938 if (off < pRam->cb)
3939 {
3940 /* does it match? */
3941 const unsigned iPage = off >> PAGE_SHIFT;
3942 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3943#ifdef LOG_ENABLED
3944RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3945Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3946#endif
3947 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3948 {
3949 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3950 return;
3951 }
3952 break;
3953 }
3954 pRam = pRam->CTX_SUFF(pNext);
3955 }
3956 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3957}
3958
3959
3960/**
3961 * Clear references to guest physical memory.
3962 *
3963 * @param pPool The pool.
3964 * @param pPage The page.
3965 * @param HCPhys The host physical address corresponding to the guest page.
3966 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3967 */
3968void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3969{
3970 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3971
3972 /*
3973 * Walk range list.
3974 */
3975 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3976 while (pRam)
3977 {
3978 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3979 if (off < pRam->cb)
3980 {
3981 /* does it match? */
3982 const unsigned iPage = off >> PAGE_SHIFT;
3983 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3984 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3985 {
3986 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3987 return;
3988 }
3989 break;
3990 }
3991 pRam = pRam->CTX_SUFF(pNext);
3992 }
3993
3994 /*
3995 * Damn, the hint didn't work. We'll have to do an expensive linear search.
3996 */
3997 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3998 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3999 while (pRam)
4000 {
4001 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4002 while (iPage-- > 0)
4003 {
4004 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4005 {
4006 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4007 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4008 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4009 return;
4010 }
4011 }
4012 pRam = pRam->CTX_SUFF(pNext);
4013 }
4014
4015 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
4016}
4017
4018
4019/**
4020 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
4021 *
4022 * @param pPool The pool.
4023 * @param pPage The page.
4024 * @param pShwPT The shadow page table (mapping of the page).
4025 * @param pGstPT The guest page table.
4026 */
4027DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4028{
4029 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4030 if (pShwPT->a[i].n.u1Present)
4031 {
4032 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4033 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4034 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4035 if (!--pPage->cPresent)
4036 break;
4037 }
4038}
4039
4040
4041/**
4042 * Clear references to guest physical memory in a PAE / 32-bit page table.
4043 *
4044 * @param pPool The pool.
4045 * @param pPage The page.
4046 * @param pShwPT The shadow page table (mapping of the page).
4047 * @param pGstPT The guest page table (just a half one).
4048 */
4049DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
4050{
4051 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4052 if (pShwPT->a[i].n.u1Present)
4053 {
4054 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4055 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4056 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4057 if (!--pPage->cPresent)
4058 break;
4059 }
4060}
4061
4062
4063/**
4064 * Clear references to guest physical memory in a PAE / PAE page table.
4065 *
4066 * @param pPool The pool.
4067 * @param pPage The page.
4068 * @param pShwPT The shadow page table (mapping of the page).
4069 * @param pGstPT The guest page table.
4070 */
4071DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4072{
4073 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4074 if (pShwPT->a[i].n.u1Present)
4075 {
4076 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4077 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4078 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
4079 if (!--pPage->cPresent)
4080 break;
4081 }
4082}
4083
4084
4085/**
4086 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4087 *
4088 * @param pPool The pool.
4089 * @param pPage The page.
4090 * @param pShwPT The shadow page table (mapping of the page).
4091 */
4092DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4093{
4094 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4095 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4096 if (pShwPT->a[i].n.u1Present)
4097 {
4098 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4099 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4100 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
4101 if (!--pPage->cPresent)
4102 break;
4103 }
4104}
4105
4106
4107/**
4108 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4109 *
4110 * @param pPool The pool.
4111 * @param pPage The page.
4112 * @param pShwPT The shadow page table (mapping of the page).
4113 */
4114DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4115{
4116 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4117 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4118 if (pShwPT->a[i].n.u1Present)
4119 {
4120 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4121 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4122 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
4123 if (!--pPage->cPresent)
4124 break;
4125 }
4126}
4127
4128
4129/**
4130 * Clear references to shadowed pages in an EPT page table.
4131 *
4132 * @param pPool The pool.
4133 * @param pPage The page.
4134 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4135 */
4136DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4137{
4138 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4139 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4140 if (pShwPT->a[i].n.u1Present)
4141 {
4142 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4143 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4144 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
4145 if (!--pPage->cPresent)
4146 break;
4147 }
4148}
4149
4150#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4151
4152
4153/**
4154 * Clear references to shadowed pages in a 32 bits page directory.
4155 *
4156 * @param pPool The pool.
4157 * @param pPage The page.
4158 * @param pShwPD The shadow page directory (mapping of the page).
4159 */
4160DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4161{
4162 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4163 {
4164 if ( pShwPD->a[i].n.u1Present
4165 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4166 )
4167 {
4168 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4169 if (pSubPage)
4170 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4171 else
4172 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4173 }
4174 }
4175}
4176
4177/**
4178 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4179 *
4180 * @param pPool The pool.
4181 * @param pPage The page.
4182 * @param pShwPD The shadow page directory (mapping of the page).
4183 */
4184DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4185{
4186 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4187 {
4188 if ( pShwPD->a[i].n.u1Present
4189 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4190 )
4191 {
4192 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4193 if (pSubPage)
4194 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4195 else
4196 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4197 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4198 }
4199 }
4200}
4201
4202/**
4203 * Clear references to shadowed pages in a PAE page directory pointer table.
4204 *
4205 * @param pPool The pool.
4206 * @param pPage The page.
4207 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4208 */
4209DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4210{
4211 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4212 {
4213 if ( pShwPDPT->a[i].n.u1Present
4214 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4215 )
4216 {
4217 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4218 if (pSubPage)
4219 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4220 else
4221 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4222 }
4223 }
4224}
4225
4226
4227/**
4228 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4229 *
4230 * @param pPool The pool.
4231 * @param pPage The page.
4232 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4233 */
4234DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4235{
4236 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4237 {
4238 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4239 if (pShwPDPT->a[i].n.u1Present)
4240 {
4241 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4242 if (pSubPage)
4243 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4244 else
4245 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4246 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4247 }
4248 }
4249}
4250
4251
4252/**
4253 * Clear references to shadowed pages in a 64-bit level 4 page table.
4254 *
4255 * @param pPool The pool.
4256 * @param pPage The page.
4257 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4258 */
4259DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4260{
4261 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4262 {
4263 if (pShwPML4->a[i].n.u1Present)
4264 {
4265 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4266 if (pSubPage)
4267 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4268 else
4269 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4270 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4271 }
4272 }
4273}
4274
4275
4276/**
4277 * Clear references to shadowed pages in an EPT page directory.
4278 *
4279 * @param pPool The pool.
4280 * @param pPage The page.
4281 * @param pShwPD The shadow page directory (mapping of the page).
4282 */
4283DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4284{
4285 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4286 {
4287 if (pShwPD->a[i].n.u1Present)
4288 {
4289 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4290 if (pSubPage)
4291 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4292 else
4293 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4294 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4295 }
4296 }
4297}
4298
4299
4300/**
4301 * Clear references to shadowed pages in an EPT page directory pointer table.
4302 *
4303 * @param pPool The pool.
4304 * @param pPage The page.
4305 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4306 */
4307DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4308{
4309 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4310 {
4311 if (pShwPDPT->a[i].n.u1Present)
4312 {
4313 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4314 if (pSubPage)
4315 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4316 else
4317 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4318 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4319 }
4320 }
4321}
4322
4323
4324/**
4325 * Clears all references made by this page.
4326 *
4327 * This includes other shadow pages and GC physical addresses.
4328 *
4329 * @param pPool The pool.
4330 * @param pPage The page.
4331 */
4332static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4333{
4334 /*
4335 * Map the shadow page and take action according to the page kind.
4336 */
4337 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
4338 switch (pPage->enmKind)
4339 {
4340#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4341 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4342 {
4343 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4344 void *pvGst;
4345 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4346 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4347 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4348 break;
4349 }
4350
4351 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4352 {
4353 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4354 void *pvGst;
4355 int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4356 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4357 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4358 break;
4359 }
4360
4361 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4362 {
4363 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4364 void *pvGst;
4365 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4366 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4367 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4368 break;
4369 }
4370
4371 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4372 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4373 {
4374 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4375 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4376 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4377 break;
4378 }
4379
4380 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4381 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4382 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4383 {
4384 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4385 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4386 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4387 break;
4388 }
4389
4390#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4391 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4392 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4393 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4394 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4395 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4396 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4397 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4398 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4399 break;
4400#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4401
4402 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4403 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4404 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4405 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4406 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4407 case PGMPOOLKIND_PAE_PD_PHYS:
4408 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4409 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4410 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4411 break;
4412
4413 case PGMPOOLKIND_32BIT_PD_PHYS:
4414 case PGMPOOLKIND_32BIT_PD:
4415 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4416 break;
4417
4418 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4419 case PGMPOOLKIND_PAE_PDPT:
4420 case PGMPOOLKIND_PAE_PDPT_PHYS:
4421 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4422 break;
4423
4424 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4425 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4426 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4427 break;
4428
4429 case PGMPOOLKIND_64BIT_PML4:
4430 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4431 break;
4432
4433 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4434 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4435 break;
4436
4437 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4438 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4439 break;
4440
4441 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4442 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4443 break;
4444
4445 default:
4446 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4447 }
4448
4449 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4450 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4451 ASMMemZeroPage(pvShw);
4452 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4453 pPage->fZeroed = true;
4454 PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
4455}
4456#endif /* PGMPOOL_WITH_USER_TRACKING */
4457
4458/**
4459 * Flushes a pool page.
4460 *
4461 * This moves the page to the free list after removing all user references to it.
4462 *
4463 * @returns VBox status code.
4464 * @retval VINF_SUCCESS on success.
4465 * @param pPool The pool.
4466 * @param HCPhys The HC physical address of the shadow page.
4467 */
4468int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4469{
4470 PVM pVM = pPool->CTX_SUFF(pVM);
4471
4472 int rc = VINF_SUCCESS;
4473 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4474 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4475 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4476
4477 /*
4478 * Quietly reject any attempts at flushing any of the special root pages.
4479 */
4480 if (pPage->idx < PGMPOOL_IDX_FIRST)
4481 {
4482 AssertFailed(); /* can no longer happen */
4483 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4484 return VINF_SUCCESS;
4485 }
4486
4487 pgmLock(pVM);
4488
4489 /*
4490 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4491 */
4492 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4493 {
4494 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4495 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4496 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4497 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4498 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4499 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4500 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4501 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4502 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4503 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4504 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4505 pgmUnlock(pVM);
4506 return VINF_SUCCESS;
4507 }
4508
4509#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4510 /* Start a subset so we won't run out of mapping space. */
4511 PVMCPU pVCpu = VMMGetCpu(pVM);
4512 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4513#endif
4514
4515 /*
4516 * Mark the page as being in need of an ASMMemZeroPage().
4517 */
4518 pPage->fZeroed = false;
4519
4520#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4521 if (pPage->fDirty)
4522 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4523#endif
4524
4525#ifdef PGMPOOL_WITH_USER_TRACKING
4526 /*
4527 * Clear the page.
4528 */
4529 pgmPoolTrackClearPageUsers(pPool, pPage);
4530 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4531 pgmPoolTrackDeref(pPool, pPage);
4532 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4533#endif
4534
4535#ifdef PGMPOOL_WITH_CACHE
4536 /*
4537 * Flush it from the cache.
4538 */
4539 pgmPoolCacheFlushPage(pPool, pPage);
4540#endif /* PGMPOOL_WITH_CACHE */
4541
4542#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4543 /* Heavy stuff done. */
4544 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4545#endif
4546
4547#ifdef PGMPOOL_WITH_MONITORING
4548 /*
4549 * Deregistering the monitoring.
4550 */
4551 if (pPage->fMonitored)
4552 rc = pgmPoolMonitorFlush(pPool, pPage);
4553#endif
4554
4555 /*
4556 * Free the page.
4557 */
4558 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4559 pPage->iNext = pPool->iFreeHead;
4560 pPool->iFreeHead = pPage->idx;
4561 pPage->enmKind = PGMPOOLKIND_FREE;
4562 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4563 pPage->GCPhys = NIL_RTGCPHYS;
4564 pPage->fReusedFlushPending = false;
4565
4566 pPool->cUsedPages--;
4567 pgmUnlock(pVM);
4568 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4569 return rc;
4570}
4571
4572
4573/**
4574 * Frees a usage of a pool page.
4575 *
4576 * The caller is responsible to updating the user table so that it no longer
4577 * references the shadow page.
4578 *
4579 * @param pPool The pool.
4580 * @param HCPhys The HC physical address of the shadow page.
4581 * @param iUser The shadow page pool index of the user table.
4582 * @param iUserTable The index into the user table (shadowed).
4583 */
4584void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4585{
4586 PVM pVM = pPool->CTX_SUFF(pVM);
4587
4588 STAM_PROFILE_START(&pPool->StatFree, a);
4589 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4590 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4591 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4592 pgmLock(pVM);
4593#ifdef PGMPOOL_WITH_USER_TRACKING
4594 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4595#endif
4596#ifdef PGMPOOL_WITH_CACHE
4597 if (!pPage->fCached)
4598#endif
4599 pgmPoolFlushPage(pPool, pPage);
4600 pgmUnlock(pVM);
4601 STAM_PROFILE_STOP(&pPool->StatFree, a);
4602}
4603
4604
4605/**
4606 * Makes one or more free page free.
4607 *
4608 * @returns VBox status code.
4609 * @retval VINF_SUCCESS on success.
4610 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4611 *
4612 * @param pPool The pool.
4613 * @param enmKind Page table kind
4614 * @param iUser The user of the page.
4615 */
4616static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4617{
4618 PVM pVM = pPool->CTX_SUFF(pVM);
4619
4620 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4621
4622 /*
4623 * If the pool isn't full grown yet, expand it.
4624 */
4625 if ( pPool->cCurPages < pPool->cMaxPages
4626#if defined(IN_RC)
4627 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4628 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4629 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4630#endif
4631 )
4632 {
4633 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4634#ifdef IN_RING3
4635 int rc = PGMR3PoolGrow(pVM);
4636#else
4637 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4638#endif
4639 if (RT_FAILURE(rc))
4640 return rc;
4641 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4642 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4643 return VINF_SUCCESS;
4644 }
4645
4646#ifdef PGMPOOL_WITH_CACHE
4647 /*
4648 * Free one cached page.
4649 */
4650 return pgmPoolCacheFreeOne(pPool, iUser);
4651#else
4652 /*
4653 * Flush the pool.
4654 *
4655 * If we have tracking enabled, it should be possible to come up with
4656 * a cheap replacement strategy...
4657 */
4658 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
4659 AssertCompileFailed();
4660 Assert(!CPUMIsGuestInLongMode(pVM));
4661 pgmPoolFlushAllInt(pPool);
4662 return VERR_PGM_POOL_FLUSHED;
4663#endif
4664}
4665
4666/**
4667 * Allocates a page from the pool.
4668 *
4669 * This page may actually be a cached page and not in need of any processing
4670 * on the callers part.
4671 *
4672 * @returns VBox status code.
4673 * @retval VINF_SUCCESS if a NEW page was allocated.
4674 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4675 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4676 * @param pVM The VM handle.
4677 * @param GCPhys The GC physical address of the page we're gonna shadow.
4678 * For 4MB and 2MB PD entries, it's the first address the
4679 * shadow PT is covering.
4680 * @param enmKind The kind of mapping.
4681 * @param enmAccess Access type for the mapping (only relevant for big pages)
4682 * @param iUser The shadow page pool index of the user table.
4683 * @param iUserTable The index into the user table (shadowed).
4684 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4685 * @param fLockPage Lock the page
4686 */
4687int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4688{
4689 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4690 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4691 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4692 *ppPage = NULL;
4693 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4694 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4695 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4696
4697 pgmLock(pVM);
4698
4699#ifdef PGMPOOL_WITH_CACHE
4700 if (pPool->fCacheEnabled)
4701 {
4702 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4703 if (RT_SUCCESS(rc2))
4704 {
4705 if (fLockPage)
4706 pgmPoolLockPage(pPool, *ppPage);
4707 pgmUnlock(pVM);
4708 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4709 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4710 return rc2;
4711 }
4712 }
4713#endif
4714
4715 /*
4716 * Allocate a new one.
4717 */
4718 int rc = VINF_SUCCESS;
4719 uint16_t iNew = pPool->iFreeHead;
4720 if (iNew == NIL_PGMPOOL_IDX)
4721 {
4722 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4723 if (RT_FAILURE(rc))
4724 {
4725 pgmUnlock(pVM);
4726 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4727 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4728 return rc;
4729 }
4730 iNew = pPool->iFreeHead;
4731 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4732 }
4733
4734 /* unlink the free head */
4735 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4736 pPool->iFreeHead = pPage->iNext;
4737 pPage->iNext = NIL_PGMPOOL_IDX;
4738
4739 /*
4740 * Initialize it.
4741 */
4742 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4743 pPage->enmKind = enmKind;
4744 pPage->enmAccess = enmAccess;
4745 pPage->GCPhys = GCPhys;
4746 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4747 pPage->fMonitored = false;
4748 pPage->fCached = false;
4749#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4750 pPage->fDirty = false;
4751#endif
4752 pPage->fReusedFlushPending = false;
4753#ifdef PGMPOOL_WITH_MONITORING
4754 pPage->cModifications = 0;
4755 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4756 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4757#else
4758 pPage->fCR3Mix = false;
4759#endif
4760#ifdef PGMPOOL_WITH_USER_TRACKING
4761 pPage->cPresent = 0;
4762 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4763 pPage->pvLastAccessHandlerFault = 0;
4764 pPage->cLastAccessHandlerCount = 0;
4765 pPage->pvLastAccessHandlerRip = 0;
4766
4767 /*
4768 * Insert into the tracking and cache. If this fails, free the page.
4769 */
4770 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4771 if (RT_FAILURE(rc3))
4772 {
4773 pPool->cUsedPages--;
4774 pPage->enmKind = PGMPOOLKIND_FREE;
4775 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4776 pPage->GCPhys = NIL_RTGCPHYS;
4777 pPage->iNext = pPool->iFreeHead;
4778 pPool->iFreeHead = pPage->idx;
4779 pgmUnlock(pVM);
4780 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4781 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4782 return rc3;
4783 }
4784#endif /* PGMPOOL_WITH_USER_TRACKING */
4785
4786 /*
4787 * Commit the allocation, clear the page and return.
4788 */
4789#ifdef VBOX_WITH_STATISTICS
4790 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4791 pPool->cUsedPagesHigh = pPool->cUsedPages;
4792#endif
4793
4794 if (!pPage->fZeroed)
4795 {
4796 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4797 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4798 ASMMemZeroPage(pv);
4799 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4800 }
4801
4802 *ppPage = pPage;
4803 if (fLockPage)
4804 pgmPoolLockPage(pPool, pPage);
4805 pgmUnlock(pVM);
4806 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4807 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4808 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4809 return rc;
4810}
4811
4812
4813/**
4814 * Frees a usage of a pool page.
4815 *
4816 * @param pVM The VM handle.
4817 * @param HCPhys The HC physical address of the shadow page.
4818 * @param iUser The shadow page pool index of the user table.
4819 * @param iUserTable The index into the user table (shadowed).
4820 */
4821void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4822{
4823 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4824 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4825 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4826}
4827
4828/**
4829 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4830 *
4831 * @returns Pointer to the shadow page structure.
4832 * @param pPool The pool.
4833 * @param HCPhys The HC physical address of the shadow page.
4834 */
4835PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4836{
4837 PVM pVM = pPool->CTX_SUFF(pVM);
4838
4839 Assert(PGMIsLockOwner(pVM));
4840
4841 /*
4842 * Look up the page.
4843 */
4844 pgmLock(pVM);
4845 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4846 pgmUnlock(pVM);
4847
4848 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4849 return pPage;
4850}
4851
4852#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4853/**
4854 * Flush the specified page if present
4855 *
4856 * @param pVM The VM handle.
4857 * @param GCPhys Guest physical address of the page to flush
4858 */
4859void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4860{
4861#ifdef PGMPOOL_WITH_CACHE
4862 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4863
4864 VM_ASSERT_EMT(pVM);
4865
4866 /*
4867 * Look up the GCPhys in the hash.
4868 */
4869 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4870 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4871 if (i == NIL_PGMPOOL_IDX)
4872 return;
4873
4874 do
4875 {
4876 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4877 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4878 {
4879 switch (pPage->enmKind)
4880 {
4881 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4882 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4883 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4884 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4885 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4886 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4887 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4888 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4889 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4890 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4891 case PGMPOOLKIND_64BIT_PML4:
4892 case PGMPOOLKIND_32BIT_PD:
4893 case PGMPOOLKIND_PAE_PDPT:
4894 {
4895 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4896#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4897 if (pPage->fDirty)
4898 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4899 else
4900#endif
4901 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4902 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4903 pgmPoolMonitorChainFlush(pPool, pPage);
4904 return;
4905 }
4906
4907 /* ignore, no monitoring. */
4908 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4909 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4910 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4911 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4912 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4913 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4914 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4915 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4916 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4917 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4918 case PGMPOOLKIND_ROOT_NESTED:
4919 case PGMPOOLKIND_PAE_PD_PHYS:
4920 case PGMPOOLKIND_PAE_PDPT_PHYS:
4921 case PGMPOOLKIND_32BIT_PD_PHYS:
4922 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4923 break;
4924
4925 default:
4926 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4927 }
4928 }
4929
4930 /* next */
4931 i = pPage->iNext;
4932 } while (i != NIL_PGMPOOL_IDX);
4933#endif
4934 return;
4935}
4936#endif /* IN_RING3 */
4937
4938#ifdef IN_RING3
4939/**
4940 * Flushes the entire cache.
4941 *
4942 * It will assert a global CR3 flush (FF) and assumes the caller is aware of
4943 * this and execute this CR3 flush.
4944 *
4945 * @param pPool The pool.
4946 */
4947void pgmR3PoolReset(PVM pVM)
4948{
4949 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4950
4951 Assert(PGMIsLockOwner(pVM));
4952 STAM_PROFILE_START(&pPool->StatR3Reset, a);
4953 LogFlow(("pgmR3PoolReset:\n"));
4954
4955 /*
4956 * If there are no pages in the pool, there is nothing to do.
4957 */
4958 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4959 {
4960 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
4961 return;
4962 }
4963
4964 /*
4965 * Exit the shadow mode since we're going to clear everything,
4966 * including the root page.
4967 */
4968 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4969 {
4970 PVMCPU pVCpu = &pVM->aCpus[i];
4971 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4972 }
4973
4974 /*
4975 * Nuke the free list and reinsert all pages into it.
4976 */
4977 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4978 {
4979 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4980
4981 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4982#ifdef PGMPOOL_WITH_MONITORING
4983 if (pPage->fMonitored)
4984 pgmPoolMonitorFlush(pPool, pPage);
4985 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4986 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4987 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4988 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4989 pPage->cModifications = 0;
4990#endif
4991 pPage->GCPhys = NIL_RTGCPHYS;
4992 pPage->enmKind = PGMPOOLKIND_FREE;
4993 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4994 Assert(pPage->idx == i);
4995 pPage->iNext = i + 1;
4996 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4997 pPage->fSeenNonGlobal = false;
4998 pPage->fMonitored = false;
4999#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5000 pPage->fDirty = false;
5001#endif
5002 pPage->fCached = false;
5003 pPage->fReusedFlushPending = false;
5004#ifdef PGMPOOL_WITH_USER_TRACKING
5005 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5006#else
5007 pPage->fCR3Mix = false;
5008#endif
5009#ifdef PGMPOOL_WITH_CACHE
5010 pPage->iAgeNext = NIL_PGMPOOL_IDX;
5011 pPage->iAgePrev = NIL_PGMPOOL_IDX;
5012#endif
5013 pPage->cLocked = 0;
5014 }
5015 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5016 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5017 pPool->cUsedPages = 0;
5018
5019#ifdef PGMPOOL_WITH_USER_TRACKING
5020 /*
5021 * Zap and reinitialize the user records.
5022 */
5023 pPool->cPresent = 0;
5024 pPool->iUserFreeHead = 0;
5025 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5026 const unsigned cMaxUsers = pPool->cMaxUsers;
5027 for (unsigned i = 0; i < cMaxUsers; i++)
5028 {
5029 paUsers[i].iNext = i + 1;
5030 paUsers[i].iUser = NIL_PGMPOOL_IDX;
5031 paUsers[i].iUserTable = 0xfffffffe;
5032 }
5033 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5034#endif
5035
5036#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
5037 /*
5038 * Clear all the GCPhys links and rebuild the phys ext free list.
5039 */
5040 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5041 pRam;
5042 pRam = pRam->CTX_SUFF(pNext))
5043 {
5044 unsigned iPage = pRam->cb >> PAGE_SHIFT;
5045 while (iPage-- > 0)
5046 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5047 }
5048
5049 pPool->iPhysExtFreeHead = 0;
5050 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5051 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5052 for (unsigned i = 0; i < cMaxPhysExts; i++)
5053 {
5054 paPhysExts[i].iNext = i + 1;
5055 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5056 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5057 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5058 }
5059 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5060#endif
5061
5062#ifdef PGMPOOL_WITH_MONITORING
5063 /*
5064 * Just zap the modified list.
5065 */
5066 pPool->cModifiedPages = 0;
5067 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5068#endif
5069
5070#ifdef PGMPOOL_WITH_CACHE
5071 /*
5072 * Clear the GCPhys hash and the age list.
5073 */
5074 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5075 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5076 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5077 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5078#endif
5079
5080#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5081 /* Clear all dirty pages. */
5082 pPool->idxFreeDirtyPage = 0;
5083 pPool->cDirtyPages = 0;
5084 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5085 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5086#endif
5087
5088 /*
5089 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5090 */
5091 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5092 {
5093 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5094 pPage->iNext = NIL_PGMPOOL_IDX;
5095#ifdef PGMPOOL_WITH_MONITORING
5096 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5097 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5098 pPage->cModifications = 0;
5099 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5100 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5101 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5102 if (pPage->fMonitored)
5103 {
5104 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5105 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5106 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5107 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5108 pPool->pszAccessHandler);
5109 AssertFatalRCSuccess(rc);
5110# ifdef PGMPOOL_WITH_CACHE
5111 pgmPoolHashInsert(pPool, pPage);
5112# endif
5113 }
5114#endif
5115#ifdef PGMPOOL_WITH_USER_TRACKING
5116 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5117#endif
5118#ifdef PGMPOOL_WITH_CACHE
5119 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5120 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5121#endif
5122 }
5123
5124 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5125 {
5126 /*
5127 * Re-enter the shadowing mode and assert Sync CR3 FF.
5128 */
5129 PVMCPU pVCpu = &pVM->aCpus[i];
5130 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5131 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5132 }
5133
5134 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5135}
5136#endif /* IN_RING3 */
5137
5138#ifdef LOG_ENABLED
5139static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5140{
5141 switch(enmKind)
5142 {
5143 case PGMPOOLKIND_INVALID:
5144 return "PGMPOOLKIND_INVALID";
5145 case PGMPOOLKIND_FREE:
5146 return "PGMPOOLKIND_FREE";
5147 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5148 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5149 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5150 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5151 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5152 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5153 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5154 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5155 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5156 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5157 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5158 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5159 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5160 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5161 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5162 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5163 case PGMPOOLKIND_32BIT_PD:
5164 return "PGMPOOLKIND_32BIT_PD";
5165 case PGMPOOLKIND_32BIT_PD_PHYS:
5166 return "PGMPOOLKIND_32BIT_PD_PHYS";
5167 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5168 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5169 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5170 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5171 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5172 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5173 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5174 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5175 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5176 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5177 case PGMPOOLKIND_PAE_PD_PHYS:
5178 return "PGMPOOLKIND_PAE_PD_PHYS";
5179 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5180 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5181 case PGMPOOLKIND_PAE_PDPT:
5182 return "PGMPOOLKIND_PAE_PDPT";
5183 case PGMPOOLKIND_PAE_PDPT_PHYS:
5184 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5185 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5186 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5187 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5188 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5189 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5190 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5191 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5192 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5193 case PGMPOOLKIND_64BIT_PML4:
5194 return "PGMPOOLKIND_64BIT_PML4";
5195 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5196 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5197 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5198 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5199 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5200 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5201 case PGMPOOLKIND_ROOT_NESTED:
5202 return "PGMPOOLKIND_ROOT_NESTED";
5203 }
5204 return "Unknown kind!";
5205}
5206#endif /* LOG_ENABLED*/
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