VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp@ 60185

Last change on this file since 60185 was 59073, checked in by vboxsync, 9 years ago

VMM: VINF_EM_DBG_EVENT and DBGFEventGenericWithArg implementation.

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1/* $Id: PGMAllPhys.cpp 59073 2015-12-10 12:48:03Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM_PHYS
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/trpm.h>
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/iom.h>
27#include <VBox/vmm/em.h>
28#ifdef VBOX_WITH_REM
29# include <VBox/vmm/rem.h>
30#endif
31#include "PGMInternal.h"
32#include <VBox/vmm/vm.h>
33#include "PGMInline.h"
34#include <VBox/param.h>
35#include <VBox/err.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38#include <iprt/asm-amd64-x86.h>
39#include <VBox/log.h>
40#ifdef IN_RING3
41# include <iprt/thread.h>
42#endif
43
44
45/*********************************************************************************************************************************
46* Defined Constants And Macros *
47*********************************************************************************************************************************/
48/** Enable the physical TLB. */
49#define PGM_WITH_PHYS_TLB
50
51/** @def PGM_HANDLER_PHYS_IS_VALID_STATUS
52 * Checks if valid physical access handler return code (normal handler, not PF).
53 *
54 * Checks if the given strict status code is one of the expected ones for a
55 * physical access handler in the current context.
56 *
57 * @returns true or false.
58 * @param a_rcStrict The status code.
59 * @param a_fWrite Whether it is a write or read being serviced.
60 *
61 * @remarks We wish to keep the list of statuses here as short as possible.
62 * When changing, please make sure to update the PGMPhysRead,
63 * PGMPhysWrite, PGMPhysReadGCPtr and PGMPhysWriteGCPtr docs too.
64 */
65#ifdef IN_RING3
66# define PGM_HANDLER_PHYS_IS_VALID_STATUS(a_rcStrict, a_fWrite) \
67 ( (a_rcStrict) == VINF_SUCCESS \
68 || (a_rcStrict) == VINF_PGM_HANDLER_DO_DEFAULT)
69#elif defined(IN_RING0) || defined(IN_RC)
70# define PGM_HANDLER_PHYS_IS_VALID_STATUS(a_rcStrict, a_fWrite) \
71 ( (a_rcStrict) == VINF_SUCCESS \
72 || (a_rcStrict) == VINF_PGM_HANDLER_DO_DEFAULT \
73 \
74 || (a_rcStrict) == ((a_fWrite) ? VINF_IOM_R3_MMIO_WRITE : VINF_IOM_R3_MMIO_READ) \
75 || (a_rcStrict) == VINF_IOM_R3_MMIO_READ_WRITE \
76 \
77 || ((a_fWrite) ? (a_rcStrict) == VINF_EM_RAW_EMULATE_IO_BLOCK : false) \
78 \
79 || (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR \
80 || (a_rcStrict) == VINF_EM_DBG_STOP \
81 || (a_rcStrict) == VINF_EM_DBG_EVENT \
82 || (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
83 || (a_rcStrict) == VINF_EM_OFF \
84 || (a_rcStrict) == VINF_EM_SUSPEND \
85 || (a_rcStrict) == VINF_EM_RESET \
86 )
87#else
88# error "Context?"
89#endif
90
91/** @def PGM_HANDLER_VIRT_IS_VALID_STATUS
92 * Checks if valid virtual access handler return code (normal handler, not PF).
93 *
94 * Checks if the given strict status code is one of the expected ones for a
95 * virtual access handler in the current context.
96 *
97 * @returns true or false.
98 * @param a_rcStrict The status code.
99 * @param a_fWrite Whether it is a write or read being serviced.
100 *
101 * @remarks We wish to keep the list of statuses here as short as possible.
102 * When changing, please make sure to update the PGMPhysRead,
103 * PGMPhysWrite, PGMPhysReadGCPtr and PGMPhysWriteGCPtr docs too.
104 */
105#ifdef IN_RING3
106# define PGM_HANDLER_VIRT_IS_VALID_STATUS(a_rcStrict, a_fWrite) \
107 ( (a_rcStrict) == VINF_SUCCESS \
108 || (a_rcStrict) == VINF_PGM_HANDLER_DO_DEFAULT)
109#elif defined(IN_RING0)
110# define PGM_HANDLER_VIRT_IS_VALID_STATUS(a_rcStrict, a_fWrite) \
111 (false /* no virtual handlers in ring-0! */ )
112#elif defined(IN_RC)
113# define PGM_HANDLER_VIRT_IS_VALID_STATUS(a_rcStrict, a_fWrite) \
114 ( (a_rcStrict) == VINF_SUCCESS \
115 || (a_rcStrict) == VINF_PGM_HANDLER_DO_DEFAULT \
116 \
117 || ((a_fWrite) ? (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT : 0) \
118 || ((a_fWrite) ? (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT : 0) \
119 || ((a_fWrite) ? (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT : 0) \
120 || ((a_fWrite) ? (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT : 0) \
121 || ((a_fWrite) ? (a_rcStrict) == VINF_SELM_SYNC_GDT : 0) \
122 || ((a_fWrite) ? (a_rcStrict) == VINF_CSAM_PENDING_ACTION : 0) \
123 || (a_rcStrict) == VINF_PATM_CHECK_PATCH_PAGE \
124 \
125 || (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR \
126 || (a_rcStrict) == VINF_EM_DBG_STOP \
127 || (a_rcStrict) == VINF_EM_DBG_EVENT \
128 || (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
129 )
130#else
131# error "Context?"
132#endif
133
134
135
136#ifndef IN_RING3
137
138/**
139 * @callback_method_impl{FNPGMPHYSHANDLER,
140 * Dummy for forcing ring-3 handling of the access.}
141 */
142DECLEXPORT(VBOXSTRICTRC)
143pgmPhysHandlerRedirectToHC(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
144 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
145{
146 NOREF(pVM); NOREF(pVCpu); NOREF(GCPhys); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf);
147 NOREF(enmAccessType); NOREF(enmOrigin); NOREF(pvUser);
148 return VINF_EM_RAW_EMULATE_INSTR;
149}
150
151
152/**
153 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
154 * Dummy for forcing ring-3 handling of the access.}
155 */
156VMMDECL(VBOXSTRICTRC) pgmPhysPfHandlerRedirectToHC(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
157 RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
158{
159 NOREF(pVM); NOREF(pVCpu); NOREF(uErrorCode); NOREF(pRegFrame); NOREF(pvFault); NOREF(GCPhysFault); NOREF(pvUser);
160 return VINF_EM_RAW_EMULATE_INSTR;
161}
162
163
164/**
165 * @callback_method_impl{FNPGMRZPHYSPFHANDLER,
166 * \#PF access handler callback for guest ROM range write access.}
167 *
168 * @remarks The @a pvUser argument points to the PGMROMRANGE.
169 */
170DECLEXPORT(VBOXSTRICTRC) pgmPhysRomWritePfHandler(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
171 RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
172{
173 int rc;
174 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
175 uint32_t iPage = (GCPhysFault - pRom->GCPhys) >> PAGE_SHIFT;
176 NOREF(uErrorCode); NOREF(pvFault);
177
178 Assert(uErrorCode & X86_TRAP_PF_RW); /* This shall not be used for read access! */
179
180 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
181 switch (pRom->aPages[iPage].enmProt)
182 {
183 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
184 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
185 {
186 /*
187 * If it's a simple instruction which doesn't change the cpu state
188 * we will simply skip it. Otherwise we'll have to defer it to REM.
189 */
190 uint32_t cbOp;
191 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
192 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
193 if ( RT_SUCCESS(rc)
194 && pDis->uCpuMode == DISCPUMODE_32BIT /** @todo why does this matter? */
195 && !(pDis->fPrefix & (DISPREFIX_REPNE | DISPREFIX_REP | DISPREFIX_SEG)))
196 {
197 switch (pDis->bOpCode)
198 {
199 /** @todo Find other instructions we can safely skip, possibly
200 * adding this kind of detection to DIS or EM. */
201 case OP_MOV:
202 pRegFrame->rip += cbOp;
203 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestROMWriteHandled);
204 return VINF_SUCCESS;
205 }
206 }
207 break;
208 }
209
210 case PGMROMPROT_READ_RAM_WRITE_RAM:
211 pRom->aPages[iPage].LiveSave.fWrittenTo = true;
212 rc = PGMHandlerPhysicalPageTempOff(pVM, pRom->GCPhys, GCPhysFault & X86_PTE_PG_MASK);
213 AssertRC(rc);
214 break; /** @todo Must edit the shadow PT and restart the instruction, not use the interpreter! */
215
216 case PGMROMPROT_READ_ROM_WRITE_RAM:
217 /* Handle it in ring-3 because it's *way* easier there. */
218 pRom->aPages[iPage].LiveSave.fWrittenTo = true;
219 break;
220
221 default:
222 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhysFault=%RGp\n",
223 pRom->aPages[iPage].enmProt, iPage, GCPhysFault),
224 VERR_IPE_NOT_REACHED_DEFAULT_CASE);
225 }
226
227 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestROMWriteUnhandled);
228 return VINF_EM_RAW_EMULATE_INSTR;
229}
230
231#endif /* !IN_RING3 */
232
233
234/**
235 * @callback_method_impl{FNPGMPHYSHANDLER,
236 * Access handler callback for ROM write accesses.}
237 *
238 * @remarks The @a pvUser argument points to the PGMROMRANGE.
239 */
240PGM_ALL_CB2_DECL(VBOXSTRICTRC)
241pgmPhysRomWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
242 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
243{
244 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
245 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
246 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
247 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
248 Log5(("pgmPhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
249 NOREF(pVCpu); NOREF(pvPhys); NOREF(enmOrigin);
250
251 if (enmAccessType == PGMACCESSTYPE_READ)
252 {
253 switch (pRomPage->enmProt)
254 {
255 /*
256 * Take the default action.
257 */
258 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
259 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
260 case PGMROMPROT_READ_ROM_WRITE_RAM:
261 case PGMROMPROT_READ_RAM_WRITE_RAM:
262 return VINF_PGM_HANDLER_DO_DEFAULT;
263
264 default:
265 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
266 pRom->aPages[iPage].enmProt, iPage, GCPhys),
267 VERR_IPE_NOT_REACHED_DEFAULT_CASE);
268 }
269 }
270 else
271 {
272 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
273 switch (pRomPage->enmProt)
274 {
275 /*
276 * Ignore writes.
277 */
278 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
279 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
280 return VINF_SUCCESS;
281
282 /*
283 * Write to the RAM page.
284 */
285 case PGMROMPROT_READ_ROM_WRITE_RAM:
286 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
287 {
288 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
289 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
290
291 /*
292 * Take the lock, do lazy allocation, map the page and copy the data.
293 *
294 * Note that we have to bypass the mapping TLB since it works on
295 * guest physical addresses and entering the shadow page would
296 * kind of screw things up...
297 */
298 int rc = pgmLock(pVM);
299 AssertRC(rc);
300
301 PPGMPAGE pShadowPage = &pRomPage->Shadow;
302 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
303 {
304 pShadowPage = pgmPhysGetPage(pVM, GCPhys);
305 AssertLogRelReturn(pShadowPage, VERR_PGM_PHYS_PAGE_GET_IPE);
306 }
307
308 void *pvDstPage;
309 rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
310 if (RT_SUCCESS(rc))
311 {
312 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
313 pRomPage->LiveSave.fWrittenTo = true;
314
315 AssertMsg( rc == VINF_SUCCESS
316 || ( rc == VINF_PGM_SYNC_CR3
317 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
318 , ("%Rrc\n", rc));
319 rc = VINF_SUCCESS;
320 }
321
322 pgmUnlock(pVM);
323 return rc;
324 }
325
326 default:
327 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
328 pRom->aPages[iPage].enmProt, iPage, GCPhys),
329 VERR_IPE_NOT_REACHED_DEFAULT_CASE);
330 }
331 }
332}
333
334
335/**
336 * Invalidates the RAM range TLBs.
337 *
338 * @param pVM The cross context VM structure.
339 */
340void pgmPhysInvalidRamRangeTlbs(PVM pVM)
341{
342 pgmLock(pVM);
343 for (uint32_t i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
344 {
345 pVM->pgm.s.apRamRangesTlbR3[i] = NIL_RTR3PTR;
346 pVM->pgm.s.apRamRangesTlbR0[i] = NIL_RTR0PTR;
347 pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
348 }
349 pgmUnlock(pVM);
350}
351
352
353/**
354 * Tests if a value of type RTGCPHYS is negative if the type had been signed
355 * instead of unsigned.
356 *
357 * @returns @c true if negative, @c false if positive or zero.
358 * @param a_GCPhys The value to test.
359 * @todo Move me to iprt/types.h.
360 */
361#define RTGCPHYS_IS_NEGATIVE(a_GCPhys) ((a_GCPhys) & ((RTGCPHYS)1 << (sizeof(RTGCPHYS)*8 - 1)))
362
363
364/**
365 * Slow worker for pgmPhysGetRange.
366 *
367 * @copydoc pgmPhysGetRange
368 */
369PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys)
370{
371 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,RamRangeTlbMisses));
372
373 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangeTree);
374 while (pRam)
375 {
376 RTGCPHYS off = GCPhys - pRam->GCPhys;
377 if (off < pRam->cb)
378 {
379 pVM->pgm.s.CTX_SUFF(apRamRangesTlb)[PGM_RAMRANGE_TLB_IDX(GCPhys)] = pRam;
380 return pRam;
381 }
382 if (RTGCPHYS_IS_NEGATIVE(off))
383 pRam = pRam->CTX_SUFF(pLeft);
384 else
385 pRam = pRam->CTX_SUFF(pRight);
386 }
387 return NULL;
388}
389
390
391/**
392 * Slow worker for pgmPhysGetRangeAtOrAbove.
393 *
394 * @copydoc pgmPhysGetRangeAtOrAbove
395 */
396PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys)
397{
398 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,RamRangeTlbMisses));
399
400 PPGMRAMRANGE pLastLeft = NULL;
401 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangeTree);
402 while (pRam)
403 {
404 RTGCPHYS off = GCPhys - pRam->GCPhys;
405 if (off < pRam->cb)
406 {
407 pVM->pgm.s.CTX_SUFF(apRamRangesTlb)[PGM_RAMRANGE_TLB_IDX(GCPhys)] = pRam;
408 return pRam;
409 }
410 if (RTGCPHYS_IS_NEGATIVE(off))
411 {
412 pLastLeft = pRam;
413 pRam = pRam->CTX_SUFF(pLeft);
414 }
415 else
416 pRam = pRam->CTX_SUFF(pRight);
417 }
418 return pLastLeft;
419}
420
421
422/**
423 * Slow worker for pgmPhysGetPage.
424 *
425 * @copydoc pgmPhysGetPage
426 */
427PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys)
428{
429 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,RamRangeTlbMisses));
430
431 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangeTree);
432 while (pRam)
433 {
434 RTGCPHYS off = GCPhys - pRam->GCPhys;
435 if (off < pRam->cb)
436 {
437 pVM->pgm.s.CTX_SUFF(apRamRangesTlb)[PGM_RAMRANGE_TLB_IDX(GCPhys)] = pRam;
438 return &pRam->aPages[off >> PAGE_SHIFT];
439 }
440
441 if (RTGCPHYS_IS_NEGATIVE(off))
442 pRam = pRam->CTX_SUFF(pLeft);
443 else
444 pRam = pRam->CTX_SUFF(pRight);
445 }
446 return NULL;
447}
448
449
450/**
451 * Slow worker for pgmPhysGetPageEx.
452 *
453 * @copydoc pgmPhysGetPageEx
454 */
455int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
456{
457 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,RamRangeTlbMisses));
458
459 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangeTree);
460 while (pRam)
461 {
462 RTGCPHYS off = GCPhys - pRam->GCPhys;
463 if (off < pRam->cb)
464 {
465 pVM->pgm.s.CTX_SUFF(apRamRangesTlb)[PGM_RAMRANGE_TLB_IDX(GCPhys)] = pRam;
466 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
467 return VINF_SUCCESS;
468 }
469
470 if (RTGCPHYS_IS_NEGATIVE(off))
471 pRam = pRam->CTX_SUFF(pLeft);
472 else
473 pRam = pRam->CTX_SUFF(pRight);
474 }
475
476 *ppPage = NULL;
477 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
478}
479
480
481/**
482 * Slow worker for pgmPhysGetPageAndRangeEx.
483 *
484 * @copydoc pgmPhysGetPageAndRangeEx
485 */
486int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
487{
488 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,RamRangeTlbMisses));
489
490 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangeTree);
491 while (pRam)
492 {
493 RTGCPHYS off = GCPhys - pRam->GCPhys;
494 if (off < pRam->cb)
495 {
496 pVM->pgm.s.CTX_SUFF(apRamRangesTlb)[PGM_RAMRANGE_TLB_IDX(GCPhys)] = pRam;
497 *ppRam = pRam;
498 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
499 return VINF_SUCCESS;
500 }
501
502 if (RTGCPHYS_IS_NEGATIVE(off))
503 pRam = pRam->CTX_SUFF(pLeft);
504 else
505 pRam = pRam->CTX_SUFF(pRight);
506 }
507
508 *ppRam = NULL;
509 *ppPage = NULL;
510 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
511}
512
513
514/**
515 * Checks if Address Gate 20 is enabled or not.
516 *
517 * @returns true if enabled.
518 * @returns false if disabled.
519 * @param pVCpu The cross context virtual CPU structure.
520 */
521VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu)
522{
523 LogFlow(("PGMPhysIsA20Enabled %d\n", pVCpu->pgm.s.fA20Enabled));
524 return pVCpu->pgm.s.fA20Enabled;
525}
526
527
528/**
529 * Validates a GC physical address.
530 *
531 * @returns true if valid.
532 * @returns false if invalid.
533 * @param pVM The cross context VM structure.
534 * @param GCPhys The physical address to validate.
535 */
536VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys)
537{
538 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
539 return pPage != NULL;
540}
541
542
543/**
544 * Checks if a GC physical address is a normal page,
545 * i.e. not ROM, MMIO or reserved.
546 *
547 * @returns true if normal.
548 * @returns false if invalid, ROM, MMIO or reserved page.
549 * @param pVM The cross context VM structure.
550 * @param GCPhys The physical address to check.
551 */
552VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys)
553{
554 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
555 return pPage
556 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM;
557}
558
559
560/**
561 * Converts a GC physical address to a HC physical address.
562 *
563 * @returns VINF_SUCCESS on success.
564 * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
565 * page but has no physical backing.
566 * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
567 * GC physical address.
568 *
569 * @param pVM The cross context VM structure.
570 * @param GCPhys The GC physical address to convert.
571 * @param pHCPhys Where to store the HC physical address on success.
572 */
573VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
574{
575 pgmLock(pVM);
576 PPGMPAGE pPage;
577 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
578 if (RT_SUCCESS(rc))
579 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
580 pgmUnlock(pVM);
581 return rc;
582}
583
584
585/**
586 * Invalidates all page mapping TLBs.
587 *
588 * @param pVM The cross context VM structure.
589 */
590void pgmPhysInvalidatePageMapTLB(PVM pVM)
591{
592 pgmLock(pVM);
593 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatPageMapTlbFlushes);
594
595 /* Clear the shared R0/R3 TLB completely. */
596 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
597 {
598 pVM->pgm.s.PhysTlbHC.aEntries[i].GCPhys = NIL_RTGCPHYS;
599 pVM->pgm.s.PhysTlbHC.aEntries[i].pPage = 0;
600 pVM->pgm.s.PhysTlbHC.aEntries[i].pMap = 0;
601 pVM->pgm.s.PhysTlbHC.aEntries[i].pv = 0;
602 }
603
604 /** @todo clear the RC TLB whenever we add it. */
605
606 pgmUnlock(pVM);
607}
608
609
610/**
611 * Invalidates a page mapping TLB entry
612 *
613 * @param pVM The cross context VM structure.
614 * @param GCPhys GCPhys entry to flush
615 */
616void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys)
617{
618 PGM_LOCK_ASSERT_OWNER(pVM);
619
620 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatPageMapTlbFlushEntry);
621
622#ifdef IN_RC
623 unsigned idx = PGM_PAGER3MAPTLB_IDX(GCPhys);
624 pVM->pgm.s.PhysTlbHC.aEntries[idx].GCPhys = NIL_RTGCPHYS;
625 pVM->pgm.s.PhysTlbHC.aEntries[idx].pPage = 0;
626 pVM->pgm.s.PhysTlbHC.aEntries[idx].pMap = 0;
627 pVM->pgm.s.PhysTlbHC.aEntries[idx].pv = 0;
628#else
629 /* Clear the shared R0/R3 TLB entry. */
630 PPGMPAGEMAPTLBE pTlbe = &pVM->pgm.s.CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
631 pTlbe->GCPhys = NIL_RTGCPHYS;
632 pTlbe->pPage = 0;
633 pTlbe->pMap = 0;
634 pTlbe->pv = 0;
635#endif
636
637 /** @todo clear the RC TLB whenever we add it. */
638}
639
640/**
641 * Makes sure that there is at least one handy page ready for use.
642 *
643 * This will also take the appropriate actions when reaching water-marks.
644 *
645 * @returns VBox status code.
646 * @retval VINF_SUCCESS on success.
647 * @retval VERR_EM_NO_MEMORY if we're really out of memory.
648 *
649 * @param pVM The cross context VM structure.
650 *
651 * @remarks Must be called from within the PGM critical section. It may
652 * nip back to ring-3/0 in some cases.
653 */
654static int pgmPhysEnsureHandyPage(PVM pVM)
655{
656 AssertMsg(pVM->pgm.s.cHandyPages <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d\n", pVM->pgm.s.cHandyPages));
657
658 /*
659 * Do we need to do anything special?
660 */
661#ifdef IN_RING3
662 if (pVM->pgm.s.cHandyPages <= RT_MAX(PGM_HANDY_PAGES_SET_FF, PGM_HANDY_PAGES_R3_ALLOC))
663#else
664 if (pVM->pgm.s.cHandyPages <= RT_MAX(PGM_HANDY_PAGES_SET_FF, PGM_HANDY_PAGES_RZ_TO_R3))
665#endif
666 {
667 /*
668 * Allocate pages only if we're out of them, or in ring-3, almost out.
669 */
670#ifdef IN_RING3
671 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_R3_ALLOC)
672#else
673 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_RZ_ALLOC)
674#endif
675 {
676 Log(("PGM: cHandyPages=%u out of %u -> allocate more; VM_FF_PGM_NO_MEMORY=%RTbool\n",
677 pVM->pgm.s.cHandyPages, RT_ELEMENTS(pVM->pgm.s.aHandyPages), VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY) ));
678#ifdef IN_RING3
679 int rc = PGMR3PhysAllocateHandyPages(pVM);
680#else
681 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES, 0);
682#endif
683 if (RT_UNLIKELY(rc != VINF_SUCCESS))
684 {
685 if (RT_FAILURE(rc))
686 return rc;
687 AssertMsgReturn(rc == VINF_EM_NO_MEMORY, ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
688 if (!pVM->pgm.s.cHandyPages)
689 {
690 LogRel(("PGM: no more handy pages!\n"));
691 return VERR_EM_NO_MEMORY;
692 }
693 Assert(VM_FF_IS_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES));
694 Assert(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY));
695#ifdef IN_RING3
696# ifdef VBOX_WITH_REM
697 REMR3NotifyFF(pVM);
698# endif
699#else
700 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TO_R3); /* paranoia */
701#endif
702 }
703 AssertMsgReturn( pVM->pgm.s.cHandyPages > 0
704 && pVM->pgm.s.cHandyPages <= RT_ELEMENTS(pVM->pgm.s.aHandyPages),
705 ("%u\n", pVM->pgm.s.cHandyPages),
706 VERR_PGM_HANDY_PAGE_IPE);
707 }
708 else
709 {
710 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_SET_FF)
711 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
712#ifndef IN_RING3
713 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_RZ_TO_R3)
714 {
715 Log(("PGM: VM_FF_TO_R3 - cHandyPages=%u out of %u\n", pVM->pgm.s.cHandyPages, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
716 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TO_R3);
717 }
718#endif
719 }
720 }
721
722 return VINF_SUCCESS;
723}
724
725
726/**
727 * Replace a zero or shared page with new page that we can write to.
728 *
729 * @returns The following VBox status codes.
730 * @retval VINF_SUCCESS on success, pPage is modified.
731 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
732 * @retval VERR_EM_NO_MEMORY if we're totally out of memory.
733 *
734 * @todo Propagate VERR_EM_NO_MEMORY up the call tree.
735 *
736 * @param pVM The cross context VM structure.
737 * @param pPage The physical page tracking structure. This will
738 * be modified on success.
739 * @param GCPhys The address of the page.
740 *
741 * @remarks Must be called from within the PGM critical section. It may
742 * nip back to ring-3/0 in some cases.
743 *
744 * @remarks This function shouldn't really fail, however if it does
745 * it probably means we've screwed up the size of handy pages and/or
746 * the low-water mark. Or, that some device I/O is causing a lot of
747 * pages to be allocated while while the host is in a low-memory
748 * condition. This latter should be handled elsewhere and in a more
749 * controlled manner, it's on the @bugref{3170} todo list...
750 */
751int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
752{
753 LogFlow(("pgmPhysAllocPage: %R[pgmpage] %RGp\n", pPage, GCPhys));
754
755 /*
756 * Prereqs.
757 */
758 PGM_LOCK_ASSERT_OWNER(pVM);
759 AssertMsg(PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_SHARED(pPage), ("%R[pgmpage] %RGp\n", pPage, GCPhys));
760 Assert(!PGM_PAGE_IS_MMIO_OR_ALIAS(pPage));
761
762# ifdef PGM_WITH_LARGE_PAGES
763 /*
764 * Try allocate a large page if applicable.
765 */
766 if ( PGMIsUsingLargePages(pVM)
767 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
768 {
769 RTGCPHYS GCPhysBase = GCPhys & X86_PDE2M_PAE_PG_MASK;
770 PPGMPAGE pBasePage;
771
772 int rc = pgmPhysGetPageEx(pVM, GCPhysBase, &pBasePage);
773 AssertRCReturn(rc, rc); /* paranoia; can't happen. */
774 if (PGM_PAGE_GET_PDE_TYPE(pBasePage) == PGM_PAGE_PDE_TYPE_DONTCARE)
775 {
776 rc = pgmPhysAllocLargePage(pVM, GCPhys);
777 if (rc == VINF_SUCCESS)
778 return rc;
779 }
780 /* Mark the base as type page table, so we don't check over and over again. */
781 PGM_PAGE_SET_PDE_TYPE(pVM, pBasePage, PGM_PAGE_PDE_TYPE_PT);
782
783 /* fall back to 4KB pages. */
784 }
785# endif
786
787 /*
788 * Flush any shadow page table mappings of the page.
789 * When VBOX_WITH_NEW_LAZY_PAGE_ALLOC isn't defined, there shouldn't be any.
790 */
791 bool fFlushTLBs = false;
792 int rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhys, pPage, true /*fFlushTLBs*/, &fFlushTLBs);
793 AssertMsgReturn(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc), RT_FAILURE(rc) ? rc : VERR_IPE_UNEXPECTED_STATUS);
794
795 /*
796 * Ensure that we've got a page handy, take it and use it.
797 */
798 int rc2 = pgmPhysEnsureHandyPage(pVM);
799 if (RT_FAILURE(rc2))
800 {
801 if (fFlushTLBs)
802 PGM_INVL_ALL_VCPU_TLBS(pVM);
803 Assert(rc2 == VERR_EM_NO_MEMORY);
804 return rc2;
805 }
806 /* re-assert preconditions since pgmPhysEnsureHandyPage may do a context switch. */
807 PGM_LOCK_ASSERT_OWNER(pVM);
808 AssertMsg(PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_SHARED(pPage), ("%R[pgmpage] %RGp\n", pPage, GCPhys));
809 Assert(!PGM_PAGE_IS_MMIO_OR_ALIAS(pPage));
810
811 uint32_t iHandyPage = --pVM->pgm.s.cHandyPages;
812 AssertMsg(iHandyPage < RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d\n", iHandyPage));
813 Assert(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys != NIL_RTHCPHYS);
814 Assert(!(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK));
815 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idPage != NIL_GMM_PAGEID);
816 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage == NIL_GMM_PAGEID);
817
818 /*
819 * There are one or two action to be taken the next time we allocate handy pages:
820 * - Tell the GMM (global memory manager) what the page is being used for.
821 * (Speeds up replacement operations - sharing and defragmenting.)
822 * - If the current backing is shared, it must be freed.
823 */
824 const RTHCPHYS HCPhys = pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys;
825 pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
826
827 void const *pvSharedPage = NULL;
828 if (PGM_PAGE_IS_SHARED(pPage))
829 {
830 /* Mark this shared page for freeing/dereferencing. */
831 pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage = PGM_PAGE_GET_PAGEID(pPage);
832 Assert(PGM_PAGE_GET_PAGEID(pPage) != NIL_GMM_PAGEID);
833
834 Log(("PGM: Replaced shared page %#x at %RGp with %#x / %RHp\n", PGM_PAGE_GET_PAGEID(pPage),
835 GCPhys, pVM->pgm.s.aHandyPages[iHandyPage].idPage, HCPhys));
836 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageReplaceShared));
837 pVM->pgm.s.cSharedPages--;
838
839 /* Grab the address of the page so we can make a copy later on. (safe) */
840 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvSharedPage);
841 AssertRC(rc);
842 }
843 else
844 {
845 Log2(("PGM: Replaced zero page %RGp with %#x / %RHp\n", GCPhys, pVM->pgm.s.aHandyPages[iHandyPage].idPage, HCPhys));
846 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRZPageReplaceZero);
847 pVM->pgm.s.cZeroPages--;
848 }
849
850 /*
851 * Do the PGMPAGE modifications.
852 */
853 pVM->pgm.s.cPrivatePages++;
854 PGM_PAGE_SET_HCPHYS(pVM, pPage, HCPhys);
855 PGM_PAGE_SET_PAGEID(pVM, pPage, pVM->pgm.s.aHandyPages[iHandyPage].idPage);
856 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
857 PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PT);
858 pgmPhysInvalidatePageMapTLBEntry(pVM, GCPhys);
859
860 /* Copy the shared page contents to the replacement page. */
861 if (pvSharedPage)
862 {
863 /* Get the virtual address of the new page. */
864 PGMPAGEMAPLOCK PgMpLck;
865 void *pvNewPage;
866 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvNewPage, &PgMpLck); AssertRC(rc);
867 if (RT_SUCCESS(rc))
868 {
869 memcpy(pvNewPage, pvSharedPage, PAGE_SIZE); /** @todo todo write ASMMemCopyPage */
870 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
871 }
872 }
873
874 if ( fFlushTLBs
875 && rc != VINF_PGM_GCPHYS_ALIASED)
876 PGM_INVL_ALL_VCPU_TLBS(pVM);
877 return rc;
878}
879
880#ifdef PGM_WITH_LARGE_PAGES
881
882/**
883 * Replace a 2 MB range of zero pages with new pages that we can write to.
884 *
885 * @returns The following VBox status codes.
886 * @retval VINF_SUCCESS on success, pPage is modified.
887 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
888 * @retval VERR_EM_NO_MEMORY if we're totally out of memory.
889 *
890 * @todo Propagate VERR_EM_NO_MEMORY up the call tree.
891 *
892 * @param pVM The cross context VM structure.
893 * @param GCPhys The address of the page.
894 *
895 * @remarks Must be called from within the PGM critical section. It may
896 * nip back to ring-3/0 in some cases.
897 */
898int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys)
899{
900 RTGCPHYS GCPhysBase = GCPhys & X86_PDE2M_PAE_PG_MASK;
901 LogFlow(("pgmPhysAllocLargePage: %RGp base %RGp\n", GCPhys, GCPhysBase));
902
903 /*
904 * Prereqs.
905 */
906 PGM_LOCK_ASSERT_OWNER(pVM);
907 Assert(PGMIsUsingLargePages(pVM));
908
909 PPGMPAGE pFirstPage;
910 int rc = pgmPhysGetPageEx(pVM, GCPhysBase, &pFirstPage);
911 if ( RT_SUCCESS(rc)
912 && PGM_PAGE_GET_TYPE(pFirstPage) == PGMPAGETYPE_RAM)
913 {
914 unsigned uPDEType = PGM_PAGE_GET_PDE_TYPE(pFirstPage);
915
916 /* Don't call this function for already allocated pages. */
917 Assert(uPDEType != PGM_PAGE_PDE_TYPE_PDE);
918
919 if ( uPDEType == PGM_PAGE_PDE_TYPE_DONTCARE
920 && PGM_PAGE_GET_STATE(pFirstPage) == PGM_PAGE_STATE_ZERO)
921 {
922 /* Lazy approach: check all pages in the 2 MB range.
923 * The whole range must be ram and unallocated. */
924 GCPhys = GCPhysBase;
925 unsigned iPage;
926 for (iPage = 0; iPage < _2M/PAGE_SIZE; iPage++)
927 {
928 PPGMPAGE pSubPage;
929 rc = pgmPhysGetPageEx(pVM, GCPhys, &pSubPage);
930 if ( RT_FAILURE(rc)
931 || PGM_PAGE_GET_TYPE(pSubPage) != PGMPAGETYPE_RAM /* Anything other than ram implies monitoring. */
932 || PGM_PAGE_GET_STATE(pSubPage) != PGM_PAGE_STATE_ZERO) /* Allocated, monitored or shared means we can't use a large page here */
933 {
934 LogFlow(("Found page %RGp with wrong attributes (type=%d; state=%d); cancel check. rc=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pSubPage), PGM_PAGE_GET_STATE(pSubPage), rc));
935 break;
936 }
937 Assert(PGM_PAGE_GET_PDE_TYPE(pSubPage) == PGM_PAGE_PDE_TYPE_DONTCARE);
938 GCPhys += PAGE_SIZE;
939 }
940 if (iPage != _2M/PAGE_SIZE)
941 {
942 /* Failed. Mark as requiring a PT so we don't check the whole thing again in the future. */
943 STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageRefused);
944 PGM_PAGE_SET_PDE_TYPE(pVM, pFirstPage, PGM_PAGE_PDE_TYPE_PT);
945 return VERR_PGM_INVALID_LARGE_PAGE_RANGE;
946 }
947
948 /*
949 * Do the allocation.
950 */
951# ifdef IN_RING3
952 rc = PGMR3PhysAllocateLargeHandyPage(pVM, GCPhysBase);
953# else
954 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_ALLOCATE_LARGE_HANDY_PAGE, GCPhysBase);
955# endif
956 if (RT_SUCCESS(rc))
957 {
958 Assert(PGM_PAGE_GET_STATE(pFirstPage) == PGM_PAGE_STATE_ALLOCATED);
959 pVM->pgm.s.cLargePages++;
960 return VINF_SUCCESS;
961 }
962
963 /* If we fail once, it most likely means the host's memory is too
964 fragmented; don't bother trying again. */
965 LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
966 PGMSetLargePageUsage(pVM, false);
967 return rc;
968 }
969 }
970 return VERR_PGM_INVALID_LARGE_PAGE_RANGE;
971}
972
973
974/**
975 * Recheck the entire 2 MB range to see if we can use it again as a large page.
976 *
977 * @returns The following VBox status codes.
978 * @retval VINF_SUCCESS on success, the large page can be used again
979 * @retval VERR_PGM_INVALID_LARGE_PAGE_RANGE if it can't be reused
980 *
981 * @param pVM The cross context VM structure.
982 * @param GCPhys The address of the page.
983 * @param pLargePage Page structure of the base page
984 */
985int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage)
986{
987 STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageRecheck);
988
989 GCPhys &= X86_PDE2M_PAE_PG_MASK;
990
991 /* Check the base page. */
992 Assert(PGM_PAGE_GET_PDE_TYPE(pLargePage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED);
993 if ( PGM_PAGE_GET_STATE(pLargePage) != PGM_PAGE_STATE_ALLOCATED
994 || PGM_PAGE_GET_TYPE(pLargePage) != PGMPAGETYPE_RAM
995 || PGM_PAGE_GET_HNDL_PHYS_STATE(pLargePage) != PGM_PAGE_HNDL_PHYS_STATE_NONE)
996 {
997 LogFlow(("pgmPhysRecheckLargePage: checks failed for base page %x %x %x\n", PGM_PAGE_GET_STATE(pLargePage), PGM_PAGE_GET_TYPE(pLargePage), PGM_PAGE_GET_HNDL_PHYS_STATE(pLargePage)));
998 return VERR_PGM_INVALID_LARGE_PAGE_RANGE;
999 }
1000
1001 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,IsValidLargePage), a);
1002 /* Check all remaining pages in the 2 MB range. */
1003 unsigned i;
1004 GCPhys += PAGE_SIZE;
1005 for (i = 1; i < _2M/PAGE_SIZE; i++)
1006 {
1007 PPGMPAGE pPage;
1008 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1009 AssertRCBreak(rc);
1010
1011 if ( PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1012 || PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
1013 || PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
1014 || PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE)
1015 {
1016 LogFlow(("pgmPhysRecheckLargePage: checks failed for page %d; %x %x %x\n", i, PGM_PAGE_GET_STATE(pPage), PGM_PAGE_GET_TYPE(pPage), PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)));
1017 break;
1018 }
1019
1020 GCPhys += PAGE_SIZE;
1021 }
1022 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,IsValidLargePage), a);
1023
1024 if (i == _2M/PAGE_SIZE)
1025 {
1026 PGM_PAGE_SET_PDE_TYPE(pVM, pLargePage, PGM_PAGE_PDE_TYPE_PDE);
1027 pVM->pgm.s.cLargePagesDisabled--;
1028 Log(("pgmPhysRecheckLargePage: page %RGp can be reused!\n", GCPhys - _2M));
1029 return VINF_SUCCESS;
1030 }
1031
1032 return VERR_PGM_INVALID_LARGE_PAGE_RANGE;
1033}
1034
1035#endif /* PGM_WITH_LARGE_PAGES */
1036
1037/**
1038 * Deal with a write monitored page.
1039 *
1040 * @returns VBox strict status code.
1041 *
1042 * @param pVM The cross context VM structure.
1043 * @param pPage The physical page tracking structure.
1044 *
1045 * @remarks Called from within the PGM critical section.
1046 */
1047void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage)
1048{
1049 Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED);
1050 PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
1051 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1052 Assert(pVM->pgm.s.cMonitoredPages > 0);
1053 pVM->pgm.s.cMonitoredPages--;
1054 pVM->pgm.s.cWrittenToPages++;
1055}
1056
1057
1058/**
1059 * Deal with pages that are not writable, i.e. not in the ALLOCATED state.
1060 *
1061 * @returns VBox strict status code.
1062 * @retval VINF_SUCCESS on success.
1063 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
1064 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1065 *
1066 * @param pVM The cross context VM structure.
1067 * @param pPage The physical page tracking structure.
1068 * @param GCPhys The address of the page.
1069 *
1070 * @remarks Called from within the PGM critical section.
1071 */
1072int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
1073{
1074 PGM_LOCK_ASSERT_OWNER(pVM);
1075 switch (PGM_PAGE_GET_STATE(pPage))
1076 {
1077 case PGM_PAGE_STATE_WRITE_MONITORED:
1078 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
1079 /* fall thru */
1080 default: /* to shut up GCC */
1081 case PGM_PAGE_STATE_ALLOCATED:
1082 return VINF_SUCCESS;
1083
1084 /*
1085 * Zero pages can be dummy pages for MMIO or reserved memory,
1086 * so we need to check the flags before joining cause with
1087 * shared page replacement.
1088 */
1089 case PGM_PAGE_STATE_ZERO:
1090 if (PGM_PAGE_IS_MMIO(pPage))
1091 return VERR_PGM_PHYS_PAGE_RESERVED;
1092 /* fall thru */
1093 case PGM_PAGE_STATE_SHARED:
1094 return pgmPhysAllocPage(pVM, pPage, GCPhys);
1095
1096 /* Not allowed to write to ballooned pages. */
1097 case PGM_PAGE_STATE_BALLOONED:
1098 return VERR_PGM_PHYS_PAGE_BALLOONED;
1099 }
1100}
1101
1102
1103/**
1104 * Internal usage: Map the page specified by its GMM ID.
1105 *
1106 * This is similar to pgmPhysPageMap
1107 *
1108 * @returns VBox status code.
1109 *
1110 * @param pVM The cross context VM structure.
1111 * @param idPage The Page ID.
1112 * @param HCPhys The physical address (for RC).
1113 * @param ppv Where to store the mapping address.
1114 *
1115 * @remarks Called from within the PGM critical section. The mapping is only
1116 * valid while you are inside this section.
1117 */
1118int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv)
1119{
1120 /*
1121 * Validation.
1122 */
1123 PGM_LOCK_ASSERT_OWNER(pVM);
1124 AssertReturn(HCPhys && !(HCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1125 const uint32_t idChunk = idPage >> GMM_CHUNKID_SHIFT;
1126 AssertReturn(idChunk != NIL_GMM_CHUNKID, VERR_INVALID_PARAMETER);
1127
1128#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1129 /*
1130 * Map it by HCPhys.
1131 */
1132 return pgmRZDynMapHCPageInlined(VMMGetCpu(pVM), HCPhys, ppv RTLOG_COMMA_SRC_POS);
1133
1134#else
1135 /*
1136 * Find/make Chunk TLB entry for the mapping chunk.
1137 */
1138 PPGMCHUNKR3MAP pMap;
1139 PPGMCHUNKR3MAPTLBE pTlbe = &pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(idChunk)];
1140 if (pTlbe->idChunk == idChunk)
1141 {
1142 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,ChunkR3MapTlbHits));
1143 pMap = pTlbe->pChunk;
1144 }
1145 else
1146 {
1147 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,ChunkR3MapTlbMisses));
1148
1149 /*
1150 * Find the chunk, map it if necessary.
1151 */
1152 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
1153 if (pMap)
1154 pMap->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
1155 else
1156 {
1157# ifdef IN_RING0
1158 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_MAP_CHUNK, idChunk);
1159 AssertRCReturn(rc, rc);
1160 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
1161 Assert(pMap);
1162# else
1163 int rc = pgmR3PhysChunkMap(pVM, idChunk, &pMap);
1164 if (RT_FAILURE(rc))
1165 return rc;
1166# endif
1167 }
1168
1169 /*
1170 * Enter it into the Chunk TLB.
1171 */
1172 pTlbe->idChunk = idChunk;
1173 pTlbe->pChunk = pMap;
1174 }
1175
1176 *ppv = (uint8_t *)pMap->pv + ((idPage &GMM_PAGEID_IDX_MASK) << PAGE_SHIFT);
1177 return VINF_SUCCESS;
1178#endif
1179}
1180
1181
1182/**
1183 * Maps a page into the current virtual address space so it can be accessed.
1184 *
1185 * @returns VBox status code.
1186 * @retval VINF_SUCCESS on success.
1187 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1188 *
1189 * @param pVM The cross context VM structure.
1190 * @param pPage The physical page tracking structure.
1191 * @param GCPhys The address of the page.
1192 * @param ppMap Where to store the address of the mapping tracking structure.
1193 * @param ppv Where to store the mapping address of the page. The page
1194 * offset is masked off!
1195 *
1196 * @remarks Called from within the PGM critical section.
1197 */
1198static int pgmPhysPageMapCommon(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv)
1199{
1200 PGM_LOCK_ASSERT_OWNER(pVM);
1201 NOREF(GCPhys);
1202
1203#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1204 /*
1205 * Just some sketchy GC/R0-darwin code.
1206 */
1207 *ppMap = NULL;
1208 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1209 Assert(HCPhys != pVM->pgm.s.HCPhysZeroPg);
1210 pgmRZDynMapHCPageInlined(VMMGetCpu(pVM), HCPhys, ppv RTLOG_COMMA_SRC_POS);
1211 return VINF_SUCCESS;
1212
1213#else /* IN_RING3 || IN_RING0 */
1214
1215
1216 /*
1217 * Special cases: MMIO2, ZERO and specially aliased MMIO pages.
1218 */
1219 if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2
1220 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
1221 {
1222 /* Decode the page id to a page in a MMIO2 ram range. */
1223 uint8_t idMmio2 = PGM_MMIO2_PAGEID_GET_MMIO2_ID(PGM_PAGE_GET_PAGEID(pPage));
1224 uint32_t iPage = PGM_MMIO2_PAGEID_GET_IDX(PGM_PAGE_GET_PAGEID(pPage));
1225 AssertLogRelMsgReturn((uint8_t)(idMmio2 - 1U) < RT_ELEMENTS(pVM->pgm.s.CTX_SUFF(apMmio2Ranges)),
1226 ("idMmio2=%u size=%u type=%u GCPHys=%#RGp Id=%u State=%u", idMmio2,
1227 RT_ELEMENTS(pVM->pgm.s.CTX_SUFF(apMmio2Ranges)), PGM_PAGE_GET_TYPE(pPage), GCPhys,
1228 pPage->s.idPage, pPage->s.uStateY),
1229 VERR_PGM_PHYS_PAGE_MAP_MMIO2_IPE);
1230 PPGMMMIO2RANGE pMmio2Range = pVM->pgm.s.CTX_SUFF(apMmio2Ranges)[idMmio2 - 1];
1231 AssertLogRelReturn(pMmio2Range, VERR_PGM_PHYS_PAGE_MAP_MMIO2_IPE);
1232 AssertLogRelReturn(pMmio2Range->idMmio2 == idMmio2, VERR_PGM_PHYS_PAGE_MAP_MMIO2_IPE);
1233 AssertLogRelReturn(iPage < (pMmio2Range->RamRange.cb >> PAGE_SHIFT), VERR_PGM_PHYS_PAGE_MAP_MMIO2_IPE);
1234 *ppv = (uint8_t *)pMmio2Range->RamRange.pvR3 + ((uintptr_t)iPage << PAGE_SHIFT);
1235 *ppMap = NULL;
1236 return VINF_SUCCESS;
1237 }
1238
1239 const uint32_t idChunk = PGM_PAGE_GET_CHUNKID(pPage);
1240 if (idChunk == NIL_GMM_CHUNKID)
1241 {
1242 AssertMsgReturn(PGM_PAGE_GET_PAGEID(pPage) == NIL_GMM_PAGEID, ("pPage=%R[pgmpage]\n", pPage),
1243 VERR_PGM_PHYS_PAGE_MAP_IPE_1);
1244 if (!PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
1245 {
1246 AssertMsgReturn(PGM_PAGE_IS_ZERO(pPage), ("pPage=%R[pgmpage]\n", pPage),
1247 VERR_PGM_PHYS_PAGE_MAP_IPE_3);
1248 AssertMsgReturn(PGM_PAGE_GET_HCPHYS(pPage)== pVM->pgm.s.HCPhysZeroPg, ("pPage=%R[pgmpage]\n", pPage),
1249 VERR_PGM_PHYS_PAGE_MAP_IPE_4);
1250 *ppv = pVM->pgm.s.CTXALLSUFF(pvZeroPg);
1251 }
1252 else
1253# ifdef VBOX_WITH_2ND_IEM_STEP
1254 *ppv = pVM->pgm.s.CTXALLSUFF(pvZeroPg);
1255# else
1256 {
1257 /* This kind of screws up the TLB entry if accessed from a different section afterwards. */
1258 static uint8_t s_abPlayItSafe[0x1000*2]; /* I don't dare return the zero page at the moment. */
1259 *ppv = (uint8_t *)((uintptr_t)&s_abPlayItSafe[0x1000] & ~(uintptr_t)0xfff);
1260 }
1261# endif
1262 *ppMap = NULL;
1263 return VINF_SUCCESS;
1264 }
1265
1266 /*
1267 * Find/make Chunk TLB entry for the mapping chunk.
1268 */
1269 PPGMCHUNKR3MAP pMap;
1270 PPGMCHUNKR3MAPTLBE pTlbe = &pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(idChunk)];
1271 if (pTlbe->idChunk == idChunk)
1272 {
1273 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,ChunkR3MapTlbHits));
1274 pMap = pTlbe->pChunk;
1275 AssertPtr(pMap->pv);
1276 }
1277 else
1278 {
1279 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,ChunkR3MapTlbMisses));
1280
1281 /*
1282 * Find the chunk, map it if necessary.
1283 */
1284 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
1285 if (pMap)
1286 {
1287 AssertPtr(pMap->pv);
1288 pMap->iLastUsed = pVM->pgm.s.ChunkR3Map.iNow;
1289 }
1290 else
1291 {
1292#ifdef IN_RING0
1293 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_MAP_CHUNK, idChunk);
1294 AssertRCReturn(rc, rc);
1295 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
1296 Assert(pMap);
1297#else
1298 int rc = pgmR3PhysChunkMap(pVM, idChunk, &pMap);
1299 if (RT_FAILURE(rc))
1300 return rc;
1301#endif
1302 AssertPtr(pMap->pv);
1303 }
1304
1305 /*
1306 * Enter it into the Chunk TLB.
1307 */
1308 pTlbe->idChunk = idChunk;
1309 pTlbe->pChunk = pMap;
1310 }
1311
1312 *ppv = (uint8_t *)pMap->pv + (PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) << PAGE_SHIFT);
1313 *ppMap = pMap;
1314 return VINF_SUCCESS;
1315#endif /* IN_RING3 */
1316}
1317
1318
1319/**
1320 * Combination of pgmPhysPageMakeWritable and pgmPhysPageMapWritable.
1321 *
1322 * This is typically used is paths where we cannot use the TLB methods (like ROM
1323 * pages) or where there is no point in using them since we won't get many hits.
1324 *
1325 * @returns VBox strict status code.
1326 * @retval VINF_SUCCESS on success.
1327 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
1328 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1329 *
1330 * @param pVM The cross context VM structure.
1331 * @param pPage The physical page tracking structure.
1332 * @param GCPhys The address of the page.
1333 * @param ppv Where to store the mapping address of the page. The page
1334 * offset is masked off!
1335 *
1336 * @remarks Called from within the PGM critical section. The mapping is only
1337 * valid while you are inside section.
1338 */
1339int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
1340{
1341 int rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1342 if (RT_SUCCESS(rc))
1343 {
1344 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
1345 PPGMPAGEMAP pMapIgnore;
1346 int rc2 = pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, ppv);
1347 if (RT_FAILURE(rc2)) /* preserve rc */
1348 rc = rc2;
1349 }
1350 return rc;
1351}
1352
1353
1354/**
1355 * Maps a page into the current virtual address space so it can be accessed for
1356 * both writing and reading.
1357 *
1358 * This is typically used is paths where we cannot use the TLB methods (like ROM
1359 * pages) or where there is no point in using them since we won't get many hits.
1360 *
1361 * @returns VBox status code.
1362 * @retval VINF_SUCCESS on success.
1363 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1364 *
1365 * @param pVM The cross context VM structure.
1366 * @param pPage The physical page tracking structure. Must be in the
1367 * allocated state.
1368 * @param GCPhys The address of the page.
1369 * @param ppv Where to store the mapping address of the page. The page
1370 * offset is masked off!
1371 *
1372 * @remarks Called from within the PGM critical section. The mapping is only
1373 * valid while you are inside section.
1374 */
1375int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
1376{
1377 Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
1378 PPGMPAGEMAP pMapIgnore;
1379 return pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, ppv);
1380}
1381
1382
1383/**
1384 * Maps a page into the current virtual address space so it can be accessed for
1385 * reading.
1386 *
1387 * This is typically used is paths where we cannot use the TLB methods (like ROM
1388 * pages) or where there is no point in using them since we won't get many hits.
1389 *
1390 * @returns VBox status code.
1391 * @retval VINF_SUCCESS on success.
1392 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1393 *
1394 * @param pVM The cross context VM structure.
1395 * @param pPage The physical page tracking structure.
1396 * @param GCPhys The address of the page.
1397 * @param ppv Where to store the mapping address of the page. The page
1398 * offset is masked off!
1399 *
1400 * @remarks Called from within the PGM critical section. The mapping is only
1401 * valid while you are inside this section.
1402 */
1403int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv)
1404{
1405 PPGMPAGEMAP pMapIgnore;
1406 return pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, (void **)ppv);
1407}
1408
1409#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1410
1411/**
1412 * Load a guest page into the ring-3 physical TLB.
1413 *
1414 * @returns VBox status code.
1415 * @retval VINF_SUCCESS on success
1416 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1417 * @param pPGM The PGM instance pointer.
1418 * @param GCPhys The guest physical address in question.
1419 */
1420int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys)
1421{
1422 PGM_LOCK_ASSERT_OWNER(pVM);
1423
1424 /*
1425 * Find the ram range and page and hand it over to the with-page function.
1426 * 99.8% of requests are expected to be in the first range.
1427 */
1428 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
1429 if (!pPage)
1430 {
1431 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbMisses));
1432 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1433 }
1434
1435 return pgmPhysPageLoadIntoTlbWithPage(pVM, pPage, GCPhys);
1436}
1437
1438
1439/**
1440 * Load a guest page into the ring-3 physical TLB.
1441 *
1442 * @returns VBox status code.
1443 * @retval VINF_SUCCESS on success
1444 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1445 *
1446 * @param pVM The cross context VM structure.
1447 * @param pPage Pointer to the PGMPAGE structure corresponding to
1448 * GCPhys.
1449 * @param GCPhys The guest physical address in question.
1450 */
1451int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
1452{
1453 PGM_LOCK_ASSERT_OWNER(pVM);
1454 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageMapTlbMisses));
1455
1456 /*
1457 * Map the page.
1458 * Make a special case for the zero page as it is kind of special.
1459 */
1460 PPGMPAGEMAPTLBE pTlbe = &pVM->pgm.s.CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
1461 if ( !PGM_PAGE_IS_ZERO(pPage)
1462 && !PGM_PAGE_IS_BALLOONED(pPage))
1463 {
1464 void *pv;
1465 PPGMPAGEMAP pMap;
1466 int rc = pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMap, &pv);
1467 if (RT_FAILURE(rc))
1468 return rc;
1469 pTlbe->pMap = pMap;
1470 pTlbe->pv = pv;
1471 Assert(!((uintptr_t)pTlbe->pv & PAGE_OFFSET_MASK));
1472 }
1473 else
1474 {
1475 AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == pVM->pgm.s.HCPhysZeroPg, ("%RGp/%R[pgmpage]\n", GCPhys, pPage));
1476 pTlbe->pMap = NULL;
1477 pTlbe->pv = pVM->pgm.s.CTXALLSUFF(pvZeroPg);
1478 }
1479#ifdef PGM_WITH_PHYS_TLB
1480 if ( PGM_PAGE_GET_TYPE(pPage) < PGMPAGETYPE_ROM_SHADOW
1481 || PGM_PAGE_GET_TYPE(pPage) > PGMPAGETYPE_ROM)
1482 pTlbe->GCPhys = GCPhys & X86_PTE_PAE_PG_MASK;
1483 else
1484 pTlbe->GCPhys = NIL_RTGCPHYS; /* ROM: Problematic because of the two pages. :-/ */
1485#else
1486 pTlbe->GCPhys = NIL_RTGCPHYS;
1487#endif
1488 pTlbe->pPage = pPage;
1489 return VINF_SUCCESS;
1490}
1491
1492#endif /* !IN_RC && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1493
1494/**
1495 * Internal version of PGMPhysGCPhys2CCPtr that expects the caller to
1496 * own the PGM lock and therefore not need to lock the mapped page.
1497 *
1498 * @returns VBox status code.
1499 * @retval VINF_SUCCESS on success.
1500 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1501 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1502 *
1503 * @param pVM The cross context VM structure.
1504 * @param GCPhys The guest physical address of the page that should be mapped.
1505 * @param pPage Pointer to the PGMPAGE structure for the page.
1506 * @param ppv Where to store the address corresponding to GCPhys.
1507 *
1508 * @internal
1509 * @deprecated Use pgmPhysGCPhys2CCPtrInternalEx.
1510 */
1511int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
1512{
1513 int rc;
1514 AssertReturn(pPage, VERR_PGM_PHYS_NULL_PAGE_PARAM);
1515 PGM_LOCK_ASSERT_OWNER(pVM);
1516 pVM->pgm.s.cDeprecatedPageLocks++;
1517
1518 /*
1519 * Make sure the page is writable.
1520 */
1521 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1522 {
1523 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1524 if (RT_FAILURE(rc))
1525 return rc;
1526 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1527 }
1528 Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
1529
1530 /*
1531 * Get the mapping address.
1532 */
1533#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1534 void *pv;
1535 rc = pgmRZDynMapHCPageInlined(VMMGetCpu(pVM),
1536 PGM_PAGE_GET_HCPHYS(pPage),
1537 &pv
1538 RTLOG_COMMA_SRC_POS);
1539 if (RT_FAILURE(rc))
1540 return rc;
1541 *ppv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1542#else
1543 PPGMPAGEMAPTLBE pTlbe;
1544 rc = pgmPhysPageQueryTlbeWithPage(pVM, pPage, GCPhys, &pTlbe);
1545 if (RT_FAILURE(rc))
1546 return rc;
1547 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1548#endif
1549 return VINF_SUCCESS;
1550}
1551
1552#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1553
1554/**
1555 * Locks a page mapping for writing.
1556 *
1557 * @param pVM The cross context VM structure.
1558 * @param pPage The page.
1559 * @param pTlbe The mapping TLB entry for the page.
1560 * @param pLock The lock structure (output).
1561 */
1562DECLINLINE(void) pgmPhysPageMapLockForWriting(PVM pVM, PPGMPAGE pPage, PPGMPAGEMAPTLBE pTlbe, PPGMPAGEMAPLOCK pLock)
1563{
1564 PPGMPAGEMAP pMap = pTlbe->pMap;
1565 if (pMap)
1566 pMap->cRefs++;
1567
1568 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
1569 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
1570 {
1571 if (cLocks == 0)
1572 pVM->pgm.s.cWriteLockedPages++;
1573 PGM_PAGE_INC_WRITE_LOCKS(pPage);
1574 }
1575 else if (cLocks != PGM_PAGE_MAX_LOCKS)
1576 {
1577 PGM_PAGE_INC_WRITE_LOCKS(pPage);
1578 AssertMsgFailed(("%R[pgmpage] is entering permanent write locked state!\n", pPage));
1579 if (pMap)
1580 pMap->cRefs++; /* Extra ref to prevent it from going away. */
1581 }
1582
1583 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_WRITE;
1584 pLock->pvMap = pMap;
1585}
1586
1587/**
1588 * Locks a page mapping for reading.
1589 *
1590 * @param pVM The cross context VM structure.
1591 * @param pPage The page.
1592 * @param pTlbe The mapping TLB entry for the page.
1593 * @param pLock The lock structure (output).
1594 */
1595DECLINLINE(void) pgmPhysPageMapLockForReading(PVM pVM, PPGMPAGE pPage, PPGMPAGEMAPTLBE pTlbe, PPGMPAGEMAPLOCK pLock)
1596{
1597 PPGMPAGEMAP pMap = pTlbe->pMap;
1598 if (pMap)
1599 pMap->cRefs++;
1600
1601 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
1602 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
1603 {
1604 if (cLocks == 0)
1605 pVM->pgm.s.cReadLockedPages++;
1606 PGM_PAGE_INC_READ_LOCKS(pPage);
1607 }
1608 else if (cLocks != PGM_PAGE_MAX_LOCKS)
1609 {
1610 PGM_PAGE_INC_READ_LOCKS(pPage);
1611 AssertMsgFailed(("%R[pgmpage] is entering permanent read locked state!\n", pPage));
1612 if (pMap)
1613 pMap->cRefs++; /* Extra ref to prevent it from going away. */
1614 }
1615
1616 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_READ;
1617 pLock->pvMap = pMap;
1618}
1619
1620#endif /* !IN_RC && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1621
1622
1623/**
1624 * Internal version of PGMPhysGCPhys2CCPtr that expects the caller to
1625 * own the PGM lock and have access to the page structure.
1626 *
1627 * @returns VBox status code.
1628 * @retval VINF_SUCCESS on success.
1629 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1630 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1631 *
1632 * @param pVM The cross context VM structure.
1633 * @param GCPhys The guest physical address of the page that should be mapped.
1634 * @param pPage Pointer to the PGMPAGE structure for the page.
1635 * @param ppv Where to store the address corresponding to GCPhys.
1636 * @param pLock Where to store the lock information that
1637 * pgmPhysReleaseInternalPageMappingLock needs.
1638 *
1639 * @internal
1640 */
1641int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
1642{
1643 int rc;
1644 AssertReturn(pPage, VERR_PGM_PHYS_NULL_PAGE_PARAM);
1645 PGM_LOCK_ASSERT_OWNER(pVM);
1646
1647 /*
1648 * Make sure the page is writable.
1649 */
1650 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1651 {
1652 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1653 if (RT_FAILURE(rc))
1654 return rc;
1655 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1656 }
1657 Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
1658
1659 /*
1660 * Do the job.
1661 */
1662#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1663 void *pv;
1664 PVMCPU pVCpu = VMMGetCpu(pVM);
1665 rc = pgmRZDynMapHCPageInlined(pVCpu,
1666 PGM_PAGE_GET_HCPHYS(pPage),
1667 &pv
1668 RTLOG_COMMA_SRC_POS);
1669 if (RT_FAILURE(rc))
1670 return rc;
1671 *ppv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1672 pLock->pvPage = pv;
1673 pLock->pVCpu = pVCpu;
1674
1675#else
1676 PPGMPAGEMAPTLBE pTlbe;
1677 rc = pgmPhysPageQueryTlbeWithPage(pVM, pPage, GCPhys, &pTlbe);
1678 if (RT_FAILURE(rc))
1679 return rc;
1680 pgmPhysPageMapLockForWriting(pVM, pPage, pTlbe, pLock);
1681 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1682#endif
1683 return VINF_SUCCESS;
1684}
1685
1686
1687/**
1688 * Internal version of PGMPhysGCPhys2CCPtrReadOnly that expects the caller to
1689 * own the PGM lock and have access to the page structure.
1690 *
1691 * @returns VBox status code.
1692 * @retval VINF_SUCCESS on success.
1693 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1694 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1695 *
1696 * @param pVM The cross context VM structure.
1697 * @param GCPhys The guest physical address of the page that should be mapped.
1698 * @param pPage Pointer to the PGMPAGE structure for the page.
1699 * @param ppv Where to store the address corresponding to GCPhys.
1700 * @param pLock Where to store the lock information that
1701 * pgmPhysReleaseInternalPageMappingLock needs.
1702 *
1703 * @internal
1704 */
1705int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock)
1706{
1707 AssertReturn(pPage, VERR_PGM_PHYS_NULL_PAGE_PARAM);
1708 PGM_LOCK_ASSERT_OWNER(pVM);
1709 Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
1710
1711 /*
1712 * Do the job.
1713 */
1714#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1715 void *pv;
1716 PVMCPU pVCpu = VMMGetCpu(pVM);
1717 int rc = pgmRZDynMapHCPageInlined(pVCpu,
1718 PGM_PAGE_GET_HCPHYS(pPage),
1719 &pv
1720 RTLOG_COMMA_SRC_POS); /** @todo add a read only flag? */
1721 if (RT_FAILURE(rc))
1722 return rc;
1723 *ppv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1724 pLock->pvPage = pv;
1725 pLock->pVCpu = pVCpu;
1726
1727#else
1728 PPGMPAGEMAPTLBE pTlbe;
1729 int rc = pgmPhysPageQueryTlbeWithPage(pVM, pPage, GCPhys, &pTlbe);
1730 if (RT_FAILURE(rc))
1731 return rc;
1732 pgmPhysPageMapLockForReading(pVM, pPage, pTlbe, pLock);
1733 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1734#endif
1735 return VINF_SUCCESS;
1736}
1737
1738
1739/**
1740 * Requests the mapping of a guest page into the current context.
1741 *
1742 * This API should only be used for very short term, as it will consume scarse
1743 * resources (R0 and GC) in the mapping cache. When you're done with the page,
1744 * call PGMPhysReleasePageMappingLock() ASAP to release it.
1745 *
1746 * This API will assume your intention is to write to the page, and will
1747 * therefore replace shared and zero pages. If you do not intend to modify
1748 * the page, use the PGMPhysGCPhys2CCPtrReadOnly() API.
1749 *
1750 * @returns VBox status code.
1751 * @retval VINF_SUCCESS on success.
1752 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1753 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1754 *
1755 * @param pVM The cross context VM structure.
1756 * @param GCPhys The guest physical address of the page that should be
1757 * mapped.
1758 * @param ppv Where to store the address corresponding to GCPhys.
1759 * @param pLock Where to store the lock information that
1760 * PGMPhysReleasePageMappingLock needs.
1761 *
1762 * @remarks The caller is responsible for dealing with access handlers.
1763 * @todo Add an informational return code for pages with access handlers?
1764 *
1765 * @remark Avoid calling this API from within critical sections (other than
1766 * the PGM one) because of the deadlock risk. External threads may
1767 * need to delegate jobs to the EMTs.
1768 * @remarks Only one page is mapped! Make no assumption about what's after or
1769 * before the returned page!
1770 * @thread Any thread.
1771 */
1772VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
1773{
1774 int rc = pgmLock(pVM);
1775 AssertRCReturn(rc, rc);
1776
1777#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1778 /*
1779 * Find the page and make sure it's writable.
1780 */
1781 PPGMPAGE pPage;
1782 rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1783 if (RT_SUCCESS(rc))
1784 {
1785 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1786 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1787 if (RT_SUCCESS(rc))
1788 {
1789 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1790
1791 PVMCPU pVCpu = VMMGetCpu(pVM);
1792 void *pv;
1793 rc = pgmRZDynMapHCPageInlined(pVCpu,
1794 PGM_PAGE_GET_HCPHYS(pPage),
1795 &pv
1796 RTLOG_COMMA_SRC_POS);
1797 if (RT_SUCCESS(rc))
1798 {
1799 AssertRCSuccess(rc);
1800
1801 pv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1802 *ppv = pv;
1803 pLock->pvPage = pv;
1804 pLock->pVCpu = pVCpu;
1805 }
1806 }
1807 }
1808
1809#else /* IN_RING3 || IN_RING0 */
1810 /*
1811 * Query the Physical TLB entry for the page (may fail).
1812 */
1813 PPGMPAGEMAPTLBE pTlbe;
1814 rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
1815 if (RT_SUCCESS(rc))
1816 {
1817 /*
1818 * If the page is shared, the zero page, or being write monitored
1819 * it must be converted to a page that's writable if possible.
1820 */
1821 PPGMPAGE pPage = pTlbe->pPage;
1822 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1823 {
1824 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1825 if (RT_SUCCESS(rc))
1826 {
1827 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1828 rc = pgmPhysPageQueryTlbeWithPage(pVM, pPage, GCPhys, &pTlbe);
1829 }
1830 }
1831 if (RT_SUCCESS(rc))
1832 {
1833 /*
1834 * Now, just perform the locking and calculate the return address.
1835 */
1836 pgmPhysPageMapLockForWriting(pVM, pPage, pTlbe, pLock);
1837 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1838 }
1839 }
1840
1841#endif /* IN_RING3 || IN_RING0 */
1842 pgmUnlock(pVM);
1843 return rc;
1844}
1845
1846
1847/**
1848 * Requests the mapping of a guest page into the current context.
1849 *
1850 * This API should only be used for very short term, as it will consume scarse
1851 * resources (R0 and GC) in the mapping cache. When you're done with the page,
1852 * call PGMPhysReleasePageMappingLock() ASAP to release it.
1853 *
1854 * @returns VBox status code.
1855 * @retval VINF_SUCCESS on success.
1856 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1857 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1858 *
1859 * @param pVM The cross context VM structure.
1860 * @param GCPhys The guest physical address of the page that should be
1861 * mapped.
1862 * @param ppv Where to store the address corresponding to GCPhys.
1863 * @param pLock Where to store the lock information that
1864 * PGMPhysReleasePageMappingLock needs.
1865 *
1866 * @remarks The caller is responsible for dealing with access handlers.
1867 * @todo Add an informational return code for pages with access handlers?
1868 *
1869 * @remarks Avoid calling this API from within critical sections (other than
1870 * the PGM one) because of the deadlock risk.
1871 * @remarks Only one page is mapped! Make no assumption about what's after or
1872 * before the returned page!
1873 * @thread Any thread.
1874 */
1875VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
1876{
1877 int rc = pgmLock(pVM);
1878 AssertRCReturn(rc, rc);
1879
1880#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1881 /*
1882 * Find the page and make sure it's readable.
1883 */
1884 PPGMPAGE pPage;
1885 rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1886 if (RT_SUCCESS(rc))
1887 {
1888 if (RT_UNLIKELY(PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)))
1889 rc = VERR_PGM_PHYS_PAGE_RESERVED;
1890 else
1891 {
1892 PVMCPU pVCpu = VMMGetCpu(pVM);
1893 void *pv;
1894 rc = pgmRZDynMapHCPageInlined(pVCpu,
1895 PGM_PAGE_GET_HCPHYS(pPage),
1896 &pv
1897 RTLOG_COMMA_SRC_POS); /** @todo add a read only flag? */
1898 if (RT_SUCCESS(rc))
1899 {
1900 AssertRCSuccess(rc);
1901
1902 pv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1903 *ppv = pv;
1904 pLock->pvPage = pv;
1905 pLock->pVCpu = pVCpu;
1906 }
1907 }
1908 }
1909
1910#else /* IN_RING3 || IN_RING0 */
1911 /*
1912 * Query the Physical TLB entry for the page (may fail).
1913 */
1914 PPGMPAGEMAPTLBE pTlbe;
1915 rc = pgmPhysPageQueryTlbe(pVM, GCPhys, &pTlbe);
1916 if (RT_SUCCESS(rc))
1917 {
1918 /* MMIO pages doesn't have any readable backing. */
1919 PPGMPAGE pPage = pTlbe->pPage;
1920 if (RT_UNLIKELY(PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage)))
1921 rc = VERR_PGM_PHYS_PAGE_RESERVED;
1922 else
1923 {
1924 /*
1925 * Now, just perform the locking and calculate the return address.
1926 */
1927 pgmPhysPageMapLockForReading(pVM, pPage, pTlbe, pLock);
1928 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
1929 }
1930 }
1931
1932#endif /* IN_RING3 || IN_RING0 */
1933 pgmUnlock(pVM);
1934 return rc;
1935}
1936
1937
1938/**
1939 * Requests the mapping of a guest page given by virtual address into the current context.
1940 *
1941 * This API should only be used for very short term, as it will consume
1942 * scarse resources (R0 and GC) in the mapping cache. When you're done
1943 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
1944 *
1945 * This API will assume your intention is to write to the page, and will
1946 * therefore replace shared and zero pages. If you do not intend to modify
1947 * the page, use the PGMPhysGCPtr2CCPtrReadOnly() API.
1948 *
1949 * @returns VBox status code.
1950 * @retval VINF_SUCCESS on success.
1951 * @retval VERR_PAGE_TABLE_NOT_PRESENT if the page directory for the virtual address isn't present.
1952 * @retval VERR_PAGE_NOT_PRESENT if the page at the virtual address isn't present.
1953 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1954 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1955 *
1956 * @param pVCpu The cross context virtual CPU structure.
1957 * @param GCPtr The guest physical address of the page that should be
1958 * mapped.
1959 * @param ppv Where to store the address corresponding to GCPhys.
1960 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1961 *
1962 * @remark Avoid calling this API from within critical sections (other than
1963 * the PGM one) because of the deadlock risk.
1964 * @thread EMT
1965 */
1966VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock)
1967{
1968 VM_ASSERT_EMT(pVCpu->CTX_SUFF(pVM));
1969 RTGCPHYS GCPhys;
1970 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, &GCPhys);
1971 if (RT_SUCCESS(rc))
1972 rc = PGMPhysGCPhys2CCPtr(pVCpu->CTX_SUFF(pVM), GCPhys, ppv, pLock);
1973 return rc;
1974}
1975
1976
1977/**
1978 * Requests the mapping of a guest page given by virtual address into the current context.
1979 *
1980 * This API should only be used for very short term, as it will consume
1981 * scarse resources (R0 and GC) in the mapping cache. When you're done
1982 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
1983 *
1984 * @returns VBox status code.
1985 * @retval VINF_SUCCESS on success.
1986 * @retval VERR_PAGE_TABLE_NOT_PRESENT if the page directory for the virtual address isn't present.
1987 * @retval VERR_PAGE_NOT_PRESENT if the page at the virtual address isn't present.
1988 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1989 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1990 *
1991 * @param pVCpu The cross context virtual CPU structure.
1992 * @param GCPtr The guest physical address of the page that should be
1993 * mapped.
1994 * @param ppv Where to store the address corresponding to GCPtr.
1995 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1996 *
1997 * @remark Avoid calling this API from within critical sections (other than
1998 * the PGM one) because of the deadlock risk.
1999 * @thread EMT
2000 */
2001VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock)
2002{
2003 VM_ASSERT_EMT(pVCpu->CTX_SUFF(pVM));
2004 RTGCPHYS GCPhys;
2005 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, &GCPhys);
2006 if (RT_SUCCESS(rc))
2007 rc = PGMPhysGCPhys2CCPtrReadOnly(pVCpu->CTX_SUFF(pVM), GCPhys, ppv, pLock);
2008 return rc;
2009}
2010
2011
2012/**
2013 * Release the mapping of a guest page.
2014 *
2015 * This is the counter part of PGMPhysGCPhys2CCPtr, PGMPhysGCPhys2CCPtrReadOnly
2016 * PGMPhysGCPtr2CCPtr and PGMPhysGCPtr2CCPtrReadOnly.
2017 *
2018 * @param pVM The cross context VM structure.
2019 * @param pLock The lock structure initialized by the mapping function.
2020 */
2021VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock)
2022{
2023#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2024 Assert(pLock->pvPage != NULL);
2025 Assert(pLock->pVCpu == VMMGetCpu(pVM));
2026 PGM_DYNMAP_UNUSED_HINT(pLock->pVCpu, pLock->pvPage);
2027 pLock->pVCpu = NULL;
2028 pLock->pvPage = NULL;
2029
2030#else
2031 PPGMPAGEMAP pMap = (PPGMPAGEMAP)pLock->pvMap;
2032 PPGMPAGE pPage = (PPGMPAGE)(pLock->uPageAndType & ~PGMPAGEMAPLOCK_TYPE_MASK);
2033 bool fWriteLock = (pLock->uPageAndType & PGMPAGEMAPLOCK_TYPE_MASK) == PGMPAGEMAPLOCK_TYPE_WRITE;
2034
2035 pLock->uPageAndType = 0;
2036 pLock->pvMap = NULL;
2037
2038 pgmLock(pVM);
2039 if (fWriteLock)
2040 {
2041 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
2042 Assert(cLocks > 0);
2043 if (RT_LIKELY(cLocks > 0 && cLocks < PGM_PAGE_MAX_LOCKS))
2044 {
2045 if (cLocks == 1)
2046 {
2047 Assert(pVM->pgm.s.cWriteLockedPages > 0);
2048 pVM->pgm.s.cWriteLockedPages--;
2049 }
2050 PGM_PAGE_DEC_WRITE_LOCKS(pPage);
2051 }
2052
2053 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
2054 {
2055 PGM_PAGE_SET_WRITTEN_TO(pVM, pPage);
2056 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
2057 Assert(pVM->pgm.s.cMonitoredPages > 0);
2058 pVM->pgm.s.cMonitoredPages--;
2059 pVM->pgm.s.cWrittenToPages++;
2060 }
2061 }
2062 else
2063 {
2064 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
2065 Assert(cLocks > 0);
2066 if (RT_LIKELY(cLocks > 0 && cLocks < PGM_PAGE_MAX_LOCKS))
2067 {
2068 if (cLocks == 1)
2069 {
2070 Assert(pVM->pgm.s.cReadLockedPages > 0);
2071 pVM->pgm.s.cReadLockedPages--;
2072 }
2073 PGM_PAGE_DEC_READ_LOCKS(pPage);
2074 }
2075 }
2076
2077 if (pMap)
2078 {
2079 Assert(pMap->cRefs >= 1);
2080 pMap->cRefs--;
2081 }
2082 pgmUnlock(pVM);
2083#endif /* IN_RING3 */
2084}
2085
2086
2087/**
2088 * Release the internal mapping of a guest page.
2089 *
2090 * This is the counter part of pgmPhysGCPhys2CCPtrInternalEx and
2091 * pgmPhysGCPhys2CCPtrInternalReadOnly.
2092 *
2093 * @param pVM The cross context VM structure.
2094 * @param pLock The lock structure initialized by the mapping function.
2095 *
2096 * @remarks Caller must hold the PGM lock.
2097 */
2098void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock)
2099{
2100 PGM_LOCK_ASSERT_OWNER(pVM);
2101 PGMPhysReleasePageMappingLock(pVM, pLock); /* lazy for now */
2102}
2103
2104
2105/**
2106 * Converts a GC physical address to a HC ring-3 pointer.
2107 *
2108 * @returns VINF_SUCCESS on success.
2109 * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
2110 * page but has no physical backing.
2111 * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
2112 * GC physical address.
2113 * @returns VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY if the range crosses
2114 * a dynamic ram chunk boundary
2115 *
2116 * @param pVM The cross context VM structure.
2117 * @param GCPhys The GC physical address to convert.
2118 * @param pR3Ptr Where to store the R3 pointer on success.
2119 *
2120 * @deprecated Avoid when possible!
2121 */
2122int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr)
2123{
2124/** @todo this is kind of hacky and needs some more work. */
2125#ifndef DEBUG_sandervl
2126 VM_ASSERT_EMT(pVM); /* no longer safe for use outside the EMT thread! */
2127#endif
2128
2129 Log(("pgmPhysGCPhys2R3Ptr(,%RGp,): dont use this API!\n", GCPhys)); /** @todo eliminate this API! */
2130#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2131 NOREF(pVM); NOREF(pR3Ptr);
2132 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
2133#else
2134 pgmLock(pVM);
2135
2136 PPGMRAMRANGE pRam;
2137 PPGMPAGE pPage;
2138 int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
2139 if (RT_SUCCESS(rc))
2140 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)pR3Ptr);
2141
2142 pgmUnlock(pVM);
2143 Assert(rc <= VINF_SUCCESS);
2144 return rc;
2145#endif
2146}
2147
2148#if 0 /*defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)*/
2149
2150/**
2151 * Maps and locks a guest CR3 or PD (PAE) page.
2152 *
2153 * @returns VINF_SUCCESS on success.
2154 * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
2155 * page but has no physical backing.
2156 * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
2157 * GC physical address.
2158 * @returns VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY if the range crosses
2159 * a dynamic ram chunk boundary
2160 *
2161 * @param pVM The cross context VM structure.
2162 * @param GCPhys The GC physical address to convert.
2163 * @param pR3Ptr Where to store the R3 pointer on success. This may or
2164 * may not be valid in ring-0 depending on the
2165 * VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 build option.
2166 *
2167 * @remarks The caller must own the PGM lock.
2168 */
2169int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr)
2170{
2171
2172 PPGMRAMRANGE pRam;
2173 PPGMPAGE pPage;
2174 int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
2175 if (RT_SUCCESS(rc))
2176 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)pR3Ptr);
2177 Assert(rc <= VINF_SUCCESS);
2178 return rc;
2179}
2180
2181
2182int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr)
2183{
2184
2185}
2186
2187#endif
2188
2189/**
2190 * Converts a guest pointer to a GC physical address.
2191 *
2192 * This uses the current CR3/CR0/CR4 of the guest.
2193 *
2194 * @returns VBox status code.
2195 * @param pVCpu The cross context virtual CPU structure.
2196 * @param GCPtr The guest pointer to convert.
2197 * @param pGCPhys Where to store the GC physical address.
2198 */
2199VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
2200{
2201 int rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtr, NULL, pGCPhys);
2202 if (pGCPhys && RT_SUCCESS(rc))
2203 *pGCPhys |= (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
2204 return rc;
2205}
2206
2207
2208/**
2209 * Converts a guest pointer to a HC physical address.
2210 *
2211 * This uses the current CR3/CR0/CR4 of the guest.
2212 *
2213 * @returns VBox status code.
2214 * @param pVCpu The cross context virtual CPU structure.
2215 * @param GCPtr The guest pointer to convert.
2216 * @param pHCPhys Where to store the HC physical address.
2217 */
2218VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys)
2219{
2220 PVM pVM = pVCpu->CTX_SUFF(pVM);
2221 RTGCPHYS GCPhys;
2222 int rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtr, NULL, &GCPhys);
2223 if (RT_SUCCESS(rc))
2224 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhys | ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), pHCPhys);
2225 return rc;
2226}
2227
2228
2229
2230#undef LOG_GROUP
2231#define LOG_GROUP LOG_GROUP_PGM_PHYS_ACCESS
2232
2233
2234#if defined(IN_RING3) && defined(SOME_UNUSED_FUNCTION)
2235/**
2236 * Cache PGMPhys memory access
2237 *
2238 * @param pVM The cross context VM structure.
2239 * @param pCache Cache structure pointer
2240 * @param GCPhys GC physical address
2241 * @param pbHC HC pointer corresponding to physical page
2242 *
2243 * @thread EMT.
2244 */
2245static void pgmPhysCacheAdd(PVM pVM, PGMPHYSCACHE *pCache, RTGCPHYS GCPhys, uint8_t *pbR3)
2246{
2247 uint32_t iCacheIndex;
2248
2249 Assert(VM_IS_EMT(pVM));
2250
2251 GCPhys = PHYS_PAGE_ADDRESS(GCPhys);
2252 pbR3 = (uint8_t *)PAGE_ADDRESS(pbR3);
2253
2254 iCacheIndex = ((GCPhys >> PAGE_SHIFT) & PGM_MAX_PHYSCACHE_ENTRIES_MASK);
2255
2256 ASMBitSet(&pCache->aEntries, iCacheIndex);
2257
2258 pCache->Entry[iCacheIndex].GCPhys = GCPhys;
2259 pCache->Entry[iCacheIndex].pbR3 = pbR3;
2260}
2261#endif /* IN_RING3 */
2262
2263
2264/**
2265 * Deals with reading from a page with one or more ALL access handlers.
2266 *
2267 * @returns Strict VBox status code in ring-0 and raw-mode, ignorable in ring-3.
2268 * See PGM_HANDLER_PHYS_IS_VALID_STATUS and
2269 * PGM_HANDLER_VIRT_IS_VALID_STATUS for details.
2270 *
2271 * @param pVM The cross context VM structure.
2272 * @param pPage The page descriptor.
2273 * @param GCPhys The physical address to start reading at.
2274 * @param pvBuf Where to put the bits we read.
2275 * @param cb How much to read - less or equal to a page.
2276 * @param enmOrigin The origin of this call.
2277 */
2278static VBOXSTRICTRC pgmPhysReadHandler(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void *pvBuf, size_t cb,
2279 PGMACCESSORIGIN enmOrigin)
2280{
2281 /*
2282 * The most frequent access here is MMIO and shadowed ROM.
2283 * The current code ASSUMES all these access handlers covers full pages!
2284 */
2285
2286 /*
2287 * Whatever we do we need the source page, map it first.
2288 */
2289 PGMPAGEMAPLOCK PgMpLck;
2290 const void *pvSrc = NULL;
2291 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvSrc, &PgMpLck);
2292/** @todo Check how this can work for MMIO pages? */
2293 if (RT_FAILURE(rc))
2294 {
2295 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
2296 GCPhys, pPage, rc));
2297 memset(pvBuf, 0xff, cb);
2298 return VINF_SUCCESS;
2299 }
2300
2301 VBOXSTRICTRC rcStrict = VINF_PGM_HANDLER_DO_DEFAULT;
2302
2303 /*
2304 * Deal with any physical handlers.
2305 */
2306 PVMCPU pVCpu = VMMGetCpu(pVM);
2307 PPGMPHYSHANDLER pPhys = NULL;
2308 if ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL
2309 || PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
2310 {
2311 pPhys = pgmHandlerPhysicalLookup(pVM, GCPhys);
2312 AssertReleaseMsg(pPhys, ("GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2313 Assert(GCPhys >= pPhys->Core.Key && GCPhys <= pPhys->Core.KeyLast);
2314 Assert((pPhys->Core.Key & PAGE_OFFSET_MASK) == 0);
2315 Assert((pPhys->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
2316#ifndef IN_RING3
2317 if (enmOrigin != PGMACCESSORIGIN_IEM)
2318 {
2319 /* Cannot reliably handle informational status codes in this context */
2320 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2321 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2322 }
2323#endif
2324 PFNPGMPHYSHANDLER pfnHandler = PGMPHYSHANDLER_GET_TYPE(pVM, pPhys)->CTX_SUFF(pfnHandler); Assert(pfnHandler);
2325 void *pvUser = pPhys->CTX_SUFF(pvUser);
2326
2327 Log5(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cb, pPage, R3STRING(pPhys->pszDesc) ));
2328 STAM_PROFILE_START(&pPhys->Stat, h);
2329 PGM_LOCK_ASSERT_OWNER(pVM);
2330
2331 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2332 pgmUnlock(pVM);
2333 rcStrict = pfnHandler(pVM, pVCpu, GCPhys, (void *)pvSrc, pvBuf, cb, PGMACCESSTYPE_READ, enmOrigin, pvUser);
2334 pgmLock(pVM);
2335
2336#ifdef VBOX_WITH_STATISTICS
2337 pPhys = pgmHandlerPhysicalLookup(pVM, GCPhys);
2338 if (pPhys)
2339 STAM_PROFILE_STOP(&pPhys->Stat, h);
2340#else
2341 pPhys = NULL; /* might not be valid anymore. */
2342#endif
2343 AssertLogRelMsg(PGM_HANDLER_PHYS_IS_VALID_STATUS(rcStrict, false),
2344 ("rcStrict=%Rrc GCPhys=%RGp\n", VBOXSTRICTRC_VAL(rcStrict), GCPhys));
2345 if ( rcStrict != VINF_PGM_HANDLER_DO_DEFAULT
2346 && !PGM_PHYS_RW_IS_SUCCESS(rcStrict))
2347 {
2348 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2349 return rcStrict;
2350 }
2351 }
2352
2353#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
2354 /*
2355 * Deal with any virtual handlers.
2356 */
2357 if (PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL)
2358 {
2359 unsigned iPage;
2360 PPGMVIRTHANDLER pVirt = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &iPage);
2361 AssertReleaseMsg(pVirt, ("GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2362 Assert((pVirt->Core.Key & PAGE_OFFSET_MASK) == 0);
2363 Assert((pVirt->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
2364 Assert(GCPhys >= pVirt->aPhysToVirt[iPage].Core.Key && GCPhys <= pVirt->aPhysToVirt[iPage].Core.KeyLast);
2365
2366# ifndef IN_RING3
2367 if (enmOrigin != PGMACCESSORIGIN_IEM)
2368 {
2369 /* Cannot reliably handle informational status codes in this context */
2370 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2371 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2372 }
2373# endif
2374 PPGMVIRTHANDLERTYPEINT pVirtType = PGMVIRTANDLER_GET_TYPE(pVM, pVirt);
2375 if (!pPhys)
2376 Log5(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] virt %s\n", GCPhys, cb, pPage, R3STRING(pVirt->pszDesc) ));
2377 else
2378 Log(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] phys/virt %s/%s\n", GCPhys, cb, pPage, R3STRING(pVirt->pszDesc), R3STRING(pPhys->pszDesc) ));
2379 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2380 + (iPage << PAGE_SHIFT)
2381 + (GCPhys & PAGE_OFFSET_MASK);
2382
2383 STAM_PROFILE_START(&pVirt->Stat, h);
2384 VBOXSTRICTRC rcStrict2 = pVirtType->CTX_SUFF(pfnHandler)(pVM, pVCpu, GCPtr, (void *)pvSrc, pvBuf, cb,
2385 PGMACCESSTYPE_READ, enmOrigin, pVirt->CTX_SUFF(pvUser));
2386 STAM_PROFILE_STOP(&pVirt->Stat, h);
2387
2388 /* Merge status codes. */
2389 if (rcStrict2 == VINF_SUCCESS)
2390 {
2391 if (rcStrict == VINF_PGM_HANDLER_DO_DEFAULT)
2392 rcStrict = VINF_SUCCESS;
2393 }
2394 else if (rcStrict2 != VINF_PGM_HANDLER_DO_DEFAULT)
2395 {
2396 AssertLogRelMsg(PGM_HANDLER_VIRT_IS_VALID_STATUS(rcStrict2, false),
2397 ("rcStrict2=%Rrc (rcStrict=%Rrc) GCPhys=%RGp pPage=%R[pgmpage] %s\n",
2398 VBOXSTRICTRC_VAL(rcStrict2), VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, pVirt->pszDesc));
2399 if (!PGM_PHYS_RW_IS_SUCCESS(rcStrict2))
2400 {
2401 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2402 return rcStrict2;
2403 }
2404 if (rcStrict == VINF_PGM_HANDLER_DO_DEFAULT)
2405 rcStrict = rcStrict2;
2406 else
2407 PGM_PHYS_RW_DO_UPDATE_STRICT_RC(rcStrict, rcStrict2);
2408 }
2409 }
2410#endif /* !IN_RING0 && VBOX_WITH_RAW_MODE */
2411
2412 /*
2413 * Take the default action.
2414 */
2415 if (rcStrict == VINF_PGM_HANDLER_DO_DEFAULT)
2416 {
2417 memcpy(pvBuf, pvSrc, cb);
2418 rcStrict = VINF_SUCCESS;
2419 }
2420 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2421 return rcStrict;
2422}
2423
2424
2425/**
2426 * Read physical memory.
2427 *
2428 * This API respects access handlers and MMIO. Use PGMPhysSimpleReadGCPhys() if you
2429 * want to ignore those.
2430 *
2431 * @returns Strict VBox status code in raw-mode and ring-0, normal VBox status
2432 * code in ring-3. Use PGM_PHYS_RW_IS_SUCCESS to check.
2433 * @retval VINF_SUCCESS in all context - read completed.
2434 *
2435 * @retval VINF_EM_OFF in RC and R0 - read completed.
2436 * @retval VINF_EM_SUSPEND in RC and R0 - read completed.
2437 * @retval VINF_EM_RESET in RC and R0 - read completed.
2438 * @retval VINF_EM_HALT in RC and R0 - read completed.
2439 * @retval VINF_SELM_SYNC_GDT in RC only - read completed.
2440 *
2441 * @retval VINF_EM_DBG_STOP in RC and R0 - read completed.
2442 * @retval VINF_EM_DBG_BREAKPOINT in RC and R0 - read completed.
2443 * @retval VINF_EM_RAW_EMULATE_INSTR in RC and R0 only.
2444 *
2445 * @retval VINF_IOM_R3_MMIO_READ in RC and R0.
2446 * @retval VINF_IOM_R3_MMIO_READ_WRITE in RC and R0.
2447 *
2448 * @retval VINF_PATM_CHECK_PATCH_PAGE in RC only.
2449 *
2450 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in RC and R0 for access origins that
2451 * haven't been cleared for strict status codes yet.
2452 *
2453 * @param pVM The cross context VM structure.
2454 * @param GCPhys Physical address start reading from.
2455 * @param pvBuf Where to put the read bits.
2456 * @param cbRead How many bytes to read.
2457 * @param enmOrigin The origin of this call.
2458 */
2459VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin)
2460{
2461 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
2462 LogFlow(("PGMPhysRead: %RGp %d\n", GCPhys, cbRead));
2463
2464 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysRead));
2465 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysReadBytes), cbRead);
2466
2467 pgmLock(pVM);
2468
2469 /*
2470 * Copy loop on ram ranges.
2471 */
2472 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2473 PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2474 for (;;)
2475 {
2476 /* Inside range or not? */
2477 if (pRam && GCPhys >= pRam->GCPhys)
2478 {
2479 /*
2480 * Must work our way thru this page by page.
2481 */
2482 RTGCPHYS off = GCPhys - pRam->GCPhys;
2483 while (off < pRam->cb)
2484 {
2485 unsigned iPage = off >> PAGE_SHIFT;
2486 PPGMPAGE pPage = &pRam->aPages[iPage];
2487 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
2488 if (cb > cbRead)
2489 cb = cbRead;
2490
2491 /*
2492 * Normal page? Get the pointer to it.
2493 */
2494 if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
2495 && !PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
2496 {
2497 /*
2498 * Get the pointer to the page.
2499 */
2500 PGMPAGEMAPLOCK PgMpLck;
2501 const void *pvSrc;
2502 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc, &PgMpLck);
2503 if (RT_SUCCESS(rc))
2504 {
2505 memcpy(pvBuf, pvSrc, cb);
2506 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2507 }
2508 else
2509 {
2510 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
2511 pRam->GCPhys + off, pPage, rc));
2512 memset(pvBuf, 0xff, cb);
2513 }
2514 }
2515 /*
2516 * Have ALL/MMIO access handlers.
2517 */
2518 else
2519 {
2520 VBOXSTRICTRC rcStrict2 = pgmPhysReadHandler(pVM, pPage, pRam->GCPhys + off, pvBuf, cb, enmOrigin);
2521 if (PGM_PHYS_RW_IS_SUCCESS(rcStrict2))
2522 PGM_PHYS_RW_DO_UPDATE_STRICT_RC(rcStrict, rcStrict2);
2523 else
2524 {
2525 pgmUnlock(pVM);
2526 return rcStrict2;
2527 }
2528 }
2529
2530 /* next page */
2531 if (cb >= cbRead)
2532 {
2533 pgmUnlock(pVM);
2534 return rcStrict;
2535 }
2536 cbRead -= cb;
2537 off += cb;
2538 pvBuf = (char *)pvBuf + cb;
2539 } /* walk pages in ram range. */
2540
2541 GCPhys = pRam->GCPhysLast + 1;
2542 }
2543 else
2544 {
2545 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
2546
2547 /*
2548 * Unassigned address space.
2549 */
2550 size_t cb = pRam ? pRam->GCPhys - GCPhys : ~(size_t)0;
2551 if (cb >= cbRead)
2552 {
2553 memset(pvBuf, 0xff, cbRead);
2554 break;
2555 }
2556 memset(pvBuf, 0xff, cb);
2557
2558 cbRead -= cb;
2559 pvBuf = (char *)pvBuf + cb;
2560 GCPhys += cb;
2561 }
2562
2563 /* Advance range if necessary. */
2564 while (pRam && GCPhys > pRam->GCPhysLast)
2565 pRam = pRam->CTX_SUFF(pNext);
2566 } /* Ram range walk */
2567
2568 pgmUnlock(pVM);
2569 return rcStrict;
2570}
2571
2572
2573/**
2574 * Deals with writing to a page with one or more WRITE or ALL access handlers.
2575 *
2576 * @returns Strict VBox status code in ring-0 and raw-mode, ignorable in ring-3.
2577 * See PGM_HANDLER_PHYS_IS_VALID_STATUS and
2578 * PGM_HANDLER_VIRT_IS_VALID_STATUS for details.
2579 *
2580 * @param pVM The cross context VM structure.
2581 * @param pPage The page descriptor.
2582 * @param GCPhys The physical address to start writing at.
2583 * @param pvBuf What to write.
2584 * @param cbWrite How much to write - less or equal to a page.
2585 * @param enmOrigin The origin of this call.
2586 */
2587static VBOXSTRICTRC pgmPhysWriteHandler(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const *pvBuf, size_t cbWrite,
2588 PGMACCESSORIGIN enmOrigin)
2589{
2590 PGMPAGEMAPLOCK PgMpLck;
2591 void *pvDst = NULL;
2592 VBOXSTRICTRC rcStrict;
2593
2594 /*
2595 * Give priority to physical handlers (like #PF does).
2596 *
2597 * Hope for a lonely physical handler first that covers the whole
2598 * write area. This should be a pretty frequent case with MMIO and
2599 * the heavy usage of full page handlers in the page pool.
2600 */
2601 PVMCPU pVCpu = VMMGetCpu(pVM);
2602 if ( !PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage)
2603 || PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage) /* screw virtual handlers on MMIO pages */)
2604 {
2605 PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhys);
2606 if (pCur)
2607 {
2608 Assert(GCPhys >= pCur->Core.Key && GCPhys <= pCur->Core.KeyLast);
2609#ifndef IN_RING3
2610 if (enmOrigin != PGMACCESSORIGIN_IEM)
2611 /* Cannot reliably handle informational status codes in this context */
2612 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2613#endif
2614 size_t cbRange = pCur->Core.KeyLast - GCPhys + 1;
2615 if (cbRange > cbWrite)
2616 cbRange = cbWrite;
2617
2618 Assert(PGMPHYSHANDLER_GET_TYPE(pVM, pCur)->CTX_SUFF(pfnHandler));
2619 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n",
2620 GCPhys, cbRange, pPage, R3STRING(pCur->pszDesc) ));
2621 if (!PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(pPage))
2622 rcStrict = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst, &PgMpLck);
2623 else
2624 rcStrict = VINF_SUCCESS;
2625 if (RT_SUCCESS(rcStrict))
2626 {
2627 PFNPGMPHYSHANDLER pfnHandler = PGMPHYSHANDLER_GET_TYPE(pVM, pCur)->CTX_SUFF(pfnHandler);
2628 void *pvUser = pCur->CTX_SUFF(pvUser);
2629 STAM_PROFILE_START(&pCur->Stat, h);
2630
2631 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2632 PGM_LOCK_ASSERT_OWNER(pVM);
2633 pgmUnlock(pVM);
2634 rcStrict = pfnHandler(pVM, pVCpu, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, enmOrigin, pvUser);
2635 pgmLock(pVM);
2636
2637#ifdef VBOX_WITH_STATISTICS
2638 pCur = pgmHandlerPhysicalLookup(pVM, GCPhys);
2639 if (pCur)
2640 STAM_PROFILE_STOP(&pCur->Stat, h);
2641#else
2642 pCur = NULL; /* might not be valid anymore. */
2643#endif
2644 if (rcStrict == VINF_PGM_HANDLER_DO_DEFAULT)
2645 {
2646 if (pvDst)
2647 memcpy(pvDst, pvBuf, cbRange);
2648 rcStrict = VINF_SUCCESS;
2649 }
2650 else
2651 AssertLogRelMsg(PGM_HANDLER_PHYS_IS_VALID_STATUS(rcStrict, true),
2652 ("rcStrict=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n",
2653 VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, pCur ? R3STRING(pCur->pszDesc) : ""));
2654 }
2655 else
2656 AssertLogRelMsgFailedReturn(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
2657 GCPhys, pPage, VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
2658 if (RT_LIKELY(cbRange == cbWrite) || !PGM_PHYS_RW_IS_SUCCESS(rcStrict))
2659 {
2660 if (pvDst)
2661 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2662 return rcStrict;
2663 }
2664
2665 /* more fun to be had below */
2666 cbWrite -= cbRange;
2667 GCPhys += cbRange;
2668 pvBuf = (uint8_t *)pvBuf + cbRange;
2669 pvDst = (uint8_t *)pvDst + cbRange;
2670 }
2671 else /* The handler is somewhere else in the page, deal with it below. */
2672 rcStrict = VINF_SUCCESS;
2673 Assert(!PGM_PAGE_IS_MMIO_OR_ALIAS(pPage)); /* MMIO handlers are all PAGE_SIZEed! */
2674 }
2675#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
2676 /*
2677 * A virtual handler without any interfering physical handlers.
2678 * Hopefully it'll cover the whole write.
2679 */
2680 else if (!PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage))
2681 {
2682 unsigned iPage;
2683 PPGMVIRTHANDLER pVirt = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &iPage);
2684 if (pVirt)
2685 {
2686# ifndef IN_RING3
2687 if (enmOrigin != PGMACCESSORIGIN_IEM)
2688 /* Cannot reliably handle informational status codes in this context */
2689 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2690# endif
2691 PPGMVIRTHANDLERTYPEINT pVirtType = PGMVIRTANDLER_GET_TYPE(pVM, pVirt);
2692 size_t cbRange = (PAGE_OFFSET_MASK & pVirt->Core.KeyLast) - (PAGE_OFFSET_MASK & GCPhys) + 1;
2693 if (cbRange > cbWrite)
2694 cbRange = cbWrite;
2695
2696 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] virt %s\n",
2697 GCPhys, cbRange, pPage, R3STRING(pVirt->pszDesc) ));
2698 rcStrict = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst, &PgMpLck);
2699 if (RT_SUCCESS(rcStrict))
2700 {
2701 Assert(pVirtType->CTX_SUFF(pfnHandler));
2702 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2703 + (iPage << PAGE_SHIFT)
2704 + (GCPhys & PAGE_OFFSET_MASK);
2705
2706 STAM_PROFILE_START(&pVirt->Stat, h);
2707 rcStrict = pVirtType->CTX_SUFF(pfnHandler)(pVM, pVCpu, GCPtr, pvDst, (void *)pvBuf, cbRange,
2708 PGMACCESSTYPE_WRITE, enmOrigin, pVirt->CTX_SUFF(pvUser));
2709 STAM_PROFILE_STOP(&pVirt->Stat, h);
2710 if (rcStrict == VINF_PGM_HANDLER_DO_DEFAULT)
2711 {
2712 memcpy(pvDst, pvBuf, cbRange);
2713 rcStrict = VINF_SUCCESS;
2714 }
2715 else
2716 AssertLogRelMsg(PGM_HANDLER_VIRT_IS_VALID_STATUS(rcStrict, true),
2717 ("rcStrict=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n",
2718 VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, R3STRING(pVirt->pszDesc)));
2719 }
2720 else
2721 AssertLogRelMsgFailedReturn(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
2722 GCPhys, pPage, VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
2723 if (RT_LIKELY(cbRange == cbWrite) || !PGM_PHYS_RW_IS_SUCCESS(rcStrict))
2724 {
2725 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2726 return rcStrict;
2727 }
2728
2729 /* more fun to be had below */
2730 cbWrite -= cbRange;
2731 GCPhys += cbRange;
2732 pvBuf = (uint8_t *)pvBuf + cbRange;
2733 pvDst = (uint8_t *)pvDst + cbRange;
2734 }
2735 else /* The handler is somewhere else in the page, deal with it below. */
2736 rcStrict = VINF_SUCCESS;
2737 }
2738#endif /* !IN_RING0 && VBOX_WITH_RAW_MODE */
2739 else
2740 rcStrict = VINF_SUCCESS;
2741
2742
2743 /*
2744 * Deal with all the odd ends.
2745 */
2746 Assert(rcStrict != VINF_PGM_HANDLER_DO_DEFAULT);
2747
2748 /* We need a writable destination page. */
2749 if (!pvDst)
2750 {
2751 int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst, &PgMpLck);
2752 AssertLogRelMsgReturn(RT_SUCCESS(rc2),
2753 ("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n", GCPhys, pPage, rc2),
2754 rc2);
2755 }
2756
2757 /* The loop state (big + ugly). */
2758#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
2759 unsigned iVirtPage = 0;
2760 PPGMVIRTHANDLER pVirt = NULL;
2761 uint32_t offVirt = PAGE_SIZE;
2762 uint32_t offVirtLast = PAGE_SIZE;
2763 bool fMoreVirt = PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage);
2764#else
2765 uint32_t const offVirt = UINT32_MAX;
2766#endif
2767
2768 PPGMPHYSHANDLER pPhys = NULL;
2769 uint32_t offPhys = PAGE_SIZE;
2770 uint32_t offPhysLast = PAGE_SIZE;
2771 bool fMorePhys = PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage);
2772
2773 /* The loop. */
2774 for (;;)
2775 {
2776#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
2777 /*
2778 * Find the closest handler at or above GCPhys.
2779 */
2780 if (fMoreVirt && !pVirt)
2781 {
2782 pVirt = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &iVirtPage);
2783 if (pVirt)
2784 {
2785 offVirt = 0;
2786 offVirtLast = (pVirt->aPhysToVirt[iVirtPage].Core.KeyLast & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
2787 }
2788 else
2789 {
2790 PPGMPHYS2VIRTHANDLER pVirtPhys;
2791 pVirtPhys = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGetBestFit(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysToVirtHandlers,
2792 GCPhys, true /* fAbove */);
2793 if ( pVirtPhys
2794 && (pVirtPhys->Core.Key >> PAGE_SHIFT) == (GCPhys >> PAGE_SHIFT))
2795 {
2796 /* ASSUME that pVirtPhys only covers one page. */
2797 Assert((pVirtPhys->Core.Key >> PAGE_SHIFT) == (pVirtPhys->Core.KeyLast >> PAGE_SHIFT));
2798 Assert(pVirtPhys->Core.Key > GCPhys);
2799
2800 pVirt = (PPGMVIRTHANDLER)((uintptr_t)pVirtPhys + pVirtPhys->offVirtHandler);
2801 iVirtPage = pVirtPhys - &pVirt->aPhysToVirt[0]; Assert(iVirtPage == 0);
2802 offVirt = (pVirtPhys->Core.Key & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
2803 offVirtLast = (pVirtPhys->Core.KeyLast & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
2804 }
2805 else
2806 {
2807 pVirt = NULL;
2808 fMoreVirt = false;
2809 offVirt = offVirtLast = PAGE_SIZE;
2810 }
2811 }
2812 }
2813#endif
2814
2815 if (fMorePhys && !pPhys)
2816 {
2817 pPhys = pgmHandlerPhysicalLookup(pVM, GCPhys);
2818 if (pPhys)
2819 {
2820 offPhys = 0;
2821 offPhysLast = pPhys->Core.KeyLast - GCPhys; /* ASSUMES < 4GB handlers... */
2822 }
2823 else
2824 {
2825 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers,
2826 GCPhys, true /* fAbove */);
2827 if ( pPhys
2828 && pPhys->Core.Key <= GCPhys + (cbWrite - 1))
2829 {
2830 offPhys = pPhys->Core.Key - GCPhys;
2831 offPhysLast = pPhys->Core.KeyLast - GCPhys; /* ASSUMES < 4GB handlers... */
2832 }
2833 else
2834 {
2835 pPhys = NULL;
2836 fMorePhys = false;
2837 offPhys = offPhysLast = PAGE_SIZE;
2838 }
2839 }
2840 }
2841
2842 /*
2843 * Handle access to space without handlers (that's easy).
2844 */
2845 VBOXSTRICTRC rcStrict2 = VINF_PGM_HANDLER_DO_DEFAULT;
2846 uint32_t cbRange = (uint32_t)cbWrite;
2847 if (offPhys && offVirt)
2848 {
2849 if (cbRange > offPhys)
2850 cbRange = offPhys;
2851 if (cbRange > offVirt)
2852 cbRange = offVirt;
2853 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] miss\n", GCPhys, cbRange, pPage));
2854 }
2855 /*
2856 * Physical handler.
2857 */
2858 else if (!offPhys && offVirt)
2859 {
2860#ifndef IN_RING3
2861 if (enmOrigin != PGMACCESSORIGIN_IEM)
2862 /* Cannot reliably handle informational status codes in this context */
2863 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2864#endif
2865 if (cbRange > offPhysLast + 1)
2866 cbRange = offPhysLast + 1;
2867 if (cbRange > offVirt)
2868 cbRange = offVirt;
2869
2870 PFNPGMPHYSHANDLER pfnHandler = PGMPHYSHANDLER_GET_TYPE(pVM, pPhys)->CTX_SUFF(pfnHandler);
2871 void *pvUser = pPhys->CTX_SUFF(pvUser);
2872
2873 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cbRange, pPage, R3STRING(pPhys->pszDesc) ));
2874 STAM_PROFILE_START(&pPhys->Stat, h);
2875
2876 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2877 PGM_LOCK_ASSERT_OWNER(pVM);
2878 pgmUnlock(pVM);
2879 rcStrict2 = pfnHandler(pVM, pVCpu, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, enmOrigin, pvUser);
2880 pgmLock(pVM);
2881
2882#ifdef VBOX_WITH_STATISTICS
2883 pPhys = pgmHandlerPhysicalLookup(pVM, GCPhys);
2884 if (pPhys)
2885 STAM_PROFILE_STOP(&pPhys->Stat, h);
2886#else
2887 pPhys = NULL; /* might not be valid anymore. */
2888#endif
2889 AssertLogRelMsg(PGM_HANDLER_PHYS_IS_VALID_STATUS(rcStrict2, true),
2890 ("rcStrict2=%Rrc (rcStrict=%Rrc) GCPhys=%RGp pPage=%R[pgmpage] %s\n", VBOXSTRICTRC_VAL(rcStrict2),
2891 VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, pPhys ? R3STRING(pPhys->pszDesc) : ""));
2892 }
2893#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
2894 /*
2895 * Virtual handler.
2896 */
2897 else if (offPhys && !offVirt)
2898 {
2899# ifndef IN_RING3
2900 if (enmOrigin != PGMACCESSORIGIN_IEM)
2901 /* Cannot reliably handle informational status codes in this context */
2902 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2903# endif
2904 if (cbRange > offVirtLast + 1)
2905 cbRange = offVirtLast + 1;
2906 if (cbRange > offPhys)
2907 cbRange = offPhys;
2908
2909 PPGMVIRTHANDLERTYPEINT pVirtType = PGMVIRTANDLER_GET_TYPE(pVM, pVirt);
2910 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cbRange, pPage, R3STRING(pVirt->pszDesc) ));
2911 Assert(pVirtType->CTX_SUFF(pfnHandler));
2912 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2913 + (iVirtPage << PAGE_SHIFT)
2914 + (GCPhys & PAGE_OFFSET_MASK);
2915 STAM_PROFILE_START(&pVirt->Stat, h);
2916 rcStrict2 = pVirtType->CTX_SUFF(pfnHandler)(pVM, pVCpu, GCPtr, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE,
2917 enmOrigin, pVirt->CTX_SUFF(pvUser));
2918 STAM_PROFILE_STOP(&pVirt->Stat, h);
2919 AssertLogRelMsg(PGM_HANDLER_VIRT_IS_VALID_STATUS(rcStrict2, true),
2920 ("rcStrict2=%Rrc (rcStrict=%Rrc) GCPhys=%RGp pPage=%R[pgmpage] %s\n", VBOXSTRICTRC_VAL(rcStrict2),
2921 VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, pPhys ? R3STRING(pPhys->pszDesc) : ""));
2922 pVirt = NULL;
2923 }
2924 /*
2925 * Both... give the physical one priority.
2926 */
2927 else
2928 {
2929# ifndef IN_RING3
2930 if (enmOrigin != PGMACCESSORIGIN_IEM)
2931 /* Cannot reliably handle informational status codes in this context */
2932 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2933# endif
2934 Assert(!offPhys && !offVirt);
2935 if (cbRange > offVirtLast + 1)
2936 cbRange = offVirtLast + 1;
2937 if (cbRange > offPhysLast + 1)
2938 cbRange = offPhysLast + 1;
2939
2940 PPGMVIRTHANDLERTYPEINT pVirtType = PGMVIRTANDLER_GET_TYPE(pVM, pVirt);
2941 if (pVirtType->pfnHandlerR3)
2942 Log(("pgmPhysWriteHandler: overlapping phys and virt handlers at %RGp %R[pgmpage]; cbRange=%#x\n", GCPhys, pPage, cbRange));
2943 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys/virt %s/%s\n", GCPhys, cbRange, pPage, R3STRING(pPhys->pszDesc), R3STRING(pVirt->pszDesc) ));
2944
2945 PFNPGMPHYSHANDLER pfnHandler = PGMPHYSHANDLER_GET_TYPE(pVM, pPhys)->CTX_SUFF(pfnHandler);
2946 void *pvUser = pPhys->CTX_SUFF(pvUser);
2947 STAM_PROFILE_START(&pPhys->Stat, h);
2948
2949 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2950 PGM_LOCK_ASSERT_OWNER(pVM);
2951 pgmUnlock(pVM);
2952 rcStrict2 = pfnHandler(pVM, pVCpu, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, enmOrigin, pvUser);
2953 pgmLock(pVM);
2954
2955# ifdef VBOX_WITH_STATISTICS
2956 pPhys = pgmHandlerPhysicalLookup(pVM, GCPhys);
2957 if (pPhys)
2958 STAM_PROFILE_STOP(&pPhys->Stat, h);
2959# else
2960 pPhys = NULL; /* might not be valid anymore. */
2961# endif
2962 AssertLogRelMsg(PGM_HANDLER_PHYS_IS_VALID_STATUS(rcStrict2, true),
2963 ("rcStrict2=%Rrc (rcStrict=%Rrc) GCPhys=%RGp pPage=%R[pgmpage] %s\n", VBOXSTRICTRC_VAL(rcStrict2),
2964 VBOXSTRICTRC_VAL(rcStrict), GCPhys, pPage, pPhys ? R3STRING(pPhys->pszDesc) : ""));
2965 if (rcStrict2 == VINF_PGM_HANDLER_DO_DEFAULT || PGM_PHYS_RW_IS_SUCCESS(rcStrict2))
2966 {
2967 Assert(pVirtType->CTX_SUFF(pfnHandler));
2968 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2969 + (iVirtPage << PAGE_SHIFT)
2970 + (GCPhys & PAGE_OFFSET_MASK);
2971 pvUser = pVirt->CTX_SUFF(pvUser);
2972
2973 STAM_PROFILE_START(&pVirt->Stat, h2);
2974 VBOXSTRICTRC rcStrict3 = pVirtType->CTX_SUFF(pfnHandler)(pVM, pVCpu, GCPtr, pvDst, (void *)pvBuf, cbRange,
2975 PGMACCESSTYPE_WRITE, enmOrigin, pvUser);
2976 STAM_PROFILE_STOP(&pVirt->Stat, h2);
2977
2978 /* Merge the 3rd status into the 2nd. */
2979 if (rcStrict3 == VINF_SUCCESS)
2980 {
2981 if (rcStrict2 == VINF_PGM_HANDLER_DO_DEFAULT)
2982 rcStrict2 = VINF_SUCCESS;
2983 }
2984 else if (rcStrict3 != VINF_PGM_HANDLER_DO_DEFAULT)
2985 {
2986 AssertLogRelMsg(PGM_HANDLER_VIRT_IS_VALID_STATUS(rcStrict3, true),
2987 ("rcStrict3=%Rrc (rcStrict2=%Rrc) (rcStrict=%Rrc) GCPhys=%RGp pPage=%R[pgmpage] %s\n",
2988 VBOXSTRICTRC_VAL(rcStrict3), VBOXSTRICTRC_VAL(rcStrict2), VBOXSTRICTRC_VAL(rcStrict),
2989 GCPhys, pPage, R3STRING(pVirt->pszDesc) ));
2990 if (rcStrict2 == VINF_PGM_HANDLER_DO_DEFAULT)
2991 rcStrict2 = rcStrict3;
2992 else if (!PGM_PHYS_RW_IS_SUCCESS(rcStrict3))
2993 rcStrict2 = rcStrict3;
2994 else
2995 PGM_PHYS_RW_DO_UPDATE_STRICT_RC(rcStrict2, rcStrict3);
2996 }
2997 }
2998 pPhys = NULL;
2999 pVirt = NULL;
3000 }
3001#endif /* !IN_RING0 && VBOX_WITH_RAW_MODE */
3002
3003
3004 /*
3005 * Execute the default action and merge the status codes.
3006 */
3007 if (rcStrict2 == VINF_PGM_HANDLER_DO_DEFAULT)
3008 {
3009 memcpy(pvDst, pvBuf, cbRange);
3010 rcStrict2 = VINF_SUCCESS;
3011 }
3012 else if (!PGM_PHYS_RW_IS_SUCCESS(rcStrict2))
3013 {
3014 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
3015 return rcStrict2;
3016 }
3017 else
3018 PGM_PHYS_RW_DO_UPDATE_STRICT_RC(rcStrict, rcStrict2);
3019
3020 /*
3021 * Advance if we've got more stuff to do.
3022 */
3023 if (cbRange >= cbWrite)
3024 {
3025 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
3026 return rcStrict;
3027 }
3028
3029
3030 cbWrite -= cbRange;
3031 GCPhys += cbRange;
3032 pvBuf = (uint8_t *)pvBuf + cbRange;
3033 pvDst = (uint8_t *)pvDst + cbRange;
3034
3035 offPhys -= cbRange;
3036 offPhysLast -= cbRange;
3037#if !defined(IN_RING0) && defined(VBOX_WITH_RAW_MODE)
3038 offVirt -= cbRange;
3039 offVirtLast -= cbRange;
3040#endif
3041 }
3042}
3043
3044
3045/**
3046 * Write to physical memory.
3047 *
3048 * This API respects access handlers and MMIO. Use PGMPhysSimpleWriteGCPhys() if you
3049 * want to ignore those.
3050 *
3051 * @returns Strict VBox status code in raw-mode and ring-0, normal VBox status
3052 * code in ring-3. Use PGM_PHYS_RW_IS_SUCCESS to check.
3053 * @retval VINF_SUCCESS in all context - write completed.
3054 *
3055 * @retval VINF_EM_OFF in RC and R0 - write completed.
3056 * @retval VINF_EM_SUSPEND in RC and R0 - write completed.
3057 * @retval VINF_EM_RESET in RC and R0 - write completed.
3058 * @retval VINF_EM_HALT in RC and R0 - write completed.
3059 * @retval VINF_SELM_SYNC_GDT in RC only - write completed.
3060 *
3061 * @retval VINF_EM_DBG_STOP in RC and R0 - write completed.
3062 * @retval VINF_EM_DBG_BREAKPOINT in RC and R0 - write completed.
3063 * @retval VINF_EM_RAW_EMULATE_INSTR in RC and R0 only.
3064 *
3065 * @retval VINF_IOM_R3_MMIO_WRITE in RC and R0.
3066 * @retval VINF_IOM_R3_MMIO_READ_WRITE in RC and R0.
3067 *
3068 * @retval VINF_EM_RAW_EMULATE_IO_BLOCK in R0 only.
3069 *
3070 * @retval VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT in RC only - write completed.
3071 * @retval VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT in RC only.
3072 * @retval VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT in RC only.
3073 * @retval VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT in RC only.
3074 * @retval VINF_CSAM_PENDING_ACTION in RC only.
3075 * @retval VINF_PATM_CHECK_PATCH_PAGE in RC only.
3076 *
3077 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in RC and R0 for access origins that
3078 * haven't been cleared for strict status codes yet.
3079 *
3080 *
3081 * @param pVM The cross context VM structure.
3082 * @param GCPhys Physical address to write to.
3083 * @param pvBuf What to write.
3084 * @param cbWrite How many bytes to write.
3085 * @param enmOrigin Who is calling.
3086 */
3087VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin)
3088{
3089 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMPhysWrite after pgmR3Save()! enmOrigin=%d\n", enmOrigin));
3090 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
3091 LogFlow(("PGMPhysWrite: %RGp %d\n", GCPhys, cbWrite));
3092
3093 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysWrite));
3094 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysWriteBytes), cbWrite);
3095
3096 pgmLock(pVM);
3097
3098 /*
3099 * Copy loop on ram ranges.
3100 */
3101 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3102 PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3103 for (;;)
3104 {
3105 /* Inside range or not? */
3106 if (pRam && GCPhys >= pRam->GCPhys)
3107 {
3108 /*
3109 * Must work our way thru this page by page.
3110 */
3111 RTGCPTR off = GCPhys - pRam->GCPhys;
3112 while (off < pRam->cb)
3113 {
3114 RTGCPTR iPage = off >> PAGE_SHIFT;
3115 PPGMPAGE pPage = &pRam->aPages[iPage];
3116 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
3117 if (cb > cbWrite)
3118 cb = cbWrite;
3119
3120 /*
3121 * Normal page? Get the pointer to it.
3122 */
3123 if ( !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
3124 && !PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
3125 {
3126 PGMPAGEMAPLOCK PgMpLck;
3127 void *pvDst;
3128 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst, &PgMpLck);
3129 if (RT_SUCCESS(rc))
3130 {
3131 Assert(!PGM_PAGE_IS_BALLOONED(pPage));
3132 memcpy(pvDst, pvBuf, cb);
3133 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
3134 }
3135 /* Ignore writes to ballooned pages. */
3136 else if (!PGM_PAGE_IS_BALLOONED(pPage))
3137 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
3138 pRam->GCPhys + off, pPage, rc));
3139 }
3140 /*
3141 * Active WRITE or ALL access handlers.
3142 */
3143 else
3144 {
3145 VBOXSTRICTRC rcStrict2 = pgmPhysWriteHandler(pVM, pPage, pRam->GCPhys + off, pvBuf, cb, enmOrigin);
3146 if (PGM_PHYS_RW_IS_SUCCESS(rcStrict2))
3147 PGM_PHYS_RW_DO_UPDATE_STRICT_RC(rcStrict, rcStrict2);
3148 else
3149 {
3150 pgmUnlock(pVM);
3151 return rcStrict2;
3152 }
3153 }
3154
3155 /* next page */
3156 if (cb >= cbWrite)
3157 {
3158 pgmUnlock(pVM);
3159 return rcStrict;
3160 }
3161
3162 cbWrite -= cb;
3163 off += cb;
3164 pvBuf = (const char *)pvBuf + cb;
3165 } /* walk pages in ram range */
3166
3167 GCPhys = pRam->GCPhysLast + 1;
3168 }
3169 else
3170 {
3171 /*
3172 * Unassigned address space, skip it.
3173 */
3174 if (!pRam)
3175 break;
3176 size_t cb = pRam->GCPhys - GCPhys;
3177 if (cb >= cbWrite)
3178 break;
3179 cbWrite -= cb;
3180 pvBuf = (const char *)pvBuf + cb;
3181 GCPhys += cb;
3182 }
3183
3184 /* Advance range if necessary. */
3185 while (pRam && GCPhys > pRam->GCPhysLast)
3186 pRam = pRam->CTX_SUFF(pNext);
3187 } /* Ram range walk */
3188
3189 pgmUnlock(pVM);
3190 return rcStrict;
3191}
3192
3193
3194/**
3195 * Read from guest physical memory by GC physical address, bypassing
3196 * MMIO and access handlers.
3197 *
3198 * @returns VBox status code.
3199 * @param pVM The cross context VM structure.
3200 * @param pvDst The destination address.
3201 * @param GCPhysSrc The source address (GC physical address).
3202 * @param cb The number of bytes to read.
3203 */
3204VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb)
3205{
3206 /*
3207 * Treat the first page as a special case.
3208 */
3209 if (!cb)
3210 return VINF_SUCCESS;
3211
3212 /* map the 1st page */
3213 void const *pvSrc;
3214 PGMPAGEMAPLOCK Lock;
3215 int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysSrc, &pvSrc, &Lock);
3216 if (RT_FAILURE(rc))
3217 return rc;
3218
3219 /* optimize for the case where access is completely within the first page. */
3220 size_t cbPage = PAGE_SIZE - (GCPhysSrc & PAGE_OFFSET_MASK);
3221 if (RT_LIKELY(cb <= cbPage))
3222 {
3223 memcpy(pvDst, pvSrc, cb);
3224 PGMPhysReleasePageMappingLock(pVM, &Lock);
3225 return VINF_SUCCESS;
3226 }
3227
3228 /* copy to the end of the page. */
3229 memcpy(pvDst, pvSrc, cbPage);
3230 PGMPhysReleasePageMappingLock(pVM, &Lock);
3231 GCPhysSrc += cbPage;
3232 pvDst = (uint8_t *)pvDst + cbPage;
3233 cb -= cbPage;
3234
3235 /*
3236 * Page by page.
3237 */
3238 for (;;)
3239 {
3240 /* map the page */
3241 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysSrc, &pvSrc, &Lock);
3242 if (RT_FAILURE(rc))
3243 return rc;
3244
3245 /* last page? */
3246 if (cb <= PAGE_SIZE)
3247 {
3248 memcpy(pvDst, pvSrc, cb);
3249 PGMPhysReleasePageMappingLock(pVM, &Lock);
3250 return VINF_SUCCESS;
3251 }
3252
3253 /* copy the entire page and advance */
3254 memcpy(pvDst, pvSrc, PAGE_SIZE);
3255 PGMPhysReleasePageMappingLock(pVM, &Lock);
3256 GCPhysSrc += PAGE_SIZE;
3257 pvDst = (uint8_t *)pvDst + PAGE_SIZE;
3258 cb -= PAGE_SIZE;
3259 }
3260 /* won't ever get here. */
3261}
3262
3263
3264/**
3265 * Write to guest physical memory referenced by GC pointer.
3266 * Write memory to GC physical address in guest physical memory.
3267 *
3268 * This will bypass MMIO and access handlers.
3269 *
3270 * @returns VBox status code.
3271 * @param pVM The cross context VM structure.
3272 * @param GCPhysDst The GC physical address of the destination.
3273 * @param pvSrc The source buffer.
3274 * @param cb The number of bytes to write.
3275 */
3276VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb)
3277{
3278 LogFlow(("PGMPhysSimpleWriteGCPhys: %RGp %zu\n", GCPhysDst, cb));
3279
3280 /*
3281 * Treat the first page as a special case.
3282 */
3283 if (!cb)
3284 return VINF_SUCCESS;
3285
3286 /* map the 1st page */
3287 void *pvDst;
3288 PGMPAGEMAPLOCK Lock;
3289 int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysDst, &pvDst, &Lock);
3290 if (RT_FAILURE(rc))
3291 return rc;
3292
3293 /* optimize for the case where access is completely within the first page. */
3294 size_t cbPage = PAGE_SIZE - (GCPhysDst & PAGE_OFFSET_MASK);
3295 if (RT_LIKELY(cb <= cbPage))
3296 {
3297 memcpy(pvDst, pvSrc, cb);
3298 PGMPhysReleasePageMappingLock(pVM, &Lock);
3299 return VINF_SUCCESS;
3300 }
3301
3302 /* copy to the end of the page. */
3303 memcpy(pvDst, pvSrc, cbPage);
3304 PGMPhysReleasePageMappingLock(pVM, &Lock);
3305 GCPhysDst += cbPage;
3306 pvSrc = (const uint8_t *)pvSrc + cbPage;
3307 cb -= cbPage;
3308
3309 /*
3310 * Page by page.
3311 */
3312 for (;;)
3313 {
3314 /* map the page */
3315 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysDst, &pvDst, &Lock);
3316 if (RT_FAILURE(rc))
3317 return rc;
3318
3319 /* last page? */
3320 if (cb <= PAGE_SIZE)
3321 {
3322 memcpy(pvDst, pvSrc, cb);
3323 PGMPhysReleasePageMappingLock(pVM, &Lock);
3324 return VINF_SUCCESS;
3325 }
3326
3327 /* copy the entire page and advance */
3328 memcpy(pvDst, pvSrc, PAGE_SIZE);
3329 PGMPhysReleasePageMappingLock(pVM, &Lock);
3330 GCPhysDst += PAGE_SIZE;
3331 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
3332 cb -= PAGE_SIZE;
3333 }
3334 /* won't ever get here. */
3335}
3336
3337
3338/**
3339 * Read from guest physical memory referenced by GC pointer.
3340 *
3341 * This function uses the current CR3/CR0/CR4 of the guest and will
3342 * bypass access handlers and not set any accessed bits.
3343 *
3344 * @returns VBox status code.
3345 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3346 * @param pvDst The destination address.
3347 * @param GCPtrSrc The source address (GC pointer).
3348 * @param cb The number of bytes to read.
3349 */
3350VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
3351{
3352 PVM pVM = pVCpu->CTX_SUFF(pVM);
3353/** @todo fix the macro / state handling: VMCPU_ASSERT_EMT_OR_GURU(pVCpu); */
3354
3355 /*
3356 * Treat the first page as a special case.
3357 */
3358 if (!cb)
3359 return VINF_SUCCESS;
3360
3361 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysSimpleRead));
3362 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysSimpleReadBytes), cb);
3363
3364 /* Take the PGM lock here, because many called functions take the lock for a very short period. That's counter-productive
3365 * when many VCPUs are fighting for the lock.
3366 */
3367 pgmLock(pVM);
3368
3369 /* map the 1st page */
3370 void const *pvSrc;
3371 PGMPAGEMAPLOCK Lock;
3372 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrSrc, &pvSrc, &Lock);
3373 if (RT_FAILURE(rc))
3374 {
3375 pgmUnlock(pVM);
3376 return rc;
3377 }
3378
3379 /* optimize for the case where access is completely within the first page. */
3380 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
3381 if (RT_LIKELY(cb <= cbPage))
3382 {
3383 memcpy(pvDst, pvSrc, cb);
3384 PGMPhysReleasePageMappingLock(pVM, &Lock);
3385 pgmUnlock(pVM);
3386 return VINF_SUCCESS;
3387 }
3388
3389 /* copy to the end of the page. */
3390 memcpy(pvDst, pvSrc, cbPage);
3391 PGMPhysReleasePageMappingLock(pVM, &Lock);
3392 GCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCPtrSrc + cbPage);
3393 pvDst = (uint8_t *)pvDst + cbPage;
3394 cb -= cbPage;
3395
3396 /*
3397 * Page by page.
3398 */
3399 for (;;)
3400 {
3401 /* map the page */
3402 rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrSrc, &pvSrc, &Lock);
3403 if (RT_FAILURE(rc))
3404 {
3405 pgmUnlock(pVM);
3406 return rc;
3407 }
3408
3409 /* last page? */
3410 if (cb <= PAGE_SIZE)
3411 {
3412 memcpy(pvDst, pvSrc, cb);
3413 PGMPhysReleasePageMappingLock(pVM, &Lock);
3414 pgmUnlock(pVM);
3415 return VINF_SUCCESS;
3416 }
3417
3418 /* copy the entire page and advance */
3419 memcpy(pvDst, pvSrc, PAGE_SIZE);
3420 PGMPhysReleasePageMappingLock(pVM, &Lock);
3421 GCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCPtrSrc + PAGE_SIZE);
3422 pvDst = (uint8_t *)pvDst + PAGE_SIZE;
3423 cb -= PAGE_SIZE;
3424 }
3425 /* won't ever get here. */
3426}
3427
3428
3429/**
3430 * Write to guest physical memory referenced by GC pointer.
3431 *
3432 * This function uses the current CR3/CR0/CR4 of the guest and will
3433 * bypass access handlers and not set dirty or accessed bits.
3434 *
3435 * @returns VBox status code.
3436 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3437 * @param GCPtrDst The destination address (GC pointer).
3438 * @param pvSrc The source address.
3439 * @param cb The number of bytes to write.
3440 */
3441VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
3442{
3443 PVM pVM = pVCpu->CTX_SUFF(pVM);
3444 VMCPU_ASSERT_EMT(pVCpu);
3445
3446 /*
3447 * Treat the first page as a special case.
3448 */
3449 if (!cb)
3450 return VINF_SUCCESS;
3451
3452 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysSimpleWrite));
3453 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PhysSimpleWriteBytes), cb);
3454
3455 /* map the 1st page */
3456 void *pvDst;
3457 PGMPAGEMAPLOCK Lock;
3458 int rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
3459 if (RT_FAILURE(rc))
3460 return rc;
3461
3462 /* optimize for the case where access is completely within the first page. */
3463 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
3464 if (RT_LIKELY(cb <= cbPage))
3465 {
3466 memcpy(pvDst, pvSrc, cb);
3467 PGMPhysReleasePageMappingLock(pVM, &Lock);
3468 return VINF_SUCCESS;
3469 }
3470
3471 /* copy to the end of the page. */
3472 memcpy(pvDst, pvSrc, cbPage);
3473 PGMPhysReleasePageMappingLock(pVM, &Lock);
3474 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbPage);
3475 pvSrc = (const uint8_t *)pvSrc + cbPage;
3476 cb -= cbPage;
3477
3478 /*
3479 * Page by page.
3480 */
3481 for (;;)
3482 {
3483 /* map the page */
3484 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
3485 if (RT_FAILURE(rc))
3486 return rc;
3487
3488 /* last page? */
3489 if (cb <= PAGE_SIZE)
3490 {
3491 memcpy(pvDst, pvSrc, cb);
3492 PGMPhysReleasePageMappingLock(pVM, &Lock);
3493 return VINF_SUCCESS;
3494 }
3495
3496 /* copy the entire page and advance */
3497 memcpy(pvDst, pvSrc, PAGE_SIZE);
3498 PGMPhysReleasePageMappingLock(pVM, &Lock);
3499 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + PAGE_SIZE);
3500 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
3501 cb -= PAGE_SIZE;
3502 }
3503 /* won't ever get here. */
3504}
3505
3506
3507/**
3508 * Write to guest physical memory referenced by GC pointer and update the PTE.
3509 *
3510 * This function uses the current CR3/CR0/CR4 of the guest and will
3511 * bypass access handlers but will set any dirty and accessed bits in the PTE.
3512 *
3513 * If you don't want to set the dirty bit, use PGMPhysSimpleWriteGCPtr().
3514 *
3515 * @returns VBox status code.
3516 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3517 * @param GCPtrDst The destination address (GC pointer).
3518 * @param pvSrc The source address.
3519 * @param cb The number of bytes to write.
3520 */
3521VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
3522{
3523 PVM pVM = pVCpu->CTX_SUFF(pVM);
3524 VMCPU_ASSERT_EMT(pVCpu);
3525
3526 /*
3527 * Treat the first page as a special case.
3528 * Btw. this is the same code as in PGMPhyssimpleWriteGCPtr excep for the PGMGstModifyPage.
3529 */
3530 if (!cb)
3531 return VINF_SUCCESS;
3532
3533 /* map the 1st page */
3534 void *pvDst;
3535 PGMPAGEMAPLOCK Lock;
3536 int rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
3537 if (RT_FAILURE(rc))
3538 return rc;
3539
3540 /* optimize for the case where access is completely within the first page. */
3541 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
3542 if (RT_LIKELY(cb <= cbPage))
3543 {
3544 memcpy(pvDst, pvSrc, cb);
3545 PGMPhysReleasePageMappingLock(pVM, &Lock);
3546 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
3547 return VINF_SUCCESS;
3548 }
3549
3550 /* copy to the end of the page. */
3551 memcpy(pvDst, pvSrc, cbPage);
3552 PGMPhysReleasePageMappingLock(pVM, &Lock);
3553 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
3554 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbPage);
3555 pvSrc = (const uint8_t *)pvSrc + cbPage;
3556 cb -= cbPage;
3557
3558 /*
3559 * Page by page.
3560 */
3561 for (;;)
3562 {
3563 /* map the page */
3564 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
3565 if (RT_FAILURE(rc))
3566 return rc;
3567
3568 /* last page? */
3569 if (cb <= PAGE_SIZE)
3570 {
3571 memcpy(pvDst, pvSrc, cb);
3572 PGMPhysReleasePageMappingLock(pVM, &Lock);
3573 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
3574 return VINF_SUCCESS;
3575 }
3576
3577 /* copy the entire page and advance */
3578 memcpy(pvDst, pvSrc, PAGE_SIZE);
3579 PGMPhysReleasePageMappingLock(pVM, &Lock);
3580 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
3581 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + PAGE_SIZE);
3582 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
3583 cb -= PAGE_SIZE;
3584 }
3585 /* won't ever get here. */
3586}
3587
3588
3589/**
3590 * Read from guest physical memory referenced by GC pointer.
3591 *
3592 * This function uses the current CR3/CR0/CR4 of the guest and will
3593 * respect access handlers and set accessed bits.
3594 *
3595 * @returns Strict VBox status, see PGMPhysRead for details.
3596 * @retval VERR_PAGE_TABLE_NOT_PRESENT if there is no page mapped at the
3597 * specified virtual address.
3598 *
3599 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3600 * @param pvDst The destination address.
3601 * @param GCPtrSrc The source address (GC pointer).
3602 * @param cb The number of bytes to read.
3603 * @param enmOrigin Who is calling.
3604 * @thread EMT(pVCpu)
3605 */
3606VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin)
3607{
3608 RTGCPHYS GCPhys;
3609 uint64_t fFlags;
3610 int rc;
3611 PVM pVM = pVCpu->CTX_SUFF(pVM);
3612 VMCPU_ASSERT_EMT(pVCpu);
3613
3614 /*
3615 * Anything to do?
3616 */
3617 if (!cb)
3618 return VINF_SUCCESS;
3619
3620 LogFlow(("PGMPhysReadGCPtr: %RGv %zu\n", GCPtrSrc, cb));
3621
3622 /*
3623 * Optimize reads within a single page.
3624 */
3625 if (((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
3626 {
3627 /* Convert virtual to physical address + flags */
3628 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrSrc, &fFlags, &GCPhys);
3629 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrSrc), rc);
3630 GCPhys |= (RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK;
3631
3632 /* mark the guest page as accessed. */
3633 if (!(fFlags & X86_PTE_A))
3634 {
3635 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
3636 AssertRC(rc);
3637 }
3638
3639 return PGMPhysRead(pVM, GCPhys, pvDst, cb, enmOrigin);
3640 }
3641
3642 /*
3643 * Page by page.
3644 */
3645 for (;;)
3646 {
3647 /* Convert virtual to physical address + flags */
3648 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrSrc, &fFlags, &GCPhys);
3649 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrSrc), rc);
3650 GCPhys |= (RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK;
3651
3652 /* mark the guest page as accessed. */
3653 if (!(fFlags & X86_PTE_A))
3654 {
3655 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
3656 AssertRC(rc);
3657 }
3658
3659 /* copy */
3660 size_t cbRead = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
3661 if (cbRead < cb)
3662 {
3663 VBOXSTRICTRC rcStrict = PGMPhysRead(pVM, GCPhys, pvDst, cbRead, enmOrigin);
3664 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3665 { /* likely */ }
3666 else
3667 return rcStrict;
3668 }
3669 else /* Last page (cbRead is PAGE_SIZE, we only need cb!) */
3670 return PGMPhysRead(pVM, GCPhys, pvDst, cb, enmOrigin);
3671
3672 /* next */
3673 Assert(cb > cbRead);
3674 cb -= cbRead;
3675 pvDst = (uint8_t *)pvDst + cbRead;
3676 GCPtrSrc += cbRead;
3677 }
3678}
3679
3680
3681/**
3682 * Write to guest physical memory referenced by GC pointer.
3683 *
3684 * This function uses the current CR3/CR0/CR4 of the guest and will
3685 * respect access handlers and set dirty and accessed bits.
3686 *
3687 * @returns Strict VBox status, see PGMPhysWrite for details.
3688 * @retval VERR_PAGE_TABLE_NOT_PRESENT if there is no page mapped at the
3689 * specified virtual address.
3690 *
3691 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3692 * @param GCPtrDst The destination address (GC pointer).
3693 * @param pvSrc The source address.
3694 * @param cb The number of bytes to write.
3695 * @param enmOrigin Who is calling.
3696 */
3697VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin)
3698{
3699 RTGCPHYS GCPhys;
3700 uint64_t fFlags;
3701 int rc;
3702 PVM pVM = pVCpu->CTX_SUFF(pVM);
3703 VMCPU_ASSERT_EMT(pVCpu);
3704
3705 /*
3706 * Anything to do?
3707 */
3708 if (!cb)
3709 return VINF_SUCCESS;
3710
3711 LogFlow(("PGMPhysWriteGCPtr: %RGv %zu\n", GCPtrDst, cb));
3712
3713 /*
3714 * Optimize writes within a single page.
3715 */
3716 if (((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
3717 {
3718 /* Convert virtual to physical address + flags */
3719 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrDst, &fFlags, &GCPhys);
3720 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrDst), rc);
3721 GCPhys |= (RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK;
3722
3723 /* Mention when we ignore X86_PTE_RW... */
3724 if (!(fFlags & X86_PTE_RW))
3725 Log(("PGMPhysWriteGCPtr: Writing to RO page %RGv %#x\n", GCPtrDst, cb));
3726
3727 /* Mark the guest page as accessed and dirty if necessary. */
3728 if ((fFlags & (X86_PTE_A | X86_PTE_D)) != (X86_PTE_A | X86_PTE_D))
3729 {
3730 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
3731 AssertRC(rc);
3732 }
3733
3734 return PGMPhysWrite(pVM, GCPhys, pvSrc, cb, enmOrigin);
3735 }
3736
3737 /*
3738 * Page by page.
3739 */
3740 for (;;)
3741 {
3742 /* Convert virtual to physical address + flags */
3743 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrDst, &fFlags, &GCPhys);
3744 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrDst), rc);
3745 GCPhys |= (RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK;
3746
3747 /* Mention when we ignore X86_PTE_RW... */
3748 if (!(fFlags & X86_PTE_RW))
3749 Log(("PGMPhysWriteGCPtr: Writing to RO page %RGv %#x\n", GCPtrDst, cb));
3750
3751 /* Mark the guest page as accessed and dirty if necessary. */
3752 if ((fFlags & (X86_PTE_A | X86_PTE_D)) != (X86_PTE_A | X86_PTE_D))
3753 {
3754 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
3755 AssertRC(rc);
3756 }
3757
3758 /* copy */
3759 size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
3760 if (cbWrite < cb)
3761 {
3762 VBOXSTRICTRC rcStrict = PGMPhysWrite(pVM, GCPhys, pvSrc, cbWrite, enmOrigin);
3763 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3764 { /* likely */ }
3765 else
3766 return rcStrict;
3767 }
3768 else /* Last page (cbWrite is PAGE_SIZE, we only need cb!) */
3769 return PGMPhysWrite(pVM, GCPhys, pvSrc, cb, enmOrigin);
3770
3771 /* next */
3772 Assert(cb > cbWrite);
3773 cb -= cbWrite;
3774 pvSrc = (uint8_t *)pvSrc + cbWrite;
3775 GCPtrDst += cbWrite;
3776 }
3777}
3778
3779
3780/**
3781 * Performs a read of guest virtual memory for instruction emulation.
3782 *
3783 * This will check permissions, raise exceptions and update the access bits.
3784 *
3785 * The current implementation will bypass all access handlers. It may later be
3786 * changed to at least respect MMIO.
3787 *
3788 *
3789 * @returns VBox status code suitable to scheduling.
3790 * @retval VINF_SUCCESS if the read was performed successfully.
3791 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
3792 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
3793 *
3794 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3795 * @param pCtxCore The context core.
3796 * @param pvDst Where to put the bytes we've read.
3797 * @param GCPtrSrc The source address.
3798 * @param cb The number of bytes to read. Not more than a page.
3799 *
3800 * @remark This function will dynamically map physical pages in GC. This may unmap
3801 * mappings done by the caller. Be careful!
3802 */
3803VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb)
3804{
3805 PVM pVM = pVCpu->CTX_SUFF(pVM);
3806 Assert(cb <= PAGE_SIZE);
3807 VMCPU_ASSERT_EMT(pVCpu);
3808
3809/** @todo r=bird: This isn't perfect!
3810 * -# It's not checking for reserved bits being 1.
3811 * -# It's not correctly dealing with the access bit.
3812 * -# It's not respecting MMIO memory or any other access handlers.
3813 */
3814 /*
3815 * 1. Translate virtual to physical. This may fault.
3816 * 2. Map the physical address.
3817 * 3. Do the read operation.
3818 * 4. Set access bits if required.
3819 */
3820 int rc;
3821 unsigned cb1 = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
3822 if (cb <= cb1)
3823 {
3824 /*
3825 * Not crossing pages.
3826 */
3827 RTGCPHYS GCPhys;
3828 uint64_t fFlags;
3829 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags, &GCPhys);
3830 if (RT_SUCCESS(rc))
3831 {
3832 /** @todo we should check reserved bits ... */
3833 PGMPAGEMAPLOCK PgMpLck;
3834 void const *pvSrc;
3835 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvSrc, &PgMpLck);
3836 switch (rc)
3837 {
3838 case VINF_SUCCESS:
3839 Log(("PGMPhysInterpretedRead: pvDst=%p pvSrc=%p cb=%d\n", pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb));
3840 memcpy(pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
3841 PGMPhysReleasePageMappingLock(pVM, &PgMpLck);
3842 break;
3843 case VERR_PGM_PHYS_PAGE_RESERVED:
3844 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3845 memset(pvDst, 0xff, cb);
3846 break;
3847 default:
3848 Assert(RT_FAILURE_NP(rc));
3849 return rc;
3850 }
3851
3852 /** @todo access bit emulation isn't 100% correct. */
3853 if (!(fFlags & X86_PTE_A))
3854 {
3855 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3856 AssertRC(rc);
3857 }
3858 return VINF_SUCCESS;
3859 }
3860 }
3861 else
3862 {
3863 /*
3864 * Crosses pages.
3865 */
3866 size_t cb2 = cb - cb1;
3867 uint64_t fFlags1;
3868 RTGCPHYS GCPhys1;
3869 uint64_t fFlags2;
3870 RTGCPHYS GCPhys2;
3871 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags1, &GCPhys1);
3872 if (RT_SUCCESS(rc))
3873 {
3874 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc + cb1, &fFlags2, &GCPhys2);
3875 if (RT_SUCCESS(rc))
3876 {
3877 /** @todo we should check reserved bits ... */
3878 AssertMsgFailed(("cb=%d cb1=%d cb2=%d GCPtrSrc=%RGv\n", cb, cb1, cb2, GCPtrSrc));
3879 PGMPAGEMAPLOCK PgMpLck;
3880 void const *pvSrc1;
3881 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys1, &pvSrc1, &PgMpLck);
3882 switch (rc)
3883 {
3884 case VINF_SUCCESS:
3885 memcpy(pvDst, (uint8_t *)pvSrc1 + (GCPtrSrc & PAGE_OFFSET_MASK), cb1);
3886 PGMPhysReleasePageMappingLock(pVM, &PgMpLck);
3887 break;
3888 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3889 memset(pvDst, 0xff, cb1);
3890 break;
3891 default:
3892 Assert(RT_FAILURE_NP(rc));
3893 return rc;
3894 }
3895
3896 void const *pvSrc2;
3897 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys2, &pvSrc2, &PgMpLck);
3898 switch (rc)
3899 {
3900 case VINF_SUCCESS:
3901 memcpy((uint8_t *)pvDst + cb1, pvSrc2, cb2);
3902 PGMPhysReleasePageMappingLock(pVM, &PgMpLck);
3903 break;
3904 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3905 memset((uint8_t *)pvDst + cb1, 0xff, cb2);
3906 break;
3907 default:
3908 Assert(RT_FAILURE_NP(rc));
3909 return rc;
3910 }
3911
3912 if (!(fFlags1 & X86_PTE_A))
3913 {
3914 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3915 AssertRC(rc);
3916 }
3917 if (!(fFlags2 & X86_PTE_A))
3918 {
3919 rc = PGMGstModifyPage(pVCpu, GCPtrSrc + cb1, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3920 AssertRC(rc);
3921 }
3922 return VINF_SUCCESS;
3923 }
3924 }
3925 }
3926
3927 /*
3928 * Raise a #PF.
3929 */
3930 uint32_t uErr;
3931
3932 /* Get the current privilege level. */
3933 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3934 switch (rc)
3935 {
3936 case VINF_SUCCESS:
3937 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
3938 break;
3939
3940 case VERR_PAGE_NOT_PRESENT:
3941 case VERR_PAGE_TABLE_NOT_PRESENT:
3942 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
3943 break;
3944
3945 default:
3946 AssertMsgFailed(("rc=%Rrc GCPtrSrc=%RGv cb=%#x\n", rc, GCPtrSrc, cb));
3947 return rc;
3948 }
3949 Log(("PGMPhysInterpretedRead: GCPtrSrc=%RGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr));
3950 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc);
3951}
3952
3953
3954/**
3955 * Performs a read of guest virtual memory for instruction emulation.
3956 *
3957 * This will check permissions, raise exceptions and update the access bits.
3958 *
3959 * The current implementation will bypass all access handlers. It may later be
3960 * changed to at least respect MMIO.
3961 *
3962 *
3963 * @returns VBox status code suitable to scheduling.
3964 * @retval VINF_SUCCESS if the read was performed successfully.
3965 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
3966 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
3967 *
3968 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3969 * @param pCtxCore The context core.
3970 * @param pvDst Where to put the bytes we've read.
3971 * @param GCPtrSrc The source address.
3972 * @param cb The number of bytes to read. Not more than a page.
3973 * @param fRaiseTrap If set the trap will be raised on as per spec, if clear
3974 * an appropriate error status will be returned (no
3975 * informational at all).
3976 *
3977 *
3978 * @remarks Takes the PGM lock.
3979 * @remarks A page fault on the 2nd page of the access will be raised without
3980 * writing the bits on the first page since we're ASSUMING that the
3981 * caller is emulating an instruction access.
3982 * @remarks This function will dynamically map physical pages in GC. This may
3983 * unmap mappings done by the caller. Be careful!
3984 */
3985VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb,
3986 bool fRaiseTrap)
3987{
3988 PVM pVM = pVCpu->CTX_SUFF(pVM);
3989 Assert(cb <= PAGE_SIZE);
3990 VMCPU_ASSERT_EMT(pVCpu);
3991
3992 /*
3993 * 1. Translate virtual to physical. This may fault.
3994 * 2. Map the physical address.
3995 * 3. Do the read operation.
3996 * 4. Set access bits if required.
3997 */
3998 int rc;
3999 unsigned cb1 = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
4000 if (cb <= cb1)
4001 {
4002 /*
4003 * Not crossing pages.
4004 */
4005 RTGCPHYS GCPhys;
4006 uint64_t fFlags;
4007 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags, &GCPhys);
4008 if (RT_SUCCESS(rc))
4009 {
4010 if (1) /** @todo we should check reserved bits ... */
4011 {
4012 const void *pvSrc;
4013 PGMPAGEMAPLOCK Lock;
4014 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvSrc, &Lock);
4015 switch (rc)
4016 {
4017 case VINF_SUCCESS:
4018 Log(("PGMPhysInterpretedReadNoHandlers: pvDst=%p pvSrc=%p (%RGv) cb=%d\n",
4019 pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), GCPtrSrc, cb));
4020 memcpy(pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
4021 PGMPhysReleasePageMappingLock(pVM, &Lock);
4022 break;
4023 case VERR_PGM_PHYS_PAGE_RESERVED:
4024 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4025 memset(pvDst, 0xff, cb);
4026 break;
4027 default:
4028 AssertMsgFailed(("%Rrc\n", rc));
4029 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4030 return rc;
4031 }
4032
4033 if (!(fFlags & X86_PTE_A))
4034 {
4035 /** @todo access bit emulation isn't 100% correct. */
4036 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
4037 AssertRC(rc);
4038 }
4039 return VINF_SUCCESS;
4040 }
4041 }
4042 }
4043 else
4044 {
4045 /*
4046 * Crosses pages.
4047 */
4048 size_t cb2 = cb - cb1;
4049 uint64_t fFlags1;
4050 RTGCPHYS GCPhys1;
4051 uint64_t fFlags2;
4052 RTGCPHYS GCPhys2;
4053 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags1, &GCPhys1);
4054 if (RT_SUCCESS(rc))
4055 {
4056 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc + cb1, &fFlags2, &GCPhys2);
4057 if (RT_SUCCESS(rc))
4058 {
4059 if (1) /** @todo we should check reserved bits ... */
4060 {
4061 const void *pvSrc;
4062 PGMPAGEMAPLOCK Lock;
4063 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys1, &pvSrc, &Lock);
4064 switch (rc)
4065 {
4066 case VINF_SUCCESS:
4067 Log(("PGMPhysInterpretedReadNoHandlers: pvDst=%p pvSrc=%p (%RGv) cb=%d [2]\n",
4068 pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), GCPtrSrc, cb1));
4069 memcpy(pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb1);
4070 PGMPhysReleasePageMappingLock(pVM, &Lock);
4071 break;
4072 case VERR_PGM_PHYS_PAGE_RESERVED:
4073 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4074 memset(pvDst, 0xff, cb1);
4075 break;
4076 default:
4077 AssertMsgFailed(("%Rrc\n", rc));
4078 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4079 return rc;
4080 }
4081
4082 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys2, &pvSrc, &Lock);
4083 switch (rc)
4084 {
4085 case VINF_SUCCESS:
4086 memcpy((uint8_t *)pvDst + cb1, pvSrc, cb2);
4087 PGMPhysReleasePageMappingLock(pVM, &Lock);
4088 break;
4089 case VERR_PGM_PHYS_PAGE_RESERVED:
4090 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4091 memset((uint8_t *)pvDst + cb1, 0xff, cb2);
4092 break;
4093 default:
4094 AssertMsgFailed(("%Rrc\n", rc));
4095 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4096 return rc;
4097 }
4098
4099 if (!(fFlags1 & X86_PTE_A))
4100 {
4101 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
4102 AssertRC(rc);
4103 }
4104 if (!(fFlags2 & X86_PTE_A))
4105 {
4106 rc = PGMGstModifyPage(pVCpu, GCPtrSrc + cb1, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
4107 AssertRC(rc);
4108 }
4109 return VINF_SUCCESS;
4110 }
4111 /* sort out which page */
4112 }
4113 else
4114 GCPtrSrc += cb1; /* fault on 2nd page */
4115 }
4116 }
4117
4118 /*
4119 * Raise a #PF if we're allowed to do that.
4120 */
4121 /* Calc the error bits. */
4122 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
4123 uint32_t uErr;
4124 switch (rc)
4125 {
4126 case VINF_SUCCESS:
4127 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
4128 rc = VERR_ACCESS_DENIED;
4129 break;
4130
4131 case VERR_PAGE_NOT_PRESENT:
4132 case VERR_PAGE_TABLE_NOT_PRESENT:
4133 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
4134 break;
4135
4136 default:
4137 AssertMsgFailed(("rc=%Rrc GCPtrSrc=%RGv cb=%#x\n", rc, GCPtrSrc, cb));
4138 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4139 return rc;
4140 }
4141 if (fRaiseTrap)
4142 {
4143 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrSrc, cb, uErr));
4144 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc);
4145 }
4146 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrSrc, cb, uErr));
4147 return rc;
4148}
4149
4150
4151/**
4152 * Performs a write to guest virtual memory for instruction emulation.
4153 *
4154 * This will check permissions, raise exceptions and update the dirty and access
4155 * bits.
4156 *
4157 * @returns VBox status code suitable to scheduling.
4158 * @retval VINF_SUCCESS if the read was performed successfully.
4159 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
4160 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
4161 *
4162 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
4163 * @param pCtxCore The context core.
4164 * @param GCPtrDst The destination address.
4165 * @param pvSrc What to write.
4166 * @param cb The number of bytes to write. Not more than a page.
4167 * @param fRaiseTrap If set the trap will be raised on as per spec, if clear
4168 * an appropriate error status will be returned (no
4169 * informational at all).
4170 *
4171 * @remarks Takes the PGM lock.
4172 * @remarks A page fault on the 2nd page of the access will be raised without
4173 * writing the bits on the first page since we're ASSUMING that the
4174 * caller is emulating an instruction access.
4175 * @remarks This function will dynamically map physical pages in GC. This may
4176 * unmap mappings done by the caller. Be careful!
4177 */
4178VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc,
4179 size_t cb, bool fRaiseTrap)
4180{
4181 Assert(cb <= PAGE_SIZE);
4182 PVM pVM = pVCpu->CTX_SUFF(pVM);
4183 VMCPU_ASSERT_EMT(pVCpu);
4184
4185 /*
4186 * 1. Translate virtual to physical. This may fault.
4187 * 2. Map the physical address.
4188 * 3. Do the write operation.
4189 * 4. Set access bits if required.
4190 */
4191 /** @todo Since this method is frequently used by EMInterpret or IOM
4192 * upon a write fault to an write access monitored page, we can
4193 * reuse the guest page table walking from the \#PF code. */
4194 int rc;
4195 unsigned cb1 = PAGE_SIZE - (GCPtrDst & PAGE_OFFSET_MASK);
4196 if (cb <= cb1)
4197 {
4198 /*
4199 * Not crossing pages.
4200 */
4201 RTGCPHYS GCPhys;
4202 uint64_t fFlags;
4203 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst, &fFlags, &GCPhys);
4204 if (RT_SUCCESS(rc))
4205 {
4206 if ( (fFlags & X86_PTE_RW) /** @todo Also check reserved bits. */
4207 || ( !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP)
4208 && CPUMGetGuestCPL(pVCpu) <= 2) ) /** @todo it's 2, right? Check cpl check below as well. */
4209 {
4210 void *pvDst;
4211 PGMPAGEMAPLOCK Lock;
4212 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys, &pvDst, &Lock);
4213 switch (rc)
4214 {
4215 case VINF_SUCCESS:
4216 Log(("PGMPhysInterpretedWriteNoHandlers: pvDst=%p (%RGv) pvSrc=%p cb=%d\n",
4217 (uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), GCPtrDst, pvSrc, cb));
4218 memcpy((uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), pvSrc, cb);
4219 PGMPhysReleasePageMappingLock(pVM, &Lock);
4220 break;
4221 case VERR_PGM_PHYS_PAGE_RESERVED:
4222 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4223 /* bit bucket */
4224 break;
4225 default:
4226 AssertMsgFailed(("%Rrc\n", rc));
4227 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4228 return rc;
4229 }
4230
4231 if (!(fFlags & (X86_PTE_A | X86_PTE_D)))
4232 {
4233 /** @todo dirty & access bit emulation isn't 100% correct. */
4234 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
4235 AssertRC(rc);
4236 }
4237 return VINF_SUCCESS;
4238 }
4239 rc = VERR_ACCESS_DENIED;
4240 }
4241 }
4242 else
4243 {
4244 /*
4245 * Crosses pages.
4246 */
4247 size_t cb2 = cb - cb1;
4248 uint64_t fFlags1;
4249 RTGCPHYS GCPhys1;
4250 uint64_t fFlags2;
4251 RTGCPHYS GCPhys2;
4252 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst, &fFlags1, &GCPhys1);
4253 if (RT_SUCCESS(rc))
4254 {
4255 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst + cb1, &fFlags2, &GCPhys2);
4256 if (RT_SUCCESS(rc))
4257 {
4258 if ( ( (fFlags1 & X86_PTE_RW) /** @todo Also check reserved bits. */
4259 && (fFlags2 & X86_PTE_RW))
4260 || ( !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP)
4261 && CPUMGetGuestCPL(pVCpu) <= 2) )
4262 {
4263 void *pvDst;
4264 PGMPAGEMAPLOCK Lock;
4265 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys1, &pvDst, &Lock);
4266 switch (rc)
4267 {
4268 case VINF_SUCCESS:
4269 Log(("PGMPhysInterpretedWriteNoHandlers: pvDst=%p (%RGv) pvSrc=%p cb=%d\n",
4270 (uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), GCPtrDst, pvSrc, cb1));
4271 memcpy((uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), pvSrc, cb1);
4272 PGMPhysReleasePageMappingLock(pVM, &Lock);
4273 break;
4274 case VERR_PGM_PHYS_PAGE_RESERVED:
4275 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4276 /* bit bucket */
4277 break;
4278 default:
4279 AssertMsgFailed(("%Rrc\n", rc));
4280 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4281 return rc;
4282 }
4283
4284 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys2, &pvDst, &Lock);
4285 switch (rc)
4286 {
4287 case VINF_SUCCESS:
4288 memcpy(pvDst, (const uint8_t *)pvSrc + cb1, cb2);
4289 PGMPhysReleasePageMappingLock(pVM, &Lock);
4290 break;
4291 case VERR_PGM_PHYS_PAGE_RESERVED:
4292 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
4293 /* bit bucket */
4294 break;
4295 default:
4296 AssertMsgFailed(("%Rrc\n", rc));
4297 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4298 return rc;
4299 }
4300
4301 if (!(fFlags1 & (X86_PTE_A | X86_PTE_RW)))
4302 {
4303 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, (X86_PTE_A | X86_PTE_RW), ~(uint64_t)(X86_PTE_A | X86_PTE_RW));
4304 AssertRC(rc);
4305 }
4306 if (!(fFlags2 & (X86_PTE_A | X86_PTE_RW)))
4307 {
4308 rc = PGMGstModifyPage(pVCpu, GCPtrDst + cb1, 1, (X86_PTE_A | X86_PTE_RW), ~(uint64_t)(X86_PTE_A | X86_PTE_RW));
4309 AssertRC(rc);
4310 }
4311 return VINF_SUCCESS;
4312 }
4313 if ((fFlags1 & (X86_PTE_RW)) == X86_PTE_RW)
4314 GCPtrDst += cb1; /* fault on the 2nd page. */
4315 rc = VERR_ACCESS_DENIED;
4316 }
4317 else
4318 GCPtrDst += cb1; /* fault on the 2nd page. */
4319 }
4320 }
4321
4322 /*
4323 * Raise a #PF if we're allowed to do that.
4324 */
4325 /* Calc the error bits. */
4326 uint32_t uErr;
4327 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
4328 switch (rc)
4329 {
4330 case VINF_SUCCESS:
4331 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
4332 rc = VERR_ACCESS_DENIED;
4333 break;
4334
4335 case VERR_ACCESS_DENIED:
4336 uErr = (cpl >= 2) ? X86_TRAP_PF_RW | X86_TRAP_PF_US : X86_TRAP_PF_RW;
4337 break;
4338
4339 case VERR_PAGE_NOT_PRESENT:
4340 case VERR_PAGE_TABLE_NOT_PRESENT:
4341 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
4342 break;
4343
4344 default:
4345 AssertMsgFailed(("rc=%Rrc GCPtrDst=%RGv cb=%#x\n", rc, GCPtrDst, cb));
4346 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
4347 return rc;
4348 }
4349 if (fRaiseTrap)
4350 {
4351 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrDst, cb, uErr));
4352 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrDst);
4353 }
4354 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrDst, cb, uErr));
4355 return rc;
4356}
4357
4358
4359/**
4360 * Return the page type of the specified physical address.
4361 *
4362 * @returns The page type.
4363 * @param pVM The cross context VM structure.
4364 * @param GCPhys Guest physical address
4365 */
4366VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys)
4367{
4368 pgmLock(pVM);
4369 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4370 PGMPAGETYPE enmPgType = pPage ? (PGMPAGETYPE)PGM_PAGE_GET_TYPE(pPage) : PGMPAGETYPE_INVALID;
4371 pgmUnlock(pVM);
4372
4373 return enmPgType;
4374}
4375
4376
4377
4378
4379/**
4380 * Converts a GC physical address to a HC ring-3 pointer, with some
4381 * additional checks.
4382 *
4383 * @returns VBox status code (no informational statuses).
4384 * @retval VINF_SUCCESS on success.
4385 * @retval VERR_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
4386 * access handler of some kind.
4387 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
4388 * accesses or is odd in any way.
4389 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
4390 *
4391 * @param pVM The cross context VM structure.
4392 * @param pVCpu The cross context virtual CPU structure of the
4393 * calling EMT.
4394 * @param GCPhys The GC physical address to convert. This API mask
4395 * the A20 line when necessary.
4396 * @param fWritable Whether write access is required.
4397 * @param fByPassHandlers Whether to bypass access handlers.
4398 * @param ppv Where to store the pointer corresponding to GCPhys
4399 * on success.
4400 * @param pLock
4401 *
4402 * @remarks This is more or a less a copy of PGMR3PhysTlbGCPhys2Ptr.
4403 * @thread EMT(pVCpu).
4404 */
4405VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers,
4406 void **ppv, PPGMPAGEMAPLOCK pLock)
4407{
4408 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
4409
4410 pgmLock(pVM);
4411
4412 PPGMRAMRANGE pRam;
4413 PPGMPAGE pPage;
4414 int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
4415 if (RT_SUCCESS(rc))
4416 {
4417 if (PGM_PAGE_IS_BALLOONED(pPage))
4418 rc = VERR_PGM_PHYS_TLB_CATCH_WRITE;
4419 else if (PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
4420 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4421 else if ( !PGM_PAGE_HAS_ANY_HANDLERS(pPage)
4422 || (fByPassHandlers && !PGM_PAGE_IS_MMIO(pPage)) )
4423 rc = VINF_SUCCESS;
4424 else
4425 {
4426 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
4427 {
4428 Assert(!fByPassHandlers || PGM_PAGE_IS_MMIO(pPage));
4429 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4430 }
4431 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && fWritable)
4432 {
4433 Assert(!fByPassHandlers);
4434 rc = VERR_PGM_PHYS_TLB_CATCH_WRITE;
4435 }
4436 }
4437 if (RT_SUCCESS(rc))
4438 {
4439 int rc2;
4440
4441 /* Make sure what we return is writable. */
4442 if (fWritable)
4443 switch (PGM_PAGE_GET_STATE(pPage))
4444 {
4445 case PGM_PAGE_STATE_ALLOCATED:
4446 break;
4447 case PGM_PAGE_STATE_BALLOONED:
4448 AssertFailed();
4449 case PGM_PAGE_STATE_ZERO:
4450 case PGM_PAGE_STATE_SHARED:
4451 case PGM_PAGE_STATE_WRITE_MONITORED:
4452 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
4453 AssertLogRelRCReturn(rc2, rc2);
4454 break;
4455 }
4456
4457#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4458 void *pv;
4459 rc = pgmRZDynMapHCPageInlined(pVCpu,
4460 PGM_PAGE_GET_HCPHYS(pPage),
4461 &pv
4462 RTLOG_COMMA_SRC_POS);
4463 if (RT_FAILURE(rc))
4464 return rc;
4465 *ppv = (void *)((uintptr_t)pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
4466 pLock->pvPage = pv;
4467 pLock->pVCpu = pVCpu;
4468
4469#else
4470 /* Get a ring-3 mapping of the address. */
4471 PPGMPAGER3MAPTLBE pTlbe;
4472 rc2 = pgmPhysPageQueryTlbeWithPage(pVM, pPage, GCPhys, &pTlbe);
4473 AssertLogRelRCReturn(rc2, rc2);
4474
4475 /* Lock it and calculate the address. */
4476 if (fWritable)
4477 pgmPhysPageMapLockForWriting(pVM, pPage, pTlbe, pLock);
4478 else
4479 pgmPhysPageMapLockForReading(pVM, pPage, pTlbe, pLock);
4480 *ppv = (void *)((uintptr_t)pTlbe->pv | (uintptr_t)(GCPhys & PAGE_OFFSET_MASK));
4481#endif
4482
4483 Log6(("PGMPhysIemGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
4484 }
4485 else
4486 Log6(("PGMPhysIemGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
4487
4488 /* else: handler catching all access, no pointer returned. */
4489 }
4490 else
4491 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
4492
4493 pgmUnlock(pVM);
4494 return rc;
4495}
4496
4497
4498/**
4499 * Checks if the give GCPhys page requires special handling for the given access
4500 * because it's MMIO or otherwise monitored.
4501 *
4502 * @returns VBox status code (no informational statuses).
4503 * @retval VINF_SUCCESS on success.
4504 * @retval VERR_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
4505 * access handler of some kind.
4506 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
4507 * accesses or is odd in any way.
4508 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
4509 *
4510 * @param pVM The cross context VM structure.
4511 * @param GCPhys The GC physical address to convert. Since this is
4512 * only used for filling the REM TLB, the A20 mask must
4513 * be applied before calling this API.
4514 * @param fWritable Whether write access is required.
4515 * @param fByPassHandlers Whether to bypass access handlers.
4516 *
4517 * @remarks This is a watered down version PGMPhysIemGCPhys2Ptr and really just
4518 * a stop gap thing that should be removed once there is a better TLB
4519 * for virtual address accesses.
4520 */
4521VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers)
4522{
4523 pgmLock(pVM);
4524 PGM_A20_ASSERT_MASKED(VMMGetCpu(pVM), GCPhys);
4525
4526 PPGMRAMRANGE pRam;
4527 PPGMPAGE pPage;
4528 int rc = pgmPhysGetPageAndRangeEx(pVM, GCPhys, &pPage, &pRam);
4529 if (RT_SUCCESS(rc))
4530 {
4531 if (PGM_PAGE_IS_BALLOONED(pPage))
4532 rc = VERR_PGM_PHYS_TLB_CATCH_WRITE;
4533 else if (PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(pPage))
4534 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4535 else if ( !PGM_PAGE_HAS_ANY_HANDLERS(pPage)
4536 || (fByPassHandlers && !PGM_PAGE_IS_MMIO(pPage)) )
4537 rc = VINF_SUCCESS;
4538 else
4539 {
4540 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
4541 {
4542 Assert(!fByPassHandlers || PGM_PAGE_IS_MMIO(pPage));
4543 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
4544 }
4545 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && fWritable)
4546 {
4547 Assert(!fByPassHandlers);
4548 rc = VERR_PGM_PHYS_TLB_CATCH_WRITE;
4549 }
4550 }
4551 }
4552
4553 pgmUnlock(pVM);
4554 return rc;
4555}
4556
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