VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp@ 24442

Last change on this file since 24442 was 23844, checked in by vboxsync, 15 years ago

Do not call ModifyPage handler with non-page aligned sizes.

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1/* $Id: PGMAllPhys.cpp 23844 2009-10-19 08:21:09Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM_PHYS
26#include <VBox/pgm.h>
27#include <VBox/trpm.h>
28#include <VBox/vmm.h>
29#include <VBox/iom.h>
30#include <VBox/em.h>
31#include <VBox/rem.h>
32#include "PGMInternal.h"
33#include <VBox/vm.h>
34#include <VBox/param.h>
35#include <VBox/err.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38#include <iprt/asm.h>
39#include <VBox/log.h>
40#ifdef IN_RING3
41# include <iprt/thread.h>
42#endif
43
44
45
46#ifndef IN_RING3
47
48/**
49 * \#PF Handler callback for Guest ROM range write access.
50 * We simply ignore the writes or fall back to the recompiler if we don't support the instruction.
51 *
52 * @returns VBox status code (appropritate for trap handling and GC return).
53 * @param pVM VM Handle.
54 * @param uErrorCode CPU Error code.
55 * @param pRegFrame Trap register frame.
56 * @param pvFault The fault address (cr2).
57 * @param GCPhysFault The GC physical address corresponding to pvFault.
58 * @param pvUser User argument. Pointer to the ROM range structure.
59 */
60VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
61{
62 int rc;
63 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
64 uint32_t iPage = (GCPhysFault - pRom->GCPhys) >> PAGE_SHIFT;
65 PVMCPU pVCpu = VMMGetCpu(pVM);
66
67 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
68 switch (pRom->aPages[iPage].enmProt)
69 {
70 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
71 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
72 {
73 /*
74 * If it's a simple instruction which doesn't change the cpu state
75 * we will simply skip it. Otherwise we'll have to defer it to REM.
76 */
77 uint32_t cbOp;
78 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
79 rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, &cbOp);
80 if ( RT_SUCCESS(rc)
81 && pDis->mode == CPUMODE_32BIT /** @todo why does this matter? */
82 && !(pDis->prefix & (PREFIX_REPNE | PREFIX_REP | PREFIX_SEG)))
83 {
84 switch (pDis->opcode)
85 {
86 /** @todo Find other instructions we can safely skip, possibly
87 * adding this kind of detection to DIS or EM. */
88 case OP_MOV:
89 pRegFrame->rip += cbOp;
90 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZGuestROMWriteHandled);
91 return VINF_SUCCESS;
92 }
93 }
94 else if (RT_UNLIKELY(rc == VERR_INTERNAL_ERROR))
95 return rc;
96 break;
97 }
98
99 case PGMROMPROT_READ_RAM_WRITE_RAM:
100 pRom->aPages[iPage].LiveSave.fWrittenTo = true;
101 rc = PGMHandlerPhysicalPageTempOff(pVM, pRom->GCPhys, GCPhysFault & X86_PTE_PG_MASK);
102 AssertRC(rc);
103 break; /** @todo Must edit the shadow PT and restart the instruction, not use the interpreter! */
104
105 case PGMROMPROT_READ_ROM_WRITE_RAM:
106 /* Handle it in ring-3 because it's *way* easier there. */
107 pRom->aPages[iPage].LiveSave.fWrittenTo = true;
108 break;
109
110 default:
111 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhysFault=%RGp\n",
112 pRom->aPages[iPage].enmProt, iPage, GCPhysFault),
113 VERR_INTERNAL_ERROR);
114 }
115
116 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZGuestROMWriteUnhandled);
117 return VINF_EM_RAW_EMULATE_INSTR;
118}
119
120#endif /* IN_RING3 */
121
122/**
123 * Checks if Address Gate 20 is enabled or not.
124 *
125 * @returns true if enabled.
126 * @returns false if disabled.
127 * @param pVCpu VMCPU handle.
128 */
129VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu)
130{
131 LogFlow(("PGMPhysIsA20Enabled %d\n", pVCpu->pgm.s.fA20Enabled));
132 return pVCpu->pgm.s.fA20Enabled;
133}
134
135
136/**
137 * Validates a GC physical address.
138 *
139 * @returns true if valid.
140 * @returns false if invalid.
141 * @param pVM The VM handle.
142 * @param GCPhys The physical address to validate.
143 */
144VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys)
145{
146 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
147 return pPage != NULL;
148}
149
150
151/**
152 * Checks if a GC physical address is a normal page,
153 * i.e. not ROM, MMIO or reserved.
154 *
155 * @returns true if normal.
156 * @returns false if invalid, ROM, MMIO or reserved page.
157 * @param pVM The VM handle.
158 * @param GCPhys The physical address to check.
159 */
160VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys)
161{
162 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
163 return pPage
164 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM;
165}
166
167
168/**
169 * Converts a GC physical address to a HC physical address.
170 *
171 * @returns VINF_SUCCESS on success.
172 * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
173 * page but has no physical backing.
174 * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
175 * GC physical address.
176 *
177 * @param pVM The VM handle.
178 * @param GCPhys The GC physical address to convert.
179 * @param pHCPhys Where to store the HC physical address on success.
180 */
181VMMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
182{
183 pgmLock(pVM);
184 PPGMPAGE pPage;
185 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
186 if (RT_SUCCESS(rc))
187 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
188 pgmUnlock(pVM);
189 return rc;
190}
191
192
193/**
194 * Invalidates the GC page mapping TLB.
195 *
196 * @param pVM The VM handle.
197 */
198VMMDECL(void) PGMPhysInvalidatePageGCMapTLB(PVM pVM)
199{
200 /* later */
201 NOREF(pVM);
202}
203
204
205/**
206 * Invalidates the ring-0 page mapping TLB.
207 *
208 * @param pVM The VM handle.
209 */
210VMMDECL(void) PGMPhysInvalidatePageR0MapTLB(PVM pVM)
211{
212 PGMPhysInvalidatePageR3MapTLB(pVM);
213}
214
215
216/**
217 * Invalidates the ring-3 page mapping TLB.
218 *
219 * @param pVM The VM handle.
220 */
221VMMDECL(void) PGMPhysInvalidatePageR3MapTLB(PVM pVM)
222{
223 pgmLock(pVM);
224 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
225 {
226 pVM->pgm.s.PhysTlbHC.aEntries[i].GCPhys = NIL_RTGCPHYS;
227 pVM->pgm.s.PhysTlbHC.aEntries[i].pPage = 0;
228 pVM->pgm.s.PhysTlbHC.aEntries[i].pMap = 0;
229 pVM->pgm.s.PhysTlbHC.aEntries[i].pv = 0;
230 }
231 pgmUnlock(pVM);
232}
233
234
235/**
236 * Makes sure that there is at least one handy page ready for use.
237 *
238 * This will also take the appropriate actions when reaching water-marks.
239 *
240 * @returns VBox status code.
241 * @retval VINF_SUCCESS on success.
242 * @retval VERR_EM_NO_MEMORY if we're really out of memory.
243 *
244 * @param pVM The VM handle.
245 *
246 * @remarks Must be called from within the PGM critical section. It may
247 * nip back to ring-3/0 in some cases.
248 */
249static int pgmPhysEnsureHandyPage(PVM pVM)
250{
251 AssertMsg(pVM->pgm.s.cHandyPages <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d\n", pVM->pgm.s.cHandyPages));
252
253 /*
254 * Do we need to do anything special?
255 */
256#ifdef IN_RING3
257 if (pVM->pgm.s.cHandyPages <= RT_MAX(PGM_HANDY_PAGES_SET_FF, PGM_HANDY_PAGES_R3_ALLOC))
258#else
259 if (pVM->pgm.s.cHandyPages <= RT_MAX(PGM_HANDY_PAGES_SET_FF, PGM_HANDY_PAGES_RZ_TO_R3))
260#endif
261 {
262 /*
263 * Allocate pages only if we're out of them, or in ring-3, almost out.
264 */
265#ifdef IN_RING3
266 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_R3_ALLOC)
267#else
268 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_RZ_ALLOC)
269#endif
270 {
271 Log(("PGM: cHandyPages=%u out of %u -> allocate more; VM_FF_PGM_NO_MEMORY=%RTbool\n",
272 pVM->pgm.s.cHandyPages, RT_ELEMENTS(pVM->pgm.s.aHandyPages), VM_FF_ISSET(pVM, VM_FF_PGM_NO_MEMORY) ));
273#ifdef IN_RING3
274 int rc = PGMR3PhysAllocateHandyPages(pVM);
275#else
276 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES, 0);
277#endif
278 if (RT_UNLIKELY(rc != VINF_SUCCESS))
279 {
280 if (RT_FAILURE(rc))
281 return rc;
282 AssertMsgReturn(rc == VINF_EM_NO_MEMORY, ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
283 if (!pVM->pgm.s.cHandyPages)
284 {
285 LogRel(("PGM: no more handy pages!\n"));
286 return VERR_EM_NO_MEMORY;
287 }
288 Assert(VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES));
289 Assert(VM_FF_ISSET(pVM, VM_FF_PGM_NO_MEMORY));
290#ifdef IN_RING3
291 REMR3NotifyFF(pVM);
292#else
293 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TO_R3); /* paranoia */
294#endif
295 }
296 AssertMsgReturn( pVM->pgm.s.cHandyPages > 0
297 && pVM->pgm.s.cHandyPages <= RT_ELEMENTS(pVM->pgm.s.aHandyPages),
298 ("%u\n", pVM->pgm.s.cHandyPages),
299 VERR_INTERNAL_ERROR);
300 }
301 else
302 {
303 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_SET_FF)
304 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
305#ifndef IN_RING3
306 if (pVM->pgm.s.cHandyPages <= PGM_HANDY_PAGES_RZ_TO_R3)
307 {
308 Log(("PGM: VM_FF_TO_R3 - cHandyPages=%u out of %u\n", pVM->pgm.s.cHandyPages, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
309 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TO_R3);
310 }
311#endif
312 }
313 }
314
315 return VINF_SUCCESS;
316}
317
318
319/**
320 * Replace a zero or shared page with new page that we can write to.
321 *
322 * @returns The following VBox status codes.
323 * @retval VINF_SUCCESS on success, pPage is modified.
324 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
325 * @retval VERR_EM_NO_MEMORY if we're totally out of memory.
326 *
327 * @todo Propagate VERR_EM_NO_MEMORY up the call tree.
328 *
329 * @param pVM The VM address.
330 * @param pPage The physical page tracking structure. This will
331 * be modified on success.
332 * @param GCPhys The address of the page.
333 *
334 * @remarks Must be called from within the PGM critical section. It may
335 * nip back to ring-3/0 in some cases.
336 *
337 * @remarks This function shouldn't really fail, however if it does
338 * it probably means we've screwed up the size of handy pages and/or
339 * the low-water mark. Or, that some device I/O is causing a lot of
340 * pages to be allocated while while the host is in a low-memory
341 * condition. This latter should be handled elsewhere and in a more
342 * controlled manner, it's on the @bugref{3170} todo list...
343 */
344int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
345{
346 LogFlow(("pgmPhysAllocPage: %R[pgmpage] %RGp\n", pPage, GCPhys));
347
348 /*
349 * Prereqs.
350 */
351 Assert(PGMIsLocked(pVM));
352 AssertMsg(PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_SHARED(pPage), ("%R[pgmpage] %RGp\n", pPage, GCPhys));
353 Assert(!PGM_PAGE_IS_MMIO(pPage));
354
355
356 /*
357 * Flush any shadow page table mappings of the page.
358 * When VBOX_WITH_NEW_LAZY_PAGE_ALLOC isn't defined, there shouldn't be any.
359 */
360 bool fFlushTLBs = false;
361 int rc = pgmPoolTrackFlushGCPhys(pVM, pPage, &fFlushTLBs);
362 AssertMsgReturn(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc), RT_FAILURE(rc) ? rc : VERR_IPE_UNEXPECTED_STATUS);
363
364 /*
365 * Ensure that we've got a page handy, take it and use it.
366 */
367 int rc2 = pgmPhysEnsureHandyPage(pVM);
368 if (RT_FAILURE(rc2))
369 {
370 if (fFlushTLBs)
371 PGM_INVL_ALL_VCPU_TLBS(pVM);
372 Assert(rc2 == VERR_EM_NO_MEMORY);
373 return rc2;
374 }
375 /* re-assert preconditions since pgmPhysEnsureHandyPage may do a context switch. */
376 Assert(PGMIsLocked(pVM));
377 AssertMsg(PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_SHARED(pPage), ("%R[pgmpage] %RGp\n", pPage, GCPhys));
378 Assert(!PGM_PAGE_IS_MMIO(pPage));
379
380 uint32_t iHandyPage = --pVM->pgm.s.cHandyPages;
381 AssertMsg(iHandyPage < RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d\n", iHandyPage));
382 Assert(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys != NIL_RTHCPHYS);
383 Assert(!(pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys & ~X86_PTE_PAE_PG_MASK));
384 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idPage != NIL_GMM_PAGEID);
385 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage == NIL_GMM_PAGEID);
386
387 /*
388 * There are one or two action to be taken the next time we allocate handy pages:
389 * - Tell the GMM (global memory manager) what the page is being used for.
390 * (Speeds up replacement operations - sharing and defragmenting.)
391 * - If the current backing is shared, it must be freed.
392 */
393 const RTHCPHYS HCPhys = pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys;
394 pVM->pgm.s.aHandyPages[iHandyPage].HCPhysGCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
395
396 if (PGM_PAGE_IS_SHARED(pPage))
397 {
398 pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage = PGM_PAGE_GET_PAGEID(pPage);
399 Assert(PGM_PAGE_GET_PAGEID(pPage) != NIL_GMM_PAGEID);
400 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
401
402 Log2(("PGM: Replaced shared page %#x at %RGp with %#x / %RHp\n", PGM_PAGE_GET_PAGEID(pPage),
403 GCPhys, pVM->pgm.s.aHandyPages[iHandyPage].idPage, HCPhys));
404 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageReplaceShared));
405 pVM->pgm.s.cSharedPages--;
406 AssertMsgFailed(("TODO: copy shared page content")); /** @todo err.. what about copying the page content? */
407 }
408 else
409 {
410 Log2(("PGM: Replaced zero page %RGp with %#x / %RHp\n", GCPhys, pVM->pgm.s.aHandyPages[iHandyPage].idPage, HCPhys));
411 STAM_COUNTER_INC(&pVM->pgm.s.StatRZPageReplaceZero);
412 pVM->pgm.s.cZeroPages--;
413 Assert(pVM->pgm.s.aHandyPages[iHandyPage].idSharedPage == NIL_GMM_PAGEID);
414 }
415
416 /*
417 * Do the PGMPAGE modifications.
418 */
419 pVM->pgm.s.cPrivatePages++;
420 PGM_PAGE_SET_HCPHYS(pPage, HCPhys);
421 PGM_PAGE_SET_PAGEID(pPage, pVM->pgm.s.aHandyPages[iHandyPage].idPage);
422 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
423
424 if ( fFlushTLBs
425 && rc != VINF_PGM_GCPHYS_ALIASED)
426 PGM_INVL_ALL_VCPU_TLBS(pVM);
427 return rc;
428}
429
430
431/**
432 * Deal with pages that are not writable, i.e. not in the ALLOCATED state.
433 *
434 * @returns VBox strict status code.
435 * @retval VINF_SUCCESS on success.
436 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
437 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
438 *
439 * @param pVM The VM address.
440 * @param pPage The physical page tracking structure.
441 * @param GCPhys The address of the page.
442 *
443 * @remarks Called from within the PGM critical section.
444 */
445int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
446{
447 switch (PGM_PAGE_GET_STATE(pPage))
448 {
449 case PGM_PAGE_STATE_WRITE_MONITORED:
450 PGM_PAGE_SET_WRITTEN_TO(pPage);
451 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
452 Assert(pVM->pgm.s.cMonitoredPages > 0);
453 pVM->pgm.s.cMonitoredPages--;
454 pVM->pgm.s.cWrittenToPages++;
455 /* fall thru */
456 default: /* to shut up GCC */
457 case PGM_PAGE_STATE_ALLOCATED:
458 return VINF_SUCCESS;
459
460 /*
461 * Zero pages can be dummy pages for MMIO or reserved memory,
462 * so we need to check the flags before joining cause with
463 * shared page replacement.
464 */
465 case PGM_PAGE_STATE_ZERO:
466 if (PGM_PAGE_IS_MMIO(pPage))
467 return VERR_PGM_PHYS_PAGE_RESERVED;
468 /* fall thru */
469 case PGM_PAGE_STATE_SHARED:
470 return pgmPhysAllocPage(pVM, pPage, GCPhys);
471 }
472}
473
474
475/**
476 * Wrapper for pgmPhysPageMakeWritable which enters the critsect.
477 *
478 * @returns VBox strict status code.
479 * @retval VINF_SUCCESS on success.
480 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
481 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
482 *
483 * @param pVM The VM address.
484 * @param pPage The physical page tracking structure.
485 * @param GCPhys The address of the page.
486 */
487int pgmPhysPageMakeWritableUnlocked(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
488{
489 int rc = pgmLock(pVM);
490 if (RT_SUCCESS(rc))
491 {
492 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
493 pgmUnlock(pVM);
494 }
495 return rc;
496}
497
498
499/**
500 * Internal usage: Map the page specified by its GMM ID.
501 *
502 * This is similar to pgmPhysPageMap
503 *
504 * @returns VBox status code.
505 *
506 * @param pVM The VM handle.
507 * @param idPage The Page ID.
508 * @param HCPhys The physical address (for RC).
509 * @param ppv Where to store the mapping address.
510 *
511 * @remarks Called from within the PGM critical section. The mapping is only
512 * valid while your inside this section.
513 */
514int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv)
515{
516 /*
517 * Validation.
518 */
519 Assert(PGMIsLocked(pVM));
520 AssertReturn(HCPhys && !(HCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
521 const uint32_t idChunk = idPage >> GMM_CHUNKID_SHIFT;
522 AssertReturn(idChunk != NIL_GMM_CHUNKID, VERR_INVALID_PARAMETER);
523
524#ifdef IN_RC
525 /*
526 * Map it by HCPhys.
527 */
528 return PGMDynMapHCPage(pVM, HCPhys, ppv);
529
530#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
531 /*
532 * Map it by HCPhys.
533 */
534 return pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
535
536#else
537 /*
538 * Find/make Chunk TLB entry for the mapping chunk.
539 */
540 PPGMCHUNKR3MAP pMap;
541 PPGMCHUNKR3MAPTLBE pTlbe = &pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(idChunk)];
542 if (pTlbe->idChunk == idChunk)
543 {
544 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,ChunkR3MapTlbHits));
545 pMap = pTlbe->pChunk;
546 }
547 else
548 {
549 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,ChunkR3MapTlbMisses));
550
551 /*
552 * Find the chunk, map it if necessary.
553 */
554 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
555 if (!pMap)
556 {
557# ifdef IN_RING0
558 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_MAP_CHUNK, idChunk);
559 AssertRCReturn(rc, rc);
560 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
561 Assert(pMap);
562# else
563 int rc = pgmR3PhysChunkMap(pVM, idChunk, &pMap);
564 if (RT_FAILURE(rc))
565 return rc;
566# endif
567 }
568
569 /*
570 * Enter it into the Chunk TLB.
571 */
572 pTlbe->idChunk = idChunk;
573 pTlbe->pChunk = pMap;
574 pMap->iAge = 0;
575 }
576
577 *ppv = (uint8_t *)pMap->pv + ((idPage &GMM_PAGEID_IDX_MASK) << PAGE_SHIFT);
578 return VINF_SUCCESS;
579#endif
580}
581
582
583/**
584 * Maps a page into the current virtual address space so it can be accessed.
585 *
586 * @returns VBox status code.
587 * @retval VINF_SUCCESS on success.
588 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
589 *
590 * @param pVM The VM address.
591 * @param pPage The physical page tracking structure.
592 * @param GCPhys The address of the page.
593 * @param ppMap Where to store the address of the mapping tracking structure.
594 * @param ppv Where to store the mapping address of the page. The page
595 * offset is masked off!
596 *
597 * @remarks Called from within the PGM critical section.
598 */
599static int pgmPhysPageMapCommon(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv)
600{
601 Assert(PGMIsLocked(pVM));
602
603#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
604 /*
605 * Just some sketchy GC/R0-darwin code.
606 */
607 *ppMap = NULL;
608 RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
609 Assert(HCPhys != pVM->pgm.s.HCPhysZeroPg);
610# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
611 pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
612# else
613 PGMDynMapHCPage(pVM, HCPhys, ppv);
614# endif
615 return VINF_SUCCESS;
616
617#else /* IN_RING3 || IN_RING0 */
618
619
620 /*
621 * Special case: ZERO and MMIO2 pages.
622 */
623 const uint32_t idChunk = PGM_PAGE_GET_CHUNKID(pPage);
624 if (idChunk == NIL_GMM_CHUNKID)
625 {
626 AssertMsgReturn(PGM_PAGE_GET_PAGEID(pPage) == NIL_GMM_PAGEID, ("pPage=%R[pgmpage]\n", pPage), VERR_INTERNAL_ERROR_2);
627 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2)
628 {
629 /* Lookup the MMIO2 range and use pvR3 to calc the address. */
630 PPGMRAMRANGE pRam = pgmPhysGetRange(&pVM->pgm.s, GCPhys);
631 AssertMsgReturn(pRam || !pRam->pvR3, ("pRam=%p pPage=%R[pgmpage]\n", pRam, pPage), VERR_INTERNAL_ERROR_2);
632 *ppv = (void *)((uintptr_t)pRam->pvR3 + (GCPhys - pRam->GCPhys));
633 }
634 else if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
635 {
636 /** @todo deal with aliased MMIO2 pages somehow...
637 * One solution would be to seed MMIO2 pages to GMM and get unique Page IDs for
638 * them, that would also avoid this mess. It would actually be kind of
639 * elegant... */
640 AssertLogRelMsgFailedReturn(("%RGp\n", GCPhys), VERR_INTERNAL_ERROR_3);
641 }
642 else
643 {
644 /** @todo handle MMIO2 */
645 AssertMsgReturn(PGM_PAGE_IS_ZERO(pPage), ("pPage=%R[pgmpage]\n", pPage), VERR_INTERNAL_ERROR_2);
646 AssertMsgReturn(PGM_PAGE_GET_HCPHYS(pPage) == pVM->pgm.s.HCPhysZeroPg,
647 ("pPage=%R[pgmpage]\n", pPage),
648 VERR_INTERNAL_ERROR_2);
649 *ppv = pVM->pgm.s.CTXALLSUFF(pvZeroPg);
650 }
651 *ppMap = NULL;
652 return VINF_SUCCESS;
653 }
654
655 /*
656 * Find/make Chunk TLB entry for the mapping chunk.
657 */
658 PPGMCHUNKR3MAP pMap;
659 PPGMCHUNKR3MAPTLBE pTlbe = &pVM->pgm.s.ChunkR3Map.Tlb.aEntries[PGM_CHUNKR3MAPTLB_IDX(idChunk)];
660 if (pTlbe->idChunk == idChunk)
661 {
662 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,ChunkR3MapTlbHits));
663 pMap = pTlbe->pChunk;
664 }
665 else
666 {
667 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,ChunkR3MapTlbMisses));
668
669 /*
670 * Find the chunk, map it if necessary.
671 */
672 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
673 if (!pMap)
674 {
675#ifdef IN_RING0
676 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_MAP_CHUNK, idChunk);
677 AssertRCReturn(rc, rc);
678 pMap = (PPGMCHUNKR3MAP)RTAvlU32Get(&pVM->pgm.s.ChunkR3Map.pTree, idChunk);
679 Assert(pMap);
680#else
681 int rc = pgmR3PhysChunkMap(pVM, idChunk, &pMap);
682 if (RT_FAILURE(rc))
683 return rc;
684#endif
685 }
686
687 /*
688 * Enter it into the Chunk TLB.
689 */
690 pTlbe->idChunk = idChunk;
691 pTlbe->pChunk = pMap;
692 pMap->iAge = 0;
693 }
694
695 *ppv = (uint8_t *)pMap->pv + (PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) << PAGE_SHIFT);
696 *ppMap = pMap;
697 return VINF_SUCCESS;
698#endif /* IN_RING3 */
699}
700
701
702/**
703 * Combination of pgmPhysPageMakeWritable and pgmPhysPageMapWritable.
704 *
705 * This is typically used is paths where we cannot use the TLB methods (like ROM
706 * pages) or where there is no point in using them since we won't get many hits.
707 *
708 * @returns VBox strict status code.
709 * @retval VINF_SUCCESS on success.
710 * @retval VINF_PGM_SYNC_CR3 on success and a page pool flush is pending.
711 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
712 *
713 * @param pVM The VM address.
714 * @param pPage The physical page tracking structure.
715 * @param GCPhys The address of the page.
716 * @param ppv Where to store the mapping address of the page. The page
717 * offset is masked off!
718 *
719 * @remarks Called from within the PGM critical section. The mapping is only
720 * valid while your inside this section.
721 */
722int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
723{
724 int rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
725 if (RT_SUCCESS(rc))
726 {
727 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
728 PPGMPAGEMAP pMapIgnore;
729 int rc2 = pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, ppv);
730 if (RT_FAILURE(rc2)) /* preserve rc */
731 rc = rc2;
732 }
733 return rc;
734}
735
736
737/**
738 * Maps a page into the current virtual address space so it can be accessed for
739 * both writing and reading.
740 *
741 * This is typically used is paths where we cannot use the TLB methods (like ROM
742 * pages) or where there is no point in using them since we won't get many hits.
743 *
744 * @returns VBox status code.
745 * @retval VINF_SUCCESS on success.
746 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
747 *
748 * @param pVM The VM address.
749 * @param pPage The physical page tracking structure. Must be in the
750 * allocated state.
751 * @param GCPhys The address of the page.
752 * @param ppv Where to store the mapping address of the page. The page
753 * offset is masked off!
754 *
755 * @remarks Called from within the PGM critical section. The mapping is only
756 * valid while your inside this section.
757 */
758int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
759{
760 Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
761 PPGMPAGEMAP pMapIgnore;
762 return pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, ppv);
763}
764
765
766/**
767 * Maps a page into the current virtual address space so it can be accessed for
768 * reading.
769 *
770 * This is typically used is paths where we cannot use the TLB methods (like ROM
771 * pages) or where there is no point in using them since we won't get many hits.
772 *
773 * @returns VBox status code.
774 * @retval VINF_SUCCESS on success.
775 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
776 *
777 * @param pVM The VM address.
778 * @param pPage The physical page tracking structure.
779 * @param GCPhys The address of the page.
780 * @param ppv Where to store the mapping address of the page. The page
781 * offset is masked off!
782 *
783 * @remarks Called from within the PGM critical section. The mapping is only
784 * valid while your inside this section.
785 */
786int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv)
787{
788 PPGMPAGEMAP pMapIgnore;
789 return pgmPhysPageMapCommon(pVM, pPage, GCPhys, &pMapIgnore, (void **)ppv);
790}
791
792
793#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
794/**
795 * Load a guest page into the ring-3 physical TLB.
796 *
797 * @returns VBox status code.
798 * @retval VINF_SUCCESS on success
799 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
800 * @param pPGM The PGM instance pointer.
801 * @param GCPhys The guest physical address in question.
802 */
803int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys)
804{
805 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbMisses));
806
807 /*
808 * Find the ram range.
809 * 99.8% of requests are expected to be in the first range.
810 */
811 PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
812 RTGCPHYS off = GCPhys - pRam->GCPhys;
813 if (RT_UNLIKELY(off >= pRam->cb))
814 {
815 do
816 {
817 pRam = pRam->CTX_SUFF(pNext);
818 if (!pRam)
819 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
820 off = GCPhys - pRam->GCPhys;
821 } while (off >= pRam->cb);
822 }
823
824 /*
825 * Map the page.
826 * Make a special case for the zero page as it is kind of special.
827 */
828 PPGMPAGE pPage = &pRam->aPages[off >> PAGE_SHIFT];
829 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
830 if (!PGM_PAGE_IS_ZERO(pPage))
831 {
832 void *pv;
833 PPGMPAGEMAP pMap;
834 int rc = pgmPhysPageMapCommon(PGM2VM(pPGM), pPage, GCPhys, &pMap, &pv);
835 if (RT_FAILURE(rc))
836 return rc;
837 pTlbe->pMap = pMap;
838 pTlbe->pv = pv;
839 }
840 else
841 {
842 Assert(PGM_PAGE_GET_HCPHYS(pPage) == pPGM->HCPhysZeroPg);
843 pTlbe->pMap = NULL;
844 pTlbe->pv = pPGM->CTXALLSUFF(pvZeroPg);
845 }
846 pTlbe->pPage = pPage;
847 return VINF_SUCCESS;
848}
849
850
851/**
852 * Load a guest page into the ring-3 physical TLB.
853 *
854 * @returns VBox status code.
855 * @retval VINF_SUCCESS on success
856 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
857 *
858 * @param pPGM The PGM instance pointer.
859 * @param pPage Pointer to the PGMPAGE structure corresponding to
860 * GCPhys.
861 * @param GCPhys The guest physical address in question.
862 */
863int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys)
864{
865 STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbMisses));
866
867 /*
868 * Map the page.
869 * Make a special case for the zero page as it is kind of special.
870 */
871 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
872 if (!PGM_PAGE_IS_ZERO(pPage))
873 {
874 void *pv;
875 PPGMPAGEMAP pMap;
876 int rc = pgmPhysPageMapCommon(PGM2VM(pPGM), pPage, GCPhys, &pMap, &pv);
877 if (RT_FAILURE(rc))
878 return rc;
879 pTlbe->pMap = pMap;
880 pTlbe->pv = pv;
881 }
882 else
883 {
884 Assert(PGM_PAGE_GET_HCPHYS(pPage) == pPGM->HCPhysZeroPg);
885 pTlbe->pMap = NULL;
886 pTlbe->pv = pPGM->CTXALLSUFF(pvZeroPg);
887 }
888 pTlbe->pPage = pPage;
889 return VINF_SUCCESS;
890}
891#endif /* !IN_RC && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
892
893
894/**
895 * Internal version of PGMPhysGCPhys2CCPtr that expects the caller to
896 * own the PGM lock and therefore not need to lock the mapped page.
897 *
898 * @returns VBox status code.
899 * @retval VINF_SUCCESS on success.
900 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
901 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
902 *
903 * @param pVM The VM handle.
904 * @param GCPhys The guest physical address of the page that should be mapped.
905 * @param pPage Pointer to the PGMPAGE structure for the page.
906 * @param ppv Where to store the address corresponding to GCPhys.
907 *
908 * @internal
909 */
910int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv)
911{
912 int rc;
913 AssertReturn(pPage, VERR_INTERNAL_ERROR);
914 Assert(PGMIsLocked(pVM));
915
916 /*
917 * Make sure the page is writable.
918 */
919 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
920 {
921 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
922 if (RT_FAILURE(rc))
923 return rc;
924 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
925 }
926 Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
927
928 /*
929 * Get the mapping address.
930 */
931#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
932 *ppv = pgmDynMapHCPageOff(&pVM->pgm.s, PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK));
933#else
934 PPGMPAGEMAPTLBE pTlbe;
935 rc = pgmPhysPageQueryTlbeWithPage(&pVM->pgm.s, pPage, GCPhys, &pTlbe);
936 if (RT_FAILURE(rc))
937 return rc;
938 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
939#endif
940 return VINF_SUCCESS;
941}
942
943
944/**
945 * Internal version of PGMPhysGCPhys2CCPtrReadOnly that expects the caller to
946 * own the PGM lock and therefore not need to lock the mapped page.
947 *
948 * @returns VBox status code.
949 * @retval VINF_SUCCESS on success.
950 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
951 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
952 *
953 * @param pVM The VM handle.
954 * @param GCPhys The guest physical address of the page that should be mapped.
955 * @param pPage Pointer to the PGMPAGE structure for the page.
956 * @param ppv Where to store the address corresponding to GCPhys.
957 *
958 * @internal
959 */
960int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv)
961{
962 AssertReturn(pPage, VERR_INTERNAL_ERROR);
963 Assert(PGMIsLocked(pVM));
964 Assert(PGM_PAGE_GET_HCPHYS(pPage) != 0);
965
966 /*
967 * Get the mapping address.
968 */
969#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
970 *ppv = pgmDynMapHCPageOff(&pVM->pgm.s, PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK)); /** @todo add a read only flag? */
971#else
972 PPGMPAGEMAPTLBE pTlbe;
973 int rc = pgmPhysPageQueryTlbeWithPage(&pVM->pgm.s, pPage, GCPhys, &pTlbe);
974 if (RT_FAILURE(rc))
975 return rc;
976 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
977#endif
978 return VINF_SUCCESS;
979}
980
981
982/**
983 * Requests the mapping of a guest page into the current context.
984 *
985 * This API should only be used for very short term, as it will consume
986 * scarse resources (R0 and GC) in the mapping cache. When you're done
987 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
988 *
989 * This API will assume your intention is to write to the page, and will
990 * therefore replace shared and zero pages. If you do not intend to modify
991 * the page, use the PGMPhysGCPhys2CCPtrReadOnly() API.
992 *
993 * @returns VBox status code.
994 * @retval VINF_SUCCESS on success.
995 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
996 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
997 *
998 * @param pVM The VM handle.
999 * @param GCPhys The guest physical address of the page that should be mapped.
1000 * @param ppv Where to store the address corresponding to GCPhys.
1001 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1002 *
1003 * @remarks The caller is responsible for dealing with access handlers.
1004 * @todo Add an informational return code for pages with access handlers?
1005 *
1006 * @remark Avoid calling this API from within critical sections (other than the
1007 * PGM one) because of the deadlock risk. External threads may need to
1008 * delegate jobs to the EMTs.
1009 * @thread Any thread.
1010 */
1011VMMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
1012{
1013#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1014
1015 /*
1016 * Find the page and make sure it's writable.
1017 */
1018 PPGMPAGE pPage;
1019 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1020 if (RT_SUCCESS(rc))
1021 {
1022 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1023 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1024 if (RT_SUCCESS(rc))
1025 {
1026 *ppv = pgmDynMapHCPageOff(&pVM->pgm.s, PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK)); /** @todo add a read only flag? */
1027# if 0
1028 pLock->pvMap = 0;
1029 pLock->pvPage = pPage;
1030# else
1031 pLock->u32Dummy = UINT32_MAX;
1032# endif
1033 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1034 rc = VINF_SUCCESS;
1035 }
1036 }
1037
1038#else /* IN_RING3 || IN_RING0 */
1039 int rc = pgmLock(pVM);
1040 AssertRCReturn(rc, rc);
1041
1042 /*
1043 * Query the Physical TLB entry for the page (may fail).
1044 */
1045 PPGMPAGEMAPTLBE pTlbe;
1046 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
1047 if (RT_SUCCESS(rc))
1048 {
1049 /*
1050 * If the page is shared, the zero page, or being write monitored
1051 * it must be converted to an page that's writable if possible.
1052 */
1053 PPGMPAGE pPage = pTlbe->pPage;
1054 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
1055 {
1056 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1057 if (RT_SUCCESS(rc))
1058 {
1059 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1060 rc = pgmPhysPageQueryTlbeWithPage(&pVM->pgm.s, pPage, GCPhys, &pTlbe);
1061 }
1062 }
1063 if (RT_SUCCESS(rc))
1064 {
1065 /*
1066 * Now, just perform the locking and calculate the return address.
1067 */
1068 PPGMPAGEMAP pMap = pTlbe->pMap;
1069 if (pMap)
1070 pMap->cRefs++;
1071
1072 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
1073 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
1074 {
1075 if (cLocks == 0)
1076 pVM->pgm.s.cWriteLockedPages++;
1077 PGM_PAGE_INC_WRITE_LOCKS(pPage);
1078 }
1079 else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
1080 {
1081 PGM_PAGE_INC_WRITE_LOCKS(pPage);
1082 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
1083 if (pMap)
1084 pMap->cRefs++; /* Extra ref to prevent it from going away. */
1085 }
1086
1087 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
1088 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_WRITE;
1089 pLock->pvMap = pMap;
1090 }
1091 }
1092
1093 pgmUnlock(pVM);
1094#endif /* IN_RING3 || IN_RING0 */
1095 return rc;
1096}
1097
1098
1099/**
1100 * Requests the mapping of a guest page into the current context.
1101 *
1102 * This API should only be used for very short term, as it will consume
1103 * scarse resources (R0 and GC) in the mapping cache. When you're done
1104 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
1105 *
1106 * @returns VBox status code.
1107 * @retval VINF_SUCCESS on success.
1108 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1109 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1110 *
1111 * @param pVM The VM handle.
1112 * @param GCPhys The guest physical address of the page that should be mapped.
1113 * @param ppv Where to store the address corresponding to GCPhys.
1114 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1115 *
1116 * @remarks The caller is responsible for dealing with access handlers.
1117 * @todo Add an informational return code for pages with access handlers?
1118 *
1119 * @remark Avoid calling this API from within critical sections (other than
1120 * the PGM one) because of the deadlock risk.
1121 * @thread Any thread.
1122 */
1123VMMDECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
1124{
1125#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1126
1127 /*
1128 * Find the page and make sure it's readable.
1129 */
1130 PPGMPAGE pPage;
1131 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1132 if (RT_SUCCESS(rc))
1133 {
1134 if (RT_UNLIKELY(PGM_PAGE_IS_MMIO(pPage)))
1135 rc = VERR_PGM_PHYS_PAGE_RESERVED;
1136 else
1137 {
1138 *ppv = pgmDynMapHCPageOff(&pVM->pgm.s, PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK)); /** @todo add a read only flag? */
1139# if 0
1140 pLock->pvMap = 0;
1141 pLock->pvPage = pPage;
1142# else
1143 pLock->u32Dummy = UINT32_MAX;
1144# endif
1145 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 /* not returned */, ("%Rrc\n", rc));
1146 rc = VINF_SUCCESS;
1147 }
1148 }
1149
1150#else /* IN_RING3 || IN_RING0 */
1151 int rc = pgmLock(pVM);
1152 AssertRCReturn(rc, rc);
1153
1154 /*
1155 * Query the Physical TLB entry for the page (may fail).
1156 */
1157 PPGMPAGEMAPTLBE pTlbe;
1158 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
1159 if (RT_SUCCESS(rc))
1160 {
1161 /* MMIO pages doesn't have any readable backing. */
1162 PPGMPAGE pPage = pTlbe->pPage;
1163 if (RT_UNLIKELY(PGM_PAGE_IS_MMIO(pPage)))
1164 rc = VERR_PGM_PHYS_PAGE_RESERVED;
1165 else
1166 {
1167 /*
1168 * Now, just perform the locking and calculate the return address.
1169 */
1170 PPGMPAGEMAP pMap = pTlbe->pMap;
1171 if (pMap)
1172 pMap->cRefs++;
1173
1174 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
1175 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
1176 {
1177 if (cLocks == 0)
1178 pVM->pgm.s.cReadLockedPages++;
1179 PGM_PAGE_INC_READ_LOCKS(pPage);
1180 }
1181 else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
1182 {
1183 PGM_PAGE_INC_READ_LOCKS(pPage);
1184 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
1185 if (pMap)
1186 pMap->cRefs++; /* Extra ref to prevent it from going away. */
1187 }
1188
1189 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
1190 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_READ;
1191 pLock->pvMap = pMap;
1192 }
1193 }
1194
1195 pgmUnlock(pVM);
1196#endif /* IN_RING3 || IN_RING0 */
1197 return rc;
1198}
1199
1200
1201/**
1202 * Requests the mapping of a guest page given by virtual address into the current context.
1203 *
1204 * This API should only be used for very short term, as it will consume
1205 * scarse resources (R0 and GC) in the mapping cache. When you're done
1206 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
1207 *
1208 * This API will assume your intention is to write to the page, and will
1209 * therefore replace shared and zero pages. If you do not intend to modify
1210 * the page, use the PGMPhysGCPtr2CCPtrReadOnly() API.
1211 *
1212 * @returns VBox status code.
1213 * @retval VINF_SUCCESS on success.
1214 * @retval VERR_PAGE_TABLE_NOT_PRESENT if the page directory for the virtual address isn't present.
1215 * @retval VERR_PAGE_NOT_PRESENT if the page at the virtual address isn't present.
1216 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1217 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1218 *
1219 * @param pVCpu VMCPU handle.
1220 * @param GCPhys The guest physical address of the page that should be mapped.
1221 * @param ppv Where to store the address corresponding to GCPhys.
1222 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1223 *
1224 * @remark Avoid calling this API from within critical sections (other than
1225 * the PGM one) because of the deadlock risk.
1226 * @thread EMT
1227 */
1228VMMDECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock)
1229{
1230 VM_ASSERT_EMT(pVCpu->CTX_SUFF(pVM));
1231 RTGCPHYS GCPhys;
1232 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, &GCPhys);
1233 if (RT_SUCCESS(rc))
1234 rc = PGMPhysGCPhys2CCPtr(pVCpu->CTX_SUFF(pVM), GCPhys, ppv, pLock);
1235 return rc;
1236}
1237
1238
1239/**
1240 * Requests the mapping of a guest page given by virtual address into the current context.
1241 *
1242 * This API should only be used for very short term, as it will consume
1243 * scarse resources (R0 and GC) in the mapping cache. When you're done
1244 * with the page, call PGMPhysReleasePageMappingLock() ASAP to release it.
1245 *
1246 * @returns VBox status code.
1247 * @retval VINF_SUCCESS on success.
1248 * @retval VERR_PAGE_TABLE_NOT_PRESENT if the page directory for the virtual address isn't present.
1249 * @retval VERR_PAGE_NOT_PRESENT if the page at the virtual address isn't present.
1250 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
1251 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
1252 *
1253 * @param pVCpu VMCPU handle.
1254 * @param GCPhys The guest physical address of the page that should be mapped.
1255 * @param ppv Where to store the address corresponding to GCPhys.
1256 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
1257 *
1258 * @remark Avoid calling this API from within critical sections (other than
1259 * the PGM one) because of the deadlock risk.
1260 * @thread EMT
1261 */
1262VMMDECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock)
1263{
1264 VM_ASSERT_EMT(pVCpu->CTX_SUFF(pVM));
1265 RTGCPHYS GCPhys;
1266 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, &GCPhys);
1267 if (RT_SUCCESS(rc))
1268 rc = PGMPhysGCPhys2CCPtrReadOnly(pVCpu->CTX_SUFF(pVM), GCPhys, ppv, pLock);
1269 return rc;
1270}
1271
1272
1273/**
1274 * Release the mapping of a guest page.
1275 *
1276 * This is the counter part of PGMPhysGCPhys2CCPtr, PGMPhysGCPhys2CCPtrReadOnly
1277 * PGMPhysGCPtr2CCPtr and PGMPhysGCPtr2CCPtrReadOnly.
1278 *
1279 * @param pVM The VM handle.
1280 * @param pLock The lock structure initialized by the mapping function.
1281 */
1282VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock)
1283{
1284#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1285 /* currently nothing to do here. */
1286 Assert(pLock->u32Dummy == UINT32_MAX);
1287 pLock->u32Dummy = 0;
1288
1289#else /* IN_RING3 */
1290 PPGMPAGEMAP pMap = (PPGMPAGEMAP)pLock->pvMap;
1291 PPGMPAGE pPage = (PPGMPAGE)(pLock->uPageAndType & ~PGMPAGEMAPLOCK_TYPE_MASK);
1292 bool fWriteLock = (pLock->uPageAndType & PGMPAGEMAPLOCK_TYPE_MASK) == PGMPAGEMAPLOCK_TYPE_WRITE;
1293
1294 pLock->uPageAndType = 0;
1295 pLock->pvMap = NULL;
1296
1297 pgmLock(pVM);
1298 if (fWriteLock)
1299 {
1300 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
1301 Assert(cLocks > 0);
1302 if (RT_LIKELY(cLocks > 0 && cLocks < PGM_PAGE_MAX_LOCKS))
1303 {
1304 if (cLocks == 1)
1305 {
1306 Assert(pVM->pgm.s.cWriteLockedPages > 0);
1307 pVM->pgm.s.cWriteLockedPages--;
1308 }
1309 PGM_PAGE_DEC_WRITE_LOCKS(pPage);
1310 }
1311
1312 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1313 {
1314 PGM_PAGE_SET_WRITTEN_TO(pPage);
1315 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1316 Assert(pVM->pgm.s.cMonitoredPages > 0);
1317 pVM->pgm.s.cMonitoredPages--;
1318 pVM->pgm.s.cWrittenToPages++;
1319 }
1320 }
1321 else
1322 {
1323 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
1324 Assert(cLocks > 0);
1325 if (RT_LIKELY(cLocks > 0 && cLocks < PGM_PAGE_MAX_LOCKS))
1326 {
1327 if (cLocks == 1)
1328 {
1329 Assert(pVM->pgm.s.cReadLockedPages > 0);
1330 pVM->pgm.s.cReadLockedPages--;
1331 }
1332 PGM_PAGE_DEC_READ_LOCKS(pPage);
1333 }
1334 }
1335
1336 if (pMap)
1337 {
1338 Assert(pMap->cRefs >= 1);
1339 pMap->cRefs--;
1340 pMap->iAge = 0;
1341 }
1342 pgmUnlock(pVM);
1343#endif /* IN_RING3 */
1344}
1345
1346
1347/**
1348 * Converts a GC physical address to a HC ring-3 pointer.
1349 *
1350 * @returns VINF_SUCCESS on success.
1351 * @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
1352 * page but has no physical backing.
1353 * @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
1354 * GC physical address.
1355 * @returns VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY if the range crosses
1356 * a dynamic ram chunk boundary
1357 *
1358 * @param pVM The VM handle.
1359 * @param GCPhys The GC physical address to convert.
1360 * @param cbRange Physical range
1361 * @param pR3Ptr Where to store the R3 pointer on success.
1362 *
1363 * @deprecated Avoid when possible!
1364 */
1365VMMDECL(int) PGMPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTR3PTR pR3Ptr)
1366{
1367/** @todo this is kind of hacky and needs some more work. */
1368#ifndef DEBUG_sandervl
1369 VM_ASSERT_EMT(pVM); /* no longer safe for use outside the EMT thread! */
1370#endif
1371
1372 Log(("PGMPhysGCPhys2R3Ptr(,%RGp,%#x,): dont use this API!\n", GCPhys, cbRange)); /** @todo eliminate this API! */
1373#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1374 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
1375#else
1376 pgmLock(pVM);
1377
1378 PPGMRAMRANGE pRam;
1379 PPGMPAGE pPage;
1380 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
1381 if (RT_SUCCESS(rc))
1382 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)pR3Ptr);
1383
1384 pgmUnlock(pVM);
1385 Assert(rc <= VINF_SUCCESS);
1386 return rc;
1387#endif
1388}
1389
1390
1391#ifdef VBOX_STRICT
1392/**
1393 * PGMPhysGCPhys2R3Ptr convenience for use with assertions.
1394 *
1395 * @returns The R3Ptr, NIL_RTR3PTR on failure.
1396 * @param pVM The VM handle.
1397 * @param GCPhys The GC Physical addresss.
1398 * @param cbRange Physical range.
1399 *
1400 * @deprecated Avoid when possible.
1401 */
1402VMMDECL(RTR3PTR) PGMPhysGCPhys2R3PtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange)
1403{
1404 RTR3PTR R3Ptr;
1405 int rc = PGMPhysGCPhys2R3Ptr(pVM, GCPhys, cbRange, &R3Ptr);
1406 if (RT_SUCCESS(rc))
1407 return R3Ptr;
1408 return NIL_RTR3PTR;
1409}
1410#endif /* VBOX_STRICT */
1411
1412
1413/**
1414 * Converts a guest pointer to a GC physical address.
1415 *
1416 * This uses the current CR3/CR0/CR4 of the guest.
1417 *
1418 * @returns VBox status code.
1419 * @param pVCpu The VMCPU Handle
1420 * @param GCPtr The guest pointer to convert.
1421 * @param pGCPhys Where to store the GC physical address.
1422 */
1423VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
1424{
1425 int rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtr, NULL, pGCPhys);
1426 if (pGCPhys && RT_SUCCESS(rc))
1427 *pGCPhys |= (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
1428 return rc;
1429}
1430
1431
1432/**
1433 * Converts a guest pointer to a HC physical address.
1434 *
1435 * This uses the current CR3/CR0/CR4 of the guest.
1436 *
1437 * @returns VBox status code.
1438 * @param pVCpu The VMCPU Handle
1439 * @param GCPtr The guest pointer to convert.
1440 * @param pHCPhys Where to store the HC physical address.
1441 */
1442VMMDECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys)
1443{
1444 PVM pVM = pVCpu->CTX_SUFF(pVM);
1445 RTGCPHYS GCPhys;
1446 int rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtr, NULL, &GCPhys);
1447 if (RT_SUCCESS(rc))
1448 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhys | ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), pHCPhys);
1449 return rc;
1450}
1451
1452
1453/**
1454 * Converts a guest pointer to a R3 pointer.
1455 *
1456 * This uses the current CR3/CR0/CR4 of the guest.
1457 *
1458 * @returns VBox status code.
1459 * @param pVCpu The VMCPU Handle
1460 * @param GCPtr The guest pointer to convert.
1461 * @param pR3Ptr Where to store the R3 virtual address.
1462 *
1463 * @deprecated Don't use this.
1464 */
1465VMMDECL(int) PGMPhysGCPtr2R3Ptr(PVMCPU pVCpu, RTGCPTR GCPtr, PRTR3PTR pR3Ptr)
1466{
1467 PVM pVM = pVCpu->CTX_SUFF(pVM);
1468 VM_ASSERT_EMT(pVM); /* no longer safe for use outside the EMT thread! */
1469 RTGCPHYS GCPhys;
1470 int rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtr, NULL, &GCPhys);
1471 if (RT_SUCCESS(rc))
1472 rc = PGMPhysGCPhys2R3Ptr(pVM, GCPhys | ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), 1 /* we always stay within one page */, pR3Ptr);
1473 return rc;
1474}
1475
1476
1477
1478#undef LOG_GROUP
1479#define LOG_GROUP LOG_GROUP_PGM_PHYS_ACCESS
1480
1481
1482#ifdef IN_RING3
1483/**
1484 * Cache PGMPhys memory access
1485 *
1486 * @param pVM VM Handle.
1487 * @param pCache Cache structure pointer
1488 * @param GCPhys GC physical address
1489 * @param pbHC HC pointer corresponding to physical page
1490 *
1491 * @thread EMT.
1492 */
1493static void pgmPhysCacheAdd(PVM pVM, PGMPHYSCACHE *pCache, RTGCPHYS GCPhys, uint8_t *pbR3)
1494{
1495 uint32_t iCacheIndex;
1496
1497 Assert(VM_IS_EMT(pVM));
1498
1499 GCPhys = PHYS_PAGE_ADDRESS(GCPhys);
1500 pbR3 = (uint8_t *)PAGE_ADDRESS(pbR3);
1501
1502 iCacheIndex = ((GCPhys >> PAGE_SHIFT) & PGM_MAX_PHYSCACHE_ENTRIES_MASK);
1503
1504 ASMBitSet(&pCache->aEntries, iCacheIndex);
1505
1506 pCache->Entry[iCacheIndex].GCPhys = GCPhys;
1507 pCache->Entry[iCacheIndex].pbR3 = pbR3;
1508}
1509#endif /* IN_RING3 */
1510
1511
1512/**
1513 * Deals with reading from a page with one or more ALL access handlers.
1514 *
1515 * @returns VBox status code. Can be ignored in ring-3.
1516 * @retval VINF_SUCCESS.
1517 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in R0 and GC, NEVER in R3.
1518 *
1519 * @param pVM The VM handle.
1520 * @param pPage The page descriptor.
1521 * @param GCPhys The physical address to start reading at.
1522 * @param pvBuf Where to put the bits we read.
1523 * @param cb How much to read - less or equal to a page.
1524 */
1525static int pgmPhysReadHandler(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void *pvBuf, size_t cb)
1526{
1527 /*
1528 * The most frequent access here is MMIO and shadowed ROM.
1529 * The current code ASSUMES all these access handlers covers full pages!
1530 */
1531
1532 /*
1533 * Whatever we do we need the source page, map it first.
1534 */
1535 const void *pvSrc = NULL;
1536 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvSrc);
1537 if (RT_FAILURE(rc))
1538 {
1539 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
1540 GCPhys, pPage, rc));
1541 memset(pvBuf, 0xff, cb);
1542 return VINF_SUCCESS;
1543 }
1544 rc = VINF_PGM_HANDLER_DO_DEFAULT;
1545
1546 /*
1547 * Deal with any physical handlers.
1548 */
1549 PPGMPHYSHANDLER pPhys = NULL;
1550 if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL)
1551 {
1552#ifdef IN_RING3
1553 PPGMPHYSHANDLER pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
1554 AssertReleaseMsg(pPhys, ("GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1555 Assert(GCPhys >= pPhys->Core.Key && GCPhys <= pPhys->Core.KeyLast);
1556 Assert((pPhys->Core.Key & PAGE_OFFSET_MASK) == 0);
1557 Assert((pPhys->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1558 Assert(pPhys->CTX_SUFF(pfnHandler));
1559
1560 PFNPGMR3PHYSHANDLER pfnHandler = pPhys->CTX_SUFF(pfnHandler);
1561 void *pvUser = pPhys->CTX_SUFF(pvUser);
1562
1563 Log5(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cb, pPage, R3STRING(pPhys->pszDesc) ));
1564 STAM_PROFILE_START(&pPhys->Stat, h);
1565 Assert(PGMIsLockOwner(pVM));
1566 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
1567 pgmUnlock(pVM);
1568 rc = pfnHandler(pVM, GCPhys, (void *)pvSrc, pvBuf, cb, PGMACCESSTYPE_READ, pvUser);
1569 pgmLock(pVM);
1570# ifdef VBOX_WITH_STATISTICS
1571 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
1572 if (pPhys)
1573 STAM_PROFILE_STOP(&pPhys->Stat, h);
1574# else
1575 pPhys = NULL; /* might not be valid anymore. */
1576# endif
1577 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys));
1578#else
1579 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
1580 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1581 return VERR_PGM_PHYS_WR_HIT_HANDLER;
1582#endif
1583 }
1584
1585 /*
1586 * Deal with any virtual handlers.
1587 */
1588 if (PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL)
1589 {
1590 unsigned iPage;
1591 PPGMVIRTHANDLER pVirt;
1592
1593 int rc2 = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pVirt, &iPage);
1594 AssertReleaseMsg(RT_SUCCESS(rc2), ("GCPhys=%RGp cb=%#x rc2=%Rrc\n", GCPhys, cb, rc2));
1595 Assert((pVirt->Core.Key & PAGE_OFFSET_MASK) == 0);
1596 Assert((pVirt->Core.KeyLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
1597 Assert(GCPhys >= pVirt->aPhysToVirt[iPage].Core.Key && GCPhys <= pVirt->aPhysToVirt[iPage].Core.KeyLast);
1598
1599#ifdef IN_RING3
1600 if (pVirt->pfnHandlerR3)
1601 {
1602 if (!pPhys)
1603 Log5(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] virt %s\n", GCPhys, cb, pPage, R3STRING(pVirt->pszDesc) ));
1604 else
1605 Log(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] phys/virt %s/%s\n", GCPhys, cb, pPage, R3STRING(pVirt->pszDesc), R3STRING(pPhys->pszDesc) ));
1606 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
1607 + (iPage << PAGE_SHIFT)
1608 + (GCPhys & PAGE_OFFSET_MASK);
1609
1610 STAM_PROFILE_START(&pVirt->Stat, h);
1611 rc2 = pVirt->CTX_SUFF(pfnHandler)(pVM, GCPtr, (void *)pvSrc, pvBuf, cb, PGMACCESSTYPE_READ, /*pVirt->CTX_SUFF(pvUser)*/ NULL);
1612 STAM_PROFILE_STOP(&pVirt->Stat, h);
1613 if (rc2 == VINF_SUCCESS)
1614 rc = VINF_SUCCESS;
1615 AssertLogRelMsg(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc2, GCPhys, pPage, pVirt->pszDesc));
1616 }
1617 else
1618 Log5(("pgmPhysReadHandler: GCPhys=%RGp cb=%#x pPage=%R[pgmpage] virt %s [no handler]\n", GCPhys, cb, pPage, R3STRING(pVirt->pszDesc) ));
1619#else
1620 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
1621 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1622 return VERR_PGM_PHYS_WR_HIT_HANDLER;
1623#endif
1624 }
1625
1626 /*
1627 * Take the default action.
1628 */
1629 if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1630 memcpy(pvBuf, pvSrc, cb);
1631 return rc;
1632}
1633
1634
1635/**
1636 * Read physical memory.
1637 *
1638 * This API respects access handlers and MMIO. Use PGMPhysSimpleReadGCPhys() if you
1639 * want to ignore those.
1640 *
1641 * @returns VBox status code. Can be ignored in ring-3.
1642 * @retval VINF_SUCCESS.
1643 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in R0 and GC, NEVER in R3.
1644 *
1645 * @param pVM VM Handle.
1646 * @param GCPhys Physical address start reading from.
1647 * @param pvBuf Where to put the read bits.
1648 * @param cbRead How many bytes to read.
1649 */
1650VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1651{
1652 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
1653 LogFlow(("PGMPhysRead: %RGp %d\n", GCPhys, cbRead));
1654
1655 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PhysRead));
1656 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_MID_Z(Stat,PhysReadBytes), cbRead);
1657
1658 pgmLock(pVM);
1659
1660 /*
1661 * Copy loop on ram ranges.
1662 */
1663 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1664 for (;;)
1665 {
1666 /* Find range. */
1667 while (pRam && GCPhys > pRam->GCPhysLast)
1668 pRam = pRam->CTX_SUFF(pNext);
1669 /* Inside range or not? */
1670 if (pRam && GCPhys >= pRam->GCPhys)
1671 {
1672 /*
1673 * Must work our way thru this page by page.
1674 */
1675 RTGCPHYS off = GCPhys - pRam->GCPhys;
1676 while (off < pRam->cb)
1677 {
1678 unsigned iPage = off >> PAGE_SHIFT;
1679 PPGMPAGE pPage = &pRam->aPages[iPage];
1680 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1681 if (cb > cbRead)
1682 cb = cbRead;
1683
1684 /*
1685 * Any ALL access handlers?
1686 */
1687 if (RT_UNLIKELY(PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)))
1688 {
1689 int rc = pgmPhysReadHandler(pVM, pPage, pRam->GCPhys + off, pvBuf, cb);
1690 if (RT_FAILURE(rc))
1691 {
1692 pgmUnlock(pVM);
1693 return rc;
1694 }
1695 }
1696 else
1697 {
1698 /*
1699 * Get the pointer to the page.
1700 */
1701 const void *pvSrc;
1702 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
1703 if (RT_SUCCESS(rc))
1704 memcpy(pvBuf, pvSrc, cb);
1705 else
1706 {
1707 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
1708 pRam->GCPhys + off, pPage, rc));
1709 memset(pvBuf, 0xff, cb);
1710 }
1711 }
1712
1713 /* next page */
1714 if (cb >= cbRead)
1715 {
1716 pgmUnlock(pVM);
1717 return VINF_SUCCESS;
1718 }
1719 cbRead -= cb;
1720 off += cb;
1721 pvBuf = (char *)pvBuf + cb;
1722 } /* walk pages in ram range. */
1723
1724 GCPhys = pRam->GCPhysLast + 1;
1725 }
1726 else
1727 {
1728 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
1729
1730 /*
1731 * Unassigned address space.
1732 */
1733 if (!pRam)
1734 break;
1735 size_t cb = pRam->GCPhys - GCPhys;
1736 if (cb >= cbRead)
1737 {
1738 memset(pvBuf, 0xff, cbRead);
1739 break;
1740 }
1741 memset(pvBuf, 0xff, cb);
1742
1743 cbRead -= cb;
1744 pvBuf = (char *)pvBuf + cb;
1745 GCPhys += cb;
1746 }
1747 } /* Ram range walk */
1748
1749 pgmUnlock(pVM);
1750 return VINF_SUCCESS;
1751}
1752
1753
1754/**
1755 * Deals with writing to a page with one or more WRITE or ALL access handlers.
1756 *
1757 * @returns VBox status code. Can be ignored in ring-3.
1758 * @retval VINF_SUCCESS.
1759 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in R0 and GC, NEVER in R3.
1760 *
1761 * @param pVM The VM handle.
1762 * @param pPage The page descriptor.
1763 * @param GCPhys The physical address to start writing at.
1764 * @param pvBuf What to write.
1765 * @param cbWrite How much to write - less or equal to a page.
1766 */
1767static int pgmPhysWriteHandler(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const *pvBuf, size_t cbWrite)
1768{
1769 void *pvDst = NULL;
1770 int rc;
1771
1772 /*
1773 * Give priority to physical handlers (like #PF does).
1774 *
1775 * Hope for a lonely physical handler first that covers the whole
1776 * write area. This should be a pretty frequent case with MMIO and
1777 * the heavy usage of full page handlers in the page pool.
1778 */
1779 if ( !PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage)
1780 || PGM_PAGE_IS_MMIO(pPage) /* screw virtual handlers on MMIO pages */)
1781 {
1782 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
1783 if (pCur)
1784 {
1785 Assert(GCPhys >= pCur->Core.Key && GCPhys <= pCur->Core.KeyLast);
1786 Assert(pCur->CTX_SUFF(pfnHandler));
1787
1788 size_t cbRange = pCur->Core.KeyLast - GCPhys + 1;
1789 if (cbRange > cbWrite)
1790 cbRange = cbWrite;
1791
1792#ifndef IN_RING3
1793 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
1794 NOREF(cbRange);
1795 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cbRange=%#x\n", GCPhys, cbRange));
1796 return VERR_PGM_PHYS_WR_HIT_HANDLER;
1797
1798#else /* IN_RING3 */
1799 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cbRange, pPage, R3STRING(pCur->pszDesc) ));
1800 if (!PGM_PAGE_IS_MMIO(pPage))
1801 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst);
1802 else
1803 rc = VINF_SUCCESS;
1804 if (RT_SUCCESS(rc))
1805 {
1806 PFNPGMR3PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
1807 void *pvUser = pCur->CTX_SUFF(pvUser);
1808
1809 STAM_PROFILE_START(&pCur->Stat, h);
1810 Assert(PGMIsLockOwner(pVM));
1811 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
1812 pgmUnlock(pVM);
1813 rc = pfnHandler(pVM, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, pvUser);
1814 pgmLock(pVM);
1815# ifdef VBOX_WITH_STATISTICS
1816 pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
1817 if (pCur)
1818 STAM_PROFILE_STOP(&pCur->Stat, h);
1819# else
1820 pCur = NULL; /* might not be valid anymore. */
1821# endif
1822 if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1823 memcpy(pvDst, pvBuf, cbRange);
1824 else
1825 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, (pCur) ? pCur->pszDesc : ""));
1826 }
1827 else
1828 AssertLogRelMsgFailedReturn(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
1829 GCPhys, pPage, rc), rc);
1830 if (RT_LIKELY(cbRange == cbWrite))
1831 return VINF_SUCCESS;
1832
1833 /* more fun to be had below */
1834 cbWrite -= cbRange;
1835 GCPhys += cbRange;
1836 pvBuf = (uint8_t *)pvBuf + cbRange;
1837 pvDst = (uint8_t *)pvDst + cbRange;
1838#endif /* IN_RING3 */
1839 }
1840 /* else: the handler is somewhere else in the page, deal with it below. */
1841 Assert(!PGM_PAGE_IS_MMIO(pPage)); /* MMIO handlers are all PAGE_SIZEed! */
1842 }
1843 /*
1844 * A virtual handler without any interfering physical handlers.
1845 * Hopefully it'll conver the whole write.
1846 */
1847 else if (!PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage))
1848 {
1849 unsigned iPage;
1850 PPGMVIRTHANDLER pCur;
1851 rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pCur, &iPage);
1852 if (RT_SUCCESS(rc))
1853 {
1854 size_t cbRange = (PAGE_OFFSET_MASK & pCur->Core.KeyLast) - (PAGE_OFFSET_MASK & GCPhys) + 1;
1855 if (cbRange > cbWrite)
1856 cbRange = cbWrite;
1857
1858#ifndef IN_RING3
1859 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
1860 NOREF(cbRange);
1861 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cbRange=%#x\n", GCPhys, cbRange));
1862 return VERR_PGM_PHYS_WR_HIT_HANDLER;
1863
1864#else /* IN_RING3 */
1865
1866 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] virt %s\n", GCPhys, cbRange, pPage, R3STRING(pCur->pszDesc) ));
1867 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst);
1868 if (RT_SUCCESS(rc))
1869 {
1870 rc = VINF_PGM_HANDLER_DO_DEFAULT;
1871 if (pCur->pfnHandlerR3)
1872 {
1873 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pCur->Core.Key & PAGE_BASE_GC_MASK)
1874 + (iPage << PAGE_SHIFT)
1875 + (GCPhys & PAGE_OFFSET_MASK);
1876
1877 STAM_PROFILE_START(&pCur->Stat, h);
1878 rc = pCur->CTX_SUFF(pfnHandler)(pVM, GCPtr, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, /*pCur->CTX_SUFF(pvUser)*/ NULL);
1879 STAM_PROFILE_STOP(&pCur->Stat, h);
1880 }
1881 if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1882 memcpy(pvDst, pvBuf, cbRange);
1883 else
1884 AssertLogRelMsg(rc == VINF_SUCCESS, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, pCur->pszDesc));
1885 }
1886 else
1887 AssertLogRelMsgFailedReturn(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
1888 GCPhys, pPage, rc), rc);
1889 if (RT_LIKELY(cbRange == cbWrite))
1890 return VINF_SUCCESS;
1891
1892 /* more fun to be had below */
1893 cbWrite -= cbRange;
1894 GCPhys += cbRange;
1895 pvBuf = (uint8_t *)pvBuf + cbRange;
1896 pvDst = (uint8_t *)pvDst + cbRange;
1897#endif
1898 }
1899 /* else: the handler is somewhere else in the page, deal with it below. */
1900 }
1901
1902 /*
1903 * Deal with all the odd ends.
1904 */
1905
1906 /* We need a writable destination page. */
1907 if (!pvDst)
1908 {
1909 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDst);
1910 AssertLogRelMsgReturn(RT_SUCCESS(rc),
1911 ("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
1912 GCPhys, pPage, rc), rc);
1913 }
1914
1915 /* The loop state (big + ugly). */
1916 unsigned iVirtPage = 0;
1917 PPGMVIRTHANDLER pVirt = NULL;
1918 uint32_t offVirt = PAGE_SIZE;
1919 uint32_t offVirtLast = PAGE_SIZE;
1920 bool fMoreVirt = PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage);
1921
1922 PPGMPHYSHANDLER pPhys = NULL;
1923 uint32_t offPhys = PAGE_SIZE;
1924 uint32_t offPhysLast = PAGE_SIZE;
1925 bool fMorePhys = PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage);
1926
1927 /* The loop. */
1928 for (;;)
1929 {
1930 /*
1931 * Find the closest handler at or above GCPhys.
1932 */
1933 if (fMoreVirt && !pVirt)
1934 {
1935 int rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pVirt, &iVirtPage);
1936 if (RT_SUCCESS(rc))
1937 {
1938 offVirt = 0;
1939 offVirtLast = (pVirt->aPhysToVirt[iVirtPage].Core.KeyLast & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
1940 }
1941 else
1942 {
1943 PPGMPHYS2VIRTHANDLER pVirtPhys;
1944 pVirtPhys = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGetBestFit(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysToVirtHandlers,
1945 GCPhys, true /* fAbove */);
1946 if ( pVirtPhys
1947 && (pVirtPhys->Core.Key >> PAGE_SHIFT) == (GCPhys >> PAGE_SHIFT))
1948 {
1949 /* ASSUME that pVirtPhys only covers one page. */
1950 Assert((pVirtPhys->Core.Key >> PAGE_SHIFT) == (pVirtPhys->Core.KeyLast >> PAGE_SHIFT));
1951 Assert(pVirtPhys->Core.Key > GCPhys);
1952
1953 pVirt = (PPGMVIRTHANDLER)((uintptr_t)pVirtPhys + pVirtPhys->offVirtHandler);
1954 iVirtPage = pVirtPhys - &pVirt->aPhysToVirt[0]; Assert(iVirtPage == 0);
1955 offVirt = (pVirtPhys->Core.Key & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
1956 offVirtLast = (pVirtPhys->Core.KeyLast & PAGE_OFFSET_MASK) - (GCPhys & PAGE_OFFSET_MASK);
1957 }
1958 else
1959 {
1960 pVirt = NULL;
1961 fMoreVirt = false;
1962 offVirt = offVirtLast = PAGE_SIZE;
1963 }
1964 }
1965 }
1966
1967 if (fMorePhys && !pPhys)
1968 {
1969 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
1970 if (pPhys)
1971 {
1972 offPhys = 0;
1973 offPhysLast = pPhys->Core.KeyLast - GCPhys; /* ASSUMES < 4GB handlers... */
1974 }
1975 else
1976 {
1977 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysGetBestFit(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers,
1978 GCPhys, true /* fAbove */);
1979 if ( pPhys
1980 && pPhys->Core.Key <= GCPhys + (cbWrite - 1))
1981 {
1982 offPhys = pPhys->Core.Key - GCPhys;
1983 offPhysLast = pPhys->Core.KeyLast - GCPhys; /* ASSUMES < 4GB handlers... */
1984 }
1985 else
1986 {
1987 pPhys = NULL;
1988 fMorePhys = false;
1989 offPhys = offPhysLast = PAGE_SIZE;
1990 }
1991 }
1992 }
1993
1994 /*
1995 * Handle access to space without handlers (that's easy).
1996 */
1997 rc = VINF_PGM_HANDLER_DO_DEFAULT;
1998 uint32_t cbRange = (uint32_t)cbWrite;
1999 if (offPhys && offVirt)
2000 {
2001 if (cbRange > offPhys)
2002 cbRange = offPhys;
2003 if (cbRange > offVirt)
2004 cbRange = offVirt;
2005 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] miss\n", GCPhys, cbRange, pPage));
2006 }
2007 /*
2008 * Physical handler.
2009 */
2010 else if (!offPhys && offVirt)
2011 {
2012 if (cbRange > offPhysLast + 1)
2013 cbRange = offPhysLast + 1;
2014 if (cbRange > offVirt)
2015 cbRange = offVirt;
2016#ifdef IN_RING3
2017 PFNPGMR3PHYSHANDLER pfnHandler = pPhys->CTX_SUFF(pfnHandler);
2018 void *pvUser = pPhys->CTX_SUFF(pvUser);
2019
2020 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cbRange, pPage, R3STRING(pPhys->pszDesc) ));
2021 STAM_PROFILE_START(&pPhys->Stat, h);
2022 Assert(PGMIsLockOwner(pVM));
2023 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2024 pgmUnlock(pVM);
2025 rc = pfnHandler(pVM, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, pvUser);
2026 pgmLock(pVM);
2027# ifdef VBOX_WITH_STATISTICS
2028 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
2029 if (pPhys)
2030 STAM_PROFILE_STOP(&pPhys->Stat, h);
2031# else
2032 pPhys = NULL; /* might not be valid anymore. */
2033# endif
2034 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, (pPhys) ? pPhys->pszDesc : ""));
2035#else
2036 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
2037 NOREF(cbRange);
2038 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cbRange=%#x\n", GCPhys, cbRange));
2039 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2040#endif
2041 }
2042 /*
2043 * Virtual handler.
2044 */
2045 else if (offPhys && !offVirt)
2046 {
2047 if (cbRange > offVirtLast + 1)
2048 cbRange = offVirtLast + 1;
2049 if (cbRange > offPhys)
2050 cbRange = offPhys;
2051#ifdef IN_RING3
2052 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys %s\n", GCPhys, cbRange, pPage, R3STRING(pVirt->pszDesc) ));
2053 if (pVirt->pfnHandlerR3)
2054 {
2055 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2056 + (iVirtPage << PAGE_SHIFT)
2057 + (GCPhys & PAGE_OFFSET_MASK);
2058 STAM_PROFILE_START(&pVirt->Stat, h);
2059 rc = pVirt->CTX_SUFF(pfnHandler)(pVM, GCPtr, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, /*pCur->CTX_SUFF(pvUser)*/ NULL);
2060 STAM_PROFILE_STOP(&pVirt->Stat, h);
2061 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, pVirt->pszDesc));
2062 }
2063 pVirt = NULL;
2064#else
2065 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
2066 NOREF(cbRange);
2067 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cbRange=%#x\n", GCPhys, cbRange));
2068 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2069#endif
2070 }
2071 /*
2072 * Both... give the physical one priority.
2073 */
2074 else
2075 {
2076 Assert(!offPhys && !offVirt);
2077 if (cbRange > offVirtLast + 1)
2078 cbRange = offVirtLast + 1;
2079 if (cbRange > offPhysLast + 1)
2080 cbRange = offPhysLast + 1;
2081
2082#ifdef IN_RING3
2083 if (pVirt->pfnHandlerR3)
2084 Log(("pgmPhysWriteHandler: overlapping phys and virt handlers at %RGp %R[pgmpage]; cbRange=%#x\n", GCPhys, pPage, cbRange));
2085 Log5(("pgmPhysWriteHandler: GCPhys=%RGp cbRange=%#x pPage=%R[pgmpage] phys/virt %s/%s\n", GCPhys, cbRange, pPage, R3STRING(pPhys->pszDesc), R3STRING(pVirt->pszDesc) ));
2086
2087 PFNPGMR3PHYSHANDLER pfnHandler = pPhys->CTX_SUFF(pfnHandler);
2088 void *pvUser = pPhys->CTX_SUFF(pvUser);
2089
2090 STAM_PROFILE_START(&pPhys->Stat, h);
2091 Assert(PGMIsLockOwner(pVM));
2092 /* Release the PGM lock as MMIO handlers take the IOM lock. (deadlock prevention) */
2093 pgmUnlock(pVM);
2094 rc = pfnHandler(pVM, GCPhys, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, pvUser);
2095 pgmLock(pVM);
2096# ifdef VBOX_WITH_STATISTICS
2097 pPhys = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
2098 if (pPhys)
2099 STAM_PROFILE_STOP(&pPhys->Stat, h);
2100# else
2101 pPhys = NULL; /* might not be valid anymore. */
2102# endif
2103 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, (pPhys) ? pPhys->pszDesc : ""));
2104 if (pVirt->pfnHandlerR3)
2105 {
2106
2107 RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirt->Core.Key & PAGE_BASE_GC_MASK)
2108 + (iVirtPage << PAGE_SHIFT)
2109 + (GCPhys & PAGE_OFFSET_MASK);
2110 STAM_PROFILE_START(&pVirt->Stat, h);
2111 int rc2 = pVirt->CTX_SUFF(pfnHandler)(pVM, GCPtr, pvDst, (void *)pvBuf, cbRange, PGMACCESSTYPE_WRITE, /*pCur->CTX_SUFF(pvUser)*/ NULL);
2112 STAM_PROFILE_STOP(&pVirt->Stat, h);
2113 if (rc2 == VINF_SUCCESS && rc == VINF_PGM_HANDLER_DO_DEFAULT)
2114 rc = VINF_SUCCESS;
2115 else
2116 AssertLogRelMsg(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_HANDLER_DO_DEFAULT, ("rc=%Rrc GCPhys=%RGp pPage=%R[pgmpage] %s\n", rc, GCPhys, pPage, pVirt->pszDesc));
2117 }
2118 pPhys = NULL;
2119 pVirt = NULL;
2120#else
2121 /* In R0 and RC the callbacks cannot handle this context, so we'll fail. */
2122 NOREF(cbRange);
2123 //AssertReleaseMsgFailed(("Wrong API! GCPhys=%RGp cbRange=%#x\n", GCPhys, cbRange));
2124 return VERR_PGM_PHYS_WR_HIT_HANDLER;
2125#endif
2126 }
2127 if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
2128 memcpy(pvDst, pvBuf, cbRange);
2129
2130 /*
2131 * Advance if we've got more stuff to do.
2132 */
2133 if (cbRange >= cbWrite)
2134 return VINF_SUCCESS;
2135
2136 cbWrite -= cbRange;
2137 GCPhys += cbRange;
2138 pvBuf = (uint8_t *)pvBuf + cbRange;
2139 pvDst = (uint8_t *)pvDst + cbRange;
2140
2141 offPhys -= cbRange;
2142 offPhysLast -= cbRange;
2143 offVirt -= cbRange;
2144 offVirtLast -= cbRange;
2145 }
2146}
2147
2148
2149/**
2150 * Write to physical memory.
2151 *
2152 * This API respects access handlers and MMIO. Use PGMPhysSimpleReadGCPhys() if you
2153 * want to ignore those.
2154 *
2155 * @returns VBox status code. Can be ignored in ring-3.
2156 * @retval VINF_SUCCESS.
2157 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in R0 and GC, NEVER in R3.
2158 *
2159 * @param pVM VM Handle.
2160 * @param GCPhys Physical address to write to.
2161 * @param pvBuf What to write.
2162 * @param cbWrite How many bytes to write.
2163 */
2164VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
2165{
2166 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMPhysWrite after pgmR3Save()!\n"));
2167 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
2168 LogFlow(("PGMPhysWrite: %RGp %d\n", GCPhys, cbWrite));
2169
2170 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PhysWrite));
2171 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_MID_Z(Stat,PhysWriteBytes), cbWrite);
2172
2173 pgmLock(pVM);
2174
2175 /*
2176 * Copy loop on ram ranges.
2177 */
2178 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2179 for (;;)
2180 {
2181 /* Find range. */
2182 while (pRam && GCPhys > pRam->GCPhysLast)
2183 pRam = pRam->CTX_SUFF(pNext);
2184 /* Inside range or not? */
2185 if (pRam && GCPhys >= pRam->GCPhys)
2186 {
2187 /*
2188 * Must work our way thru this page by page.
2189 */
2190 RTGCPTR off = GCPhys - pRam->GCPhys;
2191 while (off < pRam->cb)
2192 {
2193 RTGCPTR iPage = off >> PAGE_SHIFT;
2194 PPGMPAGE pPage = &pRam->aPages[iPage];
2195 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
2196 if (cb > cbWrite)
2197 cb = cbWrite;
2198
2199 /*
2200 * Any active WRITE or ALL access handlers?
2201 */
2202 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2203 {
2204 int rc = pgmPhysWriteHandler(pVM, pPage, pRam->GCPhys + off, pvBuf, cb);
2205 if (RT_FAILURE(rc))
2206 {
2207 pgmUnlock(pVM);
2208 return rc;
2209 }
2210 }
2211 else
2212 {
2213 /*
2214 * Get the pointer to the page.
2215 */
2216 void *pvDst;
2217 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
2218 if (RT_SUCCESS(rc))
2219 memcpy(pvDst, pvBuf, cb);
2220 else
2221 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
2222 pRam->GCPhys + off, pPage, rc));
2223 }
2224
2225 /* next page */
2226 if (cb >= cbWrite)
2227 {
2228 pgmUnlock(pVM);
2229 return VINF_SUCCESS;
2230 }
2231
2232 cbWrite -= cb;
2233 off += cb;
2234 pvBuf = (const char *)pvBuf + cb;
2235 } /* walk pages in ram range */
2236
2237 GCPhys = pRam->GCPhysLast + 1;
2238 }
2239 else
2240 {
2241 /*
2242 * Unassigned address space, skip it.
2243 */
2244 if (!pRam)
2245 break;
2246 size_t cb = pRam->GCPhys - GCPhys;
2247 if (cb >= cbWrite)
2248 break;
2249 cbWrite -= cb;
2250 pvBuf = (const char *)pvBuf + cb;
2251 GCPhys += cb;
2252 }
2253 } /* Ram range walk */
2254
2255 pgmUnlock(pVM);
2256 return VINF_SUCCESS;
2257}
2258
2259
2260/**
2261 * Read from guest physical memory by GC physical address, bypassing
2262 * MMIO and access handlers.
2263 *
2264 * @returns VBox status.
2265 * @param pVM VM handle.
2266 * @param pvDst The destination address.
2267 * @param GCPhysSrc The source address (GC physical address).
2268 * @param cb The number of bytes to read.
2269 */
2270VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb)
2271{
2272 /*
2273 * Treat the first page as a special case.
2274 */
2275 if (!cb)
2276 return VINF_SUCCESS;
2277
2278 /* map the 1st page */
2279 void const *pvSrc;
2280 PGMPAGEMAPLOCK Lock;
2281 int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysSrc, &pvSrc, &Lock);
2282 if (RT_FAILURE(rc))
2283 return rc;
2284
2285 /* optimize for the case where access is completely within the first page. */
2286 size_t cbPage = PAGE_SIZE - (GCPhysSrc & PAGE_OFFSET_MASK);
2287 if (RT_LIKELY(cb <= cbPage))
2288 {
2289 memcpy(pvDst, pvSrc, cb);
2290 PGMPhysReleasePageMappingLock(pVM, &Lock);
2291 return VINF_SUCCESS;
2292 }
2293
2294 /* copy to the end of the page. */
2295 memcpy(pvDst, pvSrc, cbPage);
2296 PGMPhysReleasePageMappingLock(pVM, &Lock);
2297 GCPhysSrc += cbPage;
2298 pvDst = (uint8_t *)pvDst + cbPage;
2299 cb -= cbPage;
2300
2301 /*
2302 * Page by page.
2303 */
2304 for (;;)
2305 {
2306 /* map the page */
2307 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhysSrc, &pvSrc, &Lock);
2308 if (RT_FAILURE(rc))
2309 return rc;
2310
2311 /* last page? */
2312 if (cb <= PAGE_SIZE)
2313 {
2314 memcpy(pvDst, pvSrc, cb);
2315 PGMPhysReleasePageMappingLock(pVM, &Lock);
2316 return VINF_SUCCESS;
2317 }
2318
2319 /* copy the entire page and advance */
2320 memcpy(pvDst, pvSrc, PAGE_SIZE);
2321 PGMPhysReleasePageMappingLock(pVM, &Lock);
2322 GCPhysSrc += PAGE_SIZE;
2323 pvDst = (uint8_t *)pvDst + PAGE_SIZE;
2324 cb -= PAGE_SIZE;
2325 }
2326 /* won't ever get here. */
2327}
2328
2329
2330/**
2331 * Write to guest physical memory referenced by GC pointer.
2332 * Write memory to GC physical address in guest physical memory.
2333 *
2334 * This will bypass MMIO and access handlers.
2335 *
2336 * @returns VBox status.
2337 * @param pVM VM handle.
2338 * @param GCPhysDst The GC physical address of the destination.
2339 * @param pvSrc The source buffer.
2340 * @param cb The number of bytes to write.
2341 */
2342VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb)
2343{
2344 LogFlow(("PGMPhysSimpleWriteGCPhys: %RGp %zu\n", GCPhysDst, cb));
2345
2346 /*
2347 * Treat the first page as a special case.
2348 */
2349 if (!cb)
2350 return VINF_SUCCESS;
2351
2352 /* map the 1st page */
2353 void *pvDst;
2354 PGMPAGEMAPLOCK Lock;
2355 int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysDst, &pvDst, &Lock);
2356 if (RT_FAILURE(rc))
2357 return rc;
2358
2359 /* optimize for the case where access is completely within the first page. */
2360 size_t cbPage = PAGE_SIZE - (GCPhysDst & PAGE_OFFSET_MASK);
2361 if (RT_LIKELY(cb <= cbPage))
2362 {
2363 memcpy(pvDst, pvSrc, cb);
2364 PGMPhysReleasePageMappingLock(pVM, &Lock);
2365 return VINF_SUCCESS;
2366 }
2367
2368 /* copy to the end of the page. */
2369 memcpy(pvDst, pvSrc, cbPage);
2370 PGMPhysReleasePageMappingLock(pVM, &Lock);
2371 GCPhysDst += cbPage;
2372 pvSrc = (const uint8_t *)pvSrc + cbPage;
2373 cb -= cbPage;
2374
2375 /*
2376 * Page by page.
2377 */
2378 for (;;)
2379 {
2380 /* map the page */
2381 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysDst, &pvDst, &Lock);
2382 if (RT_FAILURE(rc))
2383 return rc;
2384
2385 /* last page? */
2386 if (cb <= PAGE_SIZE)
2387 {
2388 memcpy(pvDst, pvSrc, cb);
2389 PGMPhysReleasePageMappingLock(pVM, &Lock);
2390 return VINF_SUCCESS;
2391 }
2392
2393 /* copy the entire page and advance */
2394 memcpy(pvDst, pvSrc, PAGE_SIZE);
2395 PGMPhysReleasePageMappingLock(pVM, &Lock);
2396 GCPhysDst += PAGE_SIZE;
2397 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
2398 cb -= PAGE_SIZE;
2399 }
2400 /* won't ever get here. */
2401}
2402
2403
2404/**
2405 * Read from guest physical memory referenced by GC pointer.
2406 *
2407 * This function uses the current CR3/CR0/CR4 of the guest and will
2408 * bypass access handlers and not set any accessed bits.
2409 *
2410 * @returns VBox status.
2411 * @param pVCpu The VMCPU handle.
2412 * @param pvDst The destination address.
2413 * @param GCPtrSrc The source address (GC pointer).
2414 * @param cb The number of bytes to read.
2415 */
2416VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
2417{
2418 PVM pVM = pVCpu->CTX_SUFF(pVM);
2419
2420 /*
2421 * Treat the first page as a special case.
2422 */
2423 if (!cb)
2424 return VINF_SUCCESS;
2425
2426 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PhysSimpleRead));
2427 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_MID_Z(Stat,PhysSimpleReadBytes), cb);
2428
2429 /* Take the PGM lock here, because many called functions take the lock for a very short period. That's counter-productive
2430 * when many VCPUs are fighting for the lock.
2431 */
2432 pgmLock(pVM);
2433
2434 /* map the 1st page */
2435 void const *pvSrc;
2436 PGMPAGEMAPLOCK Lock;
2437 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrSrc, &pvSrc, &Lock);
2438 if (RT_FAILURE(rc))
2439 {
2440 pgmUnlock(pVM);
2441 return rc;
2442 }
2443
2444 /* optimize for the case where access is completely within the first page. */
2445 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
2446 if (RT_LIKELY(cb <= cbPage))
2447 {
2448 memcpy(pvDst, pvSrc, cb);
2449 PGMPhysReleasePageMappingLock(pVM, &Lock);
2450 pgmUnlock(pVM);
2451 return VINF_SUCCESS;
2452 }
2453
2454 /* copy to the end of the page. */
2455 memcpy(pvDst, pvSrc, cbPage);
2456 PGMPhysReleasePageMappingLock(pVM, &Lock);
2457 GCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCPtrSrc + cbPage);
2458 pvDst = (uint8_t *)pvDst + cbPage;
2459 cb -= cbPage;
2460
2461 /*
2462 * Page by page.
2463 */
2464 for (;;)
2465 {
2466 /* map the page */
2467 rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrSrc, &pvSrc, &Lock);
2468 if (RT_FAILURE(rc))
2469 {
2470 pgmUnlock(pVM);
2471 return rc;
2472 }
2473
2474 /* last page? */
2475 if (cb <= PAGE_SIZE)
2476 {
2477 memcpy(pvDst, pvSrc, cb);
2478 PGMPhysReleasePageMappingLock(pVM, &Lock);
2479 pgmUnlock(pVM);
2480 return VINF_SUCCESS;
2481 }
2482
2483 /* copy the entire page and advance */
2484 memcpy(pvDst, pvSrc, PAGE_SIZE);
2485 PGMPhysReleasePageMappingLock(pVM, &Lock);
2486 GCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCPtrSrc + PAGE_SIZE);
2487 pvDst = (uint8_t *)pvDst + PAGE_SIZE;
2488 cb -= PAGE_SIZE;
2489 }
2490 /* won't ever get here. */
2491}
2492
2493
2494/**
2495 * Write to guest physical memory referenced by GC pointer.
2496 *
2497 * This function uses the current CR3/CR0/CR4 of the guest and will
2498 * bypass access handlers and not set dirty or accessed bits.
2499 *
2500 * @returns VBox status.
2501 * @param pVCpu The VMCPU handle.
2502 * @param GCPtrDst The destination address (GC pointer).
2503 * @param pvSrc The source address.
2504 * @param cb The number of bytes to write.
2505 */
2506VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2507{
2508 PVM pVM = pVCpu->CTX_SUFF(pVM);
2509
2510 /*
2511 * Treat the first page as a special case.
2512 */
2513 if (!cb)
2514 return VINF_SUCCESS;
2515
2516 STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PhysSimpleWrite));
2517 STAM_COUNTER_ADD(&pVM->pgm.s.CTX_MID_Z(Stat,PhysSimpleWriteBytes), cb);
2518
2519 /* map the 1st page */
2520 void *pvDst;
2521 PGMPAGEMAPLOCK Lock;
2522 int rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
2523 if (RT_FAILURE(rc))
2524 return rc;
2525
2526 /* optimize for the case where access is completely within the first page. */
2527 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2528 if (RT_LIKELY(cb <= cbPage))
2529 {
2530 memcpy(pvDst, pvSrc, cb);
2531 PGMPhysReleasePageMappingLock(pVM, &Lock);
2532 return VINF_SUCCESS;
2533 }
2534
2535 /* copy to the end of the page. */
2536 memcpy(pvDst, pvSrc, cbPage);
2537 PGMPhysReleasePageMappingLock(pVM, &Lock);
2538 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbPage);
2539 pvSrc = (const uint8_t *)pvSrc + cbPage;
2540 cb -= cbPage;
2541
2542 /*
2543 * Page by page.
2544 */
2545 for (;;)
2546 {
2547 /* map the page */
2548 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
2549 if (RT_FAILURE(rc))
2550 return rc;
2551
2552 /* last page? */
2553 if (cb <= PAGE_SIZE)
2554 {
2555 memcpy(pvDst, pvSrc, cb);
2556 PGMPhysReleasePageMappingLock(pVM, &Lock);
2557 return VINF_SUCCESS;
2558 }
2559
2560 /* copy the entire page and advance */
2561 memcpy(pvDst, pvSrc, PAGE_SIZE);
2562 PGMPhysReleasePageMappingLock(pVM, &Lock);
2563 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + PAGE_SIZE);
2564 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
2565 cb -= PAGE_SIZE;
2566 }
2567 /* won't ever get here. */
2568}
2569
2570
2571/**
2572 * Write to guest physical memory referenced by GC pointer and update the PTE.
2573 *
2574 * This function uses the current CR3/CR0/CR4 of the guest and will
2575 * bypass access handlers but will set any dirty and accessed bits in the PTE.
2576 *
2577 * If you don't want to set the dirty bit, use PGMPhysSimpleWriteGCPtr().
2578 *
2579 * @returns VBox status.
2580 * @param pVCpu The VMCPU handle.
2581 * @param GCPtrDst The destination address (GC pointer).
2582 * @param pvSrc The source address.
2583 * @param cb The number of bytes to write.
2584 */
2585VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2586{
2587 PVM pVM = pVCpu->CTX_SUFF(pVM);
2588
2589 /*
2590 * Treat the first page as a special case.
2591 * Btw. this is the same code as in PGMPhyssimpleWriteGCPtr excep for the PGMGstModifyPage.
2592 */
2593 if (!cb)
2594 return VINF_SUCCESS;
2595
2596 /* map the 1st page */
2597 void *pvDst;
2598 PGMPAGEMAPLOCK Lock;
2599 int rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
2600 if (RT_FAILURE(rc))
2601 return rc;
2602
2603 /* optimize for the case where access is completely within the first page. */
2604 size_t cbPage = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2605 if (RT_LIKELY(cb <= cbPage))
2606 {
2607 memcpy(pvDst, pvSrc, cb);
2608 PGMPhysReleasePageMappingLock(pVM, &Lock);
2609 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
2610 return VINF_SUCCESS;
2611 }
2612
2613 /* copy to the end of the page. */
2614 memcpy(pvDst, pvSrc, cbPage);
2615 PGMPhysReleasePageMappingLock(pVM, &Lock);
2616 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
2617 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + cbPage);
2618 pvSrc = (const uint8_t *)pvSrc + cbPage;
2619 cb -= cbPage;
2620
2621 /*
2622 * Page by page.
2623 */
2624 for (;;)
2625 {
2626 /* map the page */
2627 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrDst, &pvDst, &Lock);
2628 if (RT_FAILURE(rc))
2629 return rc;
2630
2631 /* last page? */
2632 if (cb <= PAGE_SIZE)
2633 {
2634 memcpy(pvDst, pvSrc, cb);
2635 PGMPhysReleasePageMappingLock(pVM, &Lock);
2636 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
2637 return VINF_SUCCESS;
2638 }
2639
2640 /* copy the entire page and advance */
2641 memcpy(pvDst, pvSrc, PAGE_SIZE);
2642 PGMPhysReleasePageMappingLock(pVM, &Lock);
2643 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D)); AssertRC(rc);
2644 GCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCPtrDst + PAGE_SIZE);
2645 pvSrc = (const uint8_t *)pvSrc + PAGE_SIZE;
2646 cb -= PAGE_SIZE;
2647 }
2648 /* won't ever get here. */
2649}
2650
2651
2652/**
2653 * Read from guest physical memory referenced by GC pointer.
2654 *
2655 * This function uses the current CR3/CR0/CR4 of the guest and will
2656 * respect access handlers and set accessed bits.
2657 *
2658 * @returns VBox status.
2659 * @param pVCpu The VMCPU handle.
2660 * @param pvDst The destination address.
2661 * @param GCPtrSrc The source address (GC pointer).
2662 * @param cb The number of bytes to read.
2663 * @thread The vCPU EMT.
2664 */
2665VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
2666{
2667 RTGCPHYS GCPhys;
2668 uint64_t fFlags;
2669 int rc;
2670 PVM pVM = pVCpu->CTX_SUFF(pVM);
2671
2672 /*
2673 * Anything to do?
2674 */
2675 if (!cb)
2676 return VINF_SUCCESS;
2677
2678 LogFlow(("PGMPhysReadGCPtr: %RGv %zu\n", GCPtrSrc, cb));
2679
2680 /*
2681 * Optimize reads within a single page.
2682 */
2683 if (((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2684 {
2685 /* Convert virtual to physical address + flags */
2686 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrSrc, &fFlags, &GCPhys);
2687 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrSrc), rc);
2688 GCPhys |= (RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK;
2689
2690 /* mark the guest page as accessed. */
2691 if (!(fFlags & X86_PTE_A))
2692 {
2693 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
2694 AssertRC(rc);
2695 }
2696
2697 return PGMPhysRead(pVM, GCPhys, pvDst, cb);
2698 }
2699
2700 /*
2701 * Page by page.
2702 */
2703 for (;;)
2704 {
2705 /* Convert virtual to physical address + flags */
2706 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrSrc, &fFlags, &GCPhys);
2707 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrSrc), rc);
2708 GCPhys |= (RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK;
2709
2710 /* mark the guest page as accessed. */
2711 if (!(fFlags & X86_PTE_A))
2712 {
2713 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
2714 AssertRC(rc);
2715 }
2716
2717 /* copy */
2718 size_t cbRead = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
2719 rc = PGMPhysRead(pVM, GCPhys, pvDst, cbRead);
2720 if (cbRead >= cb || RT_FAILURE(rc))
2721 return rc;
2722
2723 /* next */
2724 cb -= cbRead;
2725 pvDst = (uint8_t *)pvDst + cbRead;
2726 GCPtrSrc += cbRead;
2727 }
2728}
2729
2730
2731/**
2732 * Write to guest physical memory referenced by GC pointer.
2733 *
2734 * This function uses the current CR3/CR0/CR4 of the guest and will
2735 * respect access handlers and set dirty and accessed bits.
2736 *
2737 * @returns VBox status.
2738 * @retval VINF_SUCCESS.
2739 * @retval VERR_PGM_PHYS_WR_HIT_HANDLER in R0 and GC, NEVER in R3.
2740 *
2741 * @param pVCpu The VMCPU handle.
2742 * @param GCPtrDst The destination address (GC pointer).
2743 * @param pvSrc The source address.
2744 * @param cb The number of bytes to write.
2745 */
2746VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2747{
2748 RTGCPHYS GCPhys;
2749 uint64_t fFlags;
2750 int rc;
2751 PVM pVM = pVCpu->CTX_SUFF(pVM);
2752
2753 /*
2754 * Anything to do?
2755 */
2756 if (!cb)
2757 return VINF_SUCCESS;
2758
2759 LogFlow(("PGMPhysWriteGCPtr: %RGv %zu\n", GCPtrDst, cb));
2760
2761 /*
2762 * Optimize writes within a single page.
2763 */
2764 if (((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2765 {
2766 /* Convert virtual to physical address + flags */
2767 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrDst, &fFlags, &GCPhys);
2768 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrDst), rc);
2769 GCPhys |= (RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK;
2770
2771 /* Mention when we ignore X86_PTE_RW... */
2772 if (!(fFlags & X86_PTE_RW))
2773 Log(("PGMPhysGCPtr2GCPhys: Writing to RO page %RGv %#x\n", GCPtrDst, cb));
2774
2775 /* Mark the guest page as accessed and dirty if necessary. */
2776 if ((fFlags & (X86_PTE_A | X86_PTE_D)) != (X86_PTE_A | X86_PTE_D))
2777 {
2778 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
2779 AssertRC(rc);
2780 }
2781
2782 return PGMPhysWrite(pVM, GCPhys, pvSrc, cb);
2783 }
2784
2785 /*
2786 * Page by page.
2787 */
2788 for (;;)
2789 {
2790 /* Convert virtual to physical address + flags */
2791 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, (RTGCUINTPTR)GCPtrDst, &fFlags, &GCPhys);
2792 AssertMsgRCReturn(rc, ("GetPage failed with %Rrc for %RGv\n", rc, GCPtrDst), rc);
2793 GCPhys |= (RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK;
2794
2795 /* Mention when we ignore X86_PTE_RW... */
2796 if (!(fFlags & X86_PTE_RW))
2797 Log(("PGMPhysGCPtr2GCPhys: Writing to RO page %RGv %#x\n", GCPtrDst, cb));
2798
2799 /* Mark the guest page as accessed and dirty if necessary. */
2800 if ((fFlags & (X86_PTE_A | X86_PTE_D)) != (X86_PTE_A | X86_PTE_D))
2801 {
2802 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
2803 AssertRC(rc);
2804 }
2805
2806 /* copy */
2807 size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2808 int rc = PGMPhysWrite(pVM, GCPhys, pvSrc, cbWrite);
2809 if (cbWrite >= cb || RT_FAILURE(rc))
2810 return rc;
2811
2812 /* next */
2813 cb -= cbWrite;
2814 pvSrc = (uint8_t *)pvSrc + cbWrite;
2815 GCPtrDst += cbWrite;
2816 }
2817}
2818
2819
2820/**
2821 * Performs a read of guest virtual memory for instruction emulation.
2822 *
2823 * This will check permissions, raise exceptions and update the access bits.
2824 *
2825 * The current implementation will bypass all access handlers. It may later be
2826 * changed to at least respect MMIO.
2827 *
2828 *
2829 * @returns VBox status code suitable to scheduling.
2830 * @retval VINF_SUCCESS if the read was performed successfully.
2831 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
2832 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
2833 *
2834 * @param pVCpu The VMCPU handle.
2835 * @param pCtxCore The context core.
2836 * @param pvDst Where to put the bytes we've read.
2837 * @param GCPtrSrc The source address.
2838 * @param cb The number of bytes to read. Not more than a page.
2839 *
2840 * @remark This function will dynamically map physical pages in GC. This may unmap
2841 * mappings done by the caller. Be careful!
2842 */
2843VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb)
2844{
2845 PVM pVM = pVCpu->CTX_SUFF(pVM);
2846 Assert(cb <= PAGE_SIZE);
2847
2848/** @todo r=bird: This isn't perfect!
2849 * -# It's not checking for reserved bits being 1.
2850 * -# It's not correctly dealing with the access bit.
2851 * -# It's not respecting MMIO memory or any other access handlers.
2852 */
2853 /*
2854 * 1. Translate virtual to physical. This may fault.
2855 * 2. Map the physical address.
2856 * 3. Do the read operation.
2857 * 4. Set access bits if required.
2858 */
2859 int rc;
2860 unsigned cb1 = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
2861 if (cb <= cb1)
2862 {
2863 /*
2864 * Not crossing pages.
2865 */
2866 RTGCPHYS GCPhys;
2867 uint64_t fFlags;
2868 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags, &GCPhys);
2869 if (RT_SUCCESS(rc))
2870 {
2871 /** @todo we should check reserved bits ... */
2872 void *pvSrc;
2873 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pvSrc);
2874 switch (rc)
2875 {
2876 case VINF_SUCCESS:
2877 Log(("PGMPhysInterpretedRead: pvDst=%p pvSrc=%p cb=%d\n", pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb));
2878 memcpy(pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
2879 break;
2880 case VERR_PGM_PHYS_PAGE_RESERVED:
2881 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2882 memset(pvDst, 0, cb); /** @todo this is wrong, it should be 0xff */
2883 break;
2884 default:
2885 return rc;
2886 }
2887
2888 /** @todo access bit emulation isn't 100% correct. */
2889 if (!(fFlags & X86_PTE_A))
2890 {
2891 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2892 AssertRC(rc);
2893 }
2894 return VINF_SUCCESS;
2895 }
2896 }
2897 else
2898 {
2899 /*
2900 * Crosses pages.
2901 */
2902 size_t cb2 = cb - cb1;
2903 uint64_t fFlags1;
2904 RTGCPHYS GCPhys1;
2905 uint64_t fFlags2;
2906 RTGCPHYS GCPhys2;
2907 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags1, &GCPhys1);
2908 if (RT_SUCCESS(rc))
2909 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc + cb1, &fFlags2, &GCPhys2);
2910 if (RT_SUCCESS(rc))
2911 {
2912 /** @todo we should check reserved bits ... */
2913 AssertMsgFailed(("cb=%d cb1=%d cb2=%d GCPtrSrc=%RGv\n", cb, cb1, cb2, GCPtrSrc));
2914 void *pvSrc1;
2915 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys1, &pvSrc1);
2916 switch (rc)
2917 {
2918 case VINF_SUCCESS:
2919 memcpy(pvDst, (uint8_t *)pvSrc1 + (GCPtrSrc & PAGE_OFFSET_MASK), cb1);
2920 break;
2921 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2922 memset(pvDst, 0, cb1); /** @todo this is wrong, it should be 0xff */
2923 break;
2924 default:
2925 return rc;
2926 }
2927
2928 void *pvSrc2;
2929 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys2, &pvSrc2);
2930 switch (rc)
2931 {
2932 case VINF_SUCCESS:
2933 memcpy((uint8_t *)pvDst + cb1, pvSrc2, cb2);
2934 break;
2935 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2936 memset((uint8_t *)pvDst + cb1, 0, cb2); /** @todo this is wrong, it should be 0xff */
2937 break;
2938 default:
2939 return rc;
2940 }
2941
2942 if (!(fFlags1 & X86_PTE_A))
2943 {
2944 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2945 AssertRC(rc);
2946 }
2947 if (!(fFlags2 & X86_PTE_A))
2948 {
2949 rc = PGMGstModifyPage(pVCpu, GCPtrSrc + cb1, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2950 AssertRC(rc);
2951 }
2952 return VINF_SUCCESS;
2953 }
2954 }
2955
2956 /*
2957 * Raise a #PF.
2958 */
2959 uint32_t uErr;
2960
2961 /* Get the current privilege level. */
2962 uint32_t cpl = CPUMGetGuestCPL(pVCpu, pCtxCore);
2963 switch (rc)
2964 {
2965 case VINF_SUCCESS:
2966 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
2967 break;
2968
2969 case VERR_PAGE_NOT_PRESENT:
2970 case VERR_PAGE_TABLE_NOT_PRESENT:
2971 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
2972 break;
2973
2974 default:
2975 AssertMsgFailed(("rc=%Rrc GCPtrSrc=%RGv cb=%#x\n", rc, GCPtrSrc, cb));
2976 return rc;
2977 }
2978 Log(("PGMPhysInterpretedRead: GCPtrSrc=%RGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr));
2979 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc);
2980}
2981
2982
2983/**
2984 * Performs a read of guest virtual memory for instruction emulation.
2985 *
2986 * This will check permissions, raise exceptions and update the access bits.
2987 *
2988 * The current implementation will bypass all access handlers. It may later be
2989 * changed to at least respect MMIO.
2990 *
2991 *
2992 * @returns VBox status code suitable to scheduling.
2993 * @retval VINF_SUCCESS if the read was performed successfully.
2994 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
2995 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
2996 *
2997 * @param pVCpu The VMCPU handle.
2998 * @param pCtxCore The context core.
2999 * @param pvDst Where to put the bytes we've read.
3000 * @param GCPtrSrc The source address.
3001 * @param cb The number of bytes to read. Not more than a page.
3002 * @param fRaiseTrap If set the trap will be raised on as per spec, if clear
3003 * an appropriate error status will be returned (no
3004 * informational at all).
3005 *
3006 *
3007 * @remarks Takes the PGM lock.
3008 * @remarks A page fault on the 2nd page of the access will be raised without
3009 * writing the bits on the first page since we're ASSUMING that the
3010 * caller is emulating an instruction access.
3011 * @remarks This function will dynamically map physical pages in GC. This may
3012 * unmap mappings done by the caller. Be careful!
3013 */
3014VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap)
3015{
3016 PVM pVM = pVCpu->CTX_SUFF(pVM);
3017 Assert(cb <= PAGE_SIZE);
3018
3019 /*
3020 * 1. Translate virtual to physical. This may fault.
3021 * 2. Map the physical address.
3022 * 3. Do the read operation.
3023 * 4. Set access bits if required.
3024 */
3025 int rc;
3026 unsigned cb1 = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
3027 if (cb <= cb1)
3028 {
3029 /*
3030 * Not crossing pages.
3031 */
3032 RTGCPHYS GCPhys;
3033 uint64_t fFlags;
3034 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags, &GCPhys);
3035 if (RT_SUCCESS(rc))
3036 {
3037 if (1) /** @todo we should check reserved bits ... */
3038 {
3039 const void *pvSrc;
3040 PGMPAGEMAPLOCK Lock;
3041 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvSrc, &Lock);
3042 switch (rc)
3043 {
3044 case VINF_SUCCESS:
3045 Log(("PGMPhysInterpretedReadNoHandlers: pvDst=%p pvSrc=%p (%RGv) cb=%d\n",
3046 pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), GCPtrSrc, cb));
3047 memcpy(pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
3048 break;
3049 case VERR_PGM_PHYS_PAGE_RESERVED:
3050 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3051 memset(pvDst, 0xff, cb);
3052 break;
3053 default:
3054 AssertMsgFailed(("%Rrc\n", rc));
3055 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3056 return rc;
3057 }
3058 PGMPhysReleasePageMappingLock(pVM, &Lock);
3059
3060 if (!(fFlags & X86_PTE_A))
3061 {
3062 /** @todo access bit emulation isn't 100% correct. */
3063 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3064 AssertRC(rc);
3065 }
3066 return VINF_SUCCESS;
3067 }
3068 }
3069 }
3070 else
3071 {
3072 /*
3073 * Crosses pages.
3074 */
3075 size_t cb2 = cb - cb1;
3076 uint64_t fFlags1;
3077 RTGCPHYS GCPhys1;
3078 uint64_t fFlags2;
3079 RTGCPHYS GCPhys2;
3080 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc, &fFlags1, &GCPhys1);
3081 if (RT_SUCCESS(rc))
3082 {
3083 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrSrc + cb1, &fFlags2, &GCPhys2);
3084 if (RT_SUCCESS(rc))
3085 {
3086 if (1) /** @todo we should check reserved bits ... */
3087 {
3088 const void *pvSrc;
3089 PGMPAGEMAPLOCK Lock;
3090 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys1, &pvSrc, &Lock);
3091 switch (rc)
3092 {
3093 case VINF_SUCCESS:
3094 Log(("PGMPhysInterpretedReadNoHandlers: pvDst=%p pvSrc=%p (%RGv) cb=%d [2]\n",
3095 pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), GCPtrSrc, cb1));
3096 memcpy(pvDst, (const uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb1);
3097 PGMPhysReleasePageMappingLock(pVM, &Lock);
3098 break;
3099 case VERR_PGM_PHYS_PAGE_RESERVED:
3100 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3101 memset(pvDst, 0xff, cb1);
3102 break;
3103 default:
3104 AssertMsgFailed(("%Rrc\n", rc));
3105 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3106 return rc;
3107 }
3108
3109 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys2, &pvSrc, &Lock);
3110 switch (rc)
3111 {
3112 case VINF_SUCCESS:
3113 memcpy((uint8_t *)pvDst + cb1, pvSrc, cb2);
3114 PGMPhysReleasePageMappingLock(pVM, &Lock);
3115 break;
3116 case VERR_PGM_PHYS_PAGE_RESERVED:
3117 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3118 memset((uint8_t *)pvDst + cb1, 0xff, cb2);
3119 break;
3120 default:
3121 AssertMsgFailed(("%Rrc\n", rc));
3122 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3123 return rc;
3124 }
3125
3126 if (!(fFlags1 & X86_PTE_A))
3127 {
3128 rc = PGMGstModifyPage(pVCpu, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3129 AssertRC(rc);
3130 }
3131 if (!(fFlags2 & X86_PTE_A))
3132 {
3133 rc = PGMGstModifyPage(pVCpu, GCPtrSrc + cb1, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
3134 AssertRC(rc);
3135 }
3136 return VINF_SUCCESS;
3137 }
3138 /* sort out which page */
3139 }
3140 else
3141 GCPtrSrc += cb1; /* fault on 2nd page */
3142 }
3143 }
3144
3145 /*
3146 * Raise a #PF if we're allowed to do that.
3147 */
3148 /* Calc the error bits. */
3149 uint32_t cpl = CPUMGetGuestCPL(pVCpu, pCtxCore);
3150 uint32_t uErr;
3151 switch (rc)
3152 {
3153 case VINF_SUCCESS:
3154 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
3155 rc = VERR_ACCESS_DENIED;
3156 break;
3157
3158 case VERR_PAGE_NOT_PRESENT:
3159 case VERR_PAGE_TABLE_NOT_PRESENT:
3160 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
3161 break;
3162
3163 default:
3164 AssertMsgFailed(("rc=%Rrc GCPtrSrc=%RGv cb=%#x\n", rc, GCPtrSrc, cb));
3165 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3166 return rc;
3167 }
3168 if (fRaiseTrap)
3169 {
3170 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrSrc, cb, uErr));
3171 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc);
3172 }
3173 Log(("PGMPhysInterpretedReadNoHandlers: GCPtrSrc=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrSrc, cb, uErr));
3174 return rc;
3175}
3176
3177
3178/**
3179 * Performs a write to guest virtual memory for instruction emulation.
3180 *
3181 * This will check permissions, raise exceptions and update the dirty and access
3182 * bits.
3183 *
3184 * @returns VBox status code suitable to scheduling.
3185 * @retval VINF_SUCCESS if the read was performed successfully.
3186 * @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
3187 * @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
3188 *
3189 * @param pVCpu The VMCPU handle.
3190 * @param pCtxCore The context core.
3191 * @param GCPtrDst The destination address.
3192 * @param pvSrc What to write.
3193 * @param cb The number of bytes to write. Not more than a page.
3194 * @param fRaiseTrap If set the trap will be raised on as per spec, if clear
3195 * an appropriate error status will be returned (no
3196 * informational at all).
3197 *
3198 * @remarks Takes the PGM lock.
3199 * @remarks A page fault on the 2nd page of the access will be raised without
3200 * writing the bits on the first page since we're ASSUMING that the
3201 * caller is emulating an instruction access.
3202 * @remarks This function will dynamically map physical pages in GC. This may
3203 * unmap mappings done by the caller. Be careful!
3204 */
3205VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, bool fRaiseTrap)
3206{
3207 Assert(cb <= PAGE_SIZE);
3208 PVM pVM = pVCpu->CTX_SUFF(pVM);
3209
3210 /*
3211 * 1. Translate virtual to physical. This may fault.
3212 * 2. Map the physical address.
3213 * 3. Do the write operation.
3214 * 4. Set access bits if required.
3215 */
3216 int rc;
3217 unsigned cb1 = PAGE_SIZE - (GCPtrDst & PAGE_OFFSET_MASK);
3218 if (cb <= cb1)
3219 {
3220 /*
3221 * Not crossing pages.
3222 */
3223 RTGCPHYS GCPhys;
3224 uint64_t fFlags;
3225 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst, &fFlags, &GCPhys);
3226 if (RT_SUCCESS(rc))
3227 {
3228 if ( (fFlags & X86_PTE_RW) /** @todo Also check reserved bits. */
3229 || ( !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP)
3230 && CPUMGetGuestCPL(pVCpu, pCtxCore) <= 2) ) /** @todo it's 2, right? Check cpl check below as well. */
3231 {
3232 void *pvDst;
3233 PGMPAGEMAPLOCK Lock;
3234 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys, &pvDst, &Lock);
3235 switch (rc)
3236 {
3237 case VINF_SUCCESS:
3238 Log(("PGMPhysInterpretedWriteNoHandlers: pvDst=%p (%RGv) pvSrc=%p cb=%d\n",
3239 (uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), GCPtrDst, pvSrc, cb));
3240 memcpy((uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), pvSrc, cb);
3241 PGMPhysReleasePageMappingLock(pVM, &Lock);
3242 break;
3243 case VERR_PGM_PHYS_PAGE_RESERVED:
3244 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3245 /* bit bucket */
3246 break;
3247 default:
3248 AssertMsgFailed(("%Rrc\n", rc));
3249 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3250 return rc;
3251 }
3252
3253 if (!(fFlags & (X86_PTE_A | X86_PTE_D)))
3254 {
3255 /** @todo dirty & access bit emulation isn't 100% correct. */
3256 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, X86_PTE_A | X86_PTE_D, ~(uint64_t)(X86_PTE_A | X86_PTE_D));
3257 AssertRC(rc);
3258 }
3259 return VINF_SUCCESS;
3260 }
3261 rc = VERR_ACCESS_DENIED;
3262 }
3263 }
3264 else
3265 {
3266 /*
3267 * Crosses pages.
3268 */
3269 size_t cb2 = cb - cb1;
3270 uint64_t fFlags1;
3271 RTGCPHYS GCPhys1;
3272 uint64_t fFlags2;
3273 RTGCPHYS GCPhys2;
3274 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst, &fFlags1, &GCPhys1);
3275 if (RT_SUCCESS(rc))
3276 {
3277 rc = PGM_GST_PFN(GetPage,pVCpu)(pVCpu, GCPtrDst + cb1, &fFlags2, &GCPhys2);
3278 if (RT_SUCCESS(rc))
3279 {
3280 if ( ( (fFlags1 & X86_PTE_RW) /** @todo Also check reserved bits. */
3281 && (fFlags2 & X86_PTE_RW))
3282 || ( !(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP)
3283 && CPUMGetGuestCPL(pVCpu, pCtxCore) <= 2) )
3284 {
3285 void *pvDst;
3286 PGMPAGEMAPLOCK Lock;
3287 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys1, &pvDst, &Lock);
3288 switch (rc)
3289 {
3290 case VINF_SUCCESS:
3291 Log(("PGMPhysInterpretedWriteNoHandlers: pvDst=%p (%RGv) pvSrc=%p cb=%d\n",
3292 (uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), GCPtrDst, pvSrc, cb1));
3293 memcpy((uint8_t *)pvDst + (GCPtrDst & PAGE_OFFSET_MASK), pvSrc, cb1);
3294 PGMPhysReleasePageMappingLock(pVM, &Lock);
3295 break;
3296 case VERR_PGM_PHYS_PAGE_RESERVED:
3297 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3298 /* bit bucket */
3299 break;
3300 default:
3301 AssertMsgFailed(("%Rrc\n", rc));
3302 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3303 return rc;
3304 }
3305
3306 rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys2, &pvDst, &Lock);
3307 switch (rc)
3308 {
3309 case VINF_SUCCESS:
3310 memcpy(pvDst, (const uint8_t *)pvSrc + cb1, cb2);
3311 PGMPhysReleasePageMappingLock(pVM, &Lock);
3312 break;
3313 case VERR_PGM_PHYS_PAGE_RESERVED:
3314 case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
3315 /* bit bucket */
3316 break;
3317 default:
3318 AssertMsgFailed(("%Rrc\n", rc));
3319 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3320 return rc;
3321 }
3322
3323 if (!(fFlags1 & (X86_PTE_A | X86_PTE_RW)))
3324 {
3325 rc = PGMGstModifyPage(pVCpu, GCPtrDst, 1, (X86_PTE_A | X86_PTE_RW), ~(uint64_t)(X86_PTE_A | X86_PTE_RW));
3326 AssertRC(rc);
3327 }
3328 if (!(fFlags2 & (X86_PTE_A | X86_PTE_RW)))
3329 {
3330 rc = PGMGstModifyPage(pVCpu, GCPtrDst + cb1, 1, (X86_PTE_A | X86_PTE_RW), ~(uint64_t)(X86_PTE_A | X86_PTE_RW));
3331 AssertRC(rc);
3332 }
3333 return VINF_SUCCESS;
3334 }
3335 if ((fFlags1 & (X86_PTE_RW)) == X86_PTE_RW)
3336 GCPtrDst += cb1; /* fault on the 2nd page. */
3337 rc = VERR_ACCESS_DENIED;
3338 }
3339 else
3340 GCPtrDst += cb1; /* fault on the 2nd page. */
3341 }
3342 }
3343
3344 /*
3345 * Raise a #PF if we're allowed to do that.
3346 */
3347 /* Calc the error bits. */
3348 uint32_t uErr;
3349 uint32_t cpl = CPUMGetGuestCPL(pVCpu, pCtxCore);
3350 switch (rc)
3351 {
3352 case VINF_SUCCESS:
3353 uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD | X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
3354 rc = VERR_ACCESS_DENIED;
3355 break;
3356
3357 case VERR_ACCESS_DENIED:
3358 uErr = (cpl >= 2) ? X86_TRAP_PF_RW | X86_TRAP_PF_US : X86_TRAP_PF_RW;
3359 break;
3360
3361 case VERR_PAGE_NOT_PRESENT:
3362 case VERR_PAGE_TABLE_NOT_PRESENT:
3363 uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
3364 break;
3365
3366 default:
3367 AssertMsgFailed(("rc=%Rrc GCPtrDst=%RGv cb=%#x\n", rc, GCPtrDst, cb));
3368 AssertReturn(RT_FAILURE(rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
3369 return rc;
3370 }
3371 if (fRaiseTrap)
3372 {
3373 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> Raised #PF(%#x)\n", GCPtrDst, cb, uErr));
3374 return TRPMRaiseXcptErrCR2(pVCpu, pCtxCore, X86_XCPT_PF, uErr, GCPtrDst);
3375 }
3376 Log(("PGMPhysInterpretedWriteNoHandlers: GCPtrDst=%RGv cb=%#x -> #PF(%#x) [!raised]\n", GCPtrDst, cb, uErr));
3377 return rc;
3378}
3379
3380
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