VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h@ 106362

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1/* $Id: PGMAllGstSlatEpt.cpp.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest EPT SLAT - All context code.
4 */
5
6/*
7 * Copyright (C) 2021-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#if PGM_SLAT_TYPE != PGM_SLAT_TYPE_EPT
29# error "Unsupported SLAT type."
30#endif
31
32/**
33 * Checks if the EPT PTE permissions are valid.
34 *
35 * @returns @c true if valid, @c false otherwise.
36 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
37 * @param uEntry The EPT page table entry to check.
38 *
39 * @remarks Current this ASSUMES @c uEntry is present (debug asserted)!
40 */
41DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
42{
43 if (!(uEntry & EPT_E_READ))
44 {
45 if (uEntry & EPT_E_WRITE)
46 return false;
47
48 /*
49 * Currently all callers of this function check for the present mask prior
50 * to calling this function. Hence, the execute bit must be set now.
51 */
52 Assert(uEntry & EPT_E_EXECUTE);
53 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
54 if (pVCpu->pgm.s.uEptVpidCapMsr & VMX_BF_EPT_VPID_CAP_EXEC_ONLY_MASK)
55 return true;
56 return false;
57 }
58 return true;
59}
60
61
62/**
63 * Checks if the EPT memory type is valid.
64 *
65 * @returns @c true if valid, @c false otherwise.
66 * @param uEntry The EPT page table entry to check.
67 * @param uLevel The page table walk level.
68 */
69DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(uint64_t uEntry, uint8_t uLevel)
70{
71 Assert(uLevel <= 3 && uLevel >= 1); NOREF(uLevel);
72 uint8_t const fEptMemTypeMask = uEntry & VMX_BF_EPT_PT_MEMTYPE_MASK;
73 switch (fEptMemTypeMask)
74 {
75 case EPT_E_MEMTYPE_WB:
76 case EPT_E_MEMTYPE_UC:
77 case EPT_E_MEMTYPE_WP:
78 case EPT_E_MEMTYPE_WT:
79 case EPT_E_MEMTYPE_WC:
80 return true;
81 }
82 return false;
83}
84
85
86/**
87 * Updates page walk result info when a not-present page is encountered.
88 *
89 * @returns VERR_PAGE_TABLE_NOT_PRESENT.
90 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
91 * @param pWalk The page walk info to update.
92 * @param uEntry The EPT PTE that is not present.
93 * @param uLevel The page table walk level.
94 */
95DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
96{
97 static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
98 uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
99 uint8_t const fConvertible = RT_BOOL(uLevel == 1 || (uEntry & EPT_E_BIT_LEAF));
100 uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
101
102 pWalk->fNotPresent = true;
103 pWalk->uLevel = uLevel;
104 pWalk->fFailed = s_afEptViolations[idxViolationType] | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
105 return VERR_PAGE_TABLE_NOT_PRESENT;
106}
107
108
109/**
110 * Updates page walk result info when a bad physical address is encountered.
111 *
112 * @returns VERR_PAGE_TABLE_NOT_PRESENT .
113 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
114 * @param pWalk The page walk info to update.
115 * @param uLevel The page table walk level.
116 * @param rc The error code that caused this bad physical address situation.
117 */
118DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
119{
120 AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
121 pWalk->fBadPhysAddr = true;
122 pWalk->uLevel = uLevel;
123 pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
124 return VERR_PAGE_TABLE_NOT_PRESENT;
125}
126
127
128/**
129 * Updates page walk result info when reserved bits are encountered.
130 *
131 * @returns VERR_PAGE_TABLE_NOT_PRESENT.
132 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
133 * @param pWalk The page walk info to update.
134 * @param uLevel The page table walk level.
135 */
136DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
137{
138 NOREF(pVCpu);
139 pWalk->fRsvdError = true;
140 pWalk->uLevel = uLevel;
141 pWalk->fFailed = PGM_WALKFAIL_EPT_MISCONFIG | ((uint32_t)uLevel << PGM_WALKFAIL_LEVEL_SHIFT);
142 return VERR_PAGE_TABLE_NOT_PRESENT;
143}
144
145
146/**
147 * Walks the guest's EPT page table (second-level address translation).
148 *
149 * @returns VBox status code.
150 * @retval VINF_SUCCESS on success.
151 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
152 *
153 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
154 * @param GCPhysNested The nested-guest physical address to walk.
155 * @param fIsLinearAddrValid Whether the linear-address in @c GCPtrNested caused
156 * this page walk.
157 * @param GCPtrNested The nested-guest linear address that caused this
158 * translation. If @c fIsLinearAddrValid is false, pass
159 * 0.
160 * @param pWalk The page walk info.
161 * @param pSlatWalk The SLAT mode specific page walk info.
162 */
163DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(Walk)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
164 PPGMPTWALK pWalk, PSLATPTWALK pSlatWalk)
165{
166 Assert(fIsLinearAddrValid || GCPtrNested == 0);
167
168 /*
169 * Init walk structures.
170 */
171 RT_ZERO(*pWalk);
172 RT_ZERO(*pSlatWalk);
173
174 pWalk->GCPtr = GCPtrNested;
175 pWalk->GCPhysNested = GCPhysNested;
176 pWalk->fIsLinearAddrValid = fIsLinearAddrValid;
177 pWalk->fIsSlat = true;
178
179 /*
180 * Figure out EPT attributes that are cumulative (logical-AND) across page walks.
181 * - R, W, X_SUPER are unconditionally cumulative.
182 * See Intel spec. Table 26-7 "Exit Qualification for EPT Violations".
183 *
184 * - X_USER is cumulative but relevant only when mode-based execute control for EPT
185 * which we currently don't support it (asserted below).
186 *
187 * - MEMTYPE is not cumulative and only applicable to the final paging entry.
188 *
189 * - A, D EPT bits map to the regular page-table bit positions. Thus, they're not
190 * included in the mask below and handled separately. Accessed bits are
191 * cumulative but dirty bits are not cumulative as they're only applicable to
192 * the final paging entry.
193 */
194 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
195 uint64_t const fEptAndMask = ( PGM_PTATTRS_EPT_R_MASK
196 | PGM_PTATTRS_EPT_W_MASK
197 | PGM_PTATTRS_EPT_X_SUPER_MASK) & PGM_PTATTRS_EPT_MASK;
198
199 /*
200 * Do the walk.
201 */
202 uint64_t fEffective;
203 {
204 /*
205 * EPTP.
206 *
207 * We currently only support 4-level EPT paging.
208 * EPT 5-level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
209 * but for some reason seems to have been removed from subsequent specs.
210 */
211 int const rc = pgmGstGetEptPML4PtrEx(pVCpu, &pSlatWalk->pPml4);
212 if (RT_SUCCESS(rc))
213 { /* likely */ }
214 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
215 }
216 {
217 /*
218 * PML4E.
219 */
220 PEPTPML4E pPml4e;
221 pSlatWalk->pPml4e = pPml4e = &pSlatWalk->pPml4->a[(GCPhysNested >> SLAT_PML4_SHIFT) & SLAT_PML4_MASK];
222 EPTPML4E Pml4e;
223 pSlatWalk->Pml4e.u = Pml4e.u = pPml4e->u;
224
225 if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
226 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
227
228 if (RT_LIKELY( SLAT_IS_PML4E_VALID(pVCpu, Pml4e)
229 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pml4e.u)))
230 { /* likely */ }
231 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 4);
232
233 uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK;
234 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
235 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
236 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
237 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
238 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
239 fEffective = RT_BF_MAKE(PGM_PTATTRS_R, fRead)
240 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
241 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
242 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
243 | fEptAndBits;
244 pWalk->fEffective = fEffective;
245
246 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & EPT_PML4E_PG_MASK, &pSlatWalk->pPdpt);
247 if (RT_SUCCESS(rc)) { /* probable */ }
248 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
249 }
250 {
251 /*
252 * PDPTE.
253 */
254 PEPTPDPTE pPdpte;
255 pSlatWalk->pPdpte = pPdpte = &pSlatWalk->pPdpt->a[(GCPhysNested >> SLAT_PDPT_SHIFT) & SLAT_PDPT_MASK];
256 EPTPDPTE Pdpte;
257 pSlatWalk->Pdpte.u = Pdpte.u = pPdpte->u;
258
259 if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ }
260 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
261
262 /* The order of the following "if" and "else if" statements matter. */
263 if ( SLAT_IS_PDPE_VALID(pVCpu, Pdpte)
264 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u))
265 {
266 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK;
267 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
268 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
269 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
270 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
271 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
272 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
273 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
274 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
275 | fEptAndBits;
276 fEffective |= RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute);
277 pWalk->fEffective = fEffective;
278 }
279 else if ( SLAT_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
280 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u)
281 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
282 {
283 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK;
284 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
285 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
286 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
287 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
288 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
289 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
290 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
291 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
292 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
293 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
294 | fEptAndBits;
295 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
296 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType)
297 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute);
298 pWalk->fEffective = fEffective;
299
300 pWalk->fGigantPage = true;
301 pWalk->fSucceeded = true;
302 pWalk->GCPhys = SLAT_GET_PDPE1G_GCPHYS(pVCpu, Pdpte)
303 | (GCPhysNested & SLAT_PAGE_1G_OFFSET_MASK);
304 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
305 return VINF_SUCCESS;
306 }
307 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 3);
308
309 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pSlatWalk->pPd);
310 if (RT_SUCCESS(rc)) { /* probable */ }
311 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
312 }
313 {
314 /*
315 * PDE.
316 */
317 PSLATPDE pPde;
318 pSlatWalk->pPde = pPde = &pSlatWalk->pPd->a[(GCPhysNested >> SLAT_PD_SHIFT) & SLAT_PD_MASK];
319 SLATPDE Pde;
320 pSlatWalk->Pde.u = Pde.u = pPde->u;
321
322 if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
323 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
324
325 /* The order of the following "if" and "else if" statements matter. */
326 if ( SLAT_IS_PDE_VALID(pVCpu, Pde)
327 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u))
328 {
329 uint64_t const fEptAttrs = Pde.u & EPT_PDE_ATTR_MASK;
330 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
331 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
332 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
333 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
334 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
335 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
336 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
337 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
338 | fEptAndBits;
339 fEffective |= RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute);
340 pWalk->fEffective = fEffective;
341 }
342 else if ( SLAT_IS_BIG_PDE_VALID(pVCpu, Pde)
343 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u)
344 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
345 {
346 uint64_t const fEptAttrs = Pde.u & EPT_PDE2M_ATTR_MASK;
347 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
348 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
349 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
350 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
351 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
352 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
353 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
354 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
355 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
356 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
357 | fEptAndBits;
358 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
359 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType)
360 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute);
361 pWalk->fEffective = fEffective;
362
363 pWalk->fBigPage = true;
364 pWalk->fSucceeded = true;
365 pWalk->GCPhys = SLAT_GET_PDE2M_GCPHYS(pVCpu, Pde)
366 | (GCPhysNested & SLAT_PAGE_2M_OFFSET_MASK);
367 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
368 return VINF_SUCCESS;
369 }
370 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 2);
371
372 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pde.u & EPT_PDE_PG_MASK, &pSlatWalk->pPt);
373 if (RT_SUCCESS(rc)) { /* probable */ }
374 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
375 }
376 {
377 /*
378 * PTE.
379 */
380 PSLATPTE pPte;
381 pSlatWalk->pPte = pPte = &pSlatWalk->pPt->a[(GCPhysNested >> SLAT_PT_SHIFT) & SLAT_PT_MASK];
382 SLATPTE Pte;
383 pSlatWalk->Pte.u = Pte.u = pPte->u;
384
385 if (SLAT_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
386 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pte.u, 1);
387
388 if ( SLAT_IS_PTE_VALID(pVCpu, Pte)
389 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pte.u)
390 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
391 { /* likely*/ }
392 else
393 return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 1);
394
395 uint64_t const fEptAttrs = Pte.u & EPT_PTE_ATTR_MASK;
396 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
397 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
398 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
399 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
400 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
401 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
402 uint64_t const fEptAndBits = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fEptAndMask;
403 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
404 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
405 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
406 | fEptAndBits;
407 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
408 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType)
409 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute);
410 pWalk->fEffective = fEffective;
411
412 pWalk->fSucceeded = true;
413 pWalk->GCPhys = SLAT_GET_PTE_GCPHYS(pVCpu, Pte) | (GCPhysNested & GUEST_PAGE_OFFSET_MASK);
414 return VINF_SUCCESS;
415 }
416}
417
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