VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h@ 94991

Last change on this file since 94991 was 94983, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Assertion to ensure we don't need to mask twice.
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1/* $Id: PGMAllGstSlatEpt.cpp.h 94983 2022-05-11 09:17:50Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest EPT SLAT - All context code.
4 */
5
6/*
7 * Copyright (C) 2021-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#if PGM_GST_TYPE == PGM_TYPE_EPT
19DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
20{
21 if (!(uEntry & EPT_E_READ))
22 {
23 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
24 Assert(!RT_BF_GET(pVCpu->pgm.s.uEptVpidCapMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY));
25 NOREF(pVCpu);
26 if (uEntry & (EPT_E_WRITE | EPT_E_EXECUTE))
27 return false;
28 }
29 return true;
30}
31
32
33DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(uint64_t uEntry, uint8_t uLevel)
34{
35 Assert(uLevel <= 3 && uLevel >= 1); NOREF(uLevel);
36 uint8_t const fEptMemTypeMask = uEntry & VMX_BF_EPT_PT_MEMTYPE_MASK;
37 switch (fEptMemTypeMask)
38 {
39 case EPT_E_MEMTYPE_WB:
40 case EPT_E_MEMTYPE_UC:
41 case EPT_E_MEMTYPE_WP:
42 case EPT_E_MEMTYPE_WT:
43 case EPT_E_MEMTYPE_WC:
44 return true;
45 }
46 return false;
47}
48
49
50DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
51{
52 static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
53 uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
54 uint8_t const fConvertible = RT_BOOL(uLevel == 1 || (uEntry & EPT_E_BIT_LEAF));
55 uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
56
57 pWalk->fNotPresent = true;
58 pWalk->uLevel = uLevel;
59 pWalk->fFailed = s_afEptViolations[idxViolationType];
60 return VERR_PAGE_TABLE_NOT_PRESENT;
61}
62
63
64DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
65{
66 AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
67 pWalk->fBadPhysAddr = true;
68 pWalk->uLevel = uLevel;
69 pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
70 return VERR_PAGE_TABLE_NOT_PRESENT;
71}
72
73
74DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
75{
76 NOREF(pVCpu);
77 pWalk->fRsvdError = true;
78 pWalk->uLevel = uLevel;
79 pWalk->fFailed = PGM_WALKFAIL_EPT_MISCONFIG;
80 return VERR_PAGE_TABLE_NOT_PRESENT;
81}
82
83
84/**
85 * Performs an EPT walk (second-level address translation).
86 *
87 * @returns VBox status code.
88 * @retval VINF_SUCCESS on success.
89 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
90 *
91 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
92 * @param GCPhysNested The nested-guest physical address to walk.
93 * @param fIsLinearAddrValid Whether the linear-address in @c GCPtrNested caused
94 * this page walk.
95 * @param GCPtrNested The nested-guest linear address that caused this
96 * page walk. If @c fIsLinearAddrValid is false, pass
97 * 0.
98 * @param pWalk The page walk info.
99 * @param pGstWalk The guest mode specific page walk info.
100 */
101DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(Walk)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
102 PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
103{
104 Assert(fIsLinearAddrValid || GCPtrNested == 0);
105
106 /*
107 * Init walk structures.
108 */
109 RT_ZERO(*pWalk);
110 RT_ZERO(*pGstWalk);
111
112 pWalk->GCPtr = GCPtrNested;
113 pWalk->GCPhysNested = GCPhysNested;
114 pWalk->fIsLinearAddrValid = fIsLinearAddrValid;
115 pWalk->fIsSlat = true;
116
117 /*
118 * Figure out EPT attributes that are cumulative (logical-AND) across page walks.
119 * - R, W, X_SUPER are unconditionally cumulative.
120 * See Intel spec. Table 26-7 "Exit Qualification for EPT Violations".
121 *
122 * - X_USER is cumulative but relevant only when mode-based execute control for EPT
123 * which we currently don't support it (asserted below).
124 *
125 * - MEMTYPE is not cumulative and only applicable to the final paging entry.
126 *
127 * - A, D EPT bits map to the regular page-table bit positions. Thus, they're not
128 * included in the mask below and handled separately. Accessed bits are
129 * cumulative but dirty bits are not cumulative as they're only applicable to
130 * the final paging entry.
131 */
132 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
133 uint64_t const fCumulativeEpt = PGM_PTATTRS_EPT_R_MASK
134 | PGM_PTATTRS_EPT_W_MASK
135 | PGM_PTATTRS_EPT_X_SUPER_MASK;
136 Assert(!(fCumulativeEpt & ~PGM_PTATTRS_EPT_MASK));
137
138 /*
139 * Do the walk.
140 */
141 uint64_t fEffective;
142 {
143 /*
144 * EPTP.
145 *
146 * We currently only support 4-level EPT paging.
147 * EPT 5-level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
148 * but for some reason seems to have been removed from subsequent specs.
149 */
150 int const rc = pgmGstGetEptPML4PtrEx(pVCpu, &pGstWalk->pPml4);
151 if (RT_SUCCESS(rc))
152 { /* likely */ }
153 else
154 return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
155 }
156 {
157 /*
158 * PML4E.
159 */
160 PEPTPML4E pPml4e;
161 pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK];
162 EPTPML4E Pml4e;
163 pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
164
165 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
166 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
167
168 if (RT_LIKELY( GST_IS_PML4E_VALID(pVCpu, Pml4e)
169 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pml4e.u)))
170 { /* likely */ }
171 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 4);
172
173 Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
174 uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK;
175 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
176 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
177 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
178 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
179 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
180 fEffective = RT_BF_MAKE(PGM_PTATTRS_R, fRead)
181 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
182 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
183 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
184 | fEffectiveEpt;
185 pWalk->fEffective = fEffective;
186
187 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & EPT_PML4E_PG_MASK, &pGstWalk->pPdpt);
188 if (RT_SUCCESS(rc)) { /* probable */ }
189 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
190 }
191 {
192 /*
193 * PDPTE.
194 */
195 PEPTPDPTE pPdpte;
196 pGstWalk->pPdpte = pPdpte = &pGstWalk->pPdpt->a[(GCPhysNested >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
197 EPTPDPTE Pdpte;
198 pGstWalk->Pdpte.u = Pdpte.u = pPdpte->u;
199
200 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ }
201 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
202
203 /* The order of the following "if" and "else if" statements matter. */
204 if ( GST_IS_PDPE_VALID(pVCpu, Pdpte)
205 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u))
206 {
207 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK;
208 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
209 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
210 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
211 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
212 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
213 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
214 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
215 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
216 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
217 | fEffectiveEpt;
218 pWalk->fEffective = fEffective;
219 }
220 else if ( GST_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
221 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u)
222 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
223 {
224 uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK;
225 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
226 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
227 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
228 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
229 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
230 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
231 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
232 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
233 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
234 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
235 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
236 | fEffectiveEpt;
237 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
238 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
239 pWalk->fEffective = fEffective;
240
241 pWalk->fGigantPage = true;
242 pWalk->fSucceeded = true;
243 pWalk->GCPhys = GST_GET_BIG_PDPE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pdpte)
244 | (GCPhysNested & GST_GIGANT_PAGE_OFFSET_MASK);
245 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
246 return VINF_SUCCESS;
247 }
248 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 3);
249
250 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pGstWalk->pPd);
251 if (RT_SUCCESS(rc)) { /* probable */ }
252 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
253 }
254 {
255 /*
256 * PDE.
257 */
258 PGSTPDE pPde;
259 pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPhysNested >> GST_PD_SHIFT) & GST_PD_MASK];
260 GSTPDE Pde;
261 pGstWalk->Pde.u = Pde.u = pPde->u;
262
263 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
264 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
265
266 /* The order of the following "if" and "else if" statements matter. */
267 if ( GST_IS_PDE_VALID(pVCpu, Pde)
268 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u))
269 {
270 uint64_t const fEptAttrs = Pde.u & EPT_PDE_ATTR_MASK;
271 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
272 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
273 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
274 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
275 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
276 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
277 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
278 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
279 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
280 | fEffectiveEpt;
281 pWalk->fEffective = fEffective;
282 }
283 else if ( GST_IS_BIG_PDE_VALID(pVCpu, Pde)
284 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u)
285 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
286 {
287 uint64_t const fEptAttrs = Pde.u & EPT_PDE2M_ATTR_MASK;
288 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
289 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
290 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
291 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
292 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
293 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
294 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
295 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
296 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
297 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
298 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
299 | fEffectiveEpt;
300 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
301 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
302 pWalk->fEffective = fEffective;
303
304 pWalk->fBigPage = true;
305 pWalk->fSucceeded = true;
306 pWalk->GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
307 | (GCPhysNested & GST_BIG_PAGE_OFFSET_MASK);
308 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
309 return VINF_SUCCESS;
310 }
311 else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 2);
312
313 int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pGstWalk->pPt);
314 if (RT_SUCCESS(rc)) { /* probable */ }
315 else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
316 }
317 {
318 /*
319 * PTE.
320 */
321 PGSTPTE pPte;
322 pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPhysNested >> GST_PT_SHIFT) & GST_PT_MASK];
323 GSTPTE Pte;
324 pGstWalk->Pte.u = Pte.u = pPte->u;
325
326 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
327 else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pte.u, 1);
328
329 if ( GST_IS_PTE_VALID(pVCpu, Pte)
330 && PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pte.u)
331 && PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
332 { /* likely*/ }
333 else
334 return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 1);
335
336 uint64_t const fEptAttrs = Pte.u & EPT_PTE_ATTR_MASK;
337 uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
338 uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
339 uint8_t const fExecute = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_EXECUTE);
340 uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
341 uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
342 uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
343 uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & fCumulativeEpt;
344 fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
345 | RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
346 | RT_BF_MAKE(PGM_PTATTRS_NX, !fExecute)
347 | RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
348 | fEffectiveEpt;
349 fEffective |= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
350 | RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
351 pWalk->fEffective = fEffective;
352
353 pWalk->fSucceeded = true;
354 pWalk->GCPhys = GST_GET_PTE_GCPHYS(Pte) | (GCPhysNested & GUEST_PAGE_OFFSET_MASK);
355 return VINF_SUCCESS;
356 }
357}
358#else
359# error "Guest paging type must be EPT."
360#endif
361
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