PGMAllGst.h@ 9857

Last change on this file since 9857 was 9857, checked in by vboxsync, 16 years ago
Updates for amd64 paging
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 42.3 KB

Line
1	/* $Id: PGMAllGst.h 9857 2008-06-20 14:34:46Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48
49	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
50	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
51	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
52	# define GSTPT X86PT
53	# define PGSTPT PX86PT
54	# define GSTPTE X86PTE
55	# define PGSTPTE PX86PTE
56	# define GSTPD X86PD
57	# define PGSTPD PX86PD
58	# define GSTPDE X86PDE
59	# define PGSTPDE PX86PDE
60	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
61	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
62	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
63	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
64	# define GST_PD_SHIFT X86_PD_SHIFT
65	# define GST_PD_MASK X86_PD_MASK
66	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
67	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
68	# define GST_PT_SHIFT X86_PT_SHIFT
69	# define GST_PT_MASK X86_PT_MASK
70	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
71	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
73	# define GSTPT X86PTPAE
74	# define PGSTPT PX86PTPAE
75	# define GSTPTE X86PTEPAE
76	# define PGSTPTE PX86PTEPAE
77	# define GSTPD X86PDPAE
78	# define PGSTPD PX86PDPAE
79	# define GSTPDE X86PDEPAE
80	# define PGSTPDE PX86PDEPAE
81	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
86	# define GST_PD_MASK X86_PD_PAE_MASK
87	# if PGM_GST_TYPE == PGM_TYPE_PAE
88	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
89	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
90	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK
91	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
92	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
93	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
94	# else
95	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
96	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
97	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
98	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
99	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
100	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
101	# endif
102	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
103	# define GST_PT_MASK X86_PT_PAE_MASK
104	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
105	#endif
106
107
108	/*******************************************************************************
109	* Internal Functions *
110	*******************************************************************************/
111	__BEGIN_DECLS
112	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
113	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
114	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
115	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
116	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
117	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
118	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
119	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
120	#ifndef IN_RING3
121	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
122	# if PGM_GST_TYPE == PGM_TYPE_PAE \
123	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
124	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
125	# endif
126	#endif
127	__END_DECLS
128
129
130
131	/**
132	* Gets effective Guest OS page information.
133	*
134	* When GCPtr is in a big page, the function will return as if it was a normal
135	* 4KB page. If the need for distinguishing between big and normal page becomes
136	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
137	* purpose.
138	*
139	* @returns VBox status.
140	* @param pVM VM Handle.
141	* @param GCPtr Guest Context virtual address of the page. Page aligned!
142	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
143	* @param pGCPhys Where to store the GC physical address of the page.
144	* This is page aligned. The fact that the
145	*/
146	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
147	{
148	#if PGM_GST_TYPE == PGM_TYPE_REAL \
149	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
150	/*
151	* Fake it.
152	*/
153	if (pfFlags)
154	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
155	if (pGCPhys)
156	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
157	return VINF_SUCCESS;
158
159	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
160
161	/*
162	* Get the PDE.
163	*/
164	# if PGM_GST_TYPE == PGM_TYPE_32BIT
165	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
166	#elif PGM_GST_TYPE == PGM_TYPE_PAE
167	X86PDEPAE Pde;
168	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
169
170	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
171	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
172	*/
173	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
174	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
175	PX86PML4E pPml4e;
176	X86PDPE Pdpe;
177	X86PDEPAE Pde;
178	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
179
180	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
181	Assert(pPml4e);
182	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
183	return VERR_PAGE_TABLE_NOT_PRESENT;
184
185	/* Merge accessed, write, user and no-execute bits into the PDE. */
186	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
187	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
188	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
189	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
190	# endif
191
192	/*
193	* Lookup the page.
194	*/
195	if (!Pde.n.u1Present)
196	return VERR_PAGE_TABLE_NOT_PRESENT;
197
198	if ( !Pde.b.u1Size
199	# if PGM_GST_TYPE != PGM_TYPE_AMD64
200	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
201	# endif
202	)
203	{
204	PGSTPT pPT;
205	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
206	if (VBOX_FAILURE(rc))
207	return rc;
208
209	/*
210	* Get PT entry and check presence.
211	*/
212	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
213	if (!Pte.n.u1Present)
214	return VERR_PAGE_NOT_PRESENT;
215
216	/*
217	* Store the result.
218	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
219	* where the PDPE is simplified.
220	*/
221	if (pfFlags)
222	{
223	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
224	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
225	# if PGM_WITH_NX(PGM_GST_TYPE)
226	/* The NX bit is determined by a bitwise OR between the PT and PD */
227	if (fNoExecuteBitValid)
228	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
229	# endif
230	}
231	if (pGCPhys)
232	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
233	}
234	else
235	{
236	/*
237	* Map big to 4k PTE and store the result
238	*/
239	if (pfFlags)
240	{
241	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
242	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
243	# if PGM_WITH_NX(PGM_GST_TYPE)
244	/* The NX bit is determined by a bitwise OR between the PT and PD */
245	if (fNoExecuteBitValid)
246	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
247	# endif
248	}
249	if (pGCPhys)
250	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
251	}
252	return VINF_SUCCESS;
253	#else
254	# error "shouldn't be here!"
255	/* something else... */
256	return VERR_NOT_SUPPORTED;
257	#endif
258	}
259
260
261	/**
262	* Modify page flags for a range of pages in the guest's tables
263	*
264	* The existing flags are ANDed with the fMask and ORed with the fFlags.
265	*
266	* @returns VBox status code.
267	* @param pVM VM handle.
268	* @param GCPtr Virtual address of the first page in the range. Page aligned!
269	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
270	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
271	* @param fMask The AND mask - page flags X86_PTE_*.
272	*/
273	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
274	{
275	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
276	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
277	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
278
279	for (;;)
280	{
281	/*
282	* Get the PD entry.
283	*/
284	# if PGM_GST_TYPE == PGM_TYPE_32BIT
285	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
286	# elif PGM_GST_TYPE == PGM_TYPE_PAE
287	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
288	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
289	*/
290	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
291	Assert(pPde);
292	if (!pPde)
293	return VERR_PAGE_TABLE_NOT_PRESENT;
294	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
295	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
296	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
297	Assert(pPde);
298	if (!pPde)
299	return VERR_PAGE_TABLE_NOT_PRESENT;
300	# endif
301	GSTPDE Pde = *pPde;
302	Assert(Pde.n.u1Present);
303	if (!Pde.n.u1Present)
304	return VERR_PAGE_TABLE_NOT_PRESENT;
305
306	if ( !Pde.b.u1Size
307	# if PGM_GST_TYPE != PGM_TYPE_AMD64
308	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
309	# endif
310	)
311	{
312	/*
313	* 4KB Page table
314	*
315	* Walk page tables and pages till we're done.
316	*/
317	PGSTPT pPT;
318	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
319	if (VBOX_FAILURE(rc))
320	return rc;
321
322	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
323	while (iPTE < RT_ELEMENTS(pPT->a))
324	{
325	GSTPTE Pte = pPT->a[iPTE];
326	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
327	\| (fFlags & ~GST_PTE_PG_MASK);
328	pPT->a[iPTE] = Pte;
329
330	/* next page */
331	cb -= PAGE_SIZE;
332	if (!cb)
333	return VINF_SUCCESS;
334	GCPtr += PAGE_SIZE;
335	iPTE++;
336	}
337	}
338	else
339	{
340	/*
341	* 4MB Page table
342	*/
343	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
344	\| (fFlags & ~GST_PTE_PG_MASK)
345	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
346	*pPde = Pde;
347
348	/* advance */
349	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
350	if (cbDone >= cb)
351	return VINF_SUCCESS;
352	cb -= cbDone;
353	GCPtr += cbDone;
354	}
355	}
356
357	#else
358	/* real / protected mode: ignore. */
359	return VINF_SUCCESS;
360	#endif
361	}
362
363
364	/**
365	* Retrieve guest PDE information
366	*
367	* @returns VBox status code.
368	* @param pVM The virtual machine.
369	* @param GCPtr Guest context pointer
370	* @param pPDE Pointer to guest PDE structure
371	*/
372	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
373	{
374	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
375	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
376	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
377
378	# if PGM_GST_TYPE == PGM_TYPE_32BIT
379	X86PDE Pde;
380	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
381	# elif PGM_GST_TYPE == PGM_TYPE_PAE
382	X86PDEPAE Pde;
383	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
384	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
385	X86PDEPAE Pde;
386	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
387	# endif
388
389	pPDE->u = (X86PGPAEUINT)Pde.u;
390	return VINF_SUCCESS;
391	#else
392	AssertFailed();
393	return VERR_NOT_IMPLEMENTED;
394	#endif
395	}
396
397
398
399	/**
400	* Maps the CR3 into HMA in GC and locate it in HC.
401	*
402	* @returns VBox status, no specials.
403	* @param pVM VM handle.
404	* @param GCPhysCR3 The physical address in the CR3 register.
405	*/
406	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
407	{
408	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
409	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
410	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
411
412	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
413
414	/*
415	* Map the page CR3 points at.
416	*/
417	RTHCPHYS HCPhysGuestCR3;
418	RTHCPTR HCPtrGuestCR3;
419	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
420	if (VBOX_SUCCESS(rc))
421	{
422	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
423	if (VBOX_SUCCESS(rc))
424	{
425	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
426	# if PGM_GST_TYPE == PGM_TYPE_32BIT
427	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
428	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
429
430	# elif PGM_GST_TYPE == PGM_TYPE_PAE
431	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
432	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
433	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
434	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
435
436	/*
437	* Map the 4 PDs too.
438	*/
439	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
440	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
441	{
442	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
443	{
444	RTHCPTR HCPtr;
445	RTHCPHYS HCPhys;
446	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
447	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
448	if (VBOX_SUCCESS(rc2))
449	{
450	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
451	AssertRCReturn(rc, rc);
452	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
453	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
454	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
455	PGM_INVL_PG(GCPtr);
456	continue;
457	}
458	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
459	}
460
461	pVM->pgm.s.apGstPaePDsHC[i] = 0;
462	pVM->pgm.s.apGstPaePDsGC[i] = 0;
463	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
464	PGM_INVL_PG(GCPtr);
465	}
466	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
467	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
468	# endif
469	}
470	else
471	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
472	}
473	else
474	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
475
476	#else /* prot/real stub */
477	int rc = VINF_SUCCESS;
478	#endif
479	return rc;
480	}
481
482
483	/**
484	* Unmaps the CR3.
485	*
486	* @returns VBox status, no specials.
487	* @param pVM VM handle.
488	* @param GCPhysCR3 The physical address in the CR3 register.
489	*/
490	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
491	{
492	LogFlow(("UnmapCR3\n"));
493
494	int rc = VINF_SUCCESS;
495	#if PGM_GST_TYPE == PGM_TYPE_32BIT
496	pVM->pgm.s.pGuestPDHC = 0;
497	pVM->pgm.s.pGuestPDGC = 0;
498
499	#elif PGM_GST_TYPE == PGM_TYPE_PAE
500	pVM->pgm.s.pGstPaePDPTHC = 0;
501	pVM->pgm.s.pGstPaePDPTGC = 0;
502	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
503	{
504	pVM->pgm.s.apGstPaePDsHC[i] = 0;
505	pVM->pgm.s.apGstPaePDsGC[i] = 0;
506	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
507	}
508
509	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
510	pVM->pgm.s.pGstPaePML4HC = 0;
511	#else /* prot/real mode stub */
512	/* nothing to do */
513	#endif
514	return rc;
515	}
516
517
518	#undef LOG_GROUP
519	#define LOG_GROUP LOG_GROUP_PGM_POOL
520
521	/**
522	* Registers physical page monitors for the necessary paging
523	* structures to detect conflicts with our guest mappings.
524	*
525	* This is always called after mapping CR3.
526	* This is never called with fixed mappings.
527	*
528	* @returns VBox status, no specials.
529	* @param pVM VM handle.
530	* @param GCPhysCR3 The physical address in the CR3 register.
531	*/
532	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
533	{
534	Assert(!pVM->pgm.s.fMappingsFixed);
535	int rc = VINF_SUCCESS;
536
537	/*
538	* Register/Modify write phys handler for guest's CR3 if it changed.
539	*/
540	#if PGM_GST_TYPE == PGM_TYPE_32BIT
541
542	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
543	{
544	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
545	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
546	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
547	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
548	else
549	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
550	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
551	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
552	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
553	pVM->pgm.s.pszR3GstWriteHandlerCR3);
554	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
555	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
556	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
557	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
558	? PGMPOOL_IDX_PAE_PD
559	: PGMPOOL_IDX_PD,
560	GCPhysCR3);
561	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
562	if (VBOX_FAILURE(rc))
563	{
564	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
565	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
566	return rc;
567	}
568	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
569	}
570
571	#elif PGM_GST_TYPE == PGM_TYPE_PAE
572	/* Monitor the PDPT page */
573	/*
574	* Register/Modify write phys handler for guest's CR3 if it changed.
575	*/
576	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
577	AssertFailed();
578	# endif
579	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
580	{
581	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
582	if (VBOX_FAILURE(rc))
583	{
584	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
585	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
586	return rc;
587	}
588	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
589	}
590	/*
591	* Do the 4 PDs.
592	*/
593	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
594	{
595	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
596	{
597	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
598	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
599	{
600	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
601
602	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
603	}
604
605	if (VBOX_FAILURE(rc))
606	{
607	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
608	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
609	return rc;
610	}
611	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
612	}
613	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
614	{
615	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
616	AssertRC(rc);
617	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
618	}
619	}
620
621	#else
622	/* prot/real/amd64 mode stub */
623
624	#endif
625	return rc;
626	}
627
628	/**
629	* Deregisters any physical page monitors installed by MonitorCR3.
630	*
631	* @returns VBox status code, no specials.
632	* @param pVM The VM handle.
633	*/
634	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
635	{
636	int rc = VINF_SUCCESS;
637
638	/*
639	* Deregister the access handlers.
640	*
641	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
642	* before we enter GC again.
643	*/
644	#if PGM_GST_TYPE == PGM_TYPE_32BIT
645	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
646	{
647	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
648	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
649	AssertRCReturn(rc, rc);
650	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
651	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
652	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
653	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
654	? PGMPOOL_IDX_PAE_PD
655	: PGMPOOL_IDX_PD);
656	AssertRCReturn(rc, rc);
657	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
658	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
659	}
660
661	#elif PGM_GST_TYPE == PGM_TYPE_PAE
662	/* The PDPT page */
663	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
664	AssertFailed();
665	# endif
666
667	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
668	{
669	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
670	AssertRC(rc);
671	}
672
673	/* The 4 PDs. */
674	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
675	{
676	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
677	{
678	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
679	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
680	AssertRC(rc2);
681	if (VBOX_FAILURE(rc2))
682	rc = rc2;
683	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
684	}
685	}
686	#else
687	/* prot/real/amd64 mode stub */
688	#endif
689	return rc;
690
691	}
692
693	#undef LOG_GROUP
694	#define LOG_GROUP LOG_GROUP_PGM
695
696
697	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
698	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
699	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
700	/**
701	* Updates one virtual handler range.
702	*
703	* @returns 0
704	* @param pNode Pointer to a PGMVIRTHANDLER.
705	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
706	*/
707	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
708	{
709	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
710	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
711	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
712
713	#if PGM_GST_TYPE == PGM_TYPE_32BIT
714	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
715	#endif
716
717	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
718	#if PGM_GST_MODE != PGM_MODE_AMD64
719	/* skip all stuff above 4GB if not AMD64 mode. */
720	if (GCPtr >= _4GB)
721	return 0;
722	#endif
723
724	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
725	unsigned iPage = 0;
726	while (iPage < pCur->cPages)
727	{
728	#if PGM_GST_TYPE == PGM_TYPE_32BIT
729	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
730	#elif PGM_GST_TYPE == PGM_TYPE_PAE
731	X86PDEPAE Pde;
732	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
733	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
734	X86PDEPAE Pde;
735	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
736	#endif
737	if (Pde.n.u1Present)
738	{
739	if ( !Pde.b.u1Size
740	# if PGM_GST_TYPE != PGM_TYPE_AMD64
741	\|\| !(pState->cr4 & X86_CR4_PSE)
742	# endif
743	)
744	{
745	/*
746	* Normal page table.
747	*/
748	PGSTPT pPT;
749	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
750	if (VBOX_SUCCESS(rc))
751	{
752	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
753	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
754	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
755	{
756	GSTPTE Pte = pPT->a[iPTE];
757	RTGCPHYS GCPhysNew;
758	if (Pte.n.u1Present)
759	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
760	else
761	GCPhysNew = NIL_RTGCPHYS;
762	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
763	{
764	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
765	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
766	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
767	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
768	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
769	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
770	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
771	#endif
772	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
773	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
774	}
775	}
776	}
777	else
778	{
779	/* not-present. */
780	offPage = 0;
781	AssertRC(rc);
782	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
783	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
784	iPTE++, iPage++, GCPtr += PAGE_SIZE)
785	{
786	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
787	{
788	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
789	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
790	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
791	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
792	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
793	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
794	#endif
795	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
796	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
797	}
798	}
799	}
800	}
801	else
802	{
803	/*
804	* 2/4MB page.
805	*/
806	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
807	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
808	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
809	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
810	{
811	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
812	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
813	{
814	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
815	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
816	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
817	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
818	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
819	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
820	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
821	#endif
822	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
823	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
824	}
825	}
826	} /* pde type */
827	}
828	else
829	{
830	/* not-present. */
831	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
832	cPages && iPage < pCur->cPages;
833	iPage++, GCPtr += PAGE_SIZE)
834	{
835	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
836	{
837	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
838	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
839	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
840	}
841	}
842	offPage = 0;
843	}
844	} /* for pages in virtual mapping. */
845
846	return 0;
847	}
848	#endif /* 32BIT, PAE and AMD64 */
849
850
851	/**
852	* Updates the virtual page access handlers.
853	*
854	* @returns true if bits were flushed.
855	* @returns false if bits weren't flushed.
856	* @param pVM VM handle.
857	* @param pPDSrc The page directory.
858	* @param cr4 The cr4 register value.
859	*/
860	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
861	{
862	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
863	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
864	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
865
866	/** @todo
867	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
868	*/
869
870	/*
871	* Resolve any virtual address based access handlers to GC physical addresses.
872	* This should be fairly quick.
873	*/
874	PGMHVUSTATE State;
875
876	pgmLock(pVM);
877	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
878	State.pVM = pVM;
879	State.fTodo = pVM->pgm.s.fSyncFlags;
880	State.cr4 = cr4;
881	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
882	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
883
884
885	/*
886	* Set / reset bits?
887	*/
888	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
889	{
890	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
891	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
892	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
893	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
894	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
895	}
896	pgmUnlock(pVM);
897
898	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
899
900	#else /* real / protected */
901	return false;
902	#endif
903	}
904
905
906	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
907
908	/**
909	* Write access handler for the Guest CR3 page in 32-bit mode.
910	*
911	* This will try interpret the instruction, if failure fail back to the recompiler.
912	* Check if the changed PDEs are marked present and conflicts with our
913	* mappings. If conflict, we'll switch to the host context and resolve it there
914	*
915	* @returns VBox status code (appropritate for trap handling and GC return).
916	* @param pVM VM Handle.
917	* @param uErrorCode CPU Error code.
918	* @param pRegFrame Trap register frame.
919	* @param pvFault The fault address (cr2).
920	* @param GCPhysFault The GC physical address corresponding to pvFault.
921	* @param pvUser User argument.
922	*/
923	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
924	{
925	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
926
927	/*
928	* Try interpret the instruction.
929	*/
930	uint32_t cb;
931	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
932	if (VBOX_SUCCESS(rc) && cb)
933	{
934	/*
935	* Check if the modified PDEs are present and mappings.
936	*/
937	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
938	const unsigned iPD1 = offPD / sizeof(X86PDE);
939	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
940
941	Assert(cb > 0 && cb <= 8);
942	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
943	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
944
945	#ifdef DEBUG
946	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
947	if (iPD1 != iPD2)
948	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
949	#endif
950
951	if (!pVM->pgm.s.fMappingsFixed)
952	{
953	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
954	if ( ( pPDSrc->a[iPD1].n.u1Present
955	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
956	\|\| ( iPD1 != iPD2
957	&& pPDSrc->a[iPD2].n.u1Present
958	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
959	)
960	{
961	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
962	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
963	if (rc == VINF_SUCCESS)
964	rc = VINF_PGM_SYNC_CR3;
965	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
966	return rc;
967	}
968	}
969
970	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
971	}
972	else
973	{
974	Assert(VBOX_FAILURE(rc));
975	if (rc == VERR_EM_INTERPRETER)
976	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
977	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
978	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
979	}
980	return rc;
981	}
982
983	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
984
985
986	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
987
988	/**
989	* Write access handler for the Guest CR3 page in PAE mode.
990	*
991	* This will try interpret the instruction, if failure fail back to the recompiler.
992	* Check if the changed PDEs are marked present and conflicts with our
993	* mappings. If conflict, we'll switch to the host context and resolve it there
994	*
995	* @returns VBox status code (appropritate for trap handling and GC return).
996	* @param pVM VM Handle.
997	* @param uErrorCode CPU Error code.
998	* @param pRegFrame Trap register frame.
999	* @param pvFault The fault address (cr2).
1000	* @param GCPhysFault The GC physical address corresponding to pvFault.
1001	* @param pvUser User argument.
1002	*/
1003	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1004	{
1005	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1006
1007	/*
1008	* Try interpret the instruction.
1009	*/
1010	uint32_t cb;
1011	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1012	if (VBOX_SUCCESS(rc) && cb)
1013	{
1014	/*
1015	* Check if any of the PDs have changed.
1016	* We'll simply check all of them instead of figuring out which one/two to check.
1017	*/
1018	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1019	{
1020	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1021	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1022	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1023	{
1024	/*
1025	* The PDPE has changed.
1026	* We will schedule a monitoring update for the next TLB Flush,
1027	* InvalidatePage or SyncCR3.
1028	*
1029	* This isn't perfect, because a lazy page sync might be dealing with an half
1030	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1031	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1032	* executing.
1033	*/
1034	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1035	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1036	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1037	}
1038	}
1039
1040	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1041	}
1042	else
1043	{
1044	Assert(VBOX_FAILURE(rc));
1045	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1046	if (rc == VERR_EM_INTERPRETER)
1047	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1048	}
1049	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1050	return rc;
1051	}
1052
1053
1054	/**
1055	* Write access handler for the Guest PDs in PAE mode.
1056	*
1057	* This will try interpret the instruction, if failure fail back to the recompiler.
1058	* Check if the changed PDEs are marked present and conflicts with our
1059	* mappings. If conflict, we'll switch to the host context and resolve it there
1060	*
1061	* @returns VBox status code (appropritate for trap handling and GC return).
1062	* @param pVM VM Handle.
1063	* @param uErrorCode CPU Error code.
1064	* @param pRegFrame Trap register frame.
1065	* @param pvFault The fault address (cr2).
1066	* @param GCPhysFault The GC physical address corresponding to pvFault.
1067	* @param pvUser User argument.
1068	*/
1069	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1070	{
1071	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1072
1073	/*
1074	* Try interpret the instruction.
1075	*/
1076	uint32_t cb;
1077	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1078	if (VBOX_SUCCESS(rc) && cb)
1079	{
1080	/*
1081	* Figure out which of the 4 PDs this is.
1082	*/
1083	RTGCUINTPTR i;
1084	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1085	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1086	{
1087	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1088	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1089	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1090	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1091
1092	Assert(cb > 0 && cb <= 8);
1093	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1094	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1095
1096	#ifdef DEBUG
1097	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1098	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1099	if (iPD1 != iPD2)
1100	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1101	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1102	#endif
1103
1104	if (!pVM->pgm.s.fMappingsFixed)
1105	{
1106	if ( ( pPDSrc->a[iPD1].n.u1Present
1107	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1108	\|\| ( iPD1 != iPD2
1109	&& pPDSrc->a[iPD2].n.u1Present
1110	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1111	)
1112	{
1113	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1114	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1115	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1116	return VINF_PGM_SYNC_CR3;
1117	}
1118	}
1119	break; /* ASSUMES no duplicate entries... */
1120	}
1121	Assert(i < 4);
1122
1123	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1124	}
1125	else
1126	{
1127	Assert(VBOX_FAILURE(rc));
1128	if (rc == VERR_EM_INTERPRETER)
1129	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1130	else
1131	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1132	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1133	}
1134	return rc;
1135	}
1136
1137	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1138

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 9857

Download in other formats: