PGMAllGst.h@ 9776

Last change on this file since 9776 was 9701, checked in by vboxsync, 16 years ago
Fixed mask issues in 64 bits mode
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 42.2 KB

Line
1	/* $Id: PGMAllGst.h 9701 2008-06-16 08:57:21Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48
49	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
50	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
51	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
52	# define GSTPT X86PT
53	# define PGSTPT PX86PT
54	# define GSTPTE X86PTE
55	# define PGSTPTE PX86PTE
56	# define GSTPD X86PD
57	# define PGSTPD PX86PD
58	# define GSTPDE X86PDE
59	# define PGSTPDE PX86PDE
60	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
61	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
62	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
63	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
64	# define GST_PD_SHIFT X86_PD_SHIFT
65	# define GST_PD_MASK X86_PD_MASK
66	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
67	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
68	# define GST_PT_SHIFT X86_PT_SHIFT
69	# define GST_PT_MASK X86_PT_MASK
70	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
71	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
73	# define GSTPT X86PTPAE
74	# define PGSTPT PX86PTPAE
75	# define GSTPTE X86PTEPAE
76	# define PGSTPTE PX86PTEPAE
77	# define GSTPD X86PDPAE
78	# define PGSTPD PX86PDPAE
79	# define GSTPDE X86PDEPAE
80	# define PGSTPDE PX86PDEPAE
81	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
86	# define GST_PD_MASK X86_PD_PAE_MASK
87	# if PGM_GST_TYPE == PGM_TYPE_PAE
88	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
89	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
90	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
91	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
92	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
93	# else
94	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
95	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
96	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
97	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
98	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
99	# endif
100	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
101	# define GST_PT_MASK X86_PT_PAE_MASK
102	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
103	#endif
104
105
106	/*******************************************************************************
107	* Internal Functions *
108	*******************************************************************************/
109	__BEGIN_DECLS
110	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
111	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
112	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
113	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
114	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
115	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
116	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
117	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
118	#ifndef IN_RING3
119	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
120	# if PGM_GST_TYPE == PGM_TYPE_PAE \
121	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
122	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
123	# endif
124	#endif
125	__END_DECLS
126
127
128
129	/**
130	* Gets effective Guest OS page information.
131	*
132	* When GCPtr is in a big page, the function will return as if it was a normal
133	* 4KB page. If the need for distinguishing between big and normal page becomes
134	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
135	* purpose.
136	*
137	* @returns VBox status.
138	* @param pVM VM Handle.
139	* @param GCPtr Guest Context virtual address of the page. Page aligned!
140	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
141	* @param pGCPhys Where to store the GC physical address of the page.
142	* This is page aligned. The fact that the
143	*/
144	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
145	{
146	#if PGM_GST_TYPE == PGM_TYPE_REAL \
147	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
148	/*
149	* Fake it.
150	*/
151	if (pfFlags)
152	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
153	if (pGCPhys)
154	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
155	return VINF_SUCCESS;
156
157	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
158
159	/*
160	* Get the PDE.
161	*/
162	# if PGM_GST_TYPE == PGM_TYPE_32BIT
163	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
164	#elif PGM_GST_TYPE == PGM_TYPE_PAE
165	X86PDEPAE Pde;
166	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
167
168	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
169	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
170	*/
171	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
172	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
173	PX86PML4E pPml4e;
174	X86PDPE Pdpe;
175	X86PDEPAE Pde;
176	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
177
178	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
179	Assert(pPml4e);
180	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
181	return VERR_PAGE_TABLE_NOT_PRESENT;
182
183	/* Merge accessed, write, user and no-execute bits into the PDE. */
184	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
185	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
186	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
187	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
188	# endif
189
190	/*
191	* Lookup the page.
192	*/
193	if (!Pde.n.u1Present)
194	return VERR_PAGE_TABLE_NOT_PRESENT;
195
196	if ( !Pde.b.u1Size
197	# if PGM_GST_TYPE != PGM_TYPE_AMD64
198	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
199	# endif
200	)
201	{
202	PGSTPT pPT;
203	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
204	if (VBOX_FAILURE(rc))
205	return rc;
206
207	/*
208	* Get PT entry and check presence.
209	*/
210	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
211	if (!Pte.n.u1Present)
212	return VERR_PAGE_NOT_PRESENT;
213
214	/*
215	* Store the result.
216	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
217	* where the PDPE is simplified.
218	*/
219	if (pfFlags)
220	{
221	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
222	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
223	# if PGM_WITH_NX(PGM_GST_TYPE)
224	/* The NX bit is determined by a bitwise OR between the PT and PD */
225	if (fNoExecuteBitValid)
226	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
227	# endif
228	}
229	if (pGCPhys)
230	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
231	}
232	else
233	{
234	/*
235	* Map big to 4k PTE and store the result
236	*/
237	if (pfFlags)
238	{
239	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
240	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
241	# if PGM_WITH_NX(PGM_GST_TYPE)
242	/* The NX bit is determined by a bitwise OR between the PT and PD */
243	if (fNoExecuteBitValid)
244	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
245	# endif
246	}
247	if (pGCPhys)
248	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
249	}
250	return VINF_SUCCESS;
251	#else
252	# error "shouldn't be here!"
253	/* something else... */
254	return VERR_NOT_SUPPORTED;
255	#endif
256	}
257
258
259	/**
260	* Modify page flags for a range of pages in the guest's tables
261	*
262	* The existing flags are ANDed with the fMask and ORed with the fFlags.
263	*
264	* @returns VBox status code.
265	* @param pVM VM handle.
266	* @param GCPtr Virtual address of the first page in the range. Page aligned!
267	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
268	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
269	* @param fMask The AND mask - page flags X86_PTE_*.
270	*/
271	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
272	{
273	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
274	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
275	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
276
277	for (;;)
278	{
279	/*
280	* Get the PD entry.
281	*/
282	# if PGM_GST_TYPE == PGM_TYPE_32BIT
283	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
284	# elif PGM_GST_TYPE == PGM_TYPE_PAE
285	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
286	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
287	*/
288	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
289	Assert(pPde);
290	if (!pPde)
291	return VERR_PAGE_TABLE_NOT_PRESENT;
292	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
293	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
294	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
295	Assert(pPde);
296	if (!pPde)
297	return VERR_PAGE_TABLE_NOT_PRESENT;
298	# endif
299	GSTPDE Pde = *pPde;
300	Assert(Pde.n.u1Present);
301	if (!Pde.n.u1Present)
302	return VERR_PAGE_TABLE_NOT_PRESENT;
303
304	if ( !Pde.b.u1Size
305	# if PGM_GST_TYPE != PGM_TYPE_AMD64
306	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
307	# endif
308	)
309	{
310	/*
311	* 4KB Page table
312	*
313	* Walk page tables and pages till we're done.
314	*/
315	PGSTPT pPT;
316	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
317	if (VBOX_FAILURE(rc))
318	return rc;
319
320	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
321	while (iPTE < RT_ELEMENTS(pPT->a))
322	{
323	GSTPTE Pte = pPT->a[iPTE];
324	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
325	\| (fFlags & ~GST_PTE_PG_MASK);
326	pPT->a[iPTE] = Pte;
327
328	/* next page */
329	cb -= PAGE_SIZE;
330	if (!cb)
331	return VINF_SUCCESS;
332	GCPtr += PAGE_SIZE;
333	iPTE++;
334	}
335	}
336	else
337	{
338	/*
339	* 4MB Page table
340	*/
341	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
342	\| (fFlags & ~GST_PTE_PG_MASK)
343	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
344	*pPde = Pde;
345
346	/* advance */
347	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
348	if (cbDone >= cb)
349	return VINF_SUCCESS;
350	cb -= cbDone;
351	GCPtr += cbDone;
352	}
353	}
354
355	#else
356	/* real / protected mode: ignore. */
357	return VINF_SUCCESS;
358	#endif
359	}
360
361
362	/**
363	* Retrieve guest PDE information
364	*
365	* @returns VBox status code.
366	* @param pVM The virtual machine.
367	* @param GCPtr Guest context pointer
368	* @param pPDE Pointer to guest PDE structure
369	*/
370	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
371	{
372	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
373	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
374	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
375
376	# if PGM_GST_TYPE == PGM_TYPE_32BIT
377	X86PDE Pde;
378	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
379	# elif PGM_GST_TYPE == PGM_TYPE_PAE
380	X86PDEPAE Pde;
381	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
382	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
383	X86PDEPAE Pde;
384	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
385	# endif
386
387	pPDE->u = (X86PGPAEUINT)Pde.u;
388	return VINF_SUCCESS;
389	#else
390	AssertFailed();
391	return VERR_NOT_IMPLEMENTED;
392	#endif
393	}
394
395
396
397	/**
398	* Maps the CR3 into HMA in GC and locate it in HC.
399	*
400	* @returns VBox status, no specials.
401	* @param pVM VM handle.
402	* @param GCPhysCR3 The physical address in the CR3 register.
403	*/
404	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
405	{
406	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
407	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
408	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
409
410	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
411
412	/*
413	* Map the page CR3 points at.
414	*/
415	RTHCPHYS HCPhysGuestCR3;
416	RTHCPTR HCPtrGuestCR3;
417	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
418	if (VBOX_SUCCESS(rc))
419	{
420	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
421	if (VBOX_SUCCESS(rc))
422	{
423	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
424	# if PGM_GST_TYPE == PGM_TYPE_32BIT
425	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
426	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
427
428	# elif PGM_GST_TYPE == PGM_TYPE_PAE
429	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
430	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
431	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
432	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
433
434	/*
435	* Map the 4 PDs too.
436	*/
437	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
438	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
439	{
440	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
441	{
442	RTHCPTR HCPtr;
443	RTHCPHYS HCPhys;
444	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
445	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
446	if (VBOX_SUCCESS(rc2))
447	{
448	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
449	AssertRCReturn(rc, rc);
450	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
451	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
452	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
453	PGM_INVL_PG(GCPtr);
454	continue;
455	}
456	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
457	}
458
459	pVM->pgm.s.apGstPaePDsHC[i] = 0;
460	pVM->pgm.s.apGstPaePDsGC[i] = 0;
461	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
462	PGM_INVL_PG(GCPtr);
463	}
464	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
465	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
466	# endif
467	}
468	else
469	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
470	}
471	else
472	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
473
474	#else /* prot/real stub */
475	int rc = VINF_SUCCESS;
476	#endif
477	return rc;
478	}
479
480
481	/**
482	* Unmaps the CR3.
483	*
484	* @returns VBox status, no specials.
485	* @param pVM VM handle.
486	* @param GCPhysCR3 The physical address in the CR3 register.
487	*/
488	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
489	{
490	LogFlow(("UnmapCR3\n"));
491
492	int rc = VINF_SUCCESS;
493	#if PGM_GST_TYPE == PGM_TYPE_32BIT
494	pVM->pgm.s.pGuestPDHC = 0;
495	pVM->pgm.s.pGuestPDGC = 0;
496
497	#elif PGM_GST_TYPE == PGM_TYPE_PAE
498	pVM->pgm.s.pGstPaePDPTHC = 0;
499	pVM->pgm.s.pGstPaePDPTGC = 0;
500	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
501	{
502	pVM->pgm.s.apGstPaePDsHC[i] = 0;
503	pVM->pgm.s.apGstPaePDsGC[i] = 0;
504	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
505	}
506
507	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
508	pVM->pgm.s.pGstPaePML4HC = 0;
509	#else /* prot/real mode stub */
510	/* nothing to do */
511	#endif
512	return rc;
513	}
514
515
516	#undef LOG_GROUP
517	#define LOG_GROUP LOG_GROUP_PGM_POOL
518
519	/**
520	* Registers physical page monitors for the necessary paging
521	* structures to detect conflicts with our guest mappings.
522	*
523	* This is always called after mapping CR3.
524	* This is never called with fixed mappings.
525	*
526	* @returns VBox status, no specials.
527	* @param pVM VM handle.
528	* @param GCPhysCR3 The physical address in the CR3 register.
529	*/
530	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
531	{
532	Assert(!pVM->pgm.s.fMappingsFixed);
533	int rc = VINF_SUCCESS;
534
535	/*
536	* Register/Modify write phys handler for guest's CR3 if it changed.
537	*/
538	#if PGM_GST_TYPE == PGM_TYPE_32BIT
539
540	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
541	{
542	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
543	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
544	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
545	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
546	else
547	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
548	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
549	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
550	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
551	pVM->pgm.s.pszR3GstWriteHandlerCR3);
552	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
553	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
554	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
555	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
556	? PGMPOOL_IDX_PAE_PD
557	: PGMPOOL_IDX_PD,
558	GCPhysCR3);
559	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
560	if (VBOX_FAILURE(rc))
561	{
562	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
563	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
564	return rc;
565	}
566	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
567	}
568
569	#elif PGM_GST_TYPE == PGM_TYPE_PAE
570	/* Monitor the PDPT page */
571	/*
572	* Register/Modify write phys handler for guest's CR3 if it changed.
573	*/
574	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
575	AssertFailed();
576	# endif
577	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
578	{
579	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
580	if (VBOX_FAILURE(rc))
581	{
582	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
583	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
584	return rc;
585	}
586	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
587	}
588	/*
589	* Do the 4 PDs.
590	*/
591	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
592	{
593	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
594	{
595	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
596	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
597	{
598	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
599
600	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
601	}
602
603	if (VBOX_FAILURE(rc))
604	{
605	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
606	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
607	return rc;
608	}
609	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
610	}
611	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
612	{
613	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
614	AssertRC(rc);
615	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
616	}
617	}
618
619	#else
620	/* prot/real/amd64 mode stub */
621
622	#endif
623	return rc;
624	}
625
626	/**
627	* Deregisters any physical page monitors installed by MonitorCR3.
628	*
629	* @returns VBox status code, no specials.
630	* @param pVM The VM handle.
631	*/
632	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
633	{
634	int rc = VINF_SUCCESS;
635
636	/*
637	* Deregister the access handlers.
638	*
639	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
640	* before we enter GC again.
641	*/
642	#if PGM_GST_TYPE == PGM_TYPE_32BIT
643	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
644	{
645	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
646	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
647	AssertRCReturn(rc, rc);
648	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
649	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
650	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
651	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
652	? PGMPOOL_IDX_PAE_PD
653	: PGMPOOL_IDX_PD);
654	AssertRCReturn(rc, rc);
655	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
656	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
657	}
658
659	#elif PGM_GST_TYPE == PGM_TYPE_PAE
660	/* The PDPT page */
661	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
662	AssertFailed();
663	# endif
664
665	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
666	{
667	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
668	AssertRC(rc);
669	}
670
671	/* The 4 PDs. */
672	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
673	{
674	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
675	{
676	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
677	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
678	AssertRC(rc2);
679	if (VBOX_FAILURE(rc2))
680	rc = rc2;
681	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
682	}
683	}
684	#else
685	/* prot/real/amd64 mode stub */
686	#endif
687	return rc;
688
689	}
690
691	#undef LOG_GROUP
692	#define LOG_GROUP LOG_GROUP_PGM
693
694
695	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
696	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
697	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
698	/**
699	* Updates one virtual handler range.
700	*
701	* @returns 0
702	* @param pNode Pointer to a PGMVIRTHANDLER.
703	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
704	*/
705	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
706	{
707	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
708	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
709	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
710
711	#if PGM_GST_TYPE == PGM_TYPE_32BIT
712	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
713	#endif
714
715	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
716	#if PGM_GST_MODE != PGM_MODE_AMD64
717	/* skip all stuff above 4GB if not AMD64 mode. */
718	if (GCPtr >= _4GB)
719	return 0;
720	#endif
721
722	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
723	unsigned iPage = 0;
724	while (iPage < pCur->cPages)
725	{
726	#if PGM_GST_TYPE == PGM_TYPE_32BIT
727	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
728	#elif PGM_GST_TYPE == PGM_TYPE_PAE
729	X86PDEPAE Pde;
730	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
731	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
732	X86PDEPAE Pde;
733	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
734	#endif
735	if (Pde.n.u1Present)
736	{
737	if ( !Pde.b.u1Size
738	# if PGM_GST_TYPE != PGM_TYPE_AMD64
739	\|\| !(pState->cr4 & X86_CR4_PSE)
740	# endif
741	)
742	{
743	/*
744	* Normal page table.
745	*/
746	PGSTPT pPT;
747	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
748	if (VBOX_SUCCESS(rc))
749	{
750	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
751	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
752	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
753	{
754	GSTPTE Pte = pPT->a[iPTE];
755	RTGCPHYS GCPhysNew;
756	if (Pte.n.u1Present)
757	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
758	else
759	GCPhysNew = NIL_RTGCPHYS;
760	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
761	{
762	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
763	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
764	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
765	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
766	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
767	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
768	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
769	#endif
770	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
771	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
772	}
773	}
774	}
775	else
776	{
777	/* not-present. */
778	offPage = 0;
779	AssertRC(rc);
780	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
781	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
782	iPTE++, iPage++, GCPtr += PAGE_SIZE)
783	{
784	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
785	{
786	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
787	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
788	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
789	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
790	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
791	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
792	#endif
793	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
794	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
795	}
796	}
797	}
798	}
799	else
800	{
801	/*
802	* 2/4MB page.
803	*/
804	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
805	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
806	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
807	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
808	{
809	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
810	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
811	{
812	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
813	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
814	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
815	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
816	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
817	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
818	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
819	#endif
820	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
821	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
822	}
823	}
824	} /* pde type */
825	}
826	else
827	{
828	/* not-present. */
829	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
830	cPages && iPage < pCur->cPages;
831	iPage++, GCPtr += PAGE_SIZE)
832	{
833	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
834	{
835	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
836	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
837	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
838	}
839	}
840	offPage = 0;
841	}
842	} /* for pages in virtual mapping. */
843
844	return 0;
845	}
846	#endif /* 32BIT, PAE and AMD64 */
847
848
849	/**
850	* Updates the virtual page access handlers.
851	*
852	* @returns true if bits were flushed.
853	* @returns false if bits weren't flushed.
854	* @param pVM VM handle.
855	* @param pPDSrc The page directory.
856	* @param cr4 The cr4 register value.
857	*/
858	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
859	{
860	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
861	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
862	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
863
864	/** @todo
865	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
866	*/
867
868	/*
869	* Resolve any virtual address based access handlers to GC physical addresses.
870	* This should be fairly quick.
871	*/
872	PGMHVUSTATE State;
873
874	pgmLock(pVM);
875	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
876	State.pVM = pVM;
877	State.fTodo = pVM->pgm.s.fSyncFlags;
878	State.cr4 = cr4;
879	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
880	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
881
882
883	/*
884	* Set / reset bits?
885	*/
886	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
887	{
888	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
889	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
890	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
891	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
892	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
893	}
894	pgmUnlock(pVM);
895
896	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
897
898	#else /* real / protected */
899	return false;
900	#endif
901	}
902
903
904	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
905
906	/**
907	* Write access handler for the Guest CR3 page in 32-bit mode.
908	*
909	* This will try interpret the instruction, if failure fail back to the recompiler.
910	* Check if the changed PDEs are marked present and conflicts with our
911	* mappings. If conflict, we'll switch to the host context and resolve it there
912	*
913	* @returns VBox status code (appropritate for trap handling and GC return).
914	* @param pVM VM Handle.
915	* @param uErrorCode CPU Error code.
916	* @param pRegFrame Trap register frame.
917	* @param pvFault The fault address (cr2).
918	* @param GCPhysFault The GC physical address corresponding to pvFault.
919	* @param pvUser User argument.
920	*/
921	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
922	{
923	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
924
925	/*
926	* Try interpret the instruction.
927	*/
928	uint32_t cb;
929	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
930	if (VBOX_SUCCESS(rc) && cb)
931	{
932	/*
933	* Check if the modified PDEs are present and mappings.
934	*/
935	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
936	const unsigned iPD1 = offPD / sizeof(X86PDE);
937	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
938
939	Assert(cb > 0 && cb <= 8);
940	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
941	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
942
943	#ifdef DEBUG
944	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
945	if (iPD1 != iPD2)
946	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
947	#endif
948
949	if (!pVM->pgm.s.fMappingsFixed)
950	{
951	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
952	if ( ( pPDSrc->a[iPD1].n.u1Present
953	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
954	\|\| ( iPD1 != iPD2
955	&& pPDSrc->a[iPD2].n.u1Present
956	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
957	)
958	{
959	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
960	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
961	if (rc == VINF_SUCCESS)
962	rc = VINF_PGM_SYNC_CR3;
963	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
964	return rc;
965	}
966	}
967
968	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
969	}
970	else
971	{
972	Assert(VBOX_FAILURE(rc));
973	if (rc == VERR_EM_INTERPRETER)
974	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
975	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
976	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
977	}
978	return rc;
979	}
980
981	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
982
983
984	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
985
986	/**
987	* Write access handler for the Guest CR3 page in PAE mode.
988	*
989	* This will try interpret the instruction, if failure fail back to the recompiler.
990	* Check if the changed PDEs are marked present and conflicts with our
991	* mappings. If conflict, we'll switch to the host context and resolve it there
992	*
993	* @returns VBox status code (appropritate for trap handling and GC return).
994	* @param pVM VM Handle.
995	* @param uErrorCode CPU Error code.
996	* @param pRegFrame Trap register frame.
997	* @param pvFault The fault address (cr2).
998	* @param GCPhysFault The GC physical address corresponding to pvFault.
999	* @param pvUser User argument.
1000	*/
1001	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1002	{
1003	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1004
1005	/*
1006	* Try interpret the instruction.
1007	*/
1008	uint32_t cb;
1009	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1010	if (VBOX_SUCCESS(rc) && cb)
1011	{
1012	/*
1013	* Check if any of the PDs have changed.
1014	* We'll simply check all of them instead of figuring out which one/two to check.
1015	*/
1016	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1017	{
1018	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1019	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1020	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1021	{
1022	/*
1023	* The PDPE has changed.
1024	* We will schedule a monitoring update for the next TLB Flush,
1025	* InvalidatePage or SyncCR3.
1026	*
1027	* This isn't perfect, because a lazy page sync might be dealing with an half
1028	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1029	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1030	* executing.
1031	*/
1032	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1033	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1034	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1035	}
1036	}
1037
1038	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1039	}
1040	else
1041	{
1042	Assert(VBOX_FAILURE(rc));
1043	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1044	if (rc == VERR_EM_INTERPRETER)
1045	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1046	}
1047	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1048	return rc;
1049	}
1050
1051
1052	/**
1053	* Write access handler for the Guest PDs in PAE mode.
1054	*
1055	* This will try interpret the instruction, if failure fail back to the recompiler.
1056	* Check if the changed PDEs are marked present and conflicts with our
1057	* mappings. If conflict, we'll switch to the host context and resolve it there
1058	*
1059	* @returns VBox status code (appropritate for trap handling and GC return).
1060	* @param pVM VM Handle.
1061	* @param uErrorCode CPU Error code.
1062	* @param pRegFrame Trap register frame.
1063	* @param pvFault The fault address (cr2).
1064	* @param GCPhysFault The GC physical address corresponding to pvFault.
1065	* @param pvUser User argument.
1066	*/
1067	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1068	{
1069	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1070
1071	/*
1072	* Try interpret the instruction.
1073	*/
1074	uint32_t cb;
1075	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1076	if (VBOX_SUCCESS(rc) && cb)
1077	{
1078	/*
1079	* Figure out which of the 4 PDs this is.
1080	*/
1081	RTGCUINTPTR i;
1082	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1083	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1084	{
1085	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1086	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1087	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1088	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1089
1090	Assert(cb > 0 && cb <= 8);
1091	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1092	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1093
1094	#ifdef DEBUG
1095	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1096	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1097	if (iPD1 != iPD2)
1098	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1099	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1100	#endif
1101
1102	if (!pVM->pgm.s.fMappingsFixed)
1103	{
1104	if ( ( pPDSrc->a[iPD1].n.u1Present
1105	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1106	\|\| ( iPD1 != iPD2
1107	&& pPDSrc->a[iPD2].n.u1Present
1108	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1109	)
1110	{
1111	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1112	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1113	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1114	return VINF_PGM_SYNC_CR3;
1115	}
1116	}
1117	break; /* ASSUMES no duplicate entries... */
1118	}
1119	Assert(i < 4);
1120
1121	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1122	}
1123	else
1124	{
1125	Assert(VBOX_FAILURE(rc));
1126	if (rc == VERR_EM_INTERPRETER)
1127	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1128	else
1129	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1130	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1131	}
1132	return rc;
1133	}
1134
1135	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1136

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 9776

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