PGMAllGst.h@ 9606

Last change on this file since 9606 was 9606, checked in by vboxsync, 16 years ago
X86_CR4_PSE changes for long mode (bit is ignored there)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 42.1 KB

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1	/* $Id: PGMAllGst.h 9606 2008-06-11 12:25:36Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48
49	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
50	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
51	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
52	# define GSTPT X86PT
53	# define PGSTPT PX86PT
54	# define GSTPTE X86PTE
55	# define PGSTPTE PX86PTE
56	# define GSTPD X86PD
57	# define PGSTPD PX86PD
58	# define GSTPDE X86PDE
59	# define PGSTPDE PX86PDE
60	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
61	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
62	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
63	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
64	# define GST_PD_SHIFT X86_PD_SHIFT
65	# define GST_PD_MASK X86_PD_MASK
66	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
67	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
68	# define GST_PT_SHIFT X86_PT_SHIFT
69	# define GST_PT_MASK X86_PT_MASK
70	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
71	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
73	# define GSTPT X86PTPAE
74	# define PGSTPT PX86PTPAE
75	# define GSTPTE X86PTEPAE
76	# define PGSTPTE PX86PTEPAE
77	# define GSTPD X86PDPAE
78	# define PGSTPD PX86PDPAE
79	# define GSTPDE X86PDEPAE
80	# define PGSTPDE PX86PDEPAE
81	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
86	# define GST_PD_MASK X86_PD_PAE_MASK
87	# if PGM_GST_TYPE == PGM_TYPE_PAE
88	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
89	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
90	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
91	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
92	# else
93	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
94	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
95	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
96	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
97	# endif
98	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
99	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
100	# define GST_PT_MASK X86_PT_PAE_MASK
101	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
102	#endif
103
104
105	/*******************************************************************************
106	* Internal Functions *
107	*******************************************************************************/
108	__BEGIN_DECLS
109	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
110	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
111	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
112	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
113	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
114	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
115	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
116	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
117	#ifndef IN_RING3
118	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
119	# if PGM_GST_TYPE == PGM_TYPE_PAE \
120	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
121	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
122	# endif
123	#endif
124	__END_DECLS
125
126
127
128	/**
129	* Gets effective Guest OS page information.
130	*
131	* When GCPtr is in a big page, the function will return as if it was a normal
132	* 4KB page. If the need for distinguishing between big and normal page becomes
133	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
134	* purpose.
135	*
136	* @returns VBox status.
137	* @param pVM VM Handle.
138	* @param GCPtr Guest Context virtual address of the page. Page aligned!
139	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
140	* @param pGCPhys Where to store the GC physical address of the page.
141	* This is page aligned. The fact that the
142	*/
143	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
144	{
145	#if PGM_GST_TYPE == PGM_TYPE_REAL \
146	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
147	/*
148	* Fake it.
149	*/
150	if (pfFlags)
151	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
152	if (pGCPhys)
153	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
154	return VINF_SUCCESS;
155
156	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
157
158	/*
159	* Get the PDE.
160	*/
161	# if PGM_GST_TYPE == PGM_TYPE_32BIT
162	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
163	#elif PGM_GST_TYPE == PGM_TYPE_PAE
164	X86PDEPAE Pde;
165	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
166
167	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
168	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
169	*/
170	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
171	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
172	PX86PML4E pPml4e;
173	X86PDPE Pdpe;
174	X86PDEPAE Pde;
175	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
176
177	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
178	Assert(pPml4e);
179	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
180	return VERR_PAGE_TABLE_NOT_PRESENT;
181
182	/* Merge accessed, write, user and no-execute bits into the PDE. */
183	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
184	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
185	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
186	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
187	# endif
188
189	/*
190	* Lookup the page.
191	*/
192	if (!Pde.n.u1Present)
193	return VERR_PAGE_TABLE_NOT_PRESENT;
194
195	if ( !Pde.b.u1Size
196	# if PGM_GST_TYPE != PGM_TYPE_AMD64
197	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
198	# endif
199	)
200	{
201	PGSTPT pPT;
202	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
203	if (VBOX_FAILURE(rc))
204	return rc;
205
206	/*
207	* Get PT entry and check presence.
208	*/
209	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
210	if (!Pte.n.u1Present)
211	return VERR_PAGE_NOT_PRESENT;
212
213	/*
214	* Store the result.
215	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
216	* where the PDPE is simplified.
217	*/
218	if (pfFlags)
219	{
220	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
221	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
222	# if PGM_WITH_NX(PGM_GST_TYPE)
223	/* The NX bit is determined by a bitwise OR between the PT and PD */
224	if (fNoExecuteBitValid)
225	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
226	# endif
227	}
228	if (pGCPhys)
229	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
230	}
231	else
232	{
233	/*
234	* Map big to 4k PTE and store the result
235	*/
236	if (pfFlags)
237	{
238	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
239	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
240	# if PGM_WITH_NX(PGM_GST_TYPE)
241	/* The NX bit is determined by a bitwise OR between the PT and PD */
242	if (fNoExecuteBitValid)
243	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
244	# endif
245	}
246	if (pGCPhys)
247	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
248	}
249	return VINF_SUCCESS;
250	#else
251	# error "shouldn't be here!"
252	/* something else... */
253	return VERR_NOT_SUPPORTED;
254	#endif
255	}
256
257
258	/**
259	* Modify page flags for a range of pages in the guest's tables
260	*
261	* The existing flags are ANDed with the fMask and ORed with the fFlags.
262	*
263	* @returns VBox status code.
264	* @param pVM VM handle.
265	* @param GCPtr Virtual address of the first page in the range. Page aligned!
266	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
267	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
268	* @param fMask The AND mask - page flags X86_PTE_*.
269	*/
270	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
271	{
272	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
273	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
274	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
275
276	for (;;)
277	{
278	/*
279	* Get the PD entry.
280	*/
281	# if PGM_GST_TYPE == PGM_TYPE_32BIT
282	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
283	# elif PGM_GST_TYPE == PGM_TYPE_PAE
284	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
285	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
286	*/
287	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
288	Assert(pPde);
289	if (!pPde)
290	return VERR_PAGE_TABLE_NOT_PRESENT;
291	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
292	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
293	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
294	Assert(pPde);
295	if (!pPde)
296	return VERR_PAGE_TABLE_NOT_PRESENT;
297	# endif
298	GSTPDE Pde = *pPde;
299	Assert(Pde.n.u1Present);
300	if (!Pde.n.u1Present)
301	return VERR_PAGE_TABLE_NOT_PRESENT;
302
303	if ( !Pde.b.u1Size
304	# if PGM_GST_TYPE != PGM_TYPE_AMD64
305	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
306	# endif
307	)
308	{
309	/*
310	* 4KB Page table
311	*
312	* Walk page tables and pages till we're done.
313	*/
314	PGSTPT pPT;
315	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
316	if (VBOX_FAILURE(rc))
317	return rc;
318
319	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
320	while (iPTE < RT_ELEMENTS(pPT->a))
321	{
322	GSTPTE Pte = pPT->a[iPTE];
323	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
324	\| (fFlags & ~GST_PTE_PG_MASK);
325	pPT->a[iPTE] = Pte;
326
327	/* next page */
328	cb -= PAGE_SIZE;
329	if (!cb)
330	return VINF_SUCCESS;
331	GCPtr += PAGE_SIZE;
332	iPTE++;
333	}
334	}
335	else
336	{
337	/*
338	* 4MB Page table
339	*/
340	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
341	\| (fFlags & ~GST_PTE_PG_MASK)
342	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
343	*pPde = Pde;
344
345	/* advance */
346	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
347	if (cbDone >= cb)
348	return VINF_SUCCESS;
349	cb -= cbDone;
350	GCPtr += cbDone;
351	}
352	}
353
354	#else
355	/* real / protected mode: ignore. */
356	return VINF_SUCCESS;
357	#endif
358	}
359
360
361	/**
362	* Retrieve guest PDE information
363	*
364	* @returns VBox status code.
365	* @param pVM The virtual machine.
366	* @param GCPtr Guest context pointer
367	* @param pPDE Pointer to guest PDE structure
368	*/
369	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
370	{
371	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
372	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
373	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
374
375	# if PGM_GST_TYPE == PGM_TYPE_32BIT
376	X86PDE Pde;
377	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
378	# elif PGM_GST_TYPE == PGM_TYPE_PAE
379	X86PDEPAE Pde;
380	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
381	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
382	X86PDEPAE Pde;
383	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
384	# endif
385
386	pPDE->u = (X86PGPAEUINT)Pde.u;
387	return VINF_SUCCESS;
388	#else
389	AssertFailed();
390	return VERR_NOT_IMPLEMENTED;
391	#endif
392	}
393
394
395
396	/**
397	* Maps the CR3 into HMA in GC and locate it in HC.
398	*
399	* @returns VBox status, no specials.
400	* @param pVM VM handle.
401	* @param GCPhysCR3 The physical address in the CR3 register.
402	*/
403	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
404	{
405	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
406	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
407	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
408
409	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
410
411	/*
412	* Map the page CR3 points at.
413	*/
414	RTHCPHYS HCPhysGuestCR3;
415	RTHCPTR HCPtrGuestCR3;
416	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
417	if (VBOX_SUCCESS(rc))
418	{
419	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
420	if (VBOX_SUCCESS(rc))
421	{
422	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
423	# if PGM_GST_TYPE == PGM_TYPE_32BIT
424	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
425	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
426
427	# elif PGM_GST_TYPE == PGM_TYPE_PAE
428	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
429	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
430	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
431	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
432
433	/*
434	* Map the 4 PDs too.
435	*/
436	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
437	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
438	{
439	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
440	{
441	RTHCPTR HCPtr;
442	RTHCPHYS HCPhys;
443	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
444	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
445	if (VBOX_SUCCESS(rc2))
446	{
447	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
448	AssertRCReturn(rc, rc);
449	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
450	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
451	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
452	PGM_INVL_PG(GCPtr);
453	continue;
454	}
455	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
456	}
457
458	pVM->pgm.s.apGstPaePDsHC[i] = 0;
459	pVM->pgm.s.apGstPaePDsGC[i] = 0;
460	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
461	PGM_INVL_PG(GCPtr);
462	}
463	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
464	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
465	# endif
466	}
467	else
468	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
469	}
470	else
471	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
472
473	#else /* prot/real stub */
474	int rc = VINF_SUCCESS;
475	#endif
476	return rc;
477	}
478
479
480	/**
481	* Unmaps the CR3.
482	*
483	* @returns VBox status, no specials.
484	* @param pVM VM handle.
485	* @param GCPhysCR3 The physical address in the CR3 register.
486	*/
487	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
488	{
489	LogFlow(("UnmapCR3\n"));
490
491	int rc = VINF_SUCCESS;
492	#if PGM_GST_TYPE == PGM_TYPE_32BIT
493	pVM->pgm.s.pGuestPDHC = 0;
494	pVM->pgm.s.pGuestPDGC = 0;
495
496	#elif PGM_GST_TYPE == PGM_TYPE_PAE
497	pVM->pgm.s.pGstPaePDPTHC = 0;
498	pVM->pgm.s.pGstPaePDPTGC = 0;
499	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
500	{
501	pVM->pgm.s.apGstPaePDsHC[i] = 0;
502	pVM->pgm.s.apGstPaePDsGC[i] = 0;
503	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
504	}
505
506	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
507	pVM->pgm.s.pGstPaePML4HC = 0;
508	#else /* prot/real mode stub */
509	/* nothing to do */
510	#endif
511	return rc;
512	}
513
514
515	#undef LOG_GROUP
516	#define LOG_GROUP LOG_GROUP_PGM_POOL
517
518	/**
519	* Registers physical page monitors for the necessary paging
520	* structures to detect conflicts with our guest mappings.
521	*
522	* This is always called after mapping CR3.
523	* This is never called with fixed mappings.
524	*
525	* @returns VBox status, no specials.
526	* @param pVM VM handle.
527	* @param GCPhysCR3 The physical address in the CR3 register.
528	*/
529	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
530	{
531	Assert(!pVM->pgm.s.fMappingsFixed);
532	int rc = VINF_SUCCESS;
533
534	/*
535	* Register/Modify write phys handler for guest's CR3 if it changed.
536	*/
537	#if PGM_GST_TYPE == PGM_TYPE_32BIT
538
539	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
540	{
541	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
542	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
543	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
544	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
545	else
546	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
547	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
548	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
549	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
550	pVM->pgm.s.pszR3GstWriteHandlerCR3);
551	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
552	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
553	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
554	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
555	? PGMPOOL_IDX_PAE_PD
556	: PGMPOOL_IDX_PD,
557	GCPhysCR3);
558	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
559	if (VBOX_FAILURE(rc))
560	{
561	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
562	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
563	return rc;
564	}
565	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
566	}
567
568	#elif PGM_GST_TYPE == PGM_TYPE_PAE
569	/* Monitor the PDPT page */
570	/*
571	* Register/Modify write phys handler for guest's CR3 if it changed.
572	*/
573	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
574	AssertFailed();
575	# endif
576	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
577	{
578	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
579	if (VBOX_FAILURE(rc))
580	{
581	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
582	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
583	return rc;
584	}
585	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
586	}
587	/*
588	* Do the 4 PDs.
589	*/
590	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
591	{
592	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
593	{
594	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
595	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
596	{
597	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
598
599	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
600	}
601
602	if (VBOX_FAILURE(rc))
603	{
604	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
605	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
606	return rc;
607	}
608	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
609	}
610	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
611	{
612	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
613	AssertRC(rc);
614	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
615	}
616	}
617
618	#else
619	/* prot/real/amd64 mode stub */
620
621	#endif
622	return rc;
623	}
624
625	/**
626	* Deregisters any physical page monitors installed by MonitorCR3.
627	*
628	* @returns VBox status code, no specials.
629	* @param pVM The VM handle.
630	*/
631	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
632	{
633	int rc = VINF_SUCCESS;
634
635	/*
636	* Deregister the access handlers.
637	*
638	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
639	* before we enter GC again.
640	*/
641	#if PGM_GST_TYPE == PGM_TYPE_32BIT
642	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
643	{
644	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
645	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
646	AssertRCReturn(rc, rc);
647	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
648	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
649	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
650	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
651	? PGMPOOL_IDX_PAE_PD
652	: PGMPOOL_IDX_PD);
653	AssertRCReturn(rc, rc);
654	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
655	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
656	}
657
658	#elif PGM_GST_TYPE == PGM_TYPE_PAE
659	/* The PDPT page */
660	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
661	AssertFailed();
662	# endif
663
664	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
665	{
666	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
667	AssertRC(rc);
668	}
669
670	/* The 4 PDs. */
671	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
672	{
673	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
674	{
675	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
676	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
677	AssertRC(rc2);
678	if (VBOX_FAILURE(rc2))
679	rc = rc2;
680	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
681	}
682	}
683	#else
684	/* prot/real/amd64 mode stub */
685	#endif
686	return rc;
687
688	}
689
690	#undef LOG_GROUP
691	#define LOG_GROUP LOG_GROUP_PGM
692
693
694	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
695	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
696	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
697	/**
698	* Updates one virtual handler range.
699	*
700	* @returns 0
701	* @param pNode Pointer to a PGMVIRTHANDLER.
702	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
703	*/
704	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
705	{
706	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
707	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
708	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
709
710	#if PGM_GST_TYPE == PGM_TYPE_32BIT
711	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
712	#endif
713
714	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
715	#if PGM_GST_MODE != PGM_MODE_AMD64
716	/* skip all stuff above 4GB if not AMD64 mode. */
717	if (GCPtr >= _4GB)
718	return 0;
719	#endif
720
721	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
722	unsigned iPage = 0;
723	while (iPage < pCur->cPages)
724	{
725	#if PGM_GST_TYPE == PGM_TYPE_32BIT
726	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
727	#elif PGM_GST_TYPE == PGM_TYPE_PAE
728	X86PDEPAE Pde;
729	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
730	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
731	X86PDEPAE Pde;
732	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
733	#endif
734	if (Pde.n.u1Present)
735	{
736	if ( !Pde.b.u1Size
737	# if PGM_GST_TYPE != PGM_TYPE_AMD64
738	\|\| !(pState->cr4 & X86_CR4_PSE)
739	# endif
740	)
741	{
742	/*
743	* Normal page table.
744	*/
745	PGSTPT pPT;
746	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
747	if (VBOX_SUCCESS(rc))
748	{
749	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
750	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
751	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
752	{
753	GSTPTE Pte = pPT->a[iPTE];
754	RTGCPHYS GCPhysNew;
755	if (Pte.n.u1Present)
756	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
757	else
758	GCPhysNew = NIL_RTGCPHYS;
759	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
760	{
761	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
762	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
763	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
764	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
765	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
766	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
767	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
768	#endif
769	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
770	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
771	}
772	}
773	}
774	else
775	{
776	/* not-present. */
777	offPage = 0;
778	AssertRC(rc);
779	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
780	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
781	iPTE++, iPage++, GCPtr += PAGE_SIZE)
782	{
783	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
784	{
785	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
786	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
787	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
788	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
789	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
790	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
791	#endif
792	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
793	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
794	}
795	}
796	}
797	}
798	else
799	{
800	/*
801	* 2/4MB page.
802	*/
803	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
804	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
805	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
806	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
807	{
808	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
809	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
810	{
811	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
812	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
813	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
814	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
815	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
816	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
817	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
818	#endif
819	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
820	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
821	}
822	}
823	} /* pde type */
824	}
825	else
826	{
827	/* not-present. */
828	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
829	cPages && iPage < pCur->cPages;
830	iPage++, GCPtr += PAGE_SIZE)
831	{
832	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
833	{
834	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
835	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
836	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
837	}
838	}
839	offPage = 0;
840	}
841	} /* for pages in virtual mapping. */
842
843	return 0;
844	}
845	#endif /* 32BIT, PAE and AMD64 */
846
847
848	/**
849	* Updates the virtual page access handlers.
850	*
851	* @returns true if bits were flushed.
852	* @returns false if bits weren't flushed.
853	* @param pVM VM handle.
854	* @param pPDSrc The page directory.
855	* @param cr4 The cr4 register value.
856	*/
857	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
858	{
859	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
860	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
861	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
862
863	/** @todo
864	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
865	*/
866
867	/*
868	* Resolve any virtual address based access handlers to GC physical addresses.
869	* This should be fairly quick.
870	*/
871	PGMHVUSTATE State;
872
873	pgmLock(pVM);
874	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
875	State.pVM = pVM;
876	State.fTodo = pVM->pgm.s.fSyncFlags;
877	State.cr4 = cr4;
878	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
879	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
880
881
882	/*
883	* Set / reset bits?
884	*/
885	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
886	{
887	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
888	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
889	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
890	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
891	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
892	}
893	pgmUnlock(pVM);
894
895	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
896
897	#else /* real / protected */
898	return false;
899	#endif
900	}
901
902
903	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
904
905	/**
906	* Write access handler for the Guest CR3 page in 32-bit mode.
907	*
908	* This will try interpret the instruction, if failure fail back to the recompiler.
909	* Check if the changed PDEs are marked present and conflicts with our
910	* mappings. If conflict, we'll switch to the host context and resolve it there
911	*
912	* @returns VBox status code (appropritate for trap handling and GC return).
913	* @param pVM VM Handle.
914	* @param uErrorCode CPU Error code.
915	* @param pRegFrame Trap register frame.
916	* @param pvFault The fault address (cr2).
917	* @param GCPhysFault The GC physical address corresponding to pvFault.
918	* @param pvUser User argument.
919	*/
920	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
921	{
922	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
923
924	/*
925	* Try interpret the instruction.
926	*/
927	uint32_t cb;
928	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
929	if (VBOX_SUCCESS(rc) && cb)
930	{
931	/*
932	* Check if the modified PDEs are present and mappings.
933	*/
934	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
935	const unsigned iPD1 = offPD / sizeof(X86PDE);
936	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
937
938	Assert(cb > 0 && cb <= 8);
939	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
940	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
941
942	#ifdef DEBUG
943	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
944	if (iPD1 != iPD2)
945	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
946	#endif
947
948	if (!pVM->pgm.s.fMappingsFixed)
949	{
950	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
951	if ( ( pPDSrc->a[iPD1].n.u1Present
952	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
953	\|\| ( iPD1 != iPD2
954	&& pPDSrc->a[iPD2].n.u1Present
955	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
956	)
957	{
958	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
959	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
960	if (rc == VINF_SUCCESS)
961	rc = VINF_PGM_SYNC_CR3;
962	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
963	return rc;
964	}
965	}
966
967	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
968	}
969	else
970	{
971	Assert(VBOX_FAILURE(rc));
972	if (rc == VERR_EM_INTERPRETER)
973	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
974	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
975	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
976	}
977	return rc;
978	}
979
980	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
981
982
983	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
984
985	/**
986	* Write access handler for the Guest CR3 page in PAE mode.
987	*
988	* This will try interpret the instruction, if failure fail back to the recompiler.
989	* Check if the changed PDEs are marked present and conflicts with our
990	* mappings. If conflict, we'll switch to the host context and resolve it there
991	*
992	* @returns VBox status code (appropritate for trap handling and GC return).
993	* @param pVM VM Handle.
994	* @param uErrorCode CPU Error code.
995	* @param pRegFrame Trap register frame.
996	* @param pvFault The fault address (cr2).
997	* @param GCPhysFault The GC physical address corresponding to pvFault.
998	* @param pvUser User argument.
999	*/
1000	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1001	{
1002	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1003
1004	/*
1005	* Try interpret the instruction.
1006	*/
1007	uint32_t cb;
1008	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1009	if (VBOX_SUCCESS(rc) && cb)
1010	{
1011	/*
1012	* Check if any of the PDs have changed.
1013	* We'll simply check all of them instead of figuring out which one/two to check.
1014	*/
1015	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1016	{
1017	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1018	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1019	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1020	{
1021	/*
1022	* The PDPE has changed.
1023	* We will schedule a monitoring update for the next TLB Flush,
1024	* InvalidatePage or SyncCR3.
1025	*
1026	* This isn't perfect, because a lazy page sync might be dealing with an half
1027	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1028	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1029	* executing.
1030	*/
1031	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1032	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1033	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1034	}
1035	}
1036
1037	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1038	}
1039	else
1040	{
1041	Assert(VBOX_FAILURE(rc));
1042	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1043	if (rc == VERR_EM_INTERPRETER)
1044	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1045	}
1046	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1047	return rc;
1048	}
1049
1050
1051	/**
1052	* Write access handler for the Guest PDs in PAE mode.
1053	*
1054	* This will try interpret the instruction, if failure fail back to the recompiler.
1055	* Check if the changed PDEs are marked present and conflicts with our
1056	* mappings. If conflict, we'll switch to the host context and resolve it there
1057	*
1058	* @returns VBox status code (appropritate for trap handling and GC return).
1059	* @param pVM VM Handle.
1060	* @param uErrorCode CPU Error code.
1061	* @param pRegFrame Trap register frame.
1062	* @param pvFault The fault address (cr2).
1063	* @param GCPhysFault The GC physical address corresponding to pvFault.
1064	* @param pvUser User argument.
1065	*/
1066	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1067	{
1068	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1069
1070	/*
1071	* Try interpret the instruction.
1072	*/
1073	uint32_t cb;
1074	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1075	if (VBOX_SUCCESS(rc) && cb)
1076	{
1077	/*
1078	* Figure out which of the 4 PDs this is.
1079	*/
1080	RTGCUINTPTR i;
1081	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1082	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1083	{
1084	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1085	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1086	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1087	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1088
1089	Assert(cb > 0 && cb <= 8);
1090	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1091	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1092
1093	#ifdef DEBUG
1094	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1095	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1096	if (iPD1 != iPD2)
1097	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1098	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1099	#endif
1100
1101	if (!pVM->pgm.s.fMappingsFixed)
1102	{
1103	if ( ( pPDSrc->a[iPD1].n.u1Present
1104	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1105	\|\| ( iPD1 != iPD2
1106	&& pPDSrc->a[iPD2].n.u1Present
1107	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1108	)
1109	{
1110	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1111	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1112	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1113	return VINF_PGM_SYNC_CR3;
1114	}
1115	}
1116	break; /* ASSUMES no duplicate entries... */
1117	}
1118	Assert(i < 4);
1119
1120	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1121	}
1122	else
1123	{
1124	Assert(VBOX_FAILURE(rc));
1125	if (rc == VERR_EM_INTERPRETER)
1126	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1127	else
1128	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1129	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1130	}
1131	return rc;
1132	}
1133
1134	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1135

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 9606

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