PGMAllGst.h@ 77807

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1	/* $Id: PGMAllGst.h 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Internal Functions *
21	*********************************************************************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	static int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
31	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
32
33	#ifdef IN_RING3 /* r3 only for now. */
34	PGM_GST_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
35	PGM_GST_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
36	PGM_GST_DECL(int, Exit)(PVMCPU pVCpu);
37	#endif
38	RT_C_DECLS_END
39
40
41	/**
42	* Enters the guest mode.
43	*
44	* @returns VBox status code.
45	* @param pVCpu The cross context virtual CPU structure.
46	* @param GCPhysCR3 The physical address from the CR3 register.
47	*/
48	PGM_GST_DECL(int, Enter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
49	{
50	/*
51	* Map and monitor CR3
52	*/
53	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
54	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
55	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
56	return g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
57	}
58
59
60	/**
61	* Exits the guest mode.
62	*
63	* @returns VBox status code.
64	* @param pVCpu The cross context virtual CPU structure.
65	*/
66	PGM_GST_DECL(int, Exit)(PVMCPU pVCpu)
67	{
68	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
69	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
70	AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
71	return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
72	}
73
74
75	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
76	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
77	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
78
79
80	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
81	{
82	NOREF(iLevel); NOREF(pVCpu);
83	pWalk->Core.fNotPresent = true;
84	pWalk->Core.uLevel = (uint8_t)iLevel;
85	return VERR_PAGE_TABLE_NOT_PRESENT;
86	}
87
88	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel, int rc)
89	{
90	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
91	pWalk->Core.fBadPhysAddr = true;
92	pWalk->Core.uLevel = (uint8_t)iLevel;
93	return VERR_PAGE_TABLE_NOT_PRESENT;
94	}
95
96	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
97	{
98	NOREF(pVCpu);
99	pWalk->Core.fRsvdError = true;
100	pWalk->Core.uLevel = (uint8_t)iLevel;
101	return VERR_PAGE_TABLE_NOT_PRESENT;
102	}
103
104
105	/**
106	* Performs a guest page table walk.
107	*
108	* @returns VBox status code.
109	* @retval VINF_SUCCESS on success.
110	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
111	*
112	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
113	* @param GCPtr The guest virtual address to walk by.
114	* @param pWalk Where to return the walk result. This is always set.
115	*/
116	DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
117	{
118	int rc;
119
120	/*
121	* Init the walking structure.
122	*/
123	RT_ZERO(*pWalk);
124	pWalk->Core.GCPtr = GCPtr;
125
126	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
127	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
128	/*
129	* Boundary check for PAE and 32-bit (prevents trouble further down).
130	*/
131	if (RT_UNLIKELY(GCPtr >= _4G))
132	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
133	# endif
134
135	uint32_t register fEffective = X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A \| 1;
136	{
137	# if PGM_GST_TYPE == PGM_TYPE_AMD64
138	/*
139	* The PMLE4.
140	*/
141	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
142	if (RT_SUCCESS(rc)) { /* probable */ }
143	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
144
145	PX86PML4E register pPml4e;
146	pWalk->pPml4e = pPml4e = &pWalk->pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
147	X86PML4E register Pml4e;
148	pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
149
150	if (Pml4e.n.u1Present) { /* probable */ }
151	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
152
153	if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
154	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
155
156	pWalk->Core.fEffective = fEffective = ((uint32_t)Pml4e.u & (X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_PWT \| X86_PML4E_PCD \| X86_PML4E_A))
157	\| ((uint32_t)(Pml4e.u >> 63) ^ 1) /NX /;
158
159	/*
160	* The PDPE.
161	*/
162	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pWalk->pPdpt);
163	if (RT_SUCCESS(rc)) { /* probable */ }
164	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
165
166	# elif PGM_GST_TYPE == PGM_TYPE_PAE
167	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
168	if (RT_SUCCESS(rc)) { /* probable */ }
169	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
170	# endif
171	}
172	{
173	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
174	PX86PDPE register pPdpe;
175	pWalk->pPdpe = pPdpe = &pWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
176	X86PDPE register Pdpe;
177	pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
178
179	if (Pdpe.n.u1Present) { /* probable */ }
180	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
181
182	if (RT_LIKELY(GST_IS_PDPE_VALID(pVCpu, Pdpe))) { /* likely */ }
183	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
184
185	# if PGM_GST_TYPE == PGM_TYPE_AMD64
186	pWalk->Core.fEffective = fEffective &= ((uint32_t)Pdpe.u & (X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_PWT \| X86_PDPE_PCD \| X86_PDPE_A))
187	\| ((uint32_t)(Pdpe.u >> 63) ^ 1) /NX /;
188	# else
189	pWalk->Core.fEffective = fEffective = X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A
190	\| ((uint32_t)Pdpe.u & (X86_PDPE_PWT \| X86_PDPE_PCD))
191	\| ((uint32_t)(Pdpe.u >> 63) ^ 1) /NX /;
192	# endif
193
194	/*
195	* The PDE.
196	*/
197	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pWalk->pPd);
198	if (RT_SUCCESS(rc)) { /* probable */ }
199	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
200	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
201	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
202	if (RT_SUCCESS(rc)) { /* probable */ }
203	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
204	# endif
205	}
206	{
207	PGSTPDE register pPde;
208	pWalk->pPde = pPde = &pWalk->pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
209	GSTPDE Pde;
210	pWalk->Pde.u = Pde.u = pPde->u;
211	if (Pde.n.u1Present) { /* probable */ }
212	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
213	if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
214	{
215	if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
216	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
217
218	/*
219	* We're done.
220	*/
221	# if PGM_GST_TYPE == PGM_TYPE_32BIT
222	fEffective &= Pde.u & (X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A);
223	# else
224	fEffective &= ((uint32_t)Pde.u & (X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A))
225	\| ((uint32_t)(Pde.u >> 63) ^ 1) /NX /;
226	# endif
227	fEffective \|= (uint32_t)Pde.u & (X86_PDE4M_D \| X86_PDE4M_G);
228	fEffective \|= (uint32_t)(Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT;
229	pWalk->Core.fEffective = fEffective;
230
231	pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
232	pWalk->Core.fEffectiveUS = !!(fEffective & X86_PTE_US);
233	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
234	pWalk->Core.fEffectiveNX = !(fEffective & 1) && GST_IS_NX_ACTIVE(pVCpu);
235	# else
236	pWalk->Core.fEffectiveNX = false;
237	# endif
238	pWalk->Core.fBigPage = true;
239	pWalk->Core.fSucceeded = true;
240
241	pWalk->Core.GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
242	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
243	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->Core.GCPhys);
244	return VINF_SUCCESS;
245	}
246
247	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
248	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
249	# if PGM_GST_TYPE == PGM_TYPE_32BIT
250	pWalk->Core.fEffective = fEffective &= Pde.u & (X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A);
251	# else
252	pWalk->Core.fEffective = fEffective &= ((uint32_t)Pde.u & (X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A))
253	\| ((uint32_t)(Pde.u >> 63) ^ 1) /NX /;
254	# endif
255
256	/*
257	* The PTE.
258	*/
259	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pWalk->pPt);
260	if (RT_SUCCESS(rc)) { /* probable */ }
261	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
262	}
263	{
264	PGSTPTE register pPte;
265	pWalk->pPte = pPte = &pWalk->pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
266	GSTPTE register Pte;
267	pWalk->Pte.u = Pte.u = pPte->u;
268
269	if (Pte.n.u1Present) { /* probable */ }
270	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
271
272	if (RT_LIKELY(GST_IS_PTE_VALID(pVCpu, Pte))) { /* likely */ }
273	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
274
275	/*
276	* We're done.
277	*/
278	# if PGM_GST_TYPE == PGM_TYPE_32BIT
279	fEffective &= Pte.u & (X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A);
280	# else
281	fEffective &= ((uint32_t)Pte.u & (X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A))
282	\| ((uint32_t)(Pte.u >> 63) ^ 1) /NX /;
283	# endif
284	fEffective \|= (uint32_t)Pte.u & (X86_PTE_D \| X86_PTE_PAT \| X86_PTE_G);
285	pWalk->Core.fEffective = fEffective;
286
287	pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
288	pWalk->Core.fEffectiveUS = !!(fEffective & X86_PTE_US);
289	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
290	pWalk->Core.fEffectiveNX = !(fEffective & 1) && GST_IS_NX_ACTIVE(pVCpu);
291	# else
292	pWalk->Core.fEffectiveNX = false;
293	# endif
294	pWalk->Core.fSucceeded = true;
295
296	pWalk->Core.GCPhys = GST_GET_PDE_GCPHYS(Pte)
297	\| (GCPtr & PAGE_OFFSET_MASK);
298	return VINF_SUCCESS;
299	}
300	}
301
302	#endif /* 32BIT, PAE, AMD64 */
303
304	/**
305	* Gets effective Guest OS page information.
306	*
307	* When GCPtr is in a big page, the function will return as if it was a normal
308	* 4KB page. If the need for distinguishing between big and normal page becomes
309	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
310	* purpose.
311	*
312	* @returns VBox status code.
313	* @param pVCpu The cross context virtual CPU structure.
314	* @param GCPtr Guest Context virtual address of the page.
315	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
316	* @param pGCPhys Where to store the GC physical address of the page.
317	* This is page aligned!
318	*/
319	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
320	{
321	#if PGM_GST_TYPE == PGM_TYPE_REAL \
322	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
323	/*
324	* Fake it.
325	*/
326	if (pfFlags)
327	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
328	if (pGCPhys)
329	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
330	NOREF(pVCpu);
331	return VINF_SUCCESS;
332
333	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
334	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
335	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
336
337	GSTPTWALK Walk;
338	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
339	if (RT_FAILURE(rc))
340	return rc;
341
342	if (pGCPhys)
343	*pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
344
345	if (pfFlags)
346	{
347	if (!Walk.Core.fBigPage)
348	pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK \| X86_PTE_RW \| X86_PTE_US)) / NX not needed */
349	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
350	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
351	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
352	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
353	# endif
354	;
355	else
356	{
357	pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PS)) / NX not needed */
358	\| ((Walk.Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT)
359	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
360	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
361	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
362	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
363	# endif
364	;
365	}
366	}
367
368	return VINF_SUCCESS;
369
370	#else
371	# error "shouldn't be here!"
372	/* something else... */
373	return VERR_NOT_SUPPORTED;
374	#endif
375	}
376
377
378	/**
379	* Modify page flags for a range of pages in the guest's tables
380	*
381	* The existing flags are ANDed with the fMask and ORed with the fFlags.
382	*
383	* @returns VBox status code.
384	* @param pVCpu The cross context virtual CPU structure.
385	* @param GCPtr Virtual address of the first page in the range. Page aligned!
386	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
387	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
388	* @param fMask The AND mask - page flags X86_PTE_*.
389	*/
390	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
391	{
392	Assert((cb & PAGE_OFFSET_MASK) == 0); RT_NOREF_PV(cb);
393
394	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
395	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
396	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
397	for (;;)
398	{
399	GSTPTWALK Walk;
400	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
401	if (RT_FAILURE(rc))
402	return rc;
403
404	if (!Walk.Core.fBigPage)
405	{
406	/*
407	* 4KB Page table, process
408	*
409	* Walk pages till we're done.
410	*/
411	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
412	while (iPTE < RT_ELEMENTS(Walk.pPt->a))
413	{
414	GSTPTE Pte = Walk.pPt->a[iPTE];
415	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
416	\| (fFlags & ~GST_PTE_PG_MASK);
417	Walk.pPt->a[iPTE] = Pte;
418
419	/* next page */
420	cb -= PAGE_SIZE;
421	if (!cb)
422	return VINF_SUCCESS;
423	GCPtr += PAGE_SIZE;
424	iPTE++;
425	}
426	}
427	else
428	{
429	/*
430	* 2/4MB Page table
431	*/
432	GSTPDE PdeNew;
433	# if PGM_GST_TYPE == PGM_TYPE_32BIT
434	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
435	# else
436	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
437	# endif
438	\| (fFlags & ~GST_PTE_PG_MASK)
439	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
440	*Walk.pPde = PdeNew;
441
442	/* advance */
443	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
444	if (cbDone >= cb)
445	return VINF_SUCCESS;
446	cb -= cbDone;
447	GCPtr += cbDone;
448	}
449	}
450
451	#else
452	/* real / protected mode: ignore. */
453	NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
454	return VINF_SUCCESS;
455	#endif
456	}
457
458
459	/**
460	* Retrieve guest PDE information.
461	*
462	* @returns VBox status code.
463	* @param pVCpu The cross context virtual CPU structure.
464	* @param GCPtr Guest context pointer.
465	* @param pPDE Pointer to guest PDE structure.
466	*/
467	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
468	{
469	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
470	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
471	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
472
473	# if PGM_GST_TYPE != PGM_TYPE_AMD64
474	/* Boundary check. */
475	if (RT_UNLIKELY(GCPtr >= _4G))
476	return VERR_PAGE_TABLE_NOT_PRESENT;
477	# endif
478
479	# if PGM_GST_TYPE == PGM_TYPE_32BIT
480	unsigned iPd = (GCPtr >> GST_PD_SHIFT) & GST_PD_MASK;
481	PX86PD pPd = pgmGstGet32bitPDPtr(pVCpu);
482
483	# elif PGM_GST_TYPE == PGM_TYPE_PAE
484	unsigned iPd = 0; /* shut up gcc */
485	PCX86PDPAE pPd = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPd, NULL);
486
487	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
488	PX86PML4E pPml4eIgn;
489	X86PDPE PdpeIgn;
490	unsigned iPd = 0; /* shut up gcc */
491	PCX86PDPAE pPd = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eIgn, &PdpeIgn, &iPd);
492	/* Note! We do not return an effective PDE here like we do for the PTE in GetPage method. */
493	# endif
494
495	if (RT_LIKELY(pPd))
496	pPDE->u = (X86PGPAEUINT)pPd->a[iPd].u;
497	else
498	pPDE->u = 0;
499	return VINF_SUCCESS;
500
501	#else
502	NOREF(pVCpu); NOREF(GCPtr); NOREF(pPDE);
503	AssertFailed();
504	return VERR_NOT_IMPLEMENTED;
505	#endif
506	}
507
508
509	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
510	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
511	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
512	&& defined(VBOX_WITH_RAW_MODE)
513	/**
514	* Updates one virtual handler range.
515	*
516	* @returns 0
517	* @param pNode Pointer to a PGMVIRTHANDLER.
518	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
519	*/
520	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
521	{
522	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
523	PVM pVM = pState->pVM;
524	PVMCPU pVCpu = pState->pVCpu;
525	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
526	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
527
528	Assert(pCurType->enmKind != PGMVIRTHANDLERKIND_HYPERVISOR); NOREF(pCurType);
529
530	# if PGM_GST_TYPE == PGM_TYPE_32BIT
531	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
532	# endif
533
534	RTGCPTR GCPtr = pCur->Core.Key;
535	# if PGM_GST_TYPE != PGM_TYPE_AMD64
536	/* skip all stuff above 4GB if not AMD64 mode. */
537	if (RT_UNLIKELY(GCPtr >= _4G))
538	return 0;
539	# endif
540
541	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
542	unsigned iPage = 0;
543	while (iPage < pCur->cPages)
544	{
545	# if PGM_GST_TYPE == PGM_TYPE_32BIT
546	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
547	# elif PGM_GST_TYPE == PGM_TYPE_PAE
548	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
549	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
550	X86PDEPAE Pde = pgmGstGetLongModePDE(pVCpu, GCPtr);
551	# endif
552	# if PGM_GST_TYPE == PGM_TYPE_32BIT
553	bool const fBigPage = Pde.b.u1Size && (pState->cr4 & X86_CR4_PSE);
554	# else
555	bool const fBigPage = Pde.b.u1Size;
556	# endif
557	if ( Pde.n.u1Present
558	&& ( !fBigPage
559	? GST_IS_PDE_VALID(pVCpu, Pde)
560	: GST_IS_BIG_PDE_VALID(pVCpu, Pde)) )
561	{
562	if (!fBigPage)
563	{
564	/*
565	* Normal page table.
566	*/
567	PGSTPT pPT;
568	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(Pde), &pPT);
569	if (RT_SUCCESS(rc))
570	{
571	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
572	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
573	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
574	{
575	GSTPTE Pte = pPT->a[iPTE];
576	RTGCPHYS GCPhysNew;
577	if (Pte.n.u1Present)
578	GCPhysNew = PGM_A20_APPLY(pVCpu, (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage);
579	else
580	GCPhysNew = NIL_RTGCPHYS;
581	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
582	{
583	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
584	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
585	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
586	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
587	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
588	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
589	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
590	#endif
591	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
592	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
593	}
594	}
595	}
596	else
597	{
598	/* not-present. */
599	offPage = 0;
600	AssertRC(rc);
601	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
602	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
603	iPTE++, iPage++, GCPtr += PAGE_SIZE)
604	{
605	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
606	{
607	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
608	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
609	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
610	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
611	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
612	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
613	#endif
614	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
615	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
616	}
617	}
618	}
619	}
620	else
621	{
622	/*
623	* 2/4MB page.
624	*/
625	RTGCPHYS GCPhys = (RTGCPHYS)GST_GET_PDE_GCPHYS(Pde);
626	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
627	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
628	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
629	{
630	RTGCPHYS GCPhysNew = PGM_A20_APPLY(pVCpu, GCPhys + (i4KB << PAGE_SHIFT) + offPage);
631	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
632	{
633	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
634	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
635	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
636	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
637	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
638	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
639	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
640	#endif
641	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
642	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
643	}
644	}
645	} /* pde type */
646	}
647	else
648	{
649	/* not-present / invalid. */
650	Log(("VirtHandler: Not present / invalid Pde=%RX64\n", (uint64_t)Pde.u));
651	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
652	cPages && iPage < pCur->cPages;
653	iPage++, GCPtr += PAGE_SIZE)
654	{
655	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
656	{
657	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
658	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
659	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
660	}
661	}
662	offPage = 0;
663	}
664	} /* for pages in virtual mapping. */
665
666	return 0;
667	}
668	#endif /* 32BIT, PAE and AMD64 + VBOX_WITH_RAW_MODE */
669
670
671	/**
672	* Updates the virtual page access handlers.
673	*
674	* @returns true if bits were flushed.
675	* @returns false if bits weren't flushed.
676	* @param pVM The cross context VM structure.
677	* @param cr4 The cr4 register value.
678	*/
679	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
680	{
681	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
682	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
683	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
684	&& defined(VBOX_WITH_RAW_MODE)
685
686	/** @todo
687	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
688	*/
689
690	/*
691	* Resolve any virtual address based access handlers to GC physical addresses.
692	* This should be fairly quick.
693	*/
694	RTUINT fTodo = 0;
695
696	pgmLock(pVM);
697	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
698
699	for (VMCPUID i = 0; i < pVM->cCpus; i++)
700	{
701	PGMHVUSTATE State;
702	PVMCPU pVCpu = &pVM->aCpus[i];
703
704	State.pVM = pVM;
705	State.pVCpu = pVCpu;
706	State.fTodo = pVCpu->pgm.s.fSyncFlags;
707	State.cr4 = cr4;
708	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
709
710	fTodo \|= State.fTodo;
711	}
712	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
713
714
715	/*
716	* Set / reset bits?
717	*/
718	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
719	{
720	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
721	Log(("HandlerVirtualUpdate: resets bits\n"));
722	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
723
724	for (VMCPUID i = 0; i < pVM->cCpus; i++)
725	{
726	PVMCPU pVCpu = &pVM->aCpus[i];
727	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
728	}
729
730	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
731	}
732	pgmUnlock(pVM);
733
734	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
735
736	#else /* real / protected */
737	NOREF(pVM); NOREF(cr4);
738	return false;
739	#endif
740	}
741
742
743	#ifdef IN_RING3
744	/**
745	* Relocate any GC pointers related to guest mode paging.
746	*
747	* @returns VBox status code.
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param offDelta The relocation offset.
750	*/
751	PGM_GST_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
752	{
753	pVCpu->pgm.s.pGst32BitPdRC += offDelta;
754	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsRC); i++)
755	pVCpu->pgm.s.apGstPaePDsRC[i] += offDelta;
756	pVCpu->pgm.s.pGstPaePdptRC += offDelta;
757
758	return VINF_SUCCESS;
759	}
760	#endif

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 77807

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