PGMAllGst.h@ 51906

Last change on this file since 51906 was 44528, checked in by vboxsync, 12 years ago
header (C) fixes
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1	/* $Id: PGMAllGst.h 44528 2013-02-04 14:27:54Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Internal Functions *
21	*******************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	static int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
31	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
32	RT_C_DECLS_END
33
34
35	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
36	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
37	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
38
39
40	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
41	{
42	NOREF(iLevel); NOREF(pVCpu);
43	pWalk->Core.fNotPresent = true;
44	pWalk->Core.uLevel = (uint8_t)iLevel;
45	return VERR_PAGE_TABLE_NOT_PRESENT;
46	}
47
48	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPU pVCpu, PGSTPTWALK pWalk, int rc, int iLevel)
49	{
50	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
51	pWalk->Core.fBadPhysAddr = true;
52	pWalk->Core.uLevel = (uint8_t)iLevel;
53	return VERR_PAGE_TABLE_NOT_PRESENT;
54	}
55
56	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
57	{
58	NOREF(pVCpu);
59	pWalk->Core.fRsvdError = true;
60	pWalk->Core.uLevel = (uint8_t)iLevel;
61	return VERR_PAGE_TABLE_NOT_PRESENT;
62	}
63
64
65	/**
66	* Performs a guest page table walk.
67	*
68	* @returns VBox status code.
69	* @retval VINF_SUCCESS on success.
70	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
71	*
72	* @param pVCpu The current CPU.
73	* @param GCPtr The guest virtual address to walk by.
74	* @param pWalk Where to return the walk result. This is always set.
75	*/
76	static int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
77	{
78	int rc;
79
80	/*
81	* Init the walking structure.
82	*/
83	RT_ZERO(*pWalk);
84	pWalk->Core.GCPtr = GCPtr;
85
86	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
87	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
88	/*
89	* Boundary check for PAE and 32-bit (prevents trouble further down).
90	*/
91	if (RT_UNLIKELY(GCPtr >= _4G))
92	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
93	# endif
94
95	{
96	# if PGM_GST_TYPE == PGM_TYPE_AMD64
97	/*
98	* The PMLE4.
99	*/
100	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
101	if (RT_FAILURE(rc))
102	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
103
104	PX86PML4 register pPml4 = pWalk->pPml4;
105	X86PML4E register Pml4e;
106	PX86PML4E register pPml4e;
107
108	pWalk->pPml4e = pPml4e = &pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
109	pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
110	if (!Pml4e.n.u1Present)
111	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
112	if (RT_UNLIKELY(!GST_IS_PML4E_VALID(pVCpu, Pml4e)))
113	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
114
115	/*
116	* The PDPE.
117	*/
118	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pWalk->pPdpt);
119	if (RT_FAILURE(rc))
120	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
121
122	# elif PGM_GST_TYPE == PGM_TYPE_PAE
123	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
124	if (RT_FAILURE(rc))
125	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
126	# endif
127	}
128	{
129	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
130	PX86PDPT register pPdpt = pWalk->pPdpt;
131	PX86PDPE register pPdpe;
132	X86PDPE register Pdpe;
133
134	pWalk->pPdpe = pPdpe = &pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
135	pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
136	if (!Pdpe.n.u1Present)
137	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
138	if (RT_UNLIKELY(!GST_IS_PDPE_VALID(pVCpu, Pdpe)))
139	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
140
141	/*
142	* The PDE.
143	*/
144	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pWalk->pPd);
145	if (RT_FAILURE(rc))
146	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
147	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
148	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
149	if (RT_FAILURE(rc))
150	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
151	# endif
152	}
153	{
154	PGSTPD register pPd = pWalk->pPd;
155	PGSTPDE register pPde;
156	GSTPDE Pde;
157
158	pWalk->pPde = pPde = &pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
159	pWalk->Pde.u = Pde.u = pPde->u;
160	if (!Pde.n.u1Present)
161	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
162	if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
163	{
164	if (RT_UNLIKELY(!GST_IS_BIG_PDE_VALID(pVCpu, Pde)))
165	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
166
167	pWalk->Core.GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
168	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
169	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->Core.GCPhys);
170	uint8_t fEffectiveXX = (uint8_t)pWalk->Pde.u
171	# if PGM_GST_TYPE == PGM_TYPE_AMD64
172	& (uint8_t)pWalk->Pde.u
173	& (uint8_t)pWalk->Pml4e.u
174	# endif
175	;
176	pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
177	pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
178	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
179	pWalk->Core.fEffectiveNX = ( pWalk->Pde.n.u1NoExecute
180	# if PGM_GST_TYPE == PGM_TYPE_AMD64
181	\|\| pWalk->Pde.n.u1NoExecute
182	\|\| pWalk->Pml4e.n.u1NoExecute
183	# endif
184	) && GST_IS_NX_ACTIVE(pVCpu);
185	# else
186	pWalk->Core.fEffectiveNX = false;
187	# endif
188	pWalk->Core.fBigPage = true;
189	pWalk->Core.fSucceeded = true;
190	return VINF_SUCCESS;
191	}
192
193	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
194	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
195
196	/*
197	* The PTE.
198	*/
199	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pWalk->pPt);
200	if (RT_FAILURE(rc))
201	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
202	}
203	{
204	PGSTPT register pPt = pWalk->pPt;
205	PGSTPTE register pPte;
206	GSTPTE register Pte;
207
208	pWalk->pPte = pPte = &pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
209	pWalk->Pte.u = Pte.u = pPte->u;
210	if (!Pte.n.u1Present)
211	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
212	if (RT_UNLIKELY(!GST_IS_PTE_VALID(pVCpu, Pte)))
213	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
214
215	/*
216	* We're done.
217	*/
218	pWalk->Core.GCPhys = GST_GET_PDE_GCPHYS(Pte)
219	\| (GCPtr & PAGE_OFFSET_MASK);
220	uint8_t fEffectiveXX = (uint8_t)pWalk->Pte.u
221	& (uint8_t)pWalk->Pde.u
222	# if PGM_GST_TYPE == PGM_TYPE_AMD64
223	& (uint8_t)pWalk->Pde.u
224	& (uint8_t)pWalk->Pml4e.u
225	# endif
226	;
227	pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
228	pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
229	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
230	pWalk->Core.fEffectiveNX = ( pWalk->Pte.n.u1NoExecute
231	\|\| pWalk->Pde.n.u1NoExecute
232	# if PGM_GST_TYPE == PGM_TYPE_AMD64
233	\|\| pWalk->Pde.n.u1NoExecute
234	\|\| pWalk->Pml4e.n.u1NoExecute
235	# endif
236	) && GST_IS_NX_ACTIVE(pVCpu);
237	# else
238	pWalk->Core.fEffectiveNX = false;
239	# endif
240	pWalk->Core.fSucceeded = true;
241	return VINF_SUCCESS;
242	}
243	}
244
245	#endif /* 32BIT, PAE, AMD64 */
246
247	/**
248	* Gets effective Guest OS page information.
249	*
250	* When GCPtr is in a big page, the function will return as if it was a normal
251	* 4KB page. If the need for distinguishing between big and normal page becomes
252	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
253	* purpose.
254	*
255	* @returns VBox status.
256	* @param pVCpu Pointer to the VMCPU.
257	* @param GCPtr Guest Context virtual address of the page.
258	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
259	* @param pGCPhys Where to store the GC physical address of the page.
260	* This is page aligned!
261	*/
262	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
263	{
264	#if PGM_GST_TYPE == PGM_TYPE_REAL \
265	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
266	/*
267	* Fake it.
268	*/
269	if (pfFlags)
270	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
271	if (pGCPhys)
272	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
273	NOREF(pVCpu);
274	return VINF_SUCCESS;
275
276	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
277	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
278	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
279
280	GSTPTWALK Walk;
281	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
282	if (RT_FAILURE(rc))
283	return rc;
284
285	if (pGCPhys)
286	*pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
287
288	if (pfFlags)
289	{
290	if (!Walk.Core.fBigPage)
291	pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK \| X86_PTE_RW \| X86_PTE_US)) / NX not needed */
292	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
293	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
294	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
295	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
296	# endif
297	;
298	else
299	{
300	pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PS)) / NX not needed */
301	\| ((Walk.Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT)
302	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
303	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
304	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
305	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
306	# endif
307	;
308	}
309	}
310
311	return VINF_SUCCESS;
312
313	#else
314	# error "shouldn't be here!"
315	/* something else... */
316	return VERR_NOT_SUPPORTED;
317	#endif
318	}
319
320
321	/**
322	* Modify page flags for a range of pages in the guest's tables
323	*
324	* The existing flags are ANDed with the fMask and ORed with the fFlags.
325	*
326	* @returns VBox status code.
327	* @param pVCpu Pointer to the VMCPU.
328	* @param GCPtr Virtual address of the first page in the range. Page aligned!
329	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
330	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
331	* @param fMask The AND mask - page flags X86_PTE_*.
332	*/
333	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
334	{
335	Assert((cb & PAGE_OFFSET_MASK) == 0);
336
337	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
338	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
339	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
340	for (;;)
341	{
342	GSTPTWALK Walk;
343	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
344	if (RT_FAILURE(rc))
345	return rc;
346
347	if (!Walk.Core.fBigPage)
348	{
349	/*
350	* 4KB Page table, process
351	*
352	* Walk pages till we're done.
353	*/
354	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
355	while (iPTE < RT_ELEMENTS(Walk.pPt->a))
356	{
357	GSTPTE Pte = Walk.pPt->a[iPTE];
358	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
359	\| (fFlags & ~GST_PTE_PG_MASK);
360	Walk.pPt->a[iPTE] = Pte;
361
362	/* next page */
363	cb -= PAGE_SIZE;
364	if (!cb)
365	return VINF_SUCCESS;
366	GCPtr += PAGE_SIZE;
367	iPTE++;
368	}
369	}
370	else
371	{
372	/*
373	* 2/4MB Page table
374	*/
375	GSTPDE PdeNew;
376	# if PGM_GST_TYPE == PGM_TYPE_32BIT
377	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
378	# else
379	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
380	# endif
381	\| (fFlags & ~GST_PTE_PG_MASK)
382	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
383	*Walk.pPde = PdeNew;
384
385	/* advance */
386	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
387	if (cbDone >= cb)
388	return VINF_SUCCESS;
389	cb -= cbDone;
390	GCPtr += cbDone;
391	}
392	}
393
394	#else
395	/* real / protected mode: ignore. */
396	NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
397	return VINF_SUCCESS;
398	#endif
399	}
400
401
402	/**
403	* Retrieve guest PDE information.
404	*
405	* @returns VBox status code.
406	* @param pVCpu Pointer to the VMCPU.
407	* @param GCPtr Guest context pointer.
408	* @param pPDE Pointer to guest PDE structure.
409	*/
410	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
411	{
412	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
413	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
414	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
415
416	# if PGM_GST_TYPE != PGM_TYPE_AMD64
417	/* Boundary check. */
418	if (RT_UNLIKELY(GCPtr >= _4G))
419	return VERR_PAGE_TABLE_NOT_PRESENT;
420	# endif
421
422	# if PGM_GST_TYPE == PGM_TYPE_32BIT
423	unsigned iPd = (GCPtr >> GST_PD_SHIFT) & GST_PD_MASK;
424	PX86PD pPd = pgmGstGet32bitPDPtr(pVCpu);
425
426	# elif PGM_GST_TYPE == PGM_TYPE_PAE
427	unsigned iPd = 0; /* shut up gcc */
428	PCX86PDPAE pPd = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPd, NULL);
429
430	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
431	PX86PML4E pPml4eIgn;
432	X86PDPE PdpeIgn;
433	unsigned iPd = 0; /* shut up gcc */
434	PCX86PDPAE pPd = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eIgn, &PdpeIgn, &iPd);
435	/* Note! We do not return an effective PDE here like we do for the PTE in GetPage method. */
436	# endif
437
438	if (RT_LIKELY(pPd))
439	pPDE->u = (X86PGPAEUINT)pPd->a[iPd].u;
440	else
441	pPDE->u = 0;
442	return VINF_SUCCESS;
443
444	#else
445	NOREF(pVCpu); NOREF(GCPtr); NOREF(pPDE);
446	AssertFailed();
447	return VERR_NOT_IMPLEMENTED;
448	#endif
449	}
450
451
452	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
453	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
454	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
455	/**
456	* Updates one virtual handler range.
457	*
458	* @returns 0
459	* @param pNode Pointer to a PGMVIRTHANDLER.
460	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
461	*/
462	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
463	{
464	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
465	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
466	PVM pVM = pState->pVM;
467	PVMCPU pVCpu = pState->pVCpu;
468	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
469
470	# if PGM_GST_TYPE == PGM_TYPE_32BIT
471	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
472	# endif
473
474	RTGCPTR GCPtr = pCur->Core.Key;
475	# if PGM_GST_TYPE != PGM_TYPE_AMD64
476	/* skip all stuff above 4GB if not AMD64 mode. */
477	if (RT_UNLIKELY(GCPtr >= _4G))
478	return 0;
479	# endif
480
481	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
482	unsigned iPage = 0;
483	while (iPage < pCur->cPages)
484	{
485	# if PGM_GST_TYPE == PGM_TYPE_32BIT
486	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
487	# elif PGM_GST_TYPE == PGM_TYPE_PAE
488	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
489	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
490	X86PDEPAE Pde = pgmGstGetLongModePDE(pVCpu, GCPtr);
491	# endif
492	# if PGM_GST_TYPE == PGM_TYPE_32BIT
493	bool const fBigPage = Pde.b.u1Size && (pState->cr4 & X86_CR4_PSE);
494	# else
495	bool const fBigPage = Pde.b.u1Size;
496	# endif
497	if ( Pde.n.u1Present
498	&& ( !fBigPage
499	? GST_IS_PDE_VALID(pVCpu, Pde)
500	: GST_IS_BIG_PDE_VALID(pVCpu, Pde)) )
501	{
502	if (!fBigPage)
503	{
504	/*
505	* Normal page table.
506	*/
507	PGSTPT pPT;
508	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(Pde), &pPT);
509	if (RT_SUCCESS(rc))
510	{
511	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
512	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
513	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
514	{
515	GSTPTE Pte = pPT->a[iPTE];
516	RTGCPHYS GCPhysNew;
517	if (Pte.n.u1Present)
518	GCPhysNew = PGM_A20_APPLY(pVCpu, (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage);
519	else
520	GCPhysNew = NIL_RTGCPHYS;
521	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
522	{
523	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
524	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
525	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
526	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
527	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
528	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
529	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
530	#endif
531	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
532	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
533	}
534	}
535	}
536	else
537	{
538	/* not-present. */
539	offPage = 0;
540	AssertRC(rc);
541	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
542	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
543	iPTE++, iPage++, GCPtr += PAGE_SIZE)
544	{
545	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
546	{
547	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
548	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
549	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
550	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
551	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
552	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
553	#endif
554	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
555	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
556	}
557	}
558	}
559	}
560	else
561	{
562	/*
563	* 2/4MB page.
564	*/
565	RTGCPHYS GCPhys = (RTGCPHYS)GST_GET_PDE_GCPHYS(Pde);
566	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
567	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
568	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
569	{
570	RTGCPHYS GCPhysNew = PGM_A20_APPLY(pVCpu, GCPhys + (i4KB << PAGE_SHIFT) + offPage);
571	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
572	{
573	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
574	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
575	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
576	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
577	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
578	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
579	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
580	#endif
581	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
582	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
583	}
584	}
585	} /* pde type */
586	}
587	else
588	{
589	/* not-present / invalid. */
590	Log(("VirtHandler: Not present / invalid Pde=%RX64\n", (uint64_t)Pde.u));
591	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
592	cPages && iPage < pCur->cPages;
593	iPage++, GCPtr += PAGE_SIZE)
594	{
595	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
596	{
597	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
598	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
599	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
600	}
601	}
602	offPage = 0;
603	}
604	} /* for pages in virtual mapping. */
605
606	return 0;
607	}
608	#endif /* 32BIT, PAE and AMD64 */
609
610
611	/**
612	* Updates the virtual page access handlers.
613	*
614	* @returns true if bits were flushed.
615	* @returns false if bits weren't flushed.
616	* @param pVM Pointer to the VM.
617	* @param pPDSrc The page directory.
618	* @param cr4 The cr4 register value.
619	*/
620	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
621	{
622	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
623	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
624	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
625
626	/** @todo
627	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
628	*/
629
630	/*
631	* Resolve any virtual address based access handlers to GC physical addresses.
632	* This should be fairly quick.
633	*/
634	RTUINT fTodo = 0;
635
636	pgmLock(pVM);
637	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
638
639	for (VMCPUID i = 0; i < pVM->cCpus; i++)
640	{
641	PGMHVUSTATE State;
642	PVMCPU pVCpu = &pVM->aCpus[i];
643
644	State.pVM = pVM;
645	State.pVCpu = pVCpu;
646	State.fTodo = pVCpu->pgm.s.fSyncFlags;
647	State.cr4 = cr4;
648	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
649
650	fTodo \|= State.fTodo;
651	}
652	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
653
654
655	/*
656	* Set / reset bits?
657	*/
658	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
659	{
660	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
661	Log(("HandlerVirtualUpdate: resets bits\n"));
662	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
663
664	for (VMCPUID i = 0; i < pVM->cCpus; i++)
665	{
666	PVMCPU pVCpu = &pVM->aCpus[i];
667	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
668	}
669
670	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
671	}
672	pgmUnlock(pVM);
673
674	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
675
676	#else /* real / protected */
677	NOREF(pVM); NOREF(cr4);
678	return false;
679	#endif
680	}
681

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 51906

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