PGMAllGst.h@ 37529

Last change on this file since 37529 was 36891, checked in by vboxsync, 14 years ago
PGM: Put a TLB in front of the RAM ranges to speed up lookup (disabled).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 24.4 KB

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1	/* $Id: PGMAllGst.h 36891 2011-04-29 13:22:57Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Internal Functions *
21	*******************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	static int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
31	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
32	RT_C_DECLS_END
33
34
35	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
36	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
37	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
38
39
40	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
41	{
42	NOREF(iLevel);
43	pWalk->Core.fNotPresent = true;
44	pWalk->Core.uLevel = (uint8_t)iLevel;
45	return VERR_PAGE_TABLE_NOT_PRESENT;
46	}
47
48	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPU pVCpu, PGSTPTWALK pWalk, int rc, int iLevel)
49	{
50	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
51	pWalk->Core.fBadPhysAddr = true;
52	pWalk->Core.uLevel = (uint8_t)iLevel;
53	return VERR_PAGE_TABLE_NOT_PRESENT;
54	}
55
56	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
57	{
58	pWalk->Core.fRsvdError = true;
59	pWalk->Core.uLevel = (uint8_t)iLevel;
60	return VERR_PAGE_TABLE_NOT_PRESENT;
61	}
62
63
64	/**
65	* Performs a guest page table walk.
66	*
67	* @returns VBox status code.
68	* @retval VINF_SUCCESS on success.
69	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
70	*
71	* @param pVCpu The current CPU.
72	* @param GCPtr The guest virtual address to walk by.
73	* @param pWalk Where to return the walk result. This is always set.
74	*/
75	static int PGM_GST_NAME(Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
76	{
77	int rc;
78
79	/*
80	* Init the walking structure.
81	*/
82	RT_ZERO(*pWalk);
83	pWalk->Core.GCPtr = GCPtr;
84
85	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
86	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
87	/*
88	* Boundary check for PAE and 32-bit (prevents trouble further down).
89	*/
90	if (RT_UNLIKELY(GCPtr >= _4G))
91	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
92	# endif
93
94	{
95	# if PGM_GST_TYPE == PGM_TYPE_AMD64
96	/*
97	* The PMLE4.
98	*/
99	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
100	if (RT_FAILURE(rc))
101	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
102
103	PX86PML4 register pPml4 = pWalk->pPml4;
104	X86PML4E register Pml4e;
105	PX86PML4E register pPml4e;
106
107	pWalk->pPml4e = pPml4e = &pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
108	pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
109	if (!Pml4e.n.u1Present)
110	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
111	if (RT_UNLIKELY(!GST_IS_PML4E_VALID(pVCpu, Pml4e)))
112	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
113
114	/*
115	* The PDPE.
116	*/
117	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK, &pWalk->pPdpt);
118	if (RT_FAILURE(rc))
119	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_PAE
122	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
123	if (RT_FAILURE(rc))
124	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
125	# endif
126	}
127	{
128	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
129	PX86PDPT register pPdpt = pWalk->pPdpt;
130	PX86PDPE register pPdpe;
131	X86PDPE register Pdpe;
132
133	pWalk->pPdpe = pPdpe = &pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
134	pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
135	if (!Pdpe.n.u1Present)
136	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
137	if (RT_UNLIKELY(!GST_IS_PDPE_VALID(pVCpu, Pdpe)))
138	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
139
140	/*
141	* The PDE.
142	*/
143	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpe.u & X86_PDPE_PG_MASK, &pWalk->pPd);
144	if (RT_FAILURE(rc))
145	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
146	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
147	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
148	if (RT_FAILURE(rc))
149	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
150	# endif
151	}
152	{
153	PGSTPD register pPd = pWalk->pPd;
154	PGSTPDE register pPde;
155	GSTPDE Pde;
156
157	pWalk->pPde = pPde = &pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
158	pWalk->Pde.u = Pde.u = pPde->u;
159	if (!Pde.n.u1Present)
160	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
161	if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
162	{
163	if (RT_UNLIKELY(!GST_IS_BIG_PDE_VALID(pVCpu, Pde)))
164	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
165
166	pWalk->Core.GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
167	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
168	uint8_t fEffectiveXX = (uint8_t)pWalk->Pde.u
169	# if PGM_GST_TYPE == PGM_TYPE_AMD64
170	& (uint8_t)pWalk->Pde.u
171	& (uint8_t)pWalk->Pml4e.u
172	# endif
173	;
174	pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
175	pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
176	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
177	pWalk->Core.fEffectiveNX = ( pWalk->Pde.n.u1NoExecute
178	# if PGM_GST_TYPE == PGM_TYPE_AMD64
179	\|\| pWalk->Pde.n.u1NoExecute
180	\|\| pWalk->Pml4e.n.u1NoExecute
181	# endif
182	) && GST_IS_NX_ACTIVE(pVCpu);
183	# else
184	pWalk->Core.fEffectiveNX = false;
185	# endif
186	pWalk->Core.fBigPage = true;
187	pWalk->Core.fSucceeded = true;
188	return VINF_SUCCESS;
189	}
190
191	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
192	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
193
194	/*
195	* The PTE.
196	*/
197	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pWalk->pPt);
198	if (RT_FAILURE(rc))
199	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
200	}
201	{
202	PGSTPT register pPt = pWalk->pPt;
203	PGSTPTE register pPte;
204	GSTPTE register Pte;
205
206	pWalk->pPte = pPte = &pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
207	pWalk->Pte.u = Pte.u = pPte->u;
208	if (!Pte.n.u1Present)
209	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
210	if (RT_UNLIKELY(!GST_IS_PTE_VALID(pVCpu, Pte)))
211	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
212
213	/*
214	* We're done.
215	*/
216	pWalk->Core.GCPhys = GST_GET_PDE_GCPHYS(Pte)
217	\| (GCPtr & PAGE_OFFSET_MASK);
218	uint8_t fEffectiveXX = (uint8_t)pWalk->Pte.u
219	& (uint8_t)pWalk->Pde.u
220	# if PGM_GST_TYPE == PGM_TYPE_AMD64
221	& (uint8_t)pWalk->Pde.u
222	& (uint8_t)pWalk->Pml4e.u
223	# endif
224	;
225	pWalk->Core.fEffectiveRW = !!(fEffectiveXX & X86_PTE_RW);
226	pWalk->Core.fEffectiveUS = !!(fEffectiveXX & X86_PTE_US);
227	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
228	pWalk->Core.fEffectiveNX = ( pWalk->Pte.n.u1NoExecute
229	\|\| pWalk->Pde.n.u1NoExecute
230	# if PGM_GST_TYPE == PGM_TYPE_AMD64
231	\|\| pWalk->Pde.n.u1NoExecute
232	\|\| pWalk->Pml4e.n.u1NoExecute
233	# endif
234	) && GST_IS_NX_ACTIVE(pVCpu);
235	# else
236	pWalk->Core.fEffectiveNX = false;
237	# endif
238	pWalk->Core.fSucceeded = true;
239	return VINF_SUCCESS;
240	}
241	}
242
243	#endif /* 32BIT, PAE, AMD64 */
244
245	/**
246	* Gets effective Guest OS page information.
247	*
248	* When GCPtr is in a big page, the function will return as if it was a normal
249	* 4KB page. If the need for distinguishing between big and normal page becomes
250	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
251	* purpose.
252	*
253	* @returns VBox status.
254	* @param pVCpu The VMCPU handle.
255	* @param GCPtr Guest Context virtual address of the page.
256	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
257	* @param pGCPhys Where to store the GC physical address of the page.
258	* This is page aligned!
259	*/
260	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
261	{
262	#if PGM_GST_TYPE == PGM_TYPE_REAL \
263	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
264	/*
265	* Fake it.
266	*/
267	if (pfFlags)
268	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
269	if (pGCPhys)
270	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
271	return VINF_SUCCESS;
272
273	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
274	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
275	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
276
277	GSTPTWALK Walk;
278	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
279	if (RT_FAILURE(rc))
280	return rc;
281
282	if (pGCPhys)
283	*pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
284
285	if (pfFlags)
286	{
287	if (!Walk.Core.fBigPage)
288	pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK \| X86_PTE_RW \| X86_PTE_US)) / NX not needed */
289	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
290	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
291	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
292	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
293	# endif
294	;
295	else
296	{
297	pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PS)) / NX not needed */
298	\| ((Walk.Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT)
299	\| (Walk.Core.fEffectiveRW ? X86_PTE_RW : 0)
300	\| (Walk.Core.fEffectiveUS ? X86_PTE_US : 0)
301	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
302	\| (Walk.Core.fEffectiveNX ? X86_PTE_PAE_NX : 0)
303	# endif
304	;
305	}
306	}
307
308	return VINF_SUCCESS;
309
310	#else
311	# error "shouldn't be here!"
312	/* something else... */
313	return VERR_NOT_SUPPORTED;
314	#endif
315	}
316
317
318	/**
319	* Modify page flags for a range of pages in the guest's tables
320	*
321	* The existing flags are ANDed with the fMask and ORed with the fFlags.
322	*
323	* @returns VBox status code.
324	* @param pVCpu The VMCPU handle.
325	* @param GCPtr Virtual address of the first page in the range. Page aligned!
326	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
327	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
328	* @param fMask The AND mask - page flags X86_PTE_*.
329	*/
330	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
331	{
332	Assert((cb & PAGE_OFFSET_MASK) == 0);
333
334	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
335	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
336	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
337	for (;;)
338	{
339	GSTPTWALK Walk;
340	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
341	if (RT_FAILURE(rc))
342	return rc;
343
344	if (!Walk.Core.fBigPage)
345	{
346	/*
347	* 4KB Page table, process
348	*
349	* Walk pages till we're done.
350	*/
351	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
352	while (iPTE < RT_ELEMENTS(Walk.pPt->a))
353	{
354	GSTPTE Pte = Walk.pPt->a[iPTE];
355	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
356	\| (fFlags & ~GST_PTE_PG_MASK);
357	Walk.pPt->a[iPTE] = Pte;
358
359	/* next page */
360	cb -= PAGE_SIZE;
361	if (!cb)
362	return VINF_SUCCESS;
363	GCPtr += PAGE_SIZE;
364	iPTE++;
365	}
366	}
367	else
368	{
369	/*
370	* 2/4MB Page table
371	*/
372	GSTPDE PdeNew;
373	# if PGM_GST_TYPE == PGM_TYPE_32BIT
374	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
375	# else
376	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
377	# endif
378	\| (fFlags & ~GST_PTE_PG_MASK)
379	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
380	*Walk.pPde = PdeNew;
381
382	/* advance */
383	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
384	if (cbDone >= cb)
385	return VINF_SUCCESS;
386	cb -= cbDone;
387	GCPtr += cbDone;
388	}
389	}
390
391	#else
392	/* real / protected mode: ignore. */
393	return VINF_SUCCESS;
394	#endif
395	}
396
397
398	/**
399	* Retrieve guest PDE information.
400	*
401	* @returns VBox status code.
402	* @param pVCpu The VMCPU handle.
403	* @param GCPtr Guest context pointer.
404	* @param pPDE Pointer to guest PDE structure.
405	*/
406	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
407	{
408	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
409	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
410	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
411
412	# if PGM_GST_TYPE != PGM_TYPE_AMD64
413	/* Boundary check. */
414	if (RT_UNLIKELY(GCPtr >= _4G))
415	return VERR_PAGE_TABLE_NOT_PRESENT;
416	# endif
417
418	# if PGM_GST_TYPE == PGM_TYPE_32BIT
419	unsigned iPd = (GCPtr >> GST_PD_SHIFT) & GST_PD_MASK;
420	PX86PD pPd = pgmGstGet32bitPDPtr(pVCpu);
421
422	# elif PGM_GST_TYPE == PGM_TYPE_PAE
423	unsigned iPd = 0; /* shut up gcc */
424	PCX86PDPAE pPd = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPd, NULL);
425
426	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
427	PX86PML4E pPml4eIgn;
428	X86PDPE PdpeIgn;
429	unsigned iPd = 0; /* shut up gcc */
430	PCX86PDPAE pPd = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eIgn, &PdpeIgn, &iPd);
431	/* Note! We do not return an effective PDE here like we do for the PTE in GetPage method. */
432	# endif
433
434	if (RT_LIKELY(pPd))
435	pPDE->u = (X86PGPAEUINT)pPd->a[iPd].u;
436	else
437	pPDE->u = 0;
438	return VINF_SUCCESS;
439
440	#else
441	AssertFailed();
442	return VERR_NOT_IMPLEMENTED;
443	#endif
444	}
445
446
447	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
448	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
449	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
450	/**
451	* Updates one virtual handler range.
452	*
453	* @returns 0
454	* @param pNode Pointer to a PGMVIRTHANDLER.
455	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
456	*/
457	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
458	{
459	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
460	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
461	PVM pVM = pState->pVM;
462	PVMCPU pVCpu = pState->pVCpu;
463	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
464
465	# if PGM_GST_TYPE == PGM_TYPE_32BIT
466	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
467	# endif
468
469	RTGCPTR GCPtr = pCur->Core.Key;
470	# if PGM_GST_TYPE != PGM_TYPE_AMD64
471	/* skip all stuff above 4GB if not AMD64 mode. */
472	if (RT_UNLIKELY(GCPtr >= _4G))
473	return 0;
474	# endif
475
476	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
477	unsigned iPage = 0;
478	while (iPage < pCur->cPages)
479	{
480	# if PGM_GST_TYPE == PGM_TYPE_32BIT
481	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
482	# elif PGM_GST_TYPE == PGM_TYPE_PAE
483	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
484	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
485	X86PDEPAE Pde = pgmGstGetLongModePDE(pVCpu, GCPtr);
486	# endif
487	# if PGM_GST_TYPE == PGM_TYPE_32BIT
488	bool const fBigPage = Pde.b.u1Size && (pState->cr4 & X86_CR4_PSE);
489	# else
490	bool const fBigPage = Pde.b.u1Size;
491	# endif
492	if ( Pde.n.u1Present
493	&& ( !fBigPage
494	? GST_IS_PDE_VALID(pVCpu, Pde)
495	: GST_IS_BIG_PDE_VALID(pVCpu, Pde)) )
496	{
497	if (!fBigPage)
498	{
499	/*
500	* Normal page table.
501	*/
502	PGSTPT pPT;
503	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(Pde), &pPT);
504	if (RT_SUCCESS(rc))
505	{
506	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
507	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
508	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
509	{
510	GSTPTE Pte = pPT->a[iPTE];
511	RTGCPHYS GCPhysNew;
512	if (Pte.n.u1Present)
513	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
514	else
515	GCPhysNew = NIL_RTGCPHYS;
516	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
517	{
518	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
519	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
520	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
521	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
522	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
523	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
524	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
525	#endif
526	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
527	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
528	}
529	}
530	}
531	else
532	{
533	/* not-present. */
534	offPage = 0;
535	AssertRC(rc);
536	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
537	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
538	iPTE++, iPage++, GCPtr += PAGE_SIZE)
539	{
540	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
541	{
542	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
543	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
544	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
545	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
546	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
547	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
548	#endif
549	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
550	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
551	}
552	}
553	}
554	}
555	else
556	{
557	/*
558	* 2/4MB page.
559	*/
560	RTGCPHYS GCPhys = (RTGCPHYS)GST_GET_PDE_GCPHYS(Pde);
561	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
562	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
563	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
564	{
565	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
566	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
567	{
568	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
569	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
570	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
571	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
572	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
573	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
574	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
575	#endif
576	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
577	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
578	}
579	}
580	} /* pde type */
581	}
582	else
583	{
584	/* not-present / invalid. */
585	Log(("VirtHandler: Not present / invalid Pde=%RX64\n", (uint64_t)Pde.u));
586	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
587	cPages && iPage < pCur->cPages;
588	iPage++, GCPtr += PAGE_SIZE)
589	{
590	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
591	{
592	pgmHandlerVirtualClearPage(pVM, pCur, iPage);
593	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
594	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
595	}
596	}
597	offPage = 0;
598	}
599	} /* for pages in virtual mapping. */
600
601	return 0;
602	}
603	#endif /* 32BIT, PAE and AMD64 */
604
605
606	/**
607	* Updates the virtual page access handlers.
608	*
609	* @returns true if bits were flushed.
610	* @returns false if bits weren't flushed.
611	* @param pVM VM handle.
612	* @param pPDSrc The page directory.
613	* @param cr4 The cr4 register value.
614	*/
615	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
616	{
617	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
618	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
619	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
620
621	/** @todo
622	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
623	*/
624
625	/*
626	* Resolve any virtual address based access handlers to GC physical addresses.
627	* This should be fairly quick.
628	*/
629	RTUINT fTodo = 0;
630
631	pgmLock(pVM);
632	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
633
634	for (VMCPUID i = 0; i < pVM->cCpus; i++)
635	{
636	PGMHVUSTATE State;
637	PVMCPU pVCpu = &pVM->aCpus[i];
638
639	State.pVM = pVM;
640	State.pVCpu = pVCpu;
641	State.fTodo = pVCpu->pgm.s.fSyncFlags;
642	State.cr4 = cr4;
643	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
644
645	fTodo \|= State.fTodo;
646	}
647	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
648
649
650	/*
651	* Set / reset bits?
652	*/
653	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
654	{
655	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
656	Log(("HandlerVirtualUpdate: resets bits\n"));
657	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
658
659	for (VMCPUID i = 0; i < pVM->cCpus; i++)
660	{
661	PVMCPU pVCpu = &pVM->aCpus[i];
662	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
663	}
664
665	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
666	}
667	pgmUnlock(pVM);
668
669	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
670
671	#else /* real / protected */
672	return false;
673	#endif
674	}
675

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 37529

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