PGMAllGst.h@ 25866

Last change on this file since 25866 was 25866, checked in by vboxsync, 15 years ago
VMM: More micro optimizations.
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1	/* $Id: PGMAllGst.h 25866 2010-01-15 14:26:49Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Internal Functions *
25	*******************************************************************************/
26	RT_C_DECLS_BEGIN
27	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
28	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
29	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
30	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
31	RT_C_DECLS_END
32
33
34
35	/**
36	* Gets effective Guest OS page information.
37	*
38	* When GCPtr is in a big page, the function will return as if it was a normal
39	* 4KB page. If the need for distinguishing between big and normal page becomes
40	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
41	* purpose.
42	*
43	* @returns VBox status.
44	* @param pVCpu The VMCPU handle.
45	* @param GCPtr Guest Context virtual address of the page.
46	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
47	* @param pGCPhys Where to store the GC physical address of the page.
48	* This is page aligned!
49	*/
50	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
51	{
52	#if PGM_GST_TYPE == PGM_TYPE_REAL \
53	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
54	/*
55	* Fake it.
56	*/
57	if (pfFlags)
58	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
59	if (pGCPhys)
60	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
61	return VINF_SUCCESS;
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
64
65	#if PGM_GST_MODE != PGM_MODE_AMD64
66	/* Boundary check. */
67	if (GCPtr >= _4G)
68	return VERR_INVALID_ADDRESS;
69	# endif
70
71	PVM pVM = pVCpu->CTX_SUFF(pVM);
72	/*
73	* Get the PDE.
74	*/
75	# if PGM_GST_TYPE == PGM_TYPE_32BIT
76	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
77
78	#elif PGM_GST_TYPE == PGM_TYPE_PAE
79	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
80	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
81	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
82
83	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
84	PX86PML4E pPml4e;
85	X86PDPE Pdpe;
86	X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVCpu->pgm.s, GCPtr, &pPml4e, &Pdpe);
87
88	Assert(pPml4e);
89	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
90	return VERR_PAGE_TABLE_NOT_PRESENT;
91
92	/* Merge accessed, write, user and no-execute bits into the PDE. */
93	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
94	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
95	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
96	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
97	# endif
98
99	/*
100	* Lookup the page.
101	*/
102	if (!Pde.n.u1Present)
103	return VERR_PAGE_TABLE_NOT_PRESENT;
104
105	if ( !Pde.b.u1Size
106	# if PGM_GST_TYPE != PGM_TYPE_AMD64
107	\|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu)
108	# endif
109	)
110	{
111	PGSTPT pPT;
112	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
113	if (RT_FAILURE(rc))
114	return rc;
115
116	/*
117	* Get PT entry and check presence.
118	*/
119	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
120	if (!Pte.n.u1Present)
121	return VERR_PAGE_NOT_PRESENT;
122
123	/*
124	* Store the result.
125	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
126	* where the PDPE is simplified.
127	*/
128	if (pfFlags)
129	{
130	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
131	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
132	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
133	/* The NX bit is determined by a bitwise OR between the PT and PD */
134	if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */
135	*pfFlags \|= X86_PTE_PAE_NX;
136	# endif
137	}
138	if (pGCPhys)
139	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
140	}
141	else
142	{
143	/*
144	* Map big to 4k PTE and store the result
145	*/
146	if (pfFlags)
147	{
148	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
149	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
150	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
151	if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
152	*pfFlags \|= X86_PTE_PAE_NX;
153	# endif
154	}
155	if (pGCPhys)
156	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
157	}
158	return VINF_SUCCESS;
159	#else
160	# error "shouldn't be here!"
161	/* something else... */
162	return VERR_NOT_SUPPORTED;
163	#endif
164	}
165
166
167	/**
168	* Modify page flags for a range of pages in the guest's tables
169	*
170	* The existing flags are ANDed with the fMask and ORed with the fFlags.
171	*
172	* @returns VBox status code.
173	* @param pVCpu The VMCPU handle.
174	* @param GCPtr Virtual address of the first page in the range. Page aligned!
175	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
176	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
177	* @param fMask The AND mask - page flags X86_PTE_*.
178	*/
179	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
180	{
181	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
182	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
183	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
184
185	Assert((cb & PAGE_OFFSET_MASK) == 0);
186
187	#if PGM_GST_MODE != PGM_MODE_AMD64
188	/* Boundary check. */
189	if (GCPtr >= _4G)
190	return VERR_INVALID_ADDRESS;
191	# endif
192
193	PVM pVM = pVCpu->CTX_SUFF(pVM);
194	for (;;)
195	{
196	/*
197	* Get the PD entry.
198	*/
199	# if PGM_GST_TYPE == PGM_TYPE_32BIT
200	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVCpu->pgm.s, GCPtr);
201
202	# elif PGM_GST_TYPE == PGM_TYPE_PAE
203	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
204	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
205	*/
206	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVCpu->pgm.s, GCPtr);
207	Assert(pPde);
208	if (!pPde)
209	return VERR_PAGE_TABLE_NOT_PRESENT;
210	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
211	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
212	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVCpu->pgm.s, GCPtr);
213	Assert(pPde);
214	if (!pPde)
215	return VERR_PAGE_TABLE_NOT_PRESENT;
216	# endif
217	GSTPDE Pde = *pPde;
218	Assert(Pde.n.u1Present);
219	if (!Pde.n.u1Present)
220	return VERR_PAGE_TABLE_NOT_PRESENT;
221
222	if ( !Pde.b.u1Size
223	# if PGM_GST_TYPE != PGM_TYPE_AMD64
224	\|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu)
225	# endif
226	)
227	{
228	/*
229	* 4KB Page table
230	*
231	* Walk page tables and pages till we're done.
232	*/
233	PGSTPT pPT;
234	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
235	if (RT_FAILURE(rc))
236	return rc;
237
238	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
239	while (iPTE < RT_ELEMENTS(pPT->a))
240	{
241	GSTPTE Pte = pPT->a[iPTE];
242	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
243	\| (fFlags & ~GST_PTE_PG_MASK);
244	pPT->a[iPTE] = Pte;
245
246	/* next page */
247	cb -= PAGE_SIZE;
248	if (!cb)
249	return VINF_SUCCESS;
250	GCPtr += PAGE_SIZE;
251	iPTE++;
252	}
253	}
254	else
255	{
256	/*
257	* 4MB Page table
258	*/
259	# if PGM_GST_TYPE == PGM_TYPE_32BIT
260	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
261	# else
262	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
263	# endif
264	\| (fFlags & ~GST_PTE_PG_MASK)
265	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
266	*pPde = Pde;
267
268	/* advance */
269	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
270	if (cbDone >= cb)
271	return VINF_SUCCESS;
272	cb -= cbDone;
273	GCPtr += cbDone;
274	}
275	}
276
277	#else
278	/* real / protected mode: ignore. */
279	return VINF_SUCCESS;
280	#endif
281	}
282
283
284	/**
285	* Retrieve guest PDE information
286	*
287	* @returns VBox status code.
288	* @param pVCpu The VMCPU handle.
289	* @param GCPtr Guest context pointer
290	* @param pPDE Pointer to guest PDE structure
291	*/
292	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
293	{
294	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
295	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
296	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
297
298	#if PGM_GST_MODE != PGM_MODE_AMD64
299	/* Boundary check. */
300	if (GCPtr >= _4G)
301	return VERR_INVALID_ADDRESS;
302	# endif
303
304	# if PGM_GST_TYPE == PGM_TYPE_32BIT
305	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
306	# elif PGM_GST_TYPE == PGM_TYPE_PAE
307	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
308	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
309	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
310	# endif
311
312	pPDE->u = (X86PGPAEUINT)Pde.u;
313	return VINF_SUCCESS;
314	#else
315	AssertFailed();
316	return VERR_NOT_IMPLEMENTED;
317	#endif
318	}
319
320
321	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
322	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
323	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
324	/**
325	* Updates one virtual handler range.
326	*
327	* @returns 0
328	* @param pNode Pointer to a PGMVIRTHANDLER.
329	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
330	*/
331	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
332	{
333	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
334	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
335	PVM pVM = pState->pVM;
336	PVMCPU pVCpu = pState->pVCpu;
337	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
338
339	#if PGM_GST_TYPE == PGM_TYPE_32BIT
340	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
341	#endif
342
343	RTGCPTR GCPtr = pCur->Core.Key;
344	#if PGM_GST_MODE != PGM_MODE_AMD64
345	/* skip all stuff above 4GB if not AMD64 mode. */
346	if (GCPtr >= _4GB)
347	return 0;
348	#endif
349
350	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
351	unsigned iPage = 0;
352	while (iPage < pCur->cPages)
353	{
354	#if PGM_GST_TYPE == PGM_TYPE_32BIT
355	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
356	#elif PGM_GST_TYPE == PGM_TYPE_PAE
357	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
358	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
359	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
360	#endif
361	if (Pde.n.u1Present)
362	{
363	if ( !Pde.b.u1Size
364	# if PGM_GST_TYPE != PGM_TYPE_AMD64
365	\|\| !(pState->cr4 & X86_CR4_PSE)
366	# endif
367	)
368	{
369	/*
370	* Normal page table.
371	*/
372	PGSTPT pPT;
373	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
374	if (RT_SUCCESS(rc))
375	{
376	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
377	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
378	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
379	{
380	GSTPTE Pte = pPT->a[iPTE];
381	RTGCPHYS GCPhysNew;
382	if (Pte.n.u1Present)
383	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
384	else
385	GCPhysNew = NIL_RTGCPHYS;
386	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
387	{
388	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
389	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
390	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
391	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
392	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
393	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
394	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
395	#endif
396	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
397	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
398	}
399	}
400	}
401	else
402	{
403	/* not-present. */
404	offPage = 0;
405	AssertRC(rc);
406	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
407	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
408	iPTE++, iPage++, GCPtr += PAGE_SIZE)
409	{
410	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
411	{
412	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
413	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
414	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
415	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
416	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
417	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
418	#endif
419	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
420	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
421	}
422	}
423	}
424	}
425	else
426	{
427	/*
428	* 2/4MB page.
429	*/
430	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
431	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
432	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
433	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
434	{
435	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
436	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
437	{
438	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
439	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
440	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
441	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
442	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
443	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
444	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
445	#endif
446	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
447	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
448	}
449	}
450	} /* pde type */
451	}
452	else
453	{
454	/* not-present. */
455	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
456	cPages && iPage < pCur->cPages;
457	iPage++, GCPtr += PAGE_SIZE)
458	{
459	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
460	{
461	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
462	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
463	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
464	}
465	}
466	offPage = 0;
467	}
468	} /* for pages in virtual mapping. */
469
470	return 0;
471	}
472	#endif /* 32BIT, PAE and AMD64 */
473
474
475	/**
476	* Updates the virtual page access handlers.
477	*
478	* @returns true if bits were flushed.
479	* @returns false if bits weren't flushed.
480	* @param pVM VM handle.
481	* @param pPDSrc The page directory.
482	* @param cr4 The cr4 register value.
483	*/
484	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
485	{
486	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
487	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
488	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
489
490	/** @todo
491	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
492	*/
493
494	/*
495	* Resolve any virtual address based access handlers to GC physical addresses.
496	* This should be fairly quick.
497	*/
498	RTUINT fTodo = 0;
499
500	pgmLock(pVM);
501	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
502
503	for (VMCPUID i = 0; i < pVM->cCpus; i++)
504	{
505	PGMHVUSTATE State;
506	PVMCPU pVCpu = &pVM->aCpus[i];
507
508	State.pVM = pVM;
509	State.pVCpu = pVCpu;
510	State.fTodo = pVCpu->pgm.s.fSyncFlags;
511	State.cr4 = cr4;
512	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
513
514	fTodo \|= State.fTodo;
515	}
516	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
517
518
519	/*
520	* Set / reset bits?
521	*/
522	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
523	{
524	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
525	Log(("HandlerVirtualUpdate: resets bits\n"));
526	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
527
528	for (VMCPUID i = 0; i < pVM->cCpus; i++)
529	{
530	PVMCPU pVCpu = &pVM->aCpus[i];
531	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
532	}
533
534	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
535	}
536	pgmUnlock(pVM);
537
538	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
539
540	#else /* real / protected */
541	return false;
542	#endif
543	}
544

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 25866

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