VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 11146

Last change on this file since 11146 was 10674, checked in by vboxsync, 16 years ago

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1/* $Id: PGMAllGst.h 10674 2008-07-15 15:54:43Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Defined Constants And Macros *
25*******************************************************************************/
26#undef GSTPT
27#undef PGSTPT
28#undef GSTPTE
29#undef PGSTPTE
30#undef GSTPD
31#undef PGSTPD
32#undef GSTPDE
33#undef PGSTPDE
34#undef GST_BIG_PAGE_SIZE
35#undef GST_BIG_PAGE_OFFSET_MASK
36#undef GST_PDE_PG_MASK
37#undef GST_PDE_BIG_PG_MASK
38#undef GST_PD_SHIFT
39#undef GST_PD_MASK
40#undef GST_PTE_PG_MASK
41#undef GST_PT_SHIFT
42#undef GST_PT_MASK
43#undef GST_TOTAL_PD_ENTRIES
44#undef GST_CR3_PAGE_MASK
45#undef GST_PDPE_ENTRIES
46#undef GST_PDPT_SHIFT
47#undef GST_PDPT_MASK
48#undef GST_PDPE_PG_MASK
49
50#if PGM_GST_TYPE == PGM_TYPE_REAL \
51 || PGM_GST_TYPE == PGM_TYPE_PROT
52# define GSTPT SHWPT
53# define PGSTPT PSHWPT
54# define GSTPTE SHWPTE
55# define PGSTPTE PSHWPTE
56# define GSTPD SHWPD
57# define PGSTPD PSHWPD
58# define GSTPDE SHWPDE
59# define PGSTPDE PSHWPDE
60# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
61#elif PGM_GST_TYPE == PGM_TYPE_32BIT
62# define GSTPT X86PT
63# define PGSTPT PX86PT
64# define GSTPTE X86PTE
65# define PGSTPTE PX86PTE
66# define GSTPD X86PD
67# define PGSTPD PX86PD
68# define GSTPDE X86PDE
69# define PGSTPDE PX86PDE
70# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
71# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
72# define GST_PDE_PG_MASK X86_PDE_PG_MASK
73# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
74# define GST_PD_SHIFT X86_PD_SHIFT
75# define GST_PD_MASK X86_PD_MASK
76# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
77# define GST_PTE_PG_MASK X86_PTE_PG_MASK
78# define GST_PT_SHIFT X86_PT_SHIFT
79# define GST_PT_MASK X86_PT_MASK
80# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
81#elif PGM_GST_TYPE == PGM_TYPE_PAE \
82 || PGM_GST_TYPE == PGM_TYPE_AMD64
83# define GSTPT X86PTPAE
84# define PGSTPT PX86PTPAE
85# define GSTPTE X86PTEPAE
86# define PGSTPTE PX86PTEPAE
87# define GSTPD X86PDPAE
88# define PGSTPD PX86PDPAE
89# define GSTPDE X86PDEPAE
90# define PGSTPDE PX86PDEPAE
91# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
92# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
93# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
94# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
95# define GST_PD_SHIFT X86_PD_PAE_SHIFT
96# define GST_PD_MASK X86_PD_PAE_MASK
97# if PGM_GST_TYPE == PGM_TYPE_PAE
98# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
99# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
100# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
101# define GST_PDPT_SHIFT X86_PDPT_SHIFT
102# define GST_PDPT_MASK X86_PDPT_MASK_PAE
103# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
104# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
105# else
106# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
107# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
108# define GST_PDPT_SHIFT X86_PDPT_SHIFT
109# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
110# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
111# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
112# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
113# endif
114# define GST_PT_SHIFT X86_PT_PAE_SHIFT
115# define GST_PT_MASK X86_PT_PAE_MASK
116#endif
117
118
119/*******************************************************************************
120* Internal Functions *
121*******************************************************************************/
122__BEGIN_DECLS
123PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
124PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
125PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
126PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
127PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
128PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
129PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
130PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
131#ifndef IN_RING3
132PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
133# if PGM_GST_TYPE == PGM_TYPE_PAE \
134 || PGM_GST_TYPE == PGM_TYPE_AMD64
135PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
136# endif
137#endif
138__END_DECLS
139
140
141
142/**
143 * Gets effective Guest OS page information.
144 *
145 * When GCPtr is in a big page, the function will return as if it was a normal
146 * 4KB page. If the need for distinguishing between big and normal page becomes
147 * necessary at a later point, a PGMGstGetPage Ex() will be created for that
148 * purpose.
149 *
150 * @returns VBox status.
151 * @param pVM VM Handle.
152 * @param GCPtr Guest Context virtual address of the page. Page aligned!
153 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
154 * @param pGCPhys Where to store the GC physical address of the page.
155 * This is page aligned. The fact that the
156 */
157PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
158{
159#if PGM_GST_TYPE == PGM_TYPE_REAL \
160 || PGM_GST_TYPE == PGM_TYPE_PROT
161 /*
162 * Fake it.
163 */
164 if (pfFlags)
165 *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
166 if (pGCPhys)
167 *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
168 return VINF_SUCCESS;
169
170#elif PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
171
172 /*
173 * Get the PDE.
174 */
175# if PGM_GST_TYPE == PGM_TYPE_32BIT
176 const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
177#elif PGM_GST_TYPE == PGM_TYPE_PAE
178 X86PDEPAE Pde;
179 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
180
181 /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
182 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
183 */
184 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
185#elif PGM_GST_TYPE == PGM_TYPE_AMD64
186 PX86PML4E pPml4e;
187 X86PDPE Pdpe;
188 X86PDEPAE Pde;
189 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
190
191 Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
192 Assert(pPml4e);
193 if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
194 return VERR_PAGE_TABLE_NOT_PRESENT;
195
196 /* Merge accessed, write, user and no-execute bits into the PDE. */
197 Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
198 Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
199 Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
200 Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
201# endif
202
203 /*
204 * Lookup the page.
205 */
206 if (!Pde.n.u1Present)
207 return VERR_PAGE_TABLE_NOT_PRESENT;
208
209 if ( !Pde.b.u1Size
210# if PGM_GST_TYPE != PGM_TYPE_AMD64
211 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
212# endif
213 )
214 {
215 PGSTPT pPT;
216 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
217 if (VBOX_FAILURE(rc))
218 return rc;
219
220 /*
221 * Get PT entry and check presence.
222 */
223 const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
224 if (!Pte.n.u1Present)
225 return VERR_PAGE_NOT_PRESENT;
226
227 /*
228 * Store the result.
229 * RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
230 * where the PDPE is simplified.
231 */
232 if (pfFlags)
233 {
234 *pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
235 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
236# if PGM_WITH_NX(PGM_GST_TYPE)
237 /* The NX bit is determined by a bitwise OR between the PT and PD */
238 if (fNoExecuteBitValid)
239 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
240# endif
241 }
242 if (pGCPhys)
243 *pGCPhys = Pte.u & GST_PTE_PG_MASK;
244 }
245 else
246 {
247 /*
248 * Map big to 4k PTE and store the result
249 */
250 if (pfFlags)
251 {
252 *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
253 | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
254# if PGM_WITH_NX(PGM_GST_TYPE)
255 /* The NX bit is determined by a bitwise OR between the PT and PD */
256 if (fNoExecuteBitValid)
257 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
258# endif
259 }
260 if (pGCPhys)
261 *pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /** @todo pse36 */
262 }
263 return VINF_SUCCESS;
264#else
265# error "shouldn't be here!"
266 /* something else... */
267 return VERR_NOT_SUPPORTED;
268#endif
269}
270
271
272/**
273 * Modify page flags for a range of pages in the guest's tables
274 *
275 * The existing flags are ANDed with the fMask and ORed with the fFlags.
276 *
277 * @returns VBox status code.
278 * @param pVM VM handle.
279 * @param GCPtr Virtual address of the first page in the range. Page aligned!
280 * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
281 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
282 * @param fMask The AND mask - page flags X86_PTE_*.
283 */
284PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
285{
286#if PGM_GST_TYPE == PGM_TYPE_32BIT \
287 || PGM_GST_TYPE == PGM_TYPE_PAE \
288 || PGM_GST_TYPE == PGM_TYPE_AMD64
289
290 for (;;)
291 {
292 /*
293 * Get the PD entry.
294 */
295# if PGM_GST_TYPE == PGM_TYPE_32BIT
296 PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
297# elif PGM_GST_TYPE == PGM_TYPE_PAE
298 /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
299 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
300 */
301 PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
302 Assert(pPde);
303 if (!pPde)
304 return VERR_PAGE_TABLE_NOT_PRESENT;
305# elif PGM_GST_TYPE == PGM_TYPE_AMD64
306 /** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
307 PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
308 Assert(pPde);
309 if (!pPde)
310 return VERR_PAGE_TABLE_NOT_PRESENT;
311# endif
312 GSTPDE Pde = *pPde;
313 Assert(Pde.n.u1Present);
314 if (!Pde.n.u1Present)
315 return VERR_PAGE_TABLE_NOT_PRESENT;
316
317 if ( !Pde.b.u1Size
318# if PGM_GST_TYPE != PGM_TYPE_AMD64
319 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
320# endif
321 )
322 {
323 /*
324 * 4KB Page table
325 *
326 * Walk page tables and pages till we're done.
327 */
328 PGSTPT pPT;
329 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
330 if (VBOX_FAILURE(rc))
331 return rc;
332
333 unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
334 while (iPTE < RT_ELEMENTS(pPT->a))
335 {
336 GSTPTE Pte = pPT->a[iPTE];
337 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
338 | (fFlags & ~GST_PTE_PG_MASK);
339 pPT->a[iPTE] = Pte;
340
341 /* next page */
342 cb -= PAGE_SIZE;
343 if (!cb)
344 return VINF_SUCCESS;
345 GCPtr += PAGE_SIZE;
346 iPTE++;
347 }
348 }
349 else
350 {
351 /*
352 * 4MB Page table
353 */
354 Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
355 | (fFlags & ~GST_PTE_PG_MASK)
356 | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
357 *pPde = Pde;
358
359 /* advance */
360 const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
361 if (cbDone >= cb)
362 return VINF_SUCCESS;
363 cb -= cbDone;
364 GCPtr += cbDone;
365 }
366 }
367
368#else
369 /* real / protected mode: ignore. */
370 return VINF_SUCCESS;
371#endif
372}
373
374
375/**
376 * Retrieve guest PDE information
377 *
378 * @returns VBox status code.
379 * @param pVM The virtual machine.
380 * @param GCPtr Guest context pointer
381 * @param pPDE Pointer to guest PDE structure
382 */
383PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
384{
385#if PGM_GST_TYPE == PGM_TYPE_32BIT \
386 || PGM_GST_TYPE == PGM_TYPE_PAE \
387 || PGM_GST_TYPE == PGM_TYPE_AMD64
388
389# if PGM_GST_TYPE == PGM_TYPE_32BIT
390 X86PDE Pde;
391 Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
392# elif PGM_GST_TYPE == PGM_TYPE_PAE
393 X86PDEPAE Pde;
394 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
395# elif PGM_GST_TYPE == PGM_TYPE_AMD64
396 X86PDEPAE Pde;
397 Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
398# endif
399
400 pPDE->u = (X86PGPAEUINT)Pde.u;
401 return VINF_SUCCESS;
402#else
403 AssertFailed();
404 return VERR_NOT_IMPLEMENTED;
405#endif
406}
407
408
409
410/**
411 * Maps the CR3 into HMA in GC and locate it in HC.
412 *
413 * Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
414 * CR3 is updated we simply call MapCR3 again.
415 *
416 * @returns VBox status, no specials.
417 * @param pVM VM handle.
418 * @param GCPhysCR3 The physical address in the CR3 register.
419 */
420PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
421{
422#if PGM_GST_TYPE == PGM_TYPE_32BIT \
423 || PGM_GST_TYPE == PGM_TYPE_PAE \
424 || PGM_GST_TYPE == PGM_TYPE_AMD64
425
426 LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
427
428 /*
429 * Map the page CR3 points at.
430 */
431 RTHCPHYS HCPhysGuestCR3;
432 RTHCPTR HCPtrGuestCR3;
433 int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
434 if (VBOX_SUCCESS(rc))
435 {
436 rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
437 if (VBOX_SUCCESS(rc))
438 {
439 PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
440# if PGM_GST_TYPE == PGM_TYPE_32BIT
441 pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
442 pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
443
444# elif PGM_GST_TYPE == PGM_TYPE_PAE
445 unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
446 pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
447 pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
448 Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
449
450 /*
451 * Map the 4 PDs too.
452 */
453 RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
454 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
455 {
456 if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
457 {
458 RTHCPTR HCPtr;
459 RTHCPHYS HCPhys;
460 RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
461 int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
462 if (VBOX_SUCCESS(rc2))
463 {
464 rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
465 AssertRCReturn(rc, rc);
466 pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
467 pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
468 pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
469 PGM_INVL_PG(GCPtr);
470 continue;
471 }
472 AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
473 }
474
475 pVM->pgm.s.apGstPaePDsHC[i] = 0;
476 pVM->pgm.s.apGstPaePDsGC[i] = 0;
477 pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
478 PGM_INVL_PG(GCPtr);
479 }
480# elif PGM_GST_TYPE == PGM_TYPE_AMD64
481 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
482
483 pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
484
485 if (!HWACCMIsNestedPagingActive(pVM))
486 {
487 if (pVM->pgm.s.pHCShwAmd64CR3)
488 {
489 pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
490 pVM->pgm.s.pHCShwAmd64CR3 = 0;
491 pVM->pgm.s.pHCPaePML4 = 0;
492 pVM->pgm.s.HCPhysPaePML4 = 0;
493 }
494
495 Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
496try_again:
497 rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
498 if (rc == VERR_PGM_POOL_FLUSHED)
499 {
500 Log(("MapCR3: Flush pool and try again\n"));
501 Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
502 rc = pgmPoolSyncCR3(pVM);
503 AssertRC(rc);
504 goto try_again;
505 }
506 pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
507 pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
508 }
509# endif
510 }
511 else
512 AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
513 }
514 else
515 AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
516
517#else /* prot/real stub */
518 int rc = VINF_SUCCESS;
519#endif
520 return rc;
521}
522
523
524/**
525 * Unmaps the CR3.
526 *
527 * @returns VBox status, no specials.
528 * @param pVM VM handle.
529 */
530PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
531{
532 LogFlow(("UnmapCR3\n"));
533
534 int rc = VINF_SUCCESS;
535
536#if PGM_GST_TYPE == PGM_TYPE_32BIT
537 pVM->pgm.s.pGuestPDHC = 0;
538 pVM->pgm.s.pGuestPDGC = 0;
539
540#elif PGM_GST_TYPE == PGM_TYPE_PAE
541 pVM->pgm.s.pGstPaePDPTHC = 0;
542 pVM->pgm.s.pGstPaePDPTGC = 0;
543 for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
544 {
545 pVM->pgm.s.apGstPaePDsHC[i] = 0;
546 pVM->pgm.s.apGstPaePDsGC[i] = 0;
547 pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
548 }
549
550#elif PGM_GST_TYPE == PGM_TYPE_AMD64
551 pVM->pgm.s.pGstPaePML4HC = 0;
552 if (!HWACCMIsNestedPagingActive(pVM))
553 {
554 pVM->pgm.s.pHCPaePML4 = 0;
555 if (pVM->pgm.s.pHCShwAmd64CR3)
556 {
557 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
558 pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
559 pVM->pgm.s.pHCShwAmd64CR3 = NULL;
560 }
561 }
562
563#else /* prot/real mode stub */
564 /* nothing to do */
565#endif
566 return rc;
567}
568
569
570#undef LOG_GROUP
571#define LOG_GROUP LOG_GROUP_PGM_POOL
572
573/**
574 * Registers physical page monitors for the necessary paging
575 * structures to detect conflicts with our guest mappings.
576 *
577 * This is always called after mapping CR3.
578 * This is never called with fixed mappings.
579 *
580 * @returns VBox status, no specials.
581 * @param pVM VM handle.
582 * @param GCPhysCR3 The physical address in the CR3 register.
583 */
584PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
585{
586 Assert(!pVM->pgm.s.fMappingsFixed);
587 int rc = VINF_SUCCESS;
588
589 /*
590 * Register/Modify write phys handler for guest's CR3 if it changed.
591 */
592#if PGM_GST_TYPE == PGM_TYPE_32BIT
593
594 if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
595 {
596# ifndef PGMPOOL_WITH_MIXED_PT_CR3
597 const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
598 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
599 rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
600 else
601 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
602 pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
603 pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
604 pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
605 pVM->pgm.s.pszR3GstWriteHandlerCR3);
606# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
607 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
608 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
609 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
610 ? PGMPOOL_IDX_PAE_PD
611 : PGMPOOL_IDX_PD,
612 GCPhysCR3);
613# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
614 if (VBOX_FAILURE(rc))
615 {
616 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
617 rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
618 return rc;
619 }
620 pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
621 }
622
623#elif PGM_GST_TYPE == PGM_TYPE_PAE
624 /* Monitor the PDPT page */
625 /*
626 * Register/Modify write phys handler for guest's CR3 if it changed.
627 */
628# ifndef PGMPOOL_WITH_MIXED_PT_CR3
629 AssertFailed();
630# endif
631 if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
632 {
633 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
634 if (VBOX_FAILURE(rc))
635 {
636 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
637 rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
638 return rc;
639 }
640 pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
641 }
642 /*
643 * Do the 4 PDs.
644 */
645 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
646 {
647 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
648 {
649 RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
650 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
651 {
652 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
653
654 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
655 }
656
657 if (VBOX_FAILURE(rc))
658 {
659 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
660 rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
661 return rc;
662 }
663 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
664 }
665 else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
666 {
667 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
668 AssertRC(rc);
669 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
670 }
671 }
672
673#else
674 /* prot/real/amd64 mode stub */
675
676#endif
677 return rc;
678}
679
680/**
681 * Deregisters any physical page monitors installed by MonitorCR3.
682 *
683 * @returns VBox status code, no specials.
684 * @param pVM The VM handle.
685 */
686PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
687{
688 int rc = VINF_SUCCESS;
689
690 /*
691 * Deregister the access handlers.
692 *
693 * PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
694 * before we enter GC again.
695 */
696#if PGM_GST_TYPE == PGM_TYPE_32BIT
697 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
698 {
699# ifndef PGMPOOL_WITH_MIXED_PT_CR3
700 rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
701 AssertRCReturn(rc, rc);
702# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
703 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
704 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
705 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
706 ? PGMPOOL_IDX_PAE_PD
707 : PGMPOOL_IDX_PD);
708 AssertRCReturn(rc, rc);
709# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
710 pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
711 }
712
713#elif PGM_GST_TYPE == PGM_TYPE_PAE
714 /* The PDPT page */
715# ifndef PGMPOOL_WITH_MIXED_PT_CR3
716 AssertFailed();
717# endif
718
719 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
720 {
721 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
722 AssertRC(rc);
723 }
724
725 /* The 4 PDs. */
726 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
727 {
728 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
729 {
730 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
731 int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
732 AssertRC(rc2);
733 if (VBOX_FAILURE(rc2))
734 rc = rc2;
735 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
736 }
737 }
738#else
739 /* prot/real/amd64 mode stub */
740#endif
741 return rc;
742
743}
744
745#undef LOG_GROUP
746#define LOG_GROUP LOG_GROUP_PGM
747
748
749#if PGM_GST_TYPE == PGM_TYPE_32BIT \
750 || PGM_GST_TYPE == PGM_TYPE_PAE \
751 || PGM_GST_TYPE == PGM_TYPE_AMD64
752/**
753 * Updates one virtual handler range.
754 *
755 * @returns 0
756 * @param pNode Pointer to a PGMVIRTHANDLER.
757 * @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
758 */
759static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
760{
761 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
762 PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
763 Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
764
765#if PGM_GST_TYPE == PGM_TYPE_32BIT
766 PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
767#endif
768
769 RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
770#if PGM_GST_MODE != PGM_MODE_AMD64
771 /* skip all stuff above 4GB if not AMD64 mode. */
772 if (GCPtr >= _4GB)
773 return 0;
774#endif
775
776 unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
777 unsigned iPage = 0;
778 while (iPage < pCur->cPages)
779 {
780#if PGM_GST_TYPE == PGM_TYPE_32BIT
781 X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
782#elif PGM_GST_TYPE == PGM_TYPE_PAE
783 X86PDEPAE Pde;
784 Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
785#elif PGM_GST_TYPE == PGM_TYPE_AMD64
786 X86PDEPAE Pde;
787 Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
788#endif
789 if (Pde.n.u1Present)
790 {
791 if ( !Pde.b.u1Size
792# if PGM_GST_TYPE != PGM_TYPE_AMD64
793 || !(pState->cr4 & X86_CR4_PSE)
794# endif
795 )
796 {
797 /*
798 * Normal page table.
799 */
800 PGSTPT pPT;
801 int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
802 if (VBOX_SUCCESS(rc))
803 {
804 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
805 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
806 iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
807 {
808 GSTPTE Pte = pPT->a[iPTE];
809 RTGCPHYS GCPhysNew;
810 if (Pte.n.u1Present)
811 GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
812 else
813 GCPhysNew = NIL_RTGCPHYS;
814 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
815 {
816 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
817 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
818#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
819 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
820 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
821 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
822 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
823#endif
824 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
825 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
826 }
827 }
828 }
829 else
830 {
831 /* not-present. */
832 offPage = 0;
833 AssertRC(rc);
834 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
835 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
836 iPTE++, iPage++, GCPtr += PAGE_SIZE)
837 {
838 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
839 {
840 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
841#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
842 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
843 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
844 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
845 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
846#endif
847 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
848 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
849 }
850 }
851 }
852 }
853 else
854 {
855 /*
856 * 2/4MB page.
857 */
858 RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
859 for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
860 i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
861 i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
862 {
863 RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
864 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
865 {
866 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
867 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
868#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
869 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
870 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
871 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
872 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
873#endif
874 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
875 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
876 }
877 }
878 } /* pde type */
879 }
880 else
881 {
882 /* not-present. */
883 for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
884 cPages && iPage < pCur->cPages;
885 iPage++, GCPtr += PAGE_SIZE)
886 {
887 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
888 {
889 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
890 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
891 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
892 }
893 }
894 offPage = 0;
895 }
896 } /* for pages in virtual mapping. */
897
898 return 0;
899}
900#endif /* 32BIT, PAE and AMD64 */
901
902
903/**
904 * Updates the virtual page access handlers.
905 *
906 * @returns true if bits were flushed.
907 * @returns false if bits weren't flushed.
908 * @param pVM VM handle.
909 * @param pPDSrc The page directory.
910 * @param cr4 The cr4 register value.
911 */
912PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
913{
914#if PGM_GST_TYPE == PGM_TYPE_32BIT \
915 || PGM_GST_TYPE == PGM_TYPE_PAE \
916 || PGM_GST_TYPE == PGM_TYPE_AMD64
917
918 /** @todo
919 * In theory this is not sufficient: the guest can change a single page in a range with invlpg
920 */
921
922 /*
923 * Resolve any virtual address based access handlers to GC physical addresses.
924 * This should be fairly quick.
925 */
926 PGMHVUSTATE State;
927
928 pgmLock(pVM);
929 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
930 State.pVM = pVM;
931 State.fTodo = pVM->pgm.s.fSyncFlags;
932 State.cr4 = cr4;
933 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
934 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
935
936
937 /*
938 * Set / reset bits?
939 */
940 if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
941 {
942 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
943 Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
944 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
945 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
946 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
947 }
948 pgmUnlock(pVM);
949
950 return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
951
952#else /* real / protected */
953 return false;
954#endif
955}
956
957
958#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
959
960/**
961 * Write access handler for the Guest CR3 page in 32-bit mode.
962 *
963 * This will try interpret the instruction, if failure fail back to the recompiler.
964 * Check if the changed PDEs are marked present and conflicts with our
965 * mappings. If conflict, we'll switch to the host context and resolve it there
966 *
967 * @returns VBox status code (appropritate for trap handling and GC return).
968 * @param pVM VM Handle.
969 * @param uErrorCode CPU Error code.
970 * @param pRegFrame Trap register frame.
971 * @param pvFault The fault address (cr2).
972 * @param GCPhysFault The GC physical address corresponding to pvFault.
973 * @param pvUser User argument.
974 */
975PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
976{
977 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
978
979 /*
980 * Try interpret the instruction.
981 */
982 uint32_t cb;
983 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
984 if (VBOX_SUCCESS(rc) && cb)
985 {
986 /*
987 * Check if the modified PDEs are present and mappings.
988 */
989 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
990 const unsigned iPD1 = offPD / sizeof(X86PDE);
991 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
992
993 Assert(cb > 0 && cb <= 8);
994 Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
995 Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
996
997#ifdef DEBUG
998 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
999 if (iPD1 != iPD2)
1000 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
1001#endif
1002
1003 if (!pVM->pgm.s.fMappingsFixed)
1004 {
1005 PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
1006 if ( ( pPDSrc->a[iPD1].n.u1Present
1007 && pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1008 || ( iPD1 != iPD2
1009 && pPDSrc->a[iPD2].n.u1Present
1010 && pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1011 )
1012 {
1013 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1014 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1015 if (rc == VINF_SUCCESS)
1016 rc = VINF_PGM_SYNC_CR3;
1017 Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1018 return rc;
1019 }
1020 }
1021
1022 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1023 }
1024 else
1025 {
1026 Assert(VBOX_FAILURE(rc));
1027 if (rc == VERR_EM_INTERPRETER)
1028 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1029 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1030 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1031 }
1032 return rc;
1033}
1034
1035#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1036
1037
1038#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1039
1040/**
1041 * Write access handler for the Guest CR3 page in PAE mode.
1042 *
1043 * This will try interpret the instruction, if failure fail back to the recompiler.
1044 * Check if the changed PDEs are marked present and conflicts with our
1045 * mappings. If conflict, we'll switch to the host context and resolve it there
1046 *
1047 * @returns VBox status code (appropritate for trap handling and GC return).
1048 * @param pVM VM Handle.
1049 * @param uErrorCode CPU Error code.
1050 * @param pRegFrame Trap register frame.
1051 * @param pvFault The fault address (cr2).
1052 * @param GCPhysFault The GC physical address corresponding to pvFault.
1053 * @param pvUser User argument.
1054 */
1055PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1056{
1057 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1058
1059 /*
1060 * Try interpret the instruction.
1061 */
1062 uint32_t cb;
1063 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1064 if (VBOX_SUCCESS(rc) && cb)
1065 {
1066 /*
1067 * Check if any of the PDs have changed.
1068 * We'll simply check all of them instead of figuring out which one/two to check.
1069 */
1070 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1071 {
1072 if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1073 && ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1074 != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1075 {
1076 /*
1077 * The PDPE has changed.
1078 * We will schedule a monitoring update for the next TLB Flush,
1079 * InvalidatePage or SyncCR3.
1080 *
1081 * This isn't perfect, because a lazy page sync might be dealing with an half
1082 * updated PDPE. However, we assume that the guest OS is disabling interrupts
1083 * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1084 * executing.
1085 */
1086 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1087 Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1088 i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1089 }
1090 }
1091
1092 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1093 }
1094 else
1095 {
1096 Assert(VBOX_FAILURE(rc));
1097 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1098 if (rc == VERR_EM_INTERPRETER)
1099 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1100 }
1101 Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1102 return rc;
1103}
1104
1105
1106/**
1107 * Write access handler for the Guest PDs in PAE mode.
1108 *
1109 * This will try interpret the instruction, if failure fail back to the recompiler.
1110 * Check if the changed PDEs are marked present and conflicts with our
1111 * mappings. If conflict, we'll switch to the host context and resolve it there
1112 *
1113 * @returns VBox status code (appropritate for trap handling and GC return).
1114 * @param pVM VM Handle.
1115 * @param uErrorCode CPU Error code.
1116 * @param pRegFrame Trap register frame.
1117 * @param pvFault The fault address (cr2).
1118 * @param GCPhysFault The GC physical address corresponding to pvFault.
1119 * @param pvUser User argument.
1120 */
1121PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1122{
1123 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1124
1125 /*
1126 * Try interpret the instruction.
1127 */
1128 uint32_t cb;
1129 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1130 if (VBOX_SUCCESS(rc) && cb)
1131 {
1132 /*
1133 * Figure out which of the 4 PDs this is.
1134 */
1135 RTGCUINTPTR i;
1136 for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1137 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1138 {
1139 PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1140 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1141 const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1142 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1143
1144 Assert(cb > 0 && cb <= 8);
1145 Assert(iPD1 < X86_PG_PAE_ENTRIES);
1146 Assert(iPD2 < X86_PG_PAE_ENTRIES);
1147
1148#ifdef DEBUG
1149 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1150 i, iPD1, (i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT)));
1151 if (iPD1 != iPD2)
1152 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1153 i, iPD2, (i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT)));
1154#endif
1155
1156 if (!pVM->pgm.s.fMappingsFixed)
1157 {
1158 if ( ( pPDSrc->a[iPD1].n.u1Present
1159 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT))) )
1160 || ( iPD1 != iPD2
1161 && pPDSrc->a[iPD2].n.u1Present
1162 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT))) )
1163 )
1164 {
1165 Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1166 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1167 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1168 return VINF_PGM_SYNC_CR3;
1169 }
1170 }
1171 break; /* ASSUMES no duplicate entries... */
1172 }
1173 Assert(i < 4);
1174
1175 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1176 }
1177 else
1178 {
1179 Assert(VBOX_FAILURE(rc));
1180 if (rc == VERR_EM_INTERPRETER)
1181 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1182 else
1183 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1184 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1185 }
1186 return rc;
1187}
1188
1189#endif /* PGM_TYPE_PAE && !IN_RING3 */
1190
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