PGMAllGst.h@ 93115

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1	/* $Id: PGMAllGst.h 93115 2022-01-01 11:31:46Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Internal Functions *
21	*********************************************************************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30
31	#ifdef IN_RING3 /* r3 only for now. */
32	PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
33	PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
34	PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu);
35	#endif
36	RT_C_DECLS_END
37
38
39	/**
40	* Enters the guest mode.
41	*
42	* @returns VBox status code.
43	* @param pVCpu The cross context virtual CPU structure.
44	* @param GCPhysCR3 The physical address from the CR3 register.
45	*/
46	PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
47	{
48	/*
49	* Map and monitor CR3
50	*/
51	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
52	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
53	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
54	return g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
55	}
56
57
58	/**
59	* Exits the guest mode.
60	*
61	* @returns VBox status code.
62	* @param pVCpu The cross context virtual CPU structure.
63	*/
64	PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu)
65	{
66	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
67	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
68	AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
69	return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
70	}
71
72
73	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
74	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
75	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
76
77
78	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
79	{
80	NOREF(iLevel); NOREF(pVCpu);
81	pWalk->fNotPresent = true;
82	pWalk->uLevel = (uint8_t)iLevel;
83	return VERR_PAGE_TABLE_NOT_PRESENT;
84	}
85
86	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel, int rc)
87	{
88	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
89	pWalk->fBadPhysAddr = true;
90	pWalk->uLevel = (uint8_t)iLevel;
91	return VERR_PAGE_TABLE_NOT_PRESENT;
92	}
93
94	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
95	{
96	NOREF(pVCpu);
97	pWalk->fRsvdError = true;
98	pWalk->uLevel = (uint8_t)iLevel;
99	return VERR_PAGE_TABLE_NOT_PRESENT;
100	}
101
102
103	/**
104	* Performs a guest page table walk.
105	*
106	* @returns VBox status code.
107	* @retval VINF_SUCCESS on success.
108	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
109	*
110	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
111	* @param GCPtr The guest virtual address to walk by.
112	* @param pWalk The page walk info.
113	* @param pGstWalk The guest mode specific page walk info.
114	*/
115	DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
116	{
117	int rc;
118
119	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
120	/** @def PGM_GST_SLAT_WALK
121	* Macro to perform guest second-level address translation (EPT or Nested).
122	*
123	* @param a_pVCpu The cross context virtual CPU structure of the calling
124	* EMT.
125	* @param a_GCPtrNested The nested-guest linear address that caused the
126	* second-level translation.
127	* @param a_GCPhysNested The nested-guest physical address to translate.
128	* @param a_GCPhysOut Where to store the guest-physical address (result).
129	*/
130	# define PGM_GST_SLAT_WALK(a_pVCpu, a_GCPtrNested, a_GCPhysNested, a_GCPhysOut, a_pWalk) \
131	do { \
132	if ((a_pVCpu)->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT) \
133	{ \
134	PGMPTWALK SlatWalk; \
135	PGMPTWALKGST SlatGstWalk; \
136	int const rcX = pgmGstSlatWalk(a_pVCpu, a_GCPhysNested, true /* fIsLinearAddrValid */, a_GCPtrNested, &SlatWalk, \
137	&SlatGstWalk); \
138	if (RT_SUCCESS(rcX)) \
139	(a_GCPhysOut) = SlatWalk.GCPhys; \
140	else \
141	{ \
142	*(a_pWalk) = SlatWalk; \
143	return rcX; \
144	} \
145	} \
146	} while (0)
147	#endif
148
149	/*
150	* Init the walking structures.
151	*/
152	RT_ZERO(*pWalk);
153	RT_ZERO(*pGstWalk);
154	pWalk->GCPtr = GCPtr;
155
156	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
157	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
158	/*
159	* Boundary check for PAE and 32-bit (prevents trouble further down).
160	*/
161	if (RT_UNLIKELY(GCPtr >= _4G))
162	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
163	# endif
164
165	uint64_t fEffective;
166	{
167	# if PGM_GST_TYPE == PGM_TYPE_AMD64
168	/*
169	* The PML4 table.
170	*/
171	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pGstWalk->pPml4);
172	if (RT_SUCCESS(rc)) { /* probable */ }
173	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
174
175	PX86PML4E pPml4e;
176	pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
177	X86PML4E Pml4e;
178	pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
179
180	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
181	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
182
183	if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
184	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
185
186	pWalk->fEffective = fEffective = Pml4e.u & ( X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_PWT
187	\| X86_PML4E_PCD \| X86_PML4E_A \| X86_PML4E_NX);
188
189	/*
190	* The PDPT.
191	*/
192	RTGCPHYS GCPhysPdpt = Pml4e.u & X86_PML4E_PG_MASK;
193	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
194	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPdpt, GCPhysPdpt, pWalk);
195	#endif
196	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPdpt, &pGstWalk->pPdpt);
197	if (RT_SUCCESS(rc)) { /* probable */ }
198	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
199
200	# elif PGM_GST_TYPE == PGM_TYPE_PAE
201	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pGstWalk->pPdpt);
202	if (RT_SUCCESS(rc)) { /* probable */ }
203	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
204	#endif
205	}
206	{
207	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
208	PX86PDPE pPdpe;
209	pGstWalk->pPdpe = pPdpe = &pGstWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
210	X86PDPE Pdpe;
211	pGstWalk->Pdpe.u = Pdpe.u = pPdpe->u;
212
213	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpe)) { /* probable */ }
214	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
215
216	if (RT_LIKELY(GST_IS_PDPE_VALID(pVCpu, Pdpe))) { /* likely */ }
217	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
218
219	# if PGM_GST_TYPE == PGM_TYPE_AMD64
220	pWalk->fEffective = fEffective &= (Pdpe.u & ( X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US
221	\| X86_PDPE_PWT \| X86_PDPE_PCD \| X86_PDPE_A))
222	\| (Pdpe.u & X86_PDPE_LM_NX);
223	# else
224	/* NX in the legacy-mode PAE PDPE is reserved. The valid check above ensures the NX bit is not set. */
225	pWalk->fEffective = fEffective = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A
226	\| (Pdpe.u & (X86_PDPE_PWT \| X86_PDPE_PCD));
227	# endif
228
229	/*
230	* The PD.
231	*/
232	RTGCPHYS GCPhysPd = Pdpe.u & X86_PDPE_PG_MASK;
233	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
234	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPd, GCPhysPd, pWalk);
235	# endif
236	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPd, &pGstWalk->pPd);
237	if (RT_SUCCESS(rc)) { /* probable */ }
238	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
239
240	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
241	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pGstWalk->pPd);
242	if (RT_SUCCESS(rc)) { /* probable */ }
243	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
244	# endif
245	}
246	{
247	PGSTPDE pPde;
248	pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
249	GSTPDE Pde;
250	pGstWalk->Pde.u = Pde.u = pPde->u;
251	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
252	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
253	if ((Pde.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
254	{
255	if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
256	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
257
258	/*
259	* We're done.
260	*/
261	# if PGM_GST_TYPE == PGM_TYPE_32BIT
262	fEffective = Pde.u & (X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A);
263	# else
264	fEffective &= (Pde.u & (X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A))
265	\| (Pde.u & X86_PDE2M_PAE_NX);
266	# endif
267	fEffective \|= Pde.u & (X86_PDE4M_D \| X86_PDE4M_G);
268	fEffective \|= (Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT;
269	pWalk->fEffective = fEffective;
270	Assert(GST_IS_NX_ACTIVE(pVCpu) \|\| !(fEffective & PGM_PTATTRS_NX_MASK));
271	Assert(fEffective & PGM_PTATTRS_R_MASK);
272
273	pWalk->fBigPage = true;
274	pWalk->fSucceeded = true;
275	RTGCPHYS GCPhysPde = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
276	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
277	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
278	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPde, GCPhysPde, pWalk);
279	# endif
280	pWalk->GCPhys = GCPhysPde;
281	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
282	return VINF_SUCCESS;
283	}
284
285	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
286	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
287	# if PGM_GST_TYPE == PGM_TYPE_32BIT
288	pWalk->fEffective = fEffective = Pde.u & ( X86_PDE_P \| X86_PDE_RW \| X86_PDE_US
289	\| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A);
290	# else
291	pWalk->fEffective = fEffective &= (Pde.u & ( X86_PDE_P \| X86_PDE_RW \| X86_PDE_US
292	\| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A))
293	\| (Pde.u & X86_PDE_PAE_NX);
294	# endif
295
296	/*
297	* The PT.
298	*/
299	RTGCPHYS GCPhysPt = GST_GET_PDE_GCPHYS(Pde);
300	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
301	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPt, GCPhysPt, pWalk);
302	# endif
303	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pGstWalk->pPt);
304	if (RT_SUCCESS(rc)) { /* probable */ }
305	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
306	}
307	{
308	PGSTPTE pPte;
309	pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
310	GSTPTE Pte;
311	pGstWalk->Pte.u = Pte.u = pPte->u;
312
313	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
314	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
315
316	if (RT_LIKELY(GST_IS_PTE_VALID(pVCpu, Pte))) { /* likely */ }
317	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
318
319	/*
320	* We're done.
321	*/
322	# if PGM_GST_TYPE == PGM_TYPE_32BIT
323	fEffective &= Pte.u & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A);
324	# else
325	fEffective &= (Pte.u & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A))
326	\| (Pte.u & X86_PTE_PAE_NX);
327	# endif
328	fEffective \|= Pte.u & (X86_PTE_D \| X86_PTE_PAT \| X86_PTE_G);
329	pWalk->fEffective = fEffective;
330	Assert(GST_IS_NX_ACTIVE(pVCpu) \|\| !(fEffective & PGM_PTATTRS_NX_MASK));
331	Assert(fEffective & PGM_PTATTRS_R_MASK);
332
333	pWalk->fSucceeded = true;
334	RTGCPHYS GCPhysPte = GST_GET_PTE_GCPHYS(Pte)
335	\| (GCPtr & PAGE_OFFSET_MASK);
336	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
337	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPte, GCPhysPte, pWalk);
338	# endif
339	pWalk->GCPhys = GCPhysPte;
340	return VINF_SUCCESS;
341	}
342	}
343
344	#endif /* 32BIT, PAE, AMD64 */
345
346	/**
347	* Gets effective Guest OS page information.
348	*
349	* When GCPtr is in a big page, the function will return as if it was a normal
350	* 4KB page. If the need for distinguishing between big and normal page becomes
351	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
352	* purpose.
353	*
354	* @returns VBox status code.
355	* @param pVCpu The cross context virtual CPU structure.
356	* @param GCPtr Guest Context virtual address of the page.
357	* @param pWalk Where to store the page walk info.
358	*/
359	PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
360	{
361	#if PGM_GST_TYPE == PGM_TYPE_REAL \
362	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
363	/*
364	* Fake it.
365	*/
366	RT_ZERO(*pWalk);
367	pWalk->fSucceeded = true;
368	pWalk->GCPtr = GCPtr;
369	pWalk->GCPhys = GCPtr & PAGE_BASE_GC_MASK;
370	pWalk->fEffective = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
371	pWalk->GCPhys = GCPtr & PAGE_BASE_GC_MASK;
372	NOREF(pVCpu);
373	return VINF_SUCCESS;
374
375	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
376	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
377	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
378
379	GSTPTWALK GstWalk;
380	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, pWalk, &GstWalk);
381	if (RT_FAILURE(rc))
382	return rc;
383
384	Assert(pWalk->fSucceeded);
385	Assert(pWalk->GCPtr == GCPtr);
386
387	PGMPTATTRS fFlags;
388	if (!pWalk->fBigPage)
389	fFlags = (GstWalk.Pte.u & ~(GST_PTE_PG_MASK \| X86_PTE_RW \| X86_PTE_US)) /* NX not needed */
390	\| (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
391	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
392	\| (pWalk->fEffective & PGM_PTATTRS_NX_MASK)
393	# endif
394	;
395	else
396	{
397	fFlags = (GstWalk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PS)) /* NX not needed */
398	\| (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK \| PGM_PTATTRS_PAT_MASK))
399	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
400	\| (pWalk->fEffective & PGM_PTATTRS_NX_MASK)
401	# endif
402	;
403	}
404
405	pWalk->GCPhys &= ~(RTGCPHYS)PAGE_OFFSET_MASK;
406	pWalk->fEffective = fFlags;
407	return VINF_SUCCESS;
408
409	#else
410	# error "shouldn't be here!"
411	/* something else... */
412	return VERR_NOT_SUPPORTED;
413	#endif
414	}
415
416
417	/**
418	* Modify page flags for a range of pages in the guest's tables
419	*
420	* The existing flags are ANDed with the fMask and ORed with the fFlags.
421	*
422	* @returns VBox status code.
423	* @param pVCpu The cross context virtual CPU structure.
424	* @param GCPtr Virtual address of the first page in the range. Page aligned!
425	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
426	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
427	* @param fMask The AND mask - page flags X86_PTE_*.
428	*/
429	PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
430	{
431	Assert((cb & PAGE_OFFSET_MASK) == 0); RT_NOREF_PV(cb);
432
433	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
434	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
435	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
436	for (;;)
437	{
438	PGMPTWALK Walk;
439	GSTPTWALK GstWalk;
440	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk, &GstWalk);
441	if (RT_FAILURE(rc))
442	return rc;
443
444	if (!Walk.fBigPage)
445	{
446	/*
447	* 4KB Page table, process
448	*
449	* Walk pages till we're done.
450	*/
451	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
452	while (iPTE < RT_ELEMENTS(GstWalk.pPt->a))
453	{
454	GSTPTE Pte = GstWalk.pPt->a[iPTE];
455	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
456	\| (fFlags & ~GST_PTE_PG_MASK);
457	GstWalk.pPt->a[iPTE] = Pte;
458
459	/* next page */
460	cb -= PAGE_SIZE;
461	if (!cb)
462	return VINF_SUCCESS;
463	GCPtr += PAGE_SIZE;
464	iPTE++;
465	}
466	}
467	else
468	{
469	/*
470	* 2/4MB Page table
471	*/
472	GSTPDE PdeNew;
473	# if PGM_GST_TYPE == PGM_TYPE_32BIT
474	PdeNew.u = (GstWalk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
475	# else
476	PdeNew.u = (GstWalk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
477	# endif
478	\| (fFlags & ~GST_PTE_PG_MASK)
479	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
480	*GstWalk.pPde = PdeNew;
481
482	/* advance */
483	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
484	if (cbDone >= cb)
485	return VINF_SUCCESS;
486	cb -= cbDone;
487	GCPtr += cbDone;
488	}
489	}
490
491	#else
492	/* real / protected mode: ignore. */
493	NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
494	return VINF_SUCCESS;
495	#endif
496	}
497
498
499	#ifdef IN_RING3
500	/**
501	* Relocate any GC pointers related to guest mode paging.
502	*
503	* @returns VBox status code.
504	* @param pVCpu The cross context virtual CPU structure.
505	* @param offDelta The relocation offset.
506	*/
507	PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
508	{
509	RT_NOREF(pVCpu, offDelta);
510	return VINF_SUCCESS;
511	}
512	#endif

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 93115

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