PGMAllGst.h@ 5070

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1	/* $Id: PGMAllGst.h 4977 2007-09-22 00:01:15Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Defined Constants And Macros *
21	*******************************************************************************/
22	#undef GSTPT
23	#undef PGSTPT
24	#undef GSTPTE
25	#undef PGSTPTE
26	#undef GSTPD
27	#undef PGSTPD
28	#undef GSTPDE
29	#undef PGSTPDE
30	#undef GST_BIG_PAGE_SIZE
31	#undef GST_BIG_PAGE_OFFSET_MASK
32	#undef GST_PDE_PG_MASK
33	#undef GST_PDE4M_PG_MASK
34	#undef GST_PD_SHIFT
35	#undef GST_PD_MASK
36	#undef GST_PTE_PG_MASK
37	#undef GST_PT_SHIFT
38	#undef GST_PT_MASK
39	#undef GST_TOTAL_PD_ENTRIES
40
41	#if PGM_GST_TYPE == PGM_TYPE_32BIT
42	# define GSTPT X86PT
43	# define PGSTPT PX86PT
44	# define GSTPTE X86PTE
45	# define PGSTPTE PX86PTE
46	# define GSTPD X86PD
47	# define PGSTPD PX86PD
48	# define GSTPDE X86PDE
49	# define PGSTPDE PX86PDE
50	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
51	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
52	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
53	# define GST_PDE4M_PG_MASK X86_PDE4M_PG_MASK
54	# define GST_PD_SHIFT X86_PD_SHIFT
55	# define GST_PD_MASK X86_PD_MASK
56	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
57	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
58	# define GST_PT_SHIFT X86_PT_SHIFT
59	# define GST_PT_MASK X86_PT_MASK
60	#else
61	# define GSTPT X86PTPAE
62	# define PGSTPT PX86PTPAE
63	# define GSTPTE X86PTEPAE
64	# define PGSTPTE PX86PTEPAE
65	# define GSTPD X86PDPAE
66	# define PGSTPD PX86PDPAE
67	# define GSTPDE X86PDEPAE
68	# define PGSTPDE PX86PDEPAE
69	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
70	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
71	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
72	# define GST_PDE4M_PG_MASK X86_PDE4M_PAE_PG_MASK
73	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
74	# define GST_PD_MASK X86_PD_PAE_MASK
75	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*4)
76	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
77	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
78	# define GST_PT_MASK X86_PT_PAE_MASK
79	#endif
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	__BEGIN_DECLS
86	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
87	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
88	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
89	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
90	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
91	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
92	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
93	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
94	__END_DECLS
95
96
97
98	/**
99	* Gets effective Guest OS page information.
100	*
101	* When GCPtr is in a big page, the function will return as if it was a normal
102	* 4KB page. If the need for distinguishing between big and normal page becomes
103	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
104	* purpose.
105	*
106	* @returns VBox status.
107	* @param pVM VM Handle.
108	* @param GCPtr Guest Context virtual address of the page. Page aligned!
109	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
110	* @param pGCPhys Where to store the GC physical address of the page.
111	* This is page aligned. The fact that the
112	*/
113	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
114	{
115	#if PGM_GST_TYPE == PGM_TYPE_REAL \
116	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
117	/*
118	* Fake it.
119	*/
120	if (pfFlags)
121	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
122	if (pGCPhys)
123	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
124	return VINF_SUCCESS;
125
126	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
127	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
128	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
129
130	#if PGM_GST_TYPE == PGM_TYPE_AMD64
131	/* later */
132	AssertFailed();
133	return VERR_NOT_IMPLEMENTED;
134	#endif
135
136
137	/*
138	* Get the PDE.
139	*/
140	#if PGM_GST_TYPE == PGM_TYPE_32BIT
141	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
142	#else /* PAE */
143	X86PDEPAE Pde;
144	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
145	#endif
146
147	/*
148	* Lookup the page.
149	*/
150	if (!Pde.n.u1Present)
151	return VERR_PAGE_TABLE_NOT_PRESENT;
152
153	if ( !Pde.b.u1Size
154	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
155	{
156	PGSTPT pPT;
157	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
158	if (VBOX_FAILURE(rc))
159	return rc;
160
161	/*
162	* Get PT entry and check presentness.
163	*/
164	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
165	if (!Pte.n.u1Present)
166	return VERR_PAGE_NOT_PRESENT;
167
168	/*
169	* Store the result.
170	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
171	* where the PDPE is simplified.
172	*/
173	if (pfFlags)
174	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
175	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
176	if (pGCPhys)
177	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
178	}
179	else
180	{
181	/*
182	* Map big to 4k PTE and store the result
183	*/
184	if (pfFlags)
185	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
186	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
187	if (pGCPhys)
188	pGCPhys = (Pde.u & GST_PDE4M_PG_MASK) \| (GCPtr & (~GST_PDE4M_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
189	}
190	return VINF_SUCCESS;
191	#else
192	/* something else... */
193	return VERR_NOT_SUPPORTED;
194	#endif
195	}
196
197
198	/**
199	* Modify page flags for a range of pages in the guest's tables
200	*
201	* The existing flags are ANDed with the fMask and ORed with the fFlags.
202	*
203	* @returns VBox status code.
204	* @param pVM VM handle.
205	* @param GCPtr Virtual address of the first page in the range. Page aligned!
206	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
207	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
208	* @param fMask The AND mask - page flags X86_PTE_*.
209	*/
210	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
211	{
212	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
213	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
214	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
215
216	#if PGM_GST_TYPE == PGM_TYPE_AMD64
217	/* later */
218	AssertFailed();
219	return VERR_NOT_IMPLEMENTED;
220	#endif
221
222	for (;;)
223	{
224	/*
225	* Get the PD entry.
226	*/
227	#if PGM_GST_TYPE == PGM_TYPE_32BIT
228	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
229	#else /* PAE */
230	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
231	Assert(pPde);
232	if (!pPde)
233	return VERR_PAGE_TABLE_NOT_PRESENT;
234	#endif
235	GSTPDE Pde = *pPde;
236	Assert(Pde.n.u1Present);
237	if (!Pde.n.u1Present)
238	return VERR_PAGE_TABLE_NOT_PRESENT;
239
240	if ( !Pde.b.u1Size
241	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
242	{
243	/*
244	* 4KB Page table
245	*
246	* Walk page tables and pages till we're done.
247	*/
248	PGSTPT pPT;
249	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
250	if (VBOX_FAILURE(rc))
251	return rc;
252
253	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
254	while (iPTE < ELEMENTS(pPT->a))
255	{
256	GSTPTE Pte = pPT->a[iPTE];
257	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
258	\| (fFlags & ~GST_PTE_PG_MASK);
259	pPT->a[iPTE] = Pte;
260
261	/* next page */
262	cb -= PAGE_SIZE;
263	if (!cb)
264	return VINF_SUCCESS;
265	GCPtr += PAGE_SIZE;
266	iPTE++;
267	}
268	}
269	else
270	{
271	/*
272	* 4MB Page table
273	*/
274	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| X86_PDE4M_PAE_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
275	\| (fFlags & ~GST_PTE_PG_MASK)
276	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
277	*pPde = Pde;
278
279	/* advance */
280	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
281	if (cbDone >= cb)
282	return VINF_SUCCESS;
283	cb -= cbDone;
284	GCPtr += cbDone;
285	}
286	}
287
288	#else
289	/* real / protected mode: ignore. */
290	return VINF_SUCCESS;
291	#endif
292	}
293
294
295	/**
296	* Retrieve guest PDE information
297	*
298	* @returns VBox status code.
299	* @param pVM The virtual machine.
300	* @param GCPtr Guest context pointer
301	* @param pPDE Pointer to guest PDE structure
302	*/
303	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
304	{
305	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
306	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
307	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
308
309	#if PGM_GST_TYPE == PGM_TYPE_AMD64
310	/* later */
311	AssertFailed();
312	return VERR_NOT_IMPLEMENTED;
313	#endif
314
315	# if PGM_GST_TYPE == PGM_TYPE_32BIT
316	X86PDE Pde;
317	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
318	# else
319	X86PDEPAE Pde;
320	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
321	# endif
322
323	pPDE->u = (X86PGPAEUINT)Pde.u;
324	return VINF_SUCCESS;
325	#else
326	AssertFailed();
327	return VERR_NOT_IMPLEMENTED;
328	#endif
329	}
330
331
332
333	/**
334	* Maps the CR3 into HMA in GC and locate it in HC.
335	*
336	* @returns VBox status, no specials.
337	* @param pVM VM handle.
338	* @param GCPhysCR3 The physical address in the CR3 register.
339	*/
340	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
341	{
342	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
343	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
344	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
345	/*
346	* Map the page CR3 points at.
347	*/
348	RTHCPHYS HCPhysGuestCR3;
349	RTHCPTR HCPtrGuestCR3;
350	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3, &HCPtrGuestCR3, &HCPhysGuestCR3);
351	if (VBOX_SUCCESS(rc))
352	{
353	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3 & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
354	if (VBOX_SUCCESS(rc))
355	{
356	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
357	#if PGM_GST_TYPE == PGM_TYPE_32BIT
358	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
359	pVM->pgm.s.pGuestPDGC = (GCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
360
361	#elif PGM_GST_TYPE == PGM_TYPE_PAE
362	const unsigned off = GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
363	pVM->pgm.s.pGstPaePDPTRHC = (R3R0PTRTYPE(PX86PDPTR))((RTHCUINTPTR)HCPtrGuestCR3 \| off);
364	pVM->pgm.s.pGstPaePDPTRGC = (GCPTRTYPE(PX86PDPTR))((RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping \| off);
365
366	/*
367	* Map the 4 PDs too.
368	*/
369	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
370	for (unsigned i = 0; i < 4; i++, GCPtr += PAGE_SIZE)
371	{
372	if (pVM->pgm.s.CTXSUFF(pGstPaePDPTR)->a[i].n.u1Present)
373	{
374	RTHCPTR HCPtr;
375	RTHCPHYS HCPhys;
376	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPTR)->a[i].u & X86_PDPE_PG_MASK;
377	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
378	if (VBOX_SUCCESS(rc2))
379	{
380	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
381	AssertRCReturn(rc, rc);
382	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
383	pVM->pgm.s.apGstPaePDsGC[i] = (GCPTRTYPE(PX86PDPAE))GCPtr;
384	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
385	PGM_INVL_PG(GCPtr);
386	continue;
387	}
388	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
389	}
390
391	pVM->pgm.s.apGstPaePDsHC[i] = 0;
392	pVM->pgm.s.apGstPaePDsGC[i] = 0;
393	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
394	PGM_INVL_PG(GCPtr);
395	}
396
397	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
398	rc = VERR_NOT_IMPLEMENTED;
399	#endif
400	}
401	}
402	else
403	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
404
405	#else /* prot/real mode stub */
406	int rc = VINF_SUCCESS;
407	#endif
408	return rc;
409	}
410
411
412	/**
413	* Unmaps the CR3.
414	*
415	* @returns VBox status, no specials.
416	* @param pVM VM handle.
417	* @param GCPhysCR3 The physical address in the CR3 register.
418	*/
419	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
420	{
421	int rc = VINF_SUCCESS;
422	#if PGM_GST_TYPE == PGM_TYPE_32BIT
423	pVM->pgm.s.pGuestPDHC = 0;
424	pVM->pgm.s.pGuestPDGC = 0;
425
426	#elif PGM_GST_TYPE == PGM_TYPE_PAE
427	pVM->pgm.s.pGstPaePDPTRHC = 0;
428	pVM->pgm.s.pGstPaePDPTRGC = 0;
429
430	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
431	//#error not implemented
432	rc = VERR_NOT_IMPLEMENTED;
433
434	#else /* prot/real mode stub */
435	/* nothing to do */
436	#endif
437	return rc;
438	}
439
440
441	#undef LOG_GROUP
442	#define LOG_GROUP LOG_GROUP_PGM_POOL
443
444	/**
445	* Registers physical page monitors for the necessary paging
446	* structures to detect conflicts with our guest mappings.
447	*
448	* This is always called after mapping CR3.
449	* This is never called with fixed mappings.
450	*
451	* @returns VBox status, no specials.
452	* @param pVM VM handle.
453	* @param GCPhysCR3 The physical address in the CR3 register.
454	*/
455	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
456	{
457	Assert(!pVM->pgm.s.fMappingsFixed);
458	int rc = VINF_SUCCESS;
459
460	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
461	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
462	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
463
464	/*
465	* Register/Modify write phys handler for guest's CR3 if it changed.
466	*/
467	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
468	{
469	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
470	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
471	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
472	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
473	else
474	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
475	pVM->pgm.s.pfnHCGstWriteHandlerCR3, 0,
476	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
477	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
478	pVM->pgm.s.pszHCGstWriteHandlerCR3);
479	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
480	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
481	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
482	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
483	? PGMPOOL_IDX_PAE_PD
484	: PGMPOOL_IDX_PD,
485	GCPhysCR3);
486	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
487	if (VBOX_FAILURE(rc))
488	{
489	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
490	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
491	return rc;
492	}
493	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
494	}
495
496	#if PGM_GST_TYPE == PGM_TYPE_PAE
497	AssertFatalFailed();
498	# if 0 /* later */
499	/*
500	* Do the 4 PDs.
501	*/
502	for (unsigned i = 0; i < 4; i++)
503	{
504	if (pVM->pgm.s.pGstPaePDPTRHC->a[i].n.u1Present)
505	{
506	RTGCPHYS GCPhys = pVM->pgm.s.pGstPaePDPTRHC->a[i].u & X86_PDPE_PG_MASK;
507	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
508	{
509	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
510	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys, GCPhys + PAGE_SIZE - 1);
511	else
512	rc = PGMR3HandlerPhysicalRegister(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhys, GCPhys + PAGE_SIZE - 1,
513	pgmR3GstPaePDWriteHandler, NULL,
514	NULL, "pgmGCGstPaePDWriteHandler", 0,
515	"Guest PD write access handler");
516	if (VBOX_SUCCESS(rc))
517	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
518	}
519	}
520	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
521	{
522	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
523	AssertRC(rc);
524	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
525	}
526	}
527	# endif
528	#endif /* PGM_GST_TYPE == PGM_TYPE_PAE */
529
530	#else
531	/* prot/real mode stub */
532
533	#endif
534	return rc;
535	}
536
537	/**
538	* Deregisters any physical page monitors installed by MonitorCR3.
539	*
540	* @returns VBox status code, no specials.
541	* @param pVM The VM handle.
542	*/
543	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
544	{
545	int rc = VINF_SUCCESS;
546
547	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
548	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
549	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
550
551	/*
552	* Deregister the access handlers.
553	*
554	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
555	* before we enter GC again.
556	*/
557	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
558	{
559	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
560	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
561	AssertRCReturn(rc, rc);
562	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
563	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
564	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
565	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
566	? PGMPOOL_IDX_PAE_PD
567	: PGMPOOL_IDX_PD);
568	AssertRCReturn(rc, rc);
569	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
570	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
571	}
572
573	# if PGM_GST_TYPE == PGM_TYPE_PAE
574	/* The 4 PDs. */
575	for (unsigned i = 0; i < 4; i++)
576	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
577	{
578	int rc2 = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
579	AssertRC(rc2);
580	if (VBOX_FAILURE(rc2))
581	rc = rc2;
582	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
583	}
584	# endif
585
586	#else
587	/* prot/real mode stub */
588	#endif
589	return rc;
590
591	}
592
593	#undef LOG_GROUP
594	#define LOG_GROUP LOG_GROUP_PGM
595
596
597	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
598	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
599	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
600	/**
601	* Updates one virtual handler range.
602	*
603	* @returns 0
604	* @param pNode Pointer to a PGMVIRTHANDLER.
605	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
606	*/
607	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
608	{
609	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
610	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
611
612	#if PGM_GST_TYPE == PGM_TYPE_32BIT
613	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
614	#endif
615
616	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
617	#if PGM_GST_MODE != PGM_MODE_AMD64
618	/* skip all stuff above 4GB if not AMD64 mode. */
619	if (GCPtr >= _4GB)
620	return 0;
621	#endif
622
623	unsigned fFlags;
624	switch (pCur->enmType)
625	{
626	case PGMVIRTHANDLERTYPE_EIP:
627	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
628	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
629	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
630	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
631	case PGMVIRTHANDLERTYPE_HYPERVISOR:
632	return 0;
633	}
634
635	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
636	unsigned iPage = 0;
637	while (iPage < pCur->cPages)
638	{
639	#if PGM_GST_TYPE == PGM_TYPE_32BIT
640	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
641	#else
642	X86PDEPAE Pde;
643	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
644	#endif
645	if (Pde.n.u1Present)
646	{
647	if (!Pde.b.u1Size \|\| !(pState->cr4 & X86_CR4_PSE))
648	{
649	/*
650	* Normal page table.
651	*/
652	PGSTPT pPT;
653	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
654	if (VBOX_SUCCESS(rc))
655	{
656	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
657	iPTE < ELEMENTS(pPT->a) && iPage < pCur->cPages;
658	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
659	{
660	GSTPTE Pte = pPT->a[iPTE];
661	RTGCPHYS GCPhysNew;
662	if (Pte.n.u1Present)
663	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
664	else
665	GCPhysNew = NIL_RTGCPHYS;
666	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
667	{
668	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
669	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
670	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
671	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
672	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
673	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
674	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
675	#endif
676	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
677	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
678	}
679	}
680	}
681	else
682	{
683	/* not-present. */
684	offPage = 0;
685	AssertRC(rc);
686	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
687	iPTE < ELEMENTS(pPT->a) && iPage < pCur->cPages;
688	iPTE++, iPage++, GCPtr += PAGE_SIZE)
689	{
690	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
691	{
692	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
693	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
694	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
695	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
696	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
697	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
698	#endif
699	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
700	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
701	}
702	}
703	}
704	}
705	else
706	{
707	/*
708	* 2/4MB page.
709	*/
710	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
711	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
712	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
713	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
714	{
715	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
716	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
717	{
718	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
719	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
720	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
721	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
722	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
723	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
724	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
725	#endif
726	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
727	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
728	}
729	}
730	} /* pde type */
731	}
732	else
733	{
734	/* not-present. */
735	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
736	cPages && iPage < pCur->cPages;
737	iPage++, GCPtr += PAGE_SIZE)
738	{
739	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
740	{
741	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
742	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
743	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
744	}
745	}
746	offPage = 0;
747	}
748	} /* for pages in virtual mapping. */
749
750	return 0;
751	}
752	#endif /* 32BIT, PAE and AMD64 */
753
754
755	/**
756	* Updates the virtual page access handlers.
757	*
758	* @returns true if bits were flushed.
759	* @returns false if bits weren't flushed.
760	* @param pVM VM handle.
761	* @param pPDSrc The page directory.
762	* @param cr4 The cr4 register value.
763	*/
764	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
765	{
766	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
767	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
768	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
769	#if PGM_GST_TYPE == PGM_TYPE_AMD64
770	AssertFailed();
771	#endif
772
773	/** @todo
774	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
775	*/
776
777	/*
778	* Resolve any virtual address based access handlers to GC physical addresses.
779	* This should be fairly quick.
780	*/
781	PGMHVUSTATE State;
782
783	pgmLock(pVM);
784	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
785	State.pVM = pVM;
786	State.fTodo = pVM->pgm.s.fSyncFlags;
787	State.cr4 = cr4;
788	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
789	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
790
791
792	/*
793	* Set / reset bits?
794	*/
795	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
796	{
797	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
798	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
799	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
800	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
801	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
802	}
803	pgmUnlock(pVM);
804
805	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
806
807	#else /* real / protected */
808	return false;
809	#endif
810	}
811

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 5070

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