PGMAllGst.h@ 24327

Last change on this file since 24327 was 23853, checked in by vboxsync, 15 years ago
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1	/* $Id: PGMAllGst.h 23853 2009-10-19 11:33:30Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Internal Functions *
25	*******************************************************************************/
26	RT_C_DECLS_BEGIN
27	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
28	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
29	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
30	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
31	RT_C_DECLS_END
32
33
34
35	/**
36	* Gets effective Guest OS page information.
37	*
38	* When GCPtr is in a big page, the function will return as if it was a normal
39	* 4KB page. If the need for distinguishing between big and normal page becomes
40	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
41	* purpose.
42	*
43	* @returns VBox status.
44	* @param pVCpu The VMCPU handle.
45	* @param GCPtr Guest Context virtual address of the page.
46	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
47	* @param pGCPhys Where to store the GC physical address of the page.
48	* This is page aligned!
49	*/
50	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
51	{
52	#if PGM_GST_TYPE == PGM_TYPE_REAL \
53	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
54	/*
55	* Fake it.
56	*/
57	if (pfFlags)
58	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
59	if (pGCPhys)
60	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
61	return VINF_SUCCESS;
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
64
65	PVM pVM = pVCpu->CTX_SUFF(pVM);
66	/*
67	* Get the PDE.
68	*/
69	# if PGM_GST_TYPE == PGM_TYPE_32BIT
70	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
71
72	#elif PGM_GST_TYPE == PGM_TYPE_PAE
73	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
74	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
75	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
76	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
77
78	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
79	PX86PML4E pPml4e;
80	X86PDPE Pdpe;
81	X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVCpu->pgm.s, GCPtr, &pPml4e, &Pdpe);
82	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
83
84	Assert(pPml4e);
85	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
86	return VERR_PAGE_TABLE_NOT_PRESENT;
87
88	/* Merge accessed, write, user and no-execute bits into the PDE. */
89	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
90	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
91	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
92	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
93	# endif
94
95	/*
96	* Lookup the page.
97	*/
98	if (!Pde.n.u1Present)
99	return VERR_PAGE_TABLE_NOT_PRESENT;
100
101	if ( !Pde.b.u1Size
102	# if PGM_GST_TYPE != PGM_TYPE_AMD64
103	\|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE)
104	# endif
105	)
106	{
107	PGSTPT pPT;
108	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
109	if (RT_FAILURE(rc))
110	return rc;
111
112	/*
113	* Get PT entry and check presence.
114	*/
115	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
116	if (!Pte.n.u1Present)
117	return VERR_PAGE_NOT_PRESENT;
118
119	/*
120	* Store the result.
121	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
122	* where the PDPE is simplified.
123	*/
124	if (pfFlags)
125	{
126	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
127	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
128	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
129	/* The NX bit is determined by a bitwise OR between the PT and PD */
130	if (fNoExecuteBitValid)
131	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
132	# endif
133	}
134	if (pGCPhys)
135	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
136	}
137	else
138	{
139	/*
140	* Map big to 4k PTE and store the result
141	*/
142	if (pfFlags)
143	{
144	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
145	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
146	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
147	/* The NX bit is determined by a bitwise OR between the PT and PD */
148	if (fNoExecuteBitValid)
149	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
150	# endif
151	}
152	if (pGCPhys)
153	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
154	}
155	return VINF_SUCCESS;
156	#else
157	# error "shouldn't be here!"
158	/* something else... */
159	return VERR_NOT_SUPPORTED;
160	#endif
161	}
162
163
164	/**
165	* Modify page flags for a range of pages in the guest's tables
166	*
167	* The existing flags are ANDed with the fMask and ORed with the fFlags.
168	*
169	* @returns VBox status code.
170	* @param pVCpu The VMCPU handle.
171	* @param GCPtr Virtual address of the first page in the range. Page aligned!
172	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
173	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
174	* @param fMask The AND mask - page flags X86_PTE_*.
175	*/
176	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
177	{
178	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
179	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
180	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
181
182	Assert((cb & PAGE_OFFSET_MASK) == 0);
183
184	PVM pVM = pVCpu->CTX_SUFF(pVM);
185	for (;;)
186	{
187	/*
188	* Get the PD entry.
189	*/
190	# if PGM_GST_TYPE == PGM_TYPE_32BIT
191	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVCpu->pgm.s, GCPtr);
192
193	# elif PGM_GST_TYPE == PGM_TYPE_PAE
194	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
195	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
196	*/
197	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVCpu->pgm.s, GCPtr);
198	Assert(pPde);
199	if (!pPde)
200	return VERR_PAGE_TABLE_NOT_PRESENT;
201	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
202	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
203	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVCpu->pgm.s, GCPtr);
204	Assert(pPde);
205	if (!pPde)
206	return VERR_PAGE_TABLE_NOT_PRESENT;
207	# endif
208	GSTPDE Pde = *pPde;
209	Assert(Pde.n.u1Present);
210	if (!Pde.n.u1Present)
211	return VERR_PAGE_TABLE_NOT_PRESENT;
212
213	if ( !Pde.b.u1Size
214	# if PGM_GST_TYPE != PGM_TYPE_AMD64
215	\|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE)
216	# endif
217	)
218	{
219	/*
220	* 4KB Page table
221	*
222	* Walk page tables and pages till we're done.
223	*/
224	PGSTPT pPT;
225	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
226	if (RT_FAILURE(rc))
227	return rc;
228
229	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
230	while (iPTE < RT_ELEMENTS(pPT->a))
231	{
232	GSTPTE Pte = pPT->a[iPTE];
233	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
234	\| (fFlags & ~GST_PTE_PG_MASK);
235	pPT->a[iPTE] = Pte;
236
237	/* next page */
238	cb -= PAGE_SIZE;
239	if (!cb)
240	return VINF_SUCCESS;
241	GCPtr += PAGE_SIZE;
242	iPTE++;
243	}
244	}
245	else
246	{
247	/*
248	* 4MB Page table
249	*/
250	# if PGM_GST_TYPE == PGM_TYPE_32BIT
251	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
252	# else
253	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
254	# endif
255	\| (fFlags & ~GST_PTE_PG_MASK)
256	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
257	*pPde = Pde;
258
259	/* advance */
260	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
261	if (cbDone >= cb)
262	return VINF_SUCCESS;
263	cb -= cbDone;
264	GCPtr += cbDone;
265	}
266	}
267
268	#else
269	/* real / protected mode: ignore. */
270	return VINF_SUCCESS;
271	#endif
272	}
273
274
275	/**
276	* Retrieve guest PDE information
277	*
278	* @returns VBox status code.
279	* @param pVCpu The VMCPU handle.
280	* @param GCPtr Guest context pointer
281	* @param pPDE Pointer to guest PDE structure
282	*/
283	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
284	{
285	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
286	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
287	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
288
289	# if PGM_GST_TYPE == PGM_TYPE_32BIT
290	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
291	# elif PGM_GST_TYPE == PGM_TYPE_PAE
292	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
293	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
294	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
295	# endif
296
297	pPDE->u = (X86PGPAEUINT)Pde.u;
298	return VINF_SUCCESS;
299	#else
300	AssertFailed();
301	return VERR_NOT_IMPLEMENTED;
302	#endif
303	}
304
305
306	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
307	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
308	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
309	/**
310	* Updates one virtual handler range.
311	*
312	* @returns 0
313	* @param pNode Pointer to a PGMVIRTHANDLER.
314	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
315	*/
316	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
317	{
318	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
319	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
320	PVM pVM = pState->pVM;
321	PVMCPU pVCpu = pState->pVCpu;
322	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
323
324	#if PGM_GST_TYPE == PGM_TYPE_32BIT
325	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
326	#endif
327
328	RTGCPTR GCPtr = pCur->Core.Key;
329	#if PGM_GST_MODE != PGM_MODE_AMD64
330	/* skip all stuff above 4GB if not AMD64 mode. */
331	if (GCPtr >= _4GB)
332	return 0;
333	#endif
334
335	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
336	unsigned iPage = 0;
337	while (iPage < pCur->cPages)
338	{
339	#if PGM_GST_TYPE == PGM_TYPE_32BIT
340	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
341	#elif PGM_GST_TYPE == PGM_TYPE_PAE
342	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
343	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
344	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
345	#endif
346	if (Pde.n.u1Present)
347	{
348	if ( !Pde.b.u1Size
349	# if PGM_GST_TYPE != PGM_TYPE_AMD64
350	\|\| !(pState->cr4 & X86_CR4_PSE)
351	# endif
352	)
353	{
354	/*
355	* Normal page table.
356	*/
357	PGSTPT pPT;
358	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
359	if (RT_SUCCESS(rc))
360	{
361	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
362	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
363	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
364	{
365	GSTPTE Pte = pPT->a[iPTE];
366	RTGCPHYS GCPhysNew;
367	if (Pte.n.u1Present)
368	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
369	else
370	GCPhysNew = NIL_RTGCPHYS;
371	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
372	{
373	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
374	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
375	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
376	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
377	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
378	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
379	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
380	#endif
381	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
382	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
383	}
384	}
385	}
386	else
387	{
388	/* not-present. */
389	offPage = 0;
390	AssertRC(rc);
391	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
392	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
393	iPTE++, iPage++, GCPtr += PAGE_SIZE)
394	{
395	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
396	{
397	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
398	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
399	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
400	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
401	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
402	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
403	#endif
404	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
405	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
406	}
407	}
408	}
409	}
410	else
411	{
412	/*
413	* 2/4MB page.
414	*/
415	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
416	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
417	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
418	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
419	{
420	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
421	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
422	{
423	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
424	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
425	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
426	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
427	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
428	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
429	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
430	#endif
431	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
432	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
433	}
434	}
435	} /* pde type */
436	}
437	else
438	{
439	/* not-present. */
440	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
441	cPages && iPage < pCur->cPages;
442	iPage++, GCPtr += PAGE_SIZE)
443	{
444	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
445	{
446	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
447	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
448	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
449	}
450	}
451	offPage = 0;
452	}
453	} /* for pages in virtual mapping. */
454
455	return 0;
456	}
457	#endif /* 32BIT, PAE and AMD64 */
458
459
460	/**
461	* Updates the virtual page access handlers.
462	*
463	* @returns true if bits were flushed.
464	* @returns false if bits weren't flushed.
465	* @param pVM VM handle.
466	* @param pPDSrc The page directory.
467	* @param cr4 The cr4 register value.
468	*/
469	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
470	{
471	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
472	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
473	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
474
475	/** @todo
476	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
477	*/
478
479	/*
480	* Resolve any virtual address based access handlers to GC physical addresses.
481	* This should be fairly quick.
482	*/
483	RTUINT fTodo = 0;
484
485	pgmLock(pVM);
486	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
487
488	for (VMCPUID i = 0; i < pVM->cCpus; i++)
489	{
490	PGMHVUSTATE State;
491	PVMCPU pVCpu = &pVM->aCpus[i];
492
493	State.pVM = pVM;
494	State.pVCpu = pVCpu;
495	State.fTodo = pVCpu->pgm.s.fSyncFlags;
496	State.cr4 = cr4;
497	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
498
499	fTodo \|= State.fTodo;
500	}
501	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
502
503
504	/*
505	* Set / reset bits?
506	*/
507	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
508	{
509	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
510	Log(("HandlerVirtualUpdate: resets bits\n"));
511	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
512
513	for (VMCPUID i = 0; i < pVM->cCpus; i++)
514	{
515	PVMCPU pVCpu = &pVM->aCpus[i];
516	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
517	}
518
519	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
520	}
521	pgmUnlock(pVM);
522
523	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
524
525	#else /* real / protected */
526	return false;
527	#endif
528	}
529

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 24327

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