PGMAllBth.h@ 97441

Last change on this file since 97441 was 97285, checked in by vboxsync, 2 years ago
VMM/PGMAllBth.h: nits. bugref:10092
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1	/* $Id: PGMAllBth.h 97285 2022-10-24 21:59:15Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#ifdef _MSC_VER
36	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
37	* real/prot-guest+RC mode. */
38	# pragma warning(disable: 4505)
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	RT_C_DECLS_BEGIN
46	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
47	#ifndef IN_RING3
48	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken);
49	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
50	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
51	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
52	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
53	unsigned iPte, PCPGMPTWALKGST pGstWalkAll);
54	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
55	uint32_t uErr, PPGMPTWALKGST pGstWalkAll);
56	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll);
57	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
58	#endif
59	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
60	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
61	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
62	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
63	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
64	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
65	#else
66	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
67	#endif
68	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
69	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
70	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
71	#ifdef VBOX_STRICT
72	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
73	#endif
74	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
75	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
76
77	#ifdef IN_RING3
78	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
79	#endif
80	RT_C_DECLS_END
81
82
83
84
85	/*
86	* Filter out some illegal combinations of guest and shadow paging, so we can
87	* remove redundant checks inside functions.
88	*/
89	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
90	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
91	# error "Invalid combination; PAE guest implies PAE shadow"
92	#endif
93
94	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
95	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
96	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
97	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
98	#endif
99
100	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
101	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
102	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
103	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
104	#endif
105
106	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
107	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
108	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
109	#endif
110
111
112	/**
113	* Enters the shadow+guest mode.
114	*
115	* @returns VBox status code.
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param GCPhysCR3 The physical address from the CR3 register.
118	*/
119	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
120	{
121	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
122	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
123	*/
124	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
125	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
126	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
127	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
128	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
129
130	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
131
132	Assert(!pVM->pgm.s.fNestedPaging);
133
134	PGM_LOCK_VOID(pVM);
135	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
136	* but any calls to GC need a proper shadow page setup as well.
137	*/
138	/* Free the previous root mapping if still active. */
139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
140	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
141	if (pOldShwPageCR3)
142	{
143	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
144
145	/* Mark the page as unlocked; allow flushing again. */
146	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
147
148	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
149	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
150	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
151	}
152
153	/* construct a fake address. */
154	GCPhysCR3 = RT_BIT_64(63);
155	PPGMPOOLPAGE pNewShwPageCR3;
156	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
157	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
158	&pNewShwPageCR3);
159	AssertRCReturn(rc, rc);
160
161	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
162	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
163
164	/* Mark the page as locked; disallow flushing. */
165	pgmPoolLockPage(pPool, pNewShwPageCR3);
166
167	/* Set the current hypervisor CR3. */
168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
169
170	PGM_UNLOCK(pVM);
171	return rc;
172	#else
173	NOREF(pVCpu); NOREF(GCPhysCR3);
174	return VINF_SUCCESS;
175	#endif
176	}
177
178
179	#ifndef IN_RING3
180
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	/**
183	* Deal with a guest page fault.
184	*
185	* @returns Strict VBox status code.
186	* @retval VINF_EM_RAW_GUEST_TRAP
187	* @retval VINF_EM_RAW_EMULATE_INSTR
188	*
189	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
190	* @param pWalk The guest page table walk result.
191	* @param uErr The error code.
192	*/
193	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
194	{
195	/*
196	* Calc the error code for the guest trap.
197	*/
198	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
199	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
200	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
201	if ( pWalk->fRsvdError
202	\|\| pWalk->fBadPhysAddr)
203	{
204	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
205	Assert(!pWalk->fNotPresent);
206	}
207	else if (!pWalk->fNotPresent)
208	uNewErr \|= X86_TRAP_PF_P;
209	TRPMSetErrorCode(pVCpu, uNewErr);
210
211	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
212	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
213	return VINF_EM_RAW_GUEST_TRAP;
214	}
215	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
216
217
218	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
219	/**
220	* Deal with a guest page fault.
221	*
222	* The caller has taken the PGM lock.
223	*
224	* @returns Strict VBox status code.
225	*
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param uErr The error code.
228	* @param pCtx Pointer to the register context for the CPU.
229	* @param pvFault The fault address.
230	* @param pPage The guest page at @a pvFault.
231	* @param pWalk The guest page table walk result.
232	* @param pGstWalk The guest paging-mode specific walk information.
233	* @param pfLockTaken PGM lock taken here or not (out). This is true
234	* when we're called.
235	*/
236	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
237	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
238	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
239	, PPGMPTWALK pWalk
240	, PGSTPTWALK pGstWalk
241	# endif
242	)
243	{
244	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
245	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
246	# endif
247	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
248	VBOXSTRICTRC rcStrict;
249
250	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
251	{
252	/*
253	* Physical page access handler.
254	*/
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
257	# else
258	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
259	# endif
260	PPGMPHYSHANDLER pCur;
261	rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysFault, &pCur);
262	if (RT_SUCCESS(rcStrict))
263	{
264	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
265
266	# ifdef PGM_SYNC_N_PAGES
267	/*
268	* If the region is write protected and we got a page not present fault, then sync
269	* the pages. If the fault was caused by a read, then restart the instruction.
270	* In case of write access continue to the GC write handler.
271	*
272	* ASSUMES that there is only one handler per page or that they have similar write properties.
273	*/
274	if ( !(uErr & X86_TRAP_PF_P)
275	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
276	{
277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
278	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
279	# else
280	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
281	# endif
282	if ( RT_FAILURE(rcStrict)
283	\|\| !(uErr & X86_TRAP_PF_RW)
284	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
285	{
286	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
288	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
289	return rcStrict;
290	}
291	}
292	# endif
293	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
294	/*
295	* If the access was not thru a #PF(RSVD\|...) resync the page.
296	*/
297	if ( !(uErr & X86_TRAP_PF_RSVD)
298	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
299	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
300	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
301	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
302	# endif
303	)
304	{
305	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
306	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
307	# else
308	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
309	# endif
310	if ( RT_FAILURE(rcStrict)
311	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
312	{
313	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
314	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
315	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
316	return rcStrict;
317	}
318	}
319	# endif
320
321	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
322	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
323	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
324	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
325	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
326	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
327	else
328	{
329	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
330	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
331	}
332
333	if (pCurType->pfnPfHandler)
334	{
335	STAM_PROFILE_START(&pCur->Stat, h);
336
337	if (pCurType->fKeepPgmLock)
338	{
339	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault,
340	!pCurType->fRing0DevInsIdx ? pCur->uUser
341	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
342
343	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
344	}
345	else
346	{
347	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
348	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
349	PGM_UNLOCK(pVM);
350	*pfLockTaken = false;
351
352	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser);
353
354	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
355	}
356	}
357	else
358	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
359
360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
361	return rcStrict;
362	}
363	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
364	}
365
366	/*
367	* There is a handled area of the page, but this fault doesn't belong to it.
368	* We must emulate the instruction.
369	*
370	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
371	* we first check if this was a page-not-present fault for a page with only
372	* write access handlers. Restart the instruction if it wasn't a write access.
373	*/
374	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
375
376	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
380	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
381	# else
382	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
383	# endif
384	if ( RT_FAILURE(rcStrict)
385	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
386	\|\| !(uErr & X86_TRAP_PF_RW))
387	{
388	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
389	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
390	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
391	return rcStrict;
392	}
393	}
394
395	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
396	* It's writing to an unhandled part of the LDT page several million times.
397	*/
398	rcStrict = PGMInterpretInstruction(pVCpu, pvFault);
399	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
400	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
401	return rcStrict;
402	} /* if any kind of handler */
403	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
404
405
406	/**
407	* \#PF Handler for raw-mode guest execution.
408	*
409	* @returns VBox status code (appropriate for trap handling and GC return).
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param uErr The trap error code.
413	* @param pCtx Pointer to the register context for the CPU.
414	* @param pvFault The fault address.
415	* @param pfLockTaken PGM lock taken here or not (out)
416	*/
417	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)
418	{
419	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
420
421	*pfLockTaken = false;
422
423	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
424	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
425	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
426	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
427	&& PGM_SHW_TYPE != PGM_TYPE_NONE
428	int rc;
429
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	/*
432	* Walk the guest page translation tables and check if it's a guest fault.
433	*/
434	PGMPTWALK Walk;
435	GSTPTWALK GstWalk;
436	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
437	if (RT_FAILURE_NP(rc))
438	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
439
440	/* assert some GstWalk sanity. */
441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
442	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
443	# endif
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
445	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
446	# endif
447	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
448	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
449	Assert(Walk.fSucceeded);
450	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
451
452	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
453	{
454	if ( ( (uErr & X86_TRAP_PF_RW)
455	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
456	&& ( (uErr & X86_TRAP_PF_US)
457	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
458	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
459	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
460	)
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
462	}
463
464	/* Take the big lock now before we update flags. */
465	*pfLockTaken = true;
466	PGM_LOCK_VOID(pVM);
467
468	/*
469	* Set the accessed and dirty flags.
470	*/
471	/** @todo Should probably use cmpxchg logic here as we're potentially racing
472	* other CPUs in SMP configs. (the lock isn't enough, since we take it
473	* after walking and the page tables could be stale already) */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
476	{
477	GstWalk.Pml4e.u \|= X86_PML4E_A;
478	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
479	}
480	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
481	{
482	GstWalk.Pdpe.u \|= X86_PDPE_A;
483	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
484	}
485	# endif
486	if (Walk.fBigPage)
487	{
488	Assert(GstWalk.Pde.u & X86_PDE_PS);
489	if (uErr & X86_TRAP_PF_RW)
490	{
491	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
492	{
493	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
494	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
495	}
496	}
497	else
498	{
499	if (!(GstWalk.Pde.u & X86_PDE4M_A))
500	{
501	GstWalk.Pde.u \|= X86_PDE4M_A;
502	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
503	}
504	}
505	}
506	else
507	{
508	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
509	if (!(GstWalk.Pde.u & X86_PDE_A))
510	{
511	GstWalk.Pde.u \|= X86_PDE_A;
512	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
513	}
514
515	if (uErr & X86_TRAP_PF_RW)
516	{
517	# ifdef VBOX_WITH_STATISTICS
518	if (GstWalk.Pte.u & X86_PTE_D)
519	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
520	else
521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
522	# endif
523	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
524	{
525	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
526	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
527	}
528	}
529	else
530	{
531	if (!(GstWalk.Pte.u & X86_PTE_A))
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
535	}
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	#if 0
540	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	#endif
544
545	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	PGM_LOCK_VOID(pVM);
551	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
554	/*
555	* If it is a reserved bit fault we know that it is an MMIO (access
556	* handler) related fault and can skip some 200 lines of code.
557	*/
558	if (uErr & X86_TRAP_PF_RSVD)
559	{
560	Assert(uErr & X86_TRAP_PF_P);
561	PPGMPAGE pPage;
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage,
566	pfLockTaken, &Walk, &GstWalk));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
568	# else
569	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
570	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
571	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.u & X86_PDE_P);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
665	{
666	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	/*
682	* Check if this fault address is flagged for special treatment,
683	* which means we'll have to figure out the physical address and
684	* check flags associated with it.
685	*
686	* ASSUME that we can limit any special access handling to pages
687	* in page tables which the guest believes to be present.
688	*/
689	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
690	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
691	# else
692	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK);
693	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
694	PPGMPAGE pPage;
695	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
696	if (RT_FAILURE(rc))
697	{
698	/*
699	* When the guest accesses invalid physical memory (e.g. probing
700	* of RAM or accessing a remapped MMIO range), then we'll fall
701	* back to the recompiler to emulate the instruction.
702	*/
703	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
704	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
705	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
706	return VINF_EM_RAW_EMULATE_INSTR;
707	}
708
709	/*
710	* Any handlers for this page?
711	*/
712	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
713	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
714	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken,
715	&Walk, &GstWalk));
716	# else
717	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
718	# endif
719
720	/*
721	* We are here only if page is present in Guest page tables and
722	* trap is not handled by our handlers.
723	*
724	* Check it for page out-of-sync situation.
725	*/
726	if (!(uErr & X86_TRAP_PF_P))
727	{
728	/*
729	* Page is not present in our page tables. Try to sync it!
730	*/
731	if (uErr & X86_TRAP_PF_US)
732	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
733	else /* supervisor */
734	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
735
736	if (PGM_PAGE_IS_BALLOONED(pPage))
737	{
738	/* Emulate reads from ballooned pages as they are not present in
739	our shadow page tables. (Required for e.g. Solaris guests; soft
740	ecc, random nr generator.) */
741	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
742	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
743	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
744	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
745	return rc;
746	}
747
748	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
749	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
750	# else
751	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
752	# endif
753	if (RT_SUCCESS(rc))
754	{
755	/* The page was successfully synced, return to the guest. */
756	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
757	return VINF_SUCCESS;
758	}
759	}
760	else /* uErr & X86_TRAP_PF_P: */
761	{
762	/*
763	* Write protected pages are made writable when the guest makes the
764	* first write to it. This happens for pages that are shared, write
765	* monitored or not yet allocated.
766	*
767	* We may also end up here when CR0.WP=0 in the guest.
768	*
769	* Also, a side effect of not flushing global PDEs are out of sync
770	* pages due to physical monitored regions, that are no longer valid.
771	* Assume for now it only applies to the read/write flag.
772	*/
773	if (uErr & X86_TRAP_PF_RW)
774	{
775	/*
776	* Check if it is a read-only page.
777	*/
778	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
779	{
780	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
781	Assert(!PGM_PAGE_IS_ZERO(pPage));
782	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
783	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
784
785	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
786	if (rc != VINF_SUCCESS)
787	{
788	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
789	return rc;
790	}
791	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
792	return VINF_EM_NO_MEMORY;
793	}
794
795	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
796	/*
797	* Check to see if we need to emulate the instruction if CR0.WP=0.
798	*/
799	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
800	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
801	&& CPUMGetGuestCPL(pVCpu) < 3)
802	{
803	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
804
805	/*
806	* The Netware WP0+RO+US hack.
807	*
808	* Netware sometimes(/always?) runs with WP0. It has been observed doing
809	* excessive write accesses to pages which are mapped with US=1 and RW=0
810	* while WP=0. This causes a lot of exits and extremely slow execution.
811	* To avoid trapping and emulating every write here, we change the shadow
812	* page table entry to map it as US=0 and RW=1 until user mode tries to
813	* access it again (see further below). We count these shadow page table
814	* changes so we can avoid having to clear the page pool every time the WP
815	* bit changes to 1 (see PGMCr0WpEnabled()).
816	*/
817	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
818	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
819	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
820	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
821	{
822	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
823	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
824	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
825	{
826	PGM_INVL_PG(pVCpu, pvFault);
827	pVCpu->pgm.s.cNetwareWp0Hacks++;
828	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
829	return rc;
830	}
831	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
832	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
833	}
834	# endif
835
836	/* Interpret the access. */
837	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
838	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
839	if (RT_SUCCESS(rc))
840	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
841	else
842	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
843	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
844	return rc;
845	}
846	# endif
847	/// @todo count the above case; else
848	if (uErr & X86_TRAP_PF_US)
849	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
850	else /* supervisor */
851	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
852
853	/*
854	* Sync the page.
855	*
856	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
857	* page is not present, which is not true in this case.
858	*/
859	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
860	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
861	# else
862	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
863	# endif
864	if (RT_SUCCESS(rc))
865	{
866	/*
867	* Page was successfully synced, return to guest but invalidate
868	* the TLB first as the page is very likely to be in it.
869	*/
870	# if PGM_SHW_TYPE == PGM_TYPE_EPT
871	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
872	# else
873	PGM_INVL_PG(pVCpu, pvFault);
874	# endif
875	# ifdef VBOX_STRICT
876	PGMPTWALK GstPageWalk;
877	GstPageWalk.GCPhys = RTGCPHYS_MAX;
878	if (!pVM->pgm.s.fNestedPaging)
879	{
880	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
881	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
882	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
883	}
884	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
885	uint64_t fPageShw = 0;
886	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
887	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
888	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
889	# endif
890	# endif /* VBOX_STRICT */
891	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
892	return VINF_SUCCESS;
893	}
894	}
895	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
896	/*
897	* Check for Netware WP0+RO+US hack from above and undo it when user
898	* mode accesses the page again.
899	*/
900	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
901	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
902	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
903	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
904	&& CPUMGetGuestCPL(pVCpu) == 3
905	&& pVM->cCpus == 1
906	)
907	{
908	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
909	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
910	if (RT_SUCCESS(rc))
911	{
912	PGM_INVL_PG(pVCpu, pvFault);
913	pVCpu->pgm.s.cNetwareWp0Hacks--;
914	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
915	return VINF_SUCCESS;
916	}
917	}
918	# endif /* PGM_WITH_PAGING */
919
920	/** @todo else: why are we here? */
921
922	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
923	/*
924	* Check for VMM page flags vs. Guest page flags consistency.
925	* Currently only for debug purposes.
926	*/
927	if (RT_SUCCESS(rc))
928	{
929	/* Get guest page flags. */
930	PGMPTWALK GstPageWalk;
931	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
932	if (RT_SUCCESS(rc2))
933	{
934	uint64_t fPageShw = 0;
935	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
936
937	#if 0
938	/*
939	* Compare page flags.
940	* Note: we have AVL, A, D bits desynced.
941	*/
942	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
943	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
944	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
945	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
946	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
947	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
948	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
949	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
950	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
951	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
952	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
953
954	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
955	01:01:15.625516 00:08:43.268051 Location :
956	e:\vbox\svn\trunk\srcPage flags mismatch!
957	pvFault=fffff801b0d7b000
958	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
959	GCPhys=0000000019b52000
960	fPageShw=0
961	fPageGst=77b0000000000121
962	rc=0
963	#endif
964
965	}
966	else
967	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
968	}
969	else
970	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
971	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
972	}
973
974
975	/*
976	* If we get here it is because something failed above, i.e. most like guru
977	* meditiation time.
978	*/
979	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
980	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip));
981	return rc;
982
983	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
984	NOREF(uErr); NOREF(pCtx); NOREF(pvFault);
985	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
986	return VERR_PGM_NOT_USED_IN_MODE;
987	# endif
988	}
989
990
991	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
992	/**
993	* Deals with a nested-guest \#PF fault for a guest-physical page with a handler.
994	*
995	* @returns Strict VBox status code.
996	* @param pVCpu The cross context virtual CPU structure.
997	* @param uErr The error code.
998	* @param pCtx Pointer to the register context for the CPU.
999	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1000	* @param pPage The guest page at @a GCPhysNestedFault.
1001	* @param GCPhysFault The guest-physical address of the fault.
1002	* @param pGstWalkAll The guest page walk result.
1003	* @param pfLockTaken Where to store whether the PGM is still held when
1004	* this function completes.
1005	*
1006	* @note The caller has taken the PGM lock.
1007	*/
1008	static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
1009	RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
1010	RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
1011	bool *pfLockTaken)
1012	{
1013	# if PGM_GST_TYPE == PGM_TYPE_PROT \
1014	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1015
1016	/** @todo Assert uErr isn't X86_TRAP_PF_RSVD and remove release checks. */
1017	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysFault);
1018	AssertMsgReturn(PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage), ("%RGp %RGp uErr=%u\n", GCPhysNestedFault, GCPhysFault, uErr),
1019	VERR_PGM_HANDLER_IPE_1);
1020
1021	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1022	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1023	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1024
1025	/*
1026	* Physical page access handler.
1027	*/
1028	PPGMPHYSHANDLER pCur;
1029	VBOXSTRICTRC rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysPage, &pCur);
1030	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
1031
1032	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
1033	Assert(pCurType);
1034
1035	/*
1036	* If the region is write protected and we got a page not present fault, then sync
1037	* the pages. If the fault was caused by a read, then restart the instruction.
1038	* In case of write access continue to the GC write handler.
1039	*/
1040	if ( !(uErr & X86_TRAP_PF_P)
1041	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1042	{
1043	Log7Func(("Syncing Monitored: GCPhysNestedPage=%RGp GCPhysPage=%RGp uErr=%#x\n", GCPhysNestedPage, GCPhysPage, uErr));
1044	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1045	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1046	if ( RT_FAILURE(rcStrict)
1047	\|\| !(uErr & X86_TRAP_PF_RW))
1048	{
1049	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1051	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1052	return rcStrict;
1053	}
1054	}
1055	else if ( !(uErr & X86_TRAP_PF_RSVD)
1056	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE)
1057	{
1058	/*
1059	* If the access was NOT through an EPT misconfig (i.e. RSVD), sync the page.
1060	* This can happen for the VMX APIC-access page.
1061	*/
1062	Log7Func(("Syncing MMIO: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1063	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1064	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1065	if (RT_FAILURE(rcStrict))
1066	{
1067	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1068	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1069	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1070	return rcStrict;
1071	}
1072	}
1073
1074	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
1075	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
1076	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
1077	GCPhysNestedFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
1078	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1079	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
1080	else
1081	{
1082	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
1083	if (uErr & X86_TRAP_PF_RSVD)
1084	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
1085	}
1086
1087	if (pCurType->pfnPfHandler)
1088	{
1089	STAM_PROFILE_START(&pCur->Stat, h);
1090	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
1091	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
1092
1093	if (pCurType->fKeepPgmLock)
1094	{
1095	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1096	STAM_PROFILE_STOP(&pCur->Stat, h);
1097	}
1098	else
1099	{
1100	PGM_UNLOCK(pVM);
1101	*pfLockTaken = false;
1102	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1103	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
1104	}
1105	}
1106	else
1107	{
1108	AssertMsgFailed(("What's going on here!? Fault falls outside handler range!?\n"));
1109	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
1110	}
1111
1112	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
1113	return rcStrict;
1114
1115	# else
1116	RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
1117	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1118	return VERR_PGM_NOT_USED_IN_MODE;
1119	# endif
1120	}
1121	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1122
1123
1124	/**
1125	* Nested \#PF handler for nested-guest hardware-assisted execution using nested
1126	* paging.
1127	*
1128	* @returns VBox status code (appropriate for trap handling and GC return).
1129	* @param pVCpu The cross context virtual CPU structure.
1130	* @param uErr The fault error (X86_TRAP_PF_*).
1131	* @param pCtx Pointer to the register context for the CPU.
1132	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1133	* @param fIsLinearAddrValid Whether translation of a nested-guest linear address
1134	* caused this fault. If @c false, GCPtrNestedFault
1135	* must be 0.
1136	* @param GCPtrNestedFault The nested-guest linear address of this fault.
1137	* @param pWalk The guest page table walk result.
1138	* @param pfLockTaken Where to store whether the PGM lock is still held
1139	* when this function completes.
1140	*/
1141	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1142	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
1143	{
1144	*pfLockTaken = false;
1145	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \
1146	&& PGM_GST_TYPE == PGM_TYPE_PROT \
1147	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1148
1149	Assert(CPUMIsGuestVmxEptPagingEnabled(pVCpu));
1150	Assert(PGM_A20_IS_ENABLED(pVCpu));
1151
1152	/* We don't support mode-based execute control for EPT yet. */
1153	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
1154	Assert(!(uErr & X86_TRAP_PF_US));
1155
1156	/* Take the big lock now. */
1157	*pfLockTaken = true;
1158	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1159	PGM_LOCK_VOID(pVM);
1160
1161	/*
1162	* Walk the guest EPT tables and check if it's an EPT violation or misconfiguration.
1163	*/
1164	if (fIsLinearAddrValid)
1165	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n",
1166	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
1167	else
1168	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n",
1169	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr));
1170	PGMPTWALKGST GstWalkAll;
1171	int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
1172	if (RT_FAILURE(rc))
1173	return rc;
1174
1175	Assert(GstWalkAll.enmType == PGMPTWALKGSTTYPE_EPT);
1176	Assert(pWalk->fSucceeded);
1177	Assert(pWalk->fEffective & (PGM_PTATTRS_EPT_R_MASK \| PGM_PTATTRS_EPT_W_MASK \| PGM_PTATTRS_EPT_X_SUPER_MASK));
1178	Assert(pWalk->fIsSlat);
1179
1180	# ifdef DEBUG_ramshankar
1181	/* Paranoia. */
1182	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_R_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_R_MASK));
1183	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_W_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_W_MASK));
1184	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_NX_MASK) == !RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_X_SUPER_MASK));
1185	# endif
1186
1187	/*
1188	* Check page-access permissions.
1189	*/
1190	if ( ((uErr & X86_TRAP_PF_RW) && !(pWalk->fEffective & PGM_PTATTRS_W_MASK))
1191	\|\| ((uErr & X86_TRAP_PF_ID) && (pWalk->fEffective & PGM_PTATTRS_NX_MASK)))
1192	{
1193	Log7Func(("Permission failed! GCPtrNested=%RGv GCPhysNested=%RGp uErr=%#x fEffective=%#RX64\n", GCPtrNestedFault,
1194	GCPhysNestedFault, uErr, pWalk->fEffective));
1195	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
1196	return VERR_ACCESS_DENIED;
1197	}
1198
1199	PGM_A20_ASSERT_MASKED(pVCpu, pWalk->GCPhys);
1200	RTGCPHYS const GCPhysPage = pWalk->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1201	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1202
1203	/*
1204	* If we were called via an EPT misconfig, it should've already resulted in a nested-guest VM-exit.
1205	*/
1206	AssertMsgReturn(!(uErr & X86_TRAP_PF_RSVD),
1207	("Unexpected EPT misconfig VM-exit. GCPhysPage=%RGp GCPhysNestedPage=%RGp\n", GCPhysPage, GCPhysNestedPage),
1208	VERR_PGM_MAPPING_IPE);
1209
1210	/*
1211	* Fetch and sync the nested-guest EPT page directory pointer.
1212	*/
1213	PEPTPD pEptPd;
1214	rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL /ppPdpt/, &pEptPd, &GstWalkAll);
1215	AssertRCReturn(rc, rc);
1216	Assert(pEptPd);
1217
1218	/*
1219	* A common case is the not-present error caused by lazy page table syncing.
1220	*
1221	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
1222	* here so we can safely assume that the shadow PT is present when calling
1223	* NestedSyncPage later.
1224	*
1225	* NOTE: It's possible we will be syncing the VMX APIC-access page here.
1226	* In that case, we would sync the page but will NOT go ahead with emulating
1227	* the APIC-access VM-exit through IEM. However, once the page is mapped in
1228	* the shadow tables, subsequent APIC-access VM-exits for the nested-guest
1229	* will be triggered by hardware. Maybe calling the IEM #PF handler can be
1230	* considered as an optimization later.
1231	*/
1232	unsigned const iPde = (GCPhysNestedPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1233	if ( !(uErr & X86_TRAP_PF_P)
1234	&& !(pEptPd->a[iPde].u & EPT_PRESENT_MASK))
1235	{
1236	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
1237	Log7Func(("NestedSyncPT: Lazy. GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1238	rc = PGM_BTH_NAME(NestedSyncPT)(pVCpu, GCPhysNestedPage, GCPhysPage, &GstWalkAll);
1239	if (RT_SUCCESS(rc))
1240	return rc;
1241	AssertMsgFailedReturn(("NestedSyncPT: %RGv failed! rc=%Rrc\n", GCPhysNestedPage, rc), VERR_PGM_MAPPING_IPE);
1242	}
1243
1244	/*
1245	* Check if this fault address is flagged for special treatment.
1246	* This handles faults on an MMIO or write-monitored page.
1247	*
1248	* If this happens to be the VMX APIC-access page, we don't treat is as MMIO
1249	* but rather sync it further below (as a regular guest page) which lets
1250	* hardware-assisted execution trigger the APIC-access VM-exits of the
1251	* nested-guest directly.
1252	*/
1253	PPGMPAGE pPage;
1254	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1255	AssertRCReturn(rc, rc);
1256	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1257	{
1258	Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
1259	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault,
1260	pPage, pWalk->GCPhys, &GstWalkAll,
1261	pfLockTaken));
1262	}
1263
1264	/*
1265	* We are here only if page is present in nested-guest page tables but the
1266	* trap is not handled by our handlers. Check for page out-of-sync situation.
1267	*/
1268	if (!(uErr & X86_TRAP_PF_P))
1269	{
1270	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
1271	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1272	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
1273
1274	Log7Func(("SyncPage: Not-Present: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedFault, GCPhysPage));
1275	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, PGM_SYNC_NR_PAGES, uErr, &GstWalkAll);
1276	if (RT_SUCCESS(rc))
1277	{
1278	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
1279	return VINF_SUCCESS;
1280	}
1281	}
1282	else if (uErr & X86_TRAP_PF_RW)
1283	{
1284	/*
1285	* Write protected pages are made writable when the guest makes the
1286	* first write to it. This happens for pages that are shared, write
1287	* monitored or not yet allocated.
1288	*
1289	* We may also end up here when CR0.WP=0 in the guest.
1290	*
1291	* Also, a side effect of not flushing global PDEs are out of sync
1292	* pages due to physical monitored regions, that are no longer valid.
1293	* Assume for now it only applies to the read/write flag.
1294	*/
1295	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1296	{
1297	/* This is a read-only page. */
1298	AssertMsgFailed(("Failed\n"));
1299
1300	Assert(!PGM_PAGE_IS_ZERO(pPage));
1301	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhysPage));
1302	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
1303
1304	Log7Func(("Calling pgmPhysPageMakeWritable for GCPhysPage=%RGp\n", GCPhysPage));
1305	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1306	if (rc != VINF_SUCCESS)
1307	{
1308	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1309	return rc;
1310	}
1311	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
1312	return VINF_EM_NO_MEMORY;
1313	}
1314
1315	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1316	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1317
1318	/*
1319	* Sync the write-protected page.
1320	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1321	* page is not present, which is not true in this case.
1322	*/
1323	Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
1324	pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
1325	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
1326	if (RT_SUCCESS(rc))
1327	{
1328	HMInvalidatePhysPage(pVM, GCPhysPage);
1329	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
1330	return VINF_SUCCESS;
1331	}
1332	}
1333
1334	/*
1335	* If we get here it is because something failed above => guru meditation time.
1336	*/
1337	LogRelFunc(("rc=%Rrc GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n", rc, GCPhysNestedFault, GCPhysPage,
1338	(uint32_t)uErr, pCtx->cs.Sel, pCtx->rip));
1339	return VERR_PGM_MAPPING_IPE;
1340
1341	# else /* !VBOX_WITH_NESTED_HWVIRT_VMX_EPT \|\| PGM_GST_TYPE != PGM_TYPE_PROT \|\| PGM_SHW_TYPE != PGM_TYPE_EPT */
1342	RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
1343	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1344	return VERR_PGM_NOT_USED_IN_MODE;
1345	# endif
1346	}
1347
1348	#endif /* !IN_RING3 */
1349
1350
1351	/**
1352	* Emulation of the invlpg instruction.
1353	*
1354	*
1355	* @returns VBox status code.
1356	*
1357	* @param pVCpu The cross context virtual CPU structure.
1358	* @param GCPtrPage Page to invalidate.
1359	*
1360	* @remark ASSUMES that the guest is updating before invalidating. This order
1361	* isn't required by the CPU, so this is speculative and could cause
1362	* trouble.
1363	* @remark No TLB shootdown is done on any other VCPU as we assume that
1364	* invlpg emulation is the only reason for calling this function.
1365	* (The guest has to shoot down TLB entries on other CPUs itself)
1366	* Currently true, but keep in mind!
1367	*
1368	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1369	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1370	*/
1371	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1372	{
1373	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1374	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1375	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1376	int rc;
1377	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1378	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1379
1380	PGM_LOCK_ASSERT_OWNER(pVM);
1381
1382	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1383
1384	/*
1385	* Get the shadow PD entry and skip out if this PD isn't present.
1386	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1387	*/
1388	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1389	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1390	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1391
1392	/* Fetch the pgm pool shadow descriptor. */
1393	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1394	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1395	if (!pShwPde)
1396	{
1397	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1398	return VINF_SUCCESS;
1399	}
1400	# else
1401	Assert(pShwPde);
1402	# endif
1403
1404	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1405	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1406	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1407
1408	/* If the shadow PDPE isn't present, then skip the invalidate. */
1409	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1410	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1411	# else
1412	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1413	# endif
1414	{
1415	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1416	PGM_INVL_PG(pVCpu, GCPtrPage);
1417	return VINF_SUCCESS;
1418	}
1419
1420	/* Fetch the pgm pool shadow descriptor. */
1421	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1422	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1423
1424	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1425	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1426	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1427
1428	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1429	/* PML4 */
1430	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1431	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1432	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1433	PX86PDPAE pPDDst;
1434	PX86PDPT pPdptDst;
1435	PX86PML4E pPml4eDst;
1436	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1437	if (rc != VINF_SUCCESS)
1438	{
1439	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1440	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1441	PGM_INVL_PG(pVCpu, GCPtrPage);
1442	return VINF_SUCCESS;
1443	}
1444	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1445	Assert(pPDDst);
1446	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1447
1448	/* Fetch the pgm pool shadow descriptor. */
1449	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1450	Assert(pShwPde);
1451
1452	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1453
1454	const SHWPDE PdeDst = *pPdeDst;
1455	if (!(PdeDst.u & X86_PDE_P))
1456	{
1457	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1458	PGM_INVL_PG(pVCpu, GCPtrPage);
1459	return VINF_SUCCESS;
1460	}
1461
1462	/*
1463	* Get the guest PD entry and calc big page.
1464	*/
1465	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1466	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1467	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1468	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1469	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1470	unsigned iPDSrc = 0;
1471	# if PGM_GST_TYPE == PGM_TYPE_PAE
1472	X86PDPE PdpeSrcIgn;
1473	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1474	# else /* AMD64 */
1475	PX86PML4E pPml4eSrcIgn;
1476	X86PDPE PdpeSrcIgn;
1477	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1478	# endif
1479	GSTPDE PdeSrc;
1480
1481	if (pPDSrc)
1482	PdeSrc = pPDSrc->a[iPDSrc];
1483	else
1484	PdeSrc.u = 0;
1485	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1486	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1487	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1488	if (fWasBigPage != fIsBigPage)
1489	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1490
1491	# ifdef IN_RING3
1492	/*
1493	* If a CR3 Sync is pending we may ignore the invalidate page operation
1494	* depending on the kind of sync and if it's a global page or not.
1495	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1496	*/
1497	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1498	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1499	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1500	&& fIsBigPage
1501	&& (PdeSrc.u & X86_PDE4M_G)
1502	)
1503	)
1504	# else
1505	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1506	# endif
1507	{
1508	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1509	return VINF_SUCCESS;
1510	}
1511	# endif /* IN_RING3 */
1512
1513	/*
1514	* Deal with the Guest PDE.
1515	*/
1516	rc = VINF_SUCCESS;
1517	if (PdeSrc.u & X86_PDE_P)
1518	{
1519	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1520	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1521	if (!fIsBigPage)
1522	{
1523	/*
1524	* 4KB - page.
1525	*/
1526	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1527	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1528
1529	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1530	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1531	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
1532	# endif
1533	if (pShwPage->GCPhys == GCPhys)
1534	{
1535	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1536	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1537
1538	PGSTPT pPTSrc;
1539	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1540	if (RT_SUCCESS(rc))
1541	{
1542	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1543	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1544	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1545	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1546	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1547	GCPtrPage, PteSrc.u & X86_PTE_P,
1548	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1549	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1550	(uint64_t)PteSrc.u,
1551	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1552	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1553	}
1554	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1555	PGM_INVL_PG(pVCpu, GCPtrPage);
1556	}
1557	else
1558	{
1559	/*
1560	* The page table address changed.
1561	*/
1562	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1563	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1564	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1565	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1566	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1567	PGM_INVL_VCPU_TLBS(pVCpu);
1568	}
1569	}
1570	else
1571	{
1572	/*
1573	* 2/4MB - page.
1574	*/
1575	/* Before freeing the page, check if anything really changed. */
1576	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1577	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1578	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1579	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1580	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1581	# endif
1582	if ( pShwPage->GCPhys == GCPhys
1583	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1584	{
1585	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1586	/** @todo This test is wrong as it cannot check the G bit!
1587	* FIXME */
1588	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1589	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1590	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1591	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1592	{
1593	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1594	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1595	return VINF_SUCCESS;
1596	}
1597	}
1598
1599	/*
1600	* Ok, the page table is present and it's been changed in the guest.
1601	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1602	* We could do this for some flushes in GC too, but we need an algorithm for
1603	* deciding which 4MB pages containing code likely to be executed very soon.
1604	*/
1605	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1606	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1607	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1608	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1609	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1610	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1611	}
1612	}
1613	else
1614	{
1615	/*
1616	* Page directory is not present, mark shadow PDE not present.
1617	*/
1618	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1619	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1620	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1621	PGM_INVL_PG(pVCpu, GCPtrPage);
1622	}
1623	return rc;
1624
1625	#else /* guest real and protected mode, nested + ept, none. */
1626	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1627	NOREF(pVCpu); NOREF(GCPtrPage);
1628	return VINF_SUCCESS;
1629	#endif
1630	}
1631
1632	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1633
1634	/**
1635	* Update the tracking of shadowed pages.
1636	*
1637	* @param pVCpu The cross context virtual CPU structure.
1638	* @param pShwPage The shadow page.
1639	* @param HCPhys The physical page we is being dereferenced.
1640	* @param iPte Shadow PTE index
1641	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1642	*/
1643	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1644	RTGCPHYS GCPhysPage)
1645	{
1646	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1647
1648	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1649	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1650	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1651
1652	/* Use the hint we retrieved from the cached guest PT. */
1653	if (pShwPage->fDirty)
1654	{
1655	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1656
1657	Assert(pShwPage->cPresent);
1658	Assert(pPool->cPresent);
1659	pShwPage->cPresent--;
1660	pPool->cPresent--;
1661
1662	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1663	AssertRelease(pPhysPage);
1664	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1665	return;
1666	}
1667	# else
1668	NOREF(GCPhysPage);
1669	# endif
1670
1671	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1672	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1673
1674	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1675	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1676	* 2. write protect all shadowed pages. I.e. implement caching.
1677	*/
1678	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1679
1680	/*
1681	* Find the guest address.
1682	*/
1683	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1684	pRam;
1685	pRam = pRam->CTX_SUFF(pNext))
1686	{
1687	unsigned iPage = pRam->cb >> GUEST_PAGE_SHIFT;
1688	while (iPage-- > 0)
1689	{
1690	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1691	{
1692	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1693
1694	Assert(pShwPage->cPresent);
1695	Assert(pPool->cPresent);
1696	pShwPage->cPresent--;
1697	pPool->cPresent--;
1698
1699	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1700	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1701	return;
1702	}
1703	}
1704	}
1705
1706	for (;;)
1707	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1708	}
1709
1710
1711	/**
1712	* Update the tracking of shadowed pages.
1713	*
1714	* @param pVCpu The cross context virtual CPU structure.
1715	* @param pShwPage The shadow page.
1716	* @param u16 The top 16-bit of the pPage->HCPhys.
1717	* @param pPage Pointer to the guest page. this will be modified.
1718	* @param iPTDst The index into the shadow table.
1719	*/
1720	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1721	PPGMPAGE pPage, const unsigned iPTDst)
1722	{
1723	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1724
1725	/*
1726	* Just deal with the simple first time here.
1727	*/
1728	if (!u16)
1729	{
1730	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1731	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1732	/* Save the page table index. */
1733	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1734	}
1735	else
1736	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1737
1738	/* write back */
1739	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1740	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1741
1742	/* update statistics. */
1743	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1744	pShwPage->cPresent++;
1745	if (pShwPage->iFirstPresent > iPTDst)
1746	pShwPage->iFirstPresent = iPTDst;
1747	}
1748
1749
1750	/**
1751	* Modifies a shadow PTE to account for access handlers.
1752	*
1753	* @param pVM The cross context VM structure.
1754	* @param pVCpu The cross context virtual CPU structure.
1755	* @param pPage The page in question.
1756	* @param GCPhysPage The guest-physical address of the page.
1757	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1758	* A (accessed) bit so it can be emulated correctly.
1759	* @param pPteDst The shadow PTE (output). This is temporary storage and
1760	* does not need to be set atomically.
1761	*/
1762	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PVMCPUCC pVCpu, PCPGMPAGE pPage, RTGCPHYS GCPhysPage, uint64_t fPteSrc,
1763	PSHWPTE pPteDst)
1764	{
1765	RT_NOREF_PV(pVM); RT_NOREF_PV(fPteSrc); RT_NOREF_PV(pVCpu); RT_NOREF_PV(GCPhysPage);
1766
1767	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1768	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1769	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1770	{
1771	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1772	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1773	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1774	# else
1775	if (fPteSrc & X86_PTE_A)
1776	{
1777	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1778	SHW_PTE_SET_RO(*pPteDst);
1779	}
1780	else
1781	SHW_PTE_SET(*pPteDst, 0);
1782	# endif
1783	}
1784	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1785	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1786	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1787	&& ( BTH_IS_NP_ACTIVE(pVM)
1788	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1789	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1790	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1791	# endif
1792	)
1793	{
1794	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1795	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1796	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1797	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1798	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1799	\| EPT_E_WRITE
1800	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1801	\| EPT_E_MEMTYPE_INVALID_3;
1802	# else
1803	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1804	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1805	# endif
1806	}
1807	# endif
1808	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1809	else
1810	{
1811	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1812	SHW_PTE_SET(*pPteDst, 0);
1813	}
1814	/** @todo count these kinds of entries. */
1815	}
1816
1817
1818	/**
1819	* Creates a 4K shadow page for a guest page.
1820	*
1821	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1822	* physical address. The PdeSrc argument only the flags are used. No page
1823	* structured will be mapped in this function.
1824	*
1825	* @param pVCpu The cross context virtual CPU structure.
1826	* @param pPteDst Destination page table entry.
1827	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1828	* Can safely assume that only the flags are being used.
1829	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1830	* @param pShwPage Pointer to the shadow page.
1831	* @param iPTDst The index into the shadow table.
1832	*
1833	* @remark Not used for 2/4MB pages!
1834	*/
1835	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1836	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1837	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1838	# else
1839	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1840	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1841	# endif
1842	{
1843	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1844	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1845
1846	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1847	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1848	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1849
1850	if (pShwPage->fDirty)
1851	{
1852	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1853	PGSTPT pGstPT;
1854
1855	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1856	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1857	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1858	pGstPT->a[iPTDst].u = PteSrc.u;
1859	}
1860	# else
1861	Assert(!pShwPage->fDirty);
1862	# endif
1863
1864	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1865	if ( (PteSrc.u & X86_PTE_P)
1866	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1867	# endif
1868	{
1869	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1870	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1871	# endif
1872	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1873
1874	/*
1875	* Find the ram range.
1876	*/
1877	PPGMPAGE pPage;
1878	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1879	if (RT_SUCCESS(rc))
1880	{
1881	/* Ignore ballooned pages.
1882	Don't return errors or use a fatal assert here as part of a
1883	shadow sync range might included ballooned pages. */
1884	if (PGM_PAGE_IS_BALLOONED(pPage))
1885	{
1886	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1887	return;
1888	}
1889
1890	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1891	/* Make the page writable if necessary. */
1892	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1893	&& ( PGM_PAGE_IS_ZERO(pPage)
1894	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1895	\|\| ( (PteSrc.u & X86_PTE_RW)
1896	# else
1897	\|\| ( 1
1898	# endif
1899	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1900	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1901	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1902	# endif
1903	# ifdef VBOX_WITH_PAGE_SHARING
1904	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1905	# endif
1906	)
1907	)
1908	)
1909	{
1910	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1911	AssertRC(rc);
1912	}
1913	# endif
1914
1915	/*
1916	* Make page table entry.
1917	*/
1918	SHWPTE PteDst;
1919	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1920	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1921	# else
1922	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1923	# endif
1924	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1925	{
1926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1927	/*
1928	* If the page or page directory entry is not marked accessed,
1929	* we mark the page not present.
1930	*/
1931	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1932	{
1933	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1934	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1935	SHW_PTE_SET(PteDst, 0);
1936	}
1937	/*
1938	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1939	* when the page is modified.
1940	*/
1941	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
1942	{
1943	AssertCompile(X86_PTE_RW == X86_PDE_RW);
1944	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
1945	SHW_PTE_SET(PteDst,
1946	fGstShwPteFlags
1947	\| PGM_PAGE_GET_HCPHYS(pPage)
1948	\| PGM_PTFLAGS_TRACK_DIRTY);
1949	SHW_PTE_SET_RO(PteDst);
1950	}
1951	else
1952	# endif
1953	{
1954	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
1955	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1956	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
1957	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1958	# else
1959	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1960	# endif
1961	}
1962
1963	/*
1964	* Make sure only allocated pages are mapped writable.
1965	*/
1966	if ( SHW_PTE_IS_P_RW(PteDst)
1967	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1968	{
1969	/* Still applies to shared pages. */
1970	Assert(!PGM_PAGE_IS_ZERO(pPage));
1971	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1972	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1973	}
1974	}
1975	else
1976	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhysPage, fGstShwPteFlags, &PteDst);
1977
1978	/*
1979	* Keep user track up to date.
1980	*/
1981	if (SHW_PTE_IS_P(PteDst))
1982	{
1983	if (!SHW_PTE_IS_P(*pPteDst))
1984	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1985	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1986	{
1987	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1988	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1989	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1990	}
1991	}
1992	else if (SHW_PTE_IS_P(*pPteDst))
1993	{
1994	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1995	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1996	}
1997
1998	/*
1999	* Update statistics and commit the entry.
2000	*/
2001	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2002	if (!(PteSrc.u & X86_PTE_G))
2003	pShwPage->fSeenNonGlobal = true;
2004	# endif
2005	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2006	return;
2007	}
2008
2009	/** @todo count these three different kinds. */
2010	Log2(("SyncPageWorker: invalid address in Pte\n"));
2011	}
2012	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2013	else if (!(PteSrc.u & X86_PTE_P))
2014	Log2(("SyncPageWorker: page not present in Pte\n"));
2015	else
2016	Log2(("SyncPageWorker: invalid Pte\n"));
2017	# endif
2018
2019	/*
2020	* The page is not present or the PTE is bad. Replace the shadow PTE by
2021	* an empty entry, making sure to keep the user tracking up to date.
2022	*/
2023	if (SHW_PTE_IS_P(*pPteDst))
2024	{
2025	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2026	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2027	}
2028	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
2029	}
2030
2031
2032	/**
2033	* Syncs a guest OS page.
2034	*
2035	* There are no conflicts at this point, neither is there any need for
2036	* page table allocations.
2037	*
2038	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
2039	* When called in AMD64 guest mode, the guest PML4E shall be valid.
2040	*
2041	* @returns VBox status code.
2042	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
2043	* @param pVCpu The cross context virtual CPU structure.
2044	* @param PdeSrc Page directory entry of the guest.
2045	* @param GCPtrPage Guest context page address.
2046	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2047	* @param uErr Fault error (X86_TRAP_PF_*).
2048	*/
2049	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
2050	{
2051	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2052	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2053	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
2054	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
2055
2056	PGM_LOCK_ASSERT_OWNER(pVM);
2057
2058	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2059	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2060	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2061	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
2062
2063	/*
2064	* Assert preconditions.
2065	*/
2066	Assert(PdeSrc.u & X86_PDE_P);
2067	Assert(cPages);
2068	# if 0 /* rarely useful; leave for debugging. */
2069	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
2070	# endif
2071
2072	/*
2073	* Get the shadow PDE, find the shadow page table in the pool.
2074	*/
2075	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2076	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2077	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2078
2079	/* Fetch the pgm pool shadow descriptor. */
2080	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2081	Assert(pShwPde);
2082
2083	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2084	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2085	PPGMPOOLPAGE pShwPde = NULL;
2086	PX86PDPAE pPDDst;
2087
2088	/* Fetch the pgm pool shadow descriptor. */
2089	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2090	AssertRCSuccessReturn(rc2, rc2);
2091	Assert(pShwPde);
2092
2093	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2094	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2095
2096	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2097	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2098	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2099	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2100	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2101
2102	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2103	AssertRCSuccessReturn(rc2, rc2);
2104	Assert(pPDDst && pPdptDst);
2105	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2106	# endif
2107	SHWPDE PdeDst = *pPdeDst;
2108
2109	/*
2110	* - In the guest SMP case we could have blocked while another VCPU reused
2111	* this page table.
2112	* - With W7-64 we may also take this path when the A bit is cleared on
2113	* higher level tables (PDPE/PML4E). The guest does not invalidate the
2114	* relevant TLB entries. If we're write monitoring any page mapped by
2115	* the modified entry, we may end up here with a "stale" TLB entry.
2116	*/
2117	if (!(PdeDst.u & X86_PDE_P))
2118	{
2119	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2120	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
2121	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2122	if (uErr & X86_TRAP_PF_P)
2123	PGM_INVL_PG(pVCpu, GCPtrPage);
2124	return VINF_SUCCESS; /* force the instruction to be executed again. */
2125	}
2126
2127	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2128	Assert(pShwPage);
2129
2130	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2131	/* Fetch the pgm pool shadow descriptor. */
2132	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2133	Assert(pShwPde);
2134	# endif
2135
2136	/*
2137	* Check that the page is present and that the shadow PDE isn't out of sync.
2138	*/
2139	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
2140	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2141	RTGCPHYS GCPhys;
2142	if (!fBigPage)
2143	{
2144	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2145	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2146	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2147	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
2148	# endif
2149	}
2150	else
2151	{
2152	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2153	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2154	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2155	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2156	# endif
2157	}
2158	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2159	if ( fPdeValid
2160	&& pShwPage->GCPhys == GCPhys
2161	&& (PdeSrc.u & X86_PDE_P)
2162	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
2163	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
2164	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2165	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
2166	# endif
2167	)
2168	{
2169	/*
2170	* Check that the PDE is marked accessed already.
2171	* Since we set the accessed bit before getting here on a #PF, this
2172	* check is only meant for dealing with non-#PF'ing paths.
2173	*/
2174	if (PdeSrc.u & X86_PDE_A)
2175	{
2176	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2177	if (!fBigPage)
2178	{
2179	/*
2180	* 4KB Page - Map the guest page table.
2181	*/
2182	PGSTPT pPTSrc;
2183	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2184	if (RT_SUCCESS(rc))
2185	{
2186	# ifdef PGM_SYNC_N_PAGES
2187	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2188	if ( cPages > 1
2189	&& !(uErr & X86_TRAP_PF_P)
2190	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2191	{
2192	/*
2193	* This code path is currently only taken when the caller is PGMTrap0eHandler
2194	* for non-present pages!
2195	*
2196	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2197	* deal with locality.
2198	*/
2199	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2200	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2201	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2202	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2203	# else
2204	const unsigned offPTSrc = 0;
2205	# endif
2206	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2207	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2208	iPTDst = 0;
2209	else
2210	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2211
2212	for (; iPTDst < iPTDstEnd; iPTDst++)
2213	{
2214	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2215
2216	if ( (pPteSrc->u & X86_PTE_P)
2217	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2218	{
2219	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT))
2220	\| ((offPTSrc + iPTDst) << GUEST_PAGE_SHIFT);
2221	NOREF(GCPtrCurPage);
2222	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2223	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2224	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
2225	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
2226	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
2227	(uint64_t)pPteSrc->u,
2228	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2229	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2230	}
2231	}
2232	}
2233	else
2234	# endif /* PGM_SYNC_N_PAGES */
2235	{
2236	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2237	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2238	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2239	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2240	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2241	GCPtrPage, PteSrc.u & X86_PTE_P,
2242	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2243	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2244	(uint64_t)PteSrc.u,
2245	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2246	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2247	}
2248	}
2249	else /* MMIO or invalid page: emulated in #PF handler. */
2250	{
2251	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2252	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2253	}
2254	}
2255	else
2256	{
2257	/*
2258	* 4/2MB page - lazy syncing shadow 4K pages.
2259	* (There are many causes of getting here, it's no longer only CSAM.)
2260	*/
2261	/* Calculate the GC physical address of this 4KB shadow page. */
2262	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2263	/* Find ram range. */
2264	PPGMPAGE pPage;
2265	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2266	if (RT_SUCCESS(rc))
2267	{
2268	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2269
2270	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2271	/* Try to make the page writable if necessary. */
2272	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2273	&& ( PGM_PAGE_IS_ZERO(pPage)
2274	\|\| ( (PdeSrc.u & X86_PDE_RW)
2275	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2276	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2277	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2278	# endif
2279	# ifdef VBOX_WITH_PAGE_SHARING
2280	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2281	# endif
2282	)
2283	)
2284	)
2285	{
2286	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2287	AssertRC(rc);
2288	}
2289	# endif
2290
2291	/*
2292	* Make shadow PTE entry.
2293	*/
2294	SHWPTE PteDst;
2295	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2296	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2297	else
2298	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2299
2300	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2301	if ( SHW_PTE_IS_P(PteDst)
2302	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2303	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2304
2305	/* Make sure only allocated pages are mapped writable. */
2306	if ( SHW_PTE_IS_P_RW(PteDst)
2307	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2308	{
2309	/* Still applies to shared pages. */
2310	Assert(!PGM_PAGE_IS_ZERO(pPage));
2311	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2312	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2313	}
2314
2315	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2316
2317	/*
2318	* If the page is not flagged as dirty and is writable, then make it read-only
2319	* at PD level, so we can set the dirty bit when the page is modified.
2320	*
2321	* ASSUMES that page access handlers are implemented on page table entry level.
2322	* Thus we will first catch the dirty access and set PDE.D and restart. If
2323	* there is an access handler, we'll trap again and let it work on the problem.
2324	*/
2325	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2326	* As for invlpg, it simply frees the whole shadow PT.
2327	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2328	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
2329	{
2330	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2331	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2332	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2333	}
2334	else
2335	{
2336	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
2337	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
2338	}
2339	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2340	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2341	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
2342	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2343	}
2344	else
2345	{
2346	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2347	/** @todo must wipe the shadow page table entry in this
2348	* case. */
2349	}
2350	}
2351	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2352	return VINF_SUCCESS;
2353	}
2354
2355	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
2356	}
2357	else if (fPdeValid)
2358	{
2359	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2360	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2361	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2362	}
2363	else
2364	{
2365	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2366	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2367	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2368	}
2369
2370	/*
2371	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2372	* Yea, I'm lazy.
2373	*/
2374	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2375	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2376
2377	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2378	PGM_INVL_VCPU_TLBS(pVCpu);
2379	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2380
2381
2382	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2383	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2384	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2385	NOREF(PdeSrc);
2386
2387	# ifdef PGM_SYNC_N_PAGES
2388	/*
2389	* Get the shadow PDE, find the shadow page table in the pool.
2390	*/
2391	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2392	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2393
2394	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2395	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2396
2397	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2398	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2399	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2400	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2401	X86PDEPAE PdeDst;
2402	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2403
2404	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2405	AssertRCSuccessReturn(rc, rc);
2406	Assert(pPDDst && pPdptDst);
2407	PdeDst = pPDDst->a[iPDDst];
2408
2409	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2410	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2411	PEPTPD pPDDst;
2412	EPTPDE PdeDst;
2413
2414	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2415	if (rc != VINF_SUCCESS)
2416	{
2417	AssertRC(rc);
2418	return rc;
2419	}
2420	Assert(pPDDst);
2421	PdeDst = pPDDst->a[iPDDst];
2422	# endif
2423	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2424	if (!SHW_PDE_IS_P(PdeDst))
2425	{
2426	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2427	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2428	return VINF_SUCCESS; /* force the instruction to be executed again. */
2429	}
2430
2431	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2432	if (SHW_PDE_IS_BIG(PdeDst))
2433	{
2434	Assert(pVM->pgm.s.fNestedPaging);
2435	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2436	return VINF_SUCCESS;
2437	}
2438
2439	/* Mask away the page offset. */
2440	GCPtrPage &= ~((RTGCPTR)0xfff);
2441
2442	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2443	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2444
2445	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2446	if ( cPages > 1
2447	&& !(uErr & X86_TRAP_PF_P)
2448	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2449	{
2450	/*
2451	* This code path is currently only taken when the caller is PGMTrap0eHandler
2452	* for non-present pages!
2453	*
2454	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2455	* deal with locality.
2456	*/
2457	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2458	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2459	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2460	iPTDst = 0;
2461	else
2462	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2463	for (; iPTDst < iPTDstEnd; iPTDst++)
2464	{
2465	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2466	{
2467	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2468	\| (iPTDst << GUEST_PAGE_SHIFT));
2469
2470	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2471	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2472	GCPtrCurPage,
2473	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2474	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2475
2476	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2477	break;
2478	}
2479	else
2480	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n",
2481	(GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << GUEST_PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2482	}
2483	}
2484	else
2485	# endif /* PGM_SYNC_N_PAGES */
2486	{
2487	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2488	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2489	\| (iPTDst << GUEST_PAGE_SHIFT));
2490
2491	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2492
2493	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2494	GCPtrPage,
2495	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2496	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2497	}
2498	return VINF_SUCCESS;
2499
2500	# else
2501	NOREF(PdeSrc);
2502	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2503	return VERR_PGM_NOT_USED_IN_MODE;
2504	# endif
2505	}
2506
2507	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2508
2509	#if !defined(IN_RING3) && defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
2510
2511	/**
2512	* Sync a shadow page for a nested-guest page.
2513	*
2514	* @param pVCpu The cross context virtual CPU structure.
2515	* @param pPte The shadow page table entry.
2516	* @param GCPhysPage The guest-physical address of the page.
2517	* @param pShwPage The shadow page of the page table.
2518	* @param iPte The index of the page table entry.
2519	* @param pGstWalkAll The guest page table walk result.
2520	*
2521	* @note Not to be used for 2/4MB pages!
2522	*/
2523	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
2524	unsigned iPte, PCPGMPTWALKGST pGstWalkAll)
2525	{
2526	/*
2527	* Do not make assumptions about anything other than the final PTE entry in the
2528	* guest page table walk result. For instance, while mapping 2M PDEs as 4K pages,
2529	* the PDE might still be having its leaf bit set.
2530	*
2531	* In the future, we could consider introducing a generic SLAT macro like PSLATPTE
2532	* and using that instead of passing the full SLAT translation result.
2533	*/
2534	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2535	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2536	Assert(!pShwPage->fDirty);
2537	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
2538	AssertMsg((pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK) == GCPhysPage,
2539	("PTE address mismatch. GCPhysPage=%RGp Pte=%RX64\n", GCPhysPage, pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK));
2540
2541	/*
2542	* Find the ram range.
2543	*/
2544	PPGMPAGE pPage;
2545	int rc = pgmPhysGetPageEx(pVCpu->CTX_SUFF(pVM), GCPhysPage, &pPage);
2546	AssertRCReturnVoid(rc);
2547
2548	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
2549
2550	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2551	/* Make the page writable if necessary. */
2552	/** @todo This needs to be applied to the regular case below, not here. And,
2553	* no we should NOT make the page writble, instead we need to write
2554	* protect them if necessary. */
2555	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2556	&& ( PGM_PAGE_IS_ZERO(pPage)
2557	\|\| ( (pGstWalkAll->u.Ept.Pte.u & EPT_E_WRITE)
2558	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2559	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2560	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2561	# endif
2562	# ifdef VBOX_WITH_PAGE_SHARING
2563	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2564	# endif
2565	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_BALLOONED
2566	)
2567	)
2568	)
2569	{
2570	AssertMsgFailed(("GCPhysPage=%RGp\n", GCPhysPage)); /** @todo Shouldn't happen but if it does deal with it later. */
2571	}
2572	# endif
2573
2574	/*
2575	* Make page table entry.
2576	*/
2577	SHWPTE Pte;
2578	uint64_t const fGstShwPteFlags = pGstWalkAll->u.Ept.Pte.u & pVCpu->pgm.s.fGstEptShadowedPteMask;
2579	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2580	{
2581	/** @todo access bit. */
2582	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2583	Log7Func(("regular page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2584	}
2585	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2586	{
2587	/** @todo access bit. */
2588	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| (fGstShwPteFlags & ~EPT_E_WRITE);
2589	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2590	}
2591	else
2592	{
2593	/** @todo Do MMIO optimizations here too? */
2594	Log7Func(("mmio/all page (%R[pgmpage]) at %RGp -> 0\n", pPage, GCPhysPage));
2595	Pte.u = 0;
2596	}
2597
2598	/* Make sure only allocated pages are mapped writable. */
2599	Assert(!SHW_PTE_IS_P_RW(Pte) \|\| PGM_PAGE_IS_ALLOCATED(pPage));
2600
2601	/*
2602	* Keep user track up to date.
2603	*/
2604	if (SHW_PTE_IS_P(Pte))
2605	{
2606	if (!SHW_PTE_IS_P(*pPte))
2607	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2608	else if (SHW_PTE_GET_HCPHYS(*pPte) != SHW_PTE_GET_HCPHYS(Pte))
2609	{
2610	Log2(("SyncPageWorker: deref! pPte=%RX64 Pte=%RX64\n", SHW_PTE_LOG64(pPte), SHW_PTE_LOG64(Pte)));
2611	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2612	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2613	}
2614	}
2615	else if (SHW_PTE_IS_P(*pPte))
2616	{
2617	Log2(("SyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2618	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2619	}
2620
2621	/*
2622	* Commit the entry.
2623	*/
2624	SHW_PTE_ATOMIC_SET2(*pPte, Pte);
2625	return;
2626	}
2627
2628
2629	/**
2630	* Syncs a nested-guest page.
2631	*
2632	* There are no conflicts at this point, neither is there any need for
2633	* page table allocations.
2634	*
2635	* @returns VBox status code.
2636	* @param pVCpu The cross context virtual CPU structure.
2637	* @param GCPhysNestedPage The nested-guest physical address of the page being
2638	* synced.
2639	* @param GCPhysPage The guest-physical address of the page being synced.
2640	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2641	* @param uErr The page fault error (X86_TRAP_PF_XXX).
2642	* @param pGstWalkAll The guest page table walk result.
2643	*/
2644	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
2645	uint32_t uErr, PPGMPTWALKGST pGstWalkAll)
2646	{
2647	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2648	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2649	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2650
2651	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2652	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2653	Log7Func(("GCPhysNestedPage=%RGv GCPhysPage=%RGp cPages=%u uErr=%#x\n", GCPhysNestedPage, GCPhysPage, cPages, uErr));
2654	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages);
2655
2656	PGM_LOCK_ASSERT_OWNER(pVM);
2657
2658	/*
2659	* Get the shadow PDE, find the shadow page table in the pool.
2660	*/
2661	unsigned const iPde = ((GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK);
2662	PEPTPD pPd;
2663	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL, &pPd, pGstWalkAll);
2664	if (RT_SUCCESS(rc))
2665	{ /* likely */ }
2666	else
2667	{
2668	Log(("Failed to fetch EPT PD for %RGp (%RGp) rc=%Rrc\n", GCPhysNestedPage, GCPhysPage, rc));
2669	return rc;
2670	}
2671	Assert(pPd);
2672	EPTPDE Pde = pPd->a[iPde];
2673
2674	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2675	if (!SHW_PDE_IS_P(Pde))
2676	{
2677	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)Pde.u));
2678	Log7Func(("CPU%d: SyncPage: Pde at %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2679	return VINF_SUCCESS; /* force the instruction to be executed again. */
2680	}
2681
2682	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2683	if (SHW_PDE_IS_BIG(Pde))
2684	{
2685	Log7Func(("CPU%d: SyncPage: %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2686	return VINF_SUCCESS;
2687	}
2688
2689	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, Pde.u & EPT_PDE_PG_MASK);
2690	PEPTPT pPt = (PEPTPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2691
2692	/*
2693	* If we've shadowed a guest EPT PDE that maps a 2M page using a 4K table,
2694	* then sync the 4K sub-page in the 2M range.
2695	*/
2696	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2697	{
2698	Assert(!SHW_PDE_IS_BIG(Pde));
2699
2700	Assert(pGstWalkAll->u.Ept.Pte.u == 0);
2701	Assert((Pde.u & EPT_PRESENT_MASK) == (pGstWalkAll->u.Ept.Pde.u & EPT_PRESENT_MASK));
2702	Assert(pShwPage->GCPhys == (pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK));
2703
2704	#if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
2705	PPGMPAGE pPage;
2706	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage); AssertRC(rc);
2707	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
2708	Assert(pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB);
2709	#endif
2710	uint64_t const fGstPteFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask & ~EPT_E_LEAF;
2711	pGstWalkAll->u.Ept.Pte.u = GCPhysPage \| fGstPteFlags;
2712
2713	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2714	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2715	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2716
2717	/* Restore modifications did to the guest-walk result above in case callers might inspect them later. */
2718	pGstWalkAll->u.Ept.Pte.u = 0;
2719	return VINF_SUCCESS;
2720	}
2721
2722	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2723	# ifdef PGM_SYNC_N_PAGES
2724	if ( cPages > 1
2725	&& !(uErr & X86_TRAP_PF_P)
2726	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2727	{
2728	/*
2729	* This code path is currently only taken for non-present pages!
2730	*
2731	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2732	* deal with locality.
2733	*/
2734	unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2735	unsigned const iPteEnd = RT_MIN(iPte + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPt->a));
2736	if (iPte < PGM_SYNC_NR_PAGES / 2)
2737	iPte = 0;
2738	else
2739	iPte -= PGM_SYNC_NR_PAGES / 2;
2740	for (; iPte < iPteEnd; iPte++)
2741	{
2742	if (!SHW_PTE_IS_P(pPt->a[iPte]))
2743	{
2744	PGMPTWALKGST GstWalkPt;
2745	PGMPTWALK WalkPt;
2746	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2747	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2748	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt,
2749	&GstWalkPt);
2750	if (RT_SUCCESS(rc))
2751	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], WalkPt.GCPhys, pShwPage, iPte, &GstWalkPt);
2752	else
2753	{
2754	/*
2755	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2756	* Ensure the shadow tables entry is not-present.
2757	*/
2758	/** @todo Potential room for optimization (explained in NestedSyncPT). */
2759	AssertMsg(!pPt->a[iPte].u, ("%RX64\n", pPt->a[iPte].u));
2760	}
2761	Log7Func(("Many: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2762	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2763	break;
2764	}
2765	else
2766	{
2767	# ifdef VBOX_STRICT
2768	/* Paranoia - Verify address of the page is what it should be. */
2769	PGMPTWALKGST GstWalkPt;
2770	PGMPTWALK WalkPt;
2771	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2772	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2773	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt, &GstWalkPt);
2774	AssertRC(rc);
2775	PPGMPAGE pPage;
2776	rc = pgmPhysGetPageEx(pVM, WalkPt.GCPhys, &pPage);
2777	AssertRC(rc);
2778	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2779	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp HCPhys=%RHp Shw=%RHp\n",
2780	GCPhysNestedPage, WalkPt.GCPhys, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2781	# endif
2782	Log7Func(("Many3: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2783	}
2784	}
2785	}
2786	else
2787	# endif /* PGM_SYNC_N_PAGES */
2788	{
2789	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2790	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2791	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2792	}
2793
2794	return VINF_SUCCESS;
2795	}
2796
2797
2798	/**
2799	* Sync a shadow page table for a nested-guest page table.
2800	*
2801	* The shadow page table is not present in the shadow PDE.
2802	*
2803	* Handles mapping conflicts.
2804	*
2805	* A precondition for this method is that the shadow PDE is not present. The
2806	* caller must take the PGM lock before checking this and continue to hold it
2807	* when calling this method.
2808	*
2809	* @returns VBox status code.
2810	* @param pVCpu The cross context virtual CPU structure.
2811	* @param GCPhysNestedPage The nested-guest physical page address of the page
2812	* being synced.
2813	* @param GCPhysPage The guest-physical address of the page being synced.
2814	* @param pGstWalkAll The guest page table walk result.
2815	*/
2816	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll)
2817	{
2818	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2819	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2820	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2821
2822	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2823	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2824
2825	Log7Func(("GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
2826
2827	PGM_LOCK_ASSERT_OWNER(pVM);
2828	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2829
2830	PEPTPD pPd;
2831	PEPTPDPT pPdpt;
2832	unsigned const iPde = (GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK;
2833	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, &pPdpt, &pPd, pGstWalkAll);
2834	if (RT_SUCCESS(rc))
2835	{ /* likely */ }
2836	else
2837	{
2838	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2839	AssertRC(rc);
2840	return rc;
2841	}
2842	Assert(pPd);
2843	PSHWPDE pPde = &pPd->a[iPde];
2844
2845	unsigned const iPdpt = (GCPhysNestedPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2846	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdpt->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2847	Assert(pShwPde->enmKind == PGMPOOLKIND_EPT_PD_FOR_EPT_PD);
2848
2849	SHWPDE Pde = *pPde;
2850	Assert(!SHW_PDE_IS_P(Pde)); /* We're only supposed to call SyncPT on PDE!P and conflicts. */
2851
2852	# ifdef PGM_WITH_LARGE_PAGES
2853	if (BTH_IS_NP_ACTIVE(pVM))
2854	{
2855	/*
2856	* Check if the guest is mapping a 2M page here.
2857	*/
2858	PPGMPAGE pPage;
2859	rc = pgmPhysGetPageEx(pVM, GCPhysPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2860	AssertRCReturn(rc, rc);
2861	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2862	{
2863	/* A20 is always enabled in VMX root and non-root operation. */
2864	Assert(PGM_A20_IS_ENABLED(pVCpu));
2865
2866	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2867	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2868	{
2869	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2870	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2871	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2872	}
2873	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2874	{
2875	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2876	rc = pgmPhysRecheckLargePage(pVM, GCPhysPage, pPage);
2877	if (RT_SUCCESS(rc))
2878	{
2879	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2880	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2881	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2882	}
2883	}
2884	else if (PGMIsUsingLargePages(pVM))
2885	{
2886	rc = pgmPhysAllocLargePage(pVM, GCPhysPage);
2887	if (RT_SUCCESS(rc))
2888	{
2889	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2890	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2891	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2892	}
2893	}
2894
2895	/*
2896	* If we have a 2M large page, we can map the guest's 2M large page right away.
2897	*/
2898	uint64_t const fShwBigPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask;
2899	if (HCPhys != NIL_RTHCPHYS)
2900	{
2901	Pde.u = HCPhys \| fShwBigPdeFlags;
2902	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzBigPdeMask));
2903	Assert(Pde.u & EPT_E_LEAF);
2904	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
2905
2906	/* Add a reference to the first page only. */
2907	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPde);
2908
2909	Assert(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED);
2910
2911	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2912	Log7Func(("GstPde=%RGp ShwPde=%RX64 [2M]\n", pGstWalkAll->u.Ept.Pde.u, Pde.u));
2913	return VINF_SUCCESS;
2914	}
2915
2916	/*
2917	* We didn't get a perfect 2M fit. Split the 2M page into 4K pages.
2918	* The page ought not to be marked as a big (2M) page at this point.
2919	*/
2920	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
2921
2922	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2923	PGMPOOLACCESS enmAccess;
2924	{
2925	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_USER_EXECUTE)); /* Mode-based execute control for EPT not supported. */
2926	bool const fNoExecute = !(pGstWalkAll->u.Ept.Pde.u & EPT_E_EXECUTE);
2927	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_WRITE)
2928	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2929	else
2930	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2931	}
2932
2933	/*
2934	* Allocate & map a 4K shadow table to cover the 2M guest page.
2935	*/
2936	PPGMPOOLPAGE pShwPage;
2937	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK;
2938	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_2MB, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2939	pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
2940	if ( rc == VINF_SUCCESS
2941	\|\| rc == VINF_PGM_CACHED_PAGE)
2942	{ /* likely */ }
2943	else
2944	{
2945	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2946	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2947	}
2948
2949	PSHWPT pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2950	Assert(pPt);
2951	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2952	if (rc == VINF_SUCCESS)
2953	{
2954	/* The 4K PTEs shall inherit the flags of the 2M PDE page sans the leaf bit. */
2955	uint64_t const fShwPteFlags = fShwBigPdeFlags & ~EPT_E_LEAF;
2956
2957	/* Sync each 4K pages in the 2M range. */
2958	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++)
2959	{
2960	RTGCPHYS const GCPhysSubPage = GCPhysPt \| (iPte << GUEST_PAGE_SHIFT);
2961	pGstWalkAll->u.Ept.Pte.u = GCPhysSubPage \| fShwPteFlags;
2962	Assert(!(pGstWalkAll->u.Ept.Pte.u & pVCpu->pgm.s.fGstEptMbzPteMask));
2963	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysSubPage, pShwPage, iPte, pGstWalkAll);
2964	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [2M->4K]\n", pGstWalkAll->u.Ept.Pte, pPt->a[iPte].u, iPte));
2965	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2966	break;
2967	}
2968
2969	/* Restore modifications did to the guest-walk result above in case callers might inspect them later. */
2970	pGstWalkAll->u.Ept.Pte.u = 0;
2971	}
2972	else
2973	{
2974	Assert(rc == VINF_PGM_CACHED_PAGE);
2975	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
2976	/* Paranoia - Verify address of each of the subpages are what they should be. */
2977	RTGCPHYS GCPhysSubPage = GCPhysPt;
2978	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++, GCPhysSubPage += GUEST_PAGE_SIZE)
2979	{
2980	PPGMPAGE pSubPage;
2981	rc = pgmPhysGetPageEx(pVM, GCPhysSubPage, &pSubPage);
2982	AssertRC(rc);
2983	AssertMsg( PGM_PAGE_GET_HCPHYS(pSubPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte])
2984	\|\| !SHW_PTE_IS_P(pPt->a[iPte]),
2985	("PGM 2M page and shadow PTE conflict. GCPhysSubPage=%RGp Page=%RHp Shw=%RHp\n",
2986	GCPhysSubPage, PGM_PAGE_GET_HCPHYS(pSubPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2987	}
2988	# endif
2989	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
2990	}
2991
2992	/* Save the new PDE. */
2993	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
2994	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
2995	Assert(!(Pde.u & EPT_E_LEAF));
2996	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
2997	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
2998	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2999	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3000	return rc;
3001	}
3002	}
3003	# endif /* PGM_WITH_LARGE_PAGES */
3004
3005	/*
3006	* Allocate & map the shadow page table.
3007	*/
3008	PSHWPT pPt;
3009	PPGMPOOLPAGE pShwPage;
3010
3011	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE_PG_MASK;
3012	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_PT, PGMPOOLACCESS_DONTCARE,
3013	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3014	if ( rc == VINF_SUCCESS
3015	\|\| rc == VINF_PGM_CACHED_PAGE)
3016	{ /* likely */ }
3017	else
3018	{
3019	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3020	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3021	}
3022
3023	pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3024	Assert(pPt);
3025	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3026
3027	if (rc == VINF_SUCCESS)
3028	{
3029	/* Sync the page we've already translated through SLAT. */
3030	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3031	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
3032	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3033
3034	/* Sync the rest of page table (expensive but might be cheaper than nested-guest VM-exits in hardware). */
3035	for (unsigned iPteCur = 0; iPteCur < RT_ELEMENTS(pPt->a); iPteCur++)
3036	{
3037	if (iPteCur != iPte)
3038	{
3039	PGMPTWALKGST GstWalkPt;
3040	PGMPTWALK WalkPt;
3041	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
3042	GCPhysNestedPage \|= (iPteCur << GUEST_PAGE_SHIFT);
3043	int const rc2 = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/,
3044	&WalkPt, &GstWalkPt);
3045	if (RT_SUCCESS(rc2))
3046	{
3047	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPteCur], WalkPt.GCPhys, pShwPage, iPteCur, &GstWalkPt);
3048	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", GstWalkPt.u.Ept.Pte.u, pPt->a[iPteCur].u, iPteCur));
3049	}
3050	else
3051	{
3052	/*
3053	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
3054	* Ensure the shadow tables entry is not-present.
3055	*/
3056	/** @todo We currently don't configure these to cause EPT misconfigs but rather trap
3057	* them using EPT violations and walk the guest EPT tables to determine
3058	* whether they are EPT misconfigs VM-exits for the nested-hypervisor. We
3059	* could optimize this by using a specific combination of reserved bits
3060	* which we could immediately identify as EPT misconfigs of the
3061	* nested-hypervisor without having to walk its EPT tables. However, tracking
3062	* non-present entries might be tricky...
3063	*/
3064	AssertMsg(!pPt->a[iPteCur].u, ("%RX64\n", pPt->a[iPteCur].u));
3065	}
3066	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3067	break;
3068	}
3069	}
3070	}
3071	else
3072	{
3073	Assert(rc == VINF_PGM_CACHED_PAGE);
3074	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3075	/* Paranoia - Verify address of the page is what it should be. */
3076	PPGMPAGE pPage;
3077	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
3078	AssertRC(rc);
3079	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3080	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]) \|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3081	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp Page=%RHp Shw=%RHp\n",
3082	GCPhysNestedPage, GCPhysPage, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3083	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [cache]\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3084	# endif
3085	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3086	}
3087
3088	/* Save the new PDE. */
3089	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3090	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF));
3091	Assert(!(pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3092	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3093	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3094	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3095
3096	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3097	return rc;
3098	}
3099
3100	#endif /* !IN_RING3 && VBOX_WITH_NESTED_HWVIRT_VMX_EPT && PGM_SHW_TYPE == PGM_TYPE_EPT*/
3101	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3102
3103	/**
3104	* Handle dirty bit tracking faults.
3105	*
3106	* @returns VBox status code.
3107	* @param pVCpu The cross context virtual CPU structure.
3108	* @param uErr Page fault error code.
3109	* @param pPdeSrc Guest page directory entry.
3110	* @param pPdeDst Shadow page directory entry.
3111	* @param GCPtrPage Guest context page address.
3112	*/
3113	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
3114	RTGCPTR GCPtrPage)
3115	{
3116	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3117	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3118	NOREF(uErr);
3119
3120	PGM_LOCK_ASSERT_OWNER(pVM);
3121
3122	/*
3123	* Handle big page.
3124	*/
3125	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
3126	{
3127	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3128	{
3129	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3130	Assert(pPdeSrc->u & X86_PDE_RW);
3131
3132	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
3133	* fault again and take this path to only invalidate the entry (see below). */
3134	SHWPDE PdeDst = *pPdeDst;
3135	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
3136	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
3137	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3138	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
3139	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3140	}
3141
3142	# ifdef IN_RING0
3143	/* Check for stale TLB entry; only applies to the SMP guest case. */
3144	if ( pVM->cCpus > 1
3145	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
3146	{
3147	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3148	if (pShwPage)
3149	{
3150	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3151	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3152	if (SHW_PTE_IS_P_RW(*pPteDst))
3153	{
3154	/* Stale TLB entry. */
3155	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3156	PGM_INVL_PG(pVCpu, GCPtrPage);
3157	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3158	}
3159	}
3160	}
3161	# endif /* IN_RING0 */
3162	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3163	}
3164
3165	/*
3166	* Map the guest page table.
3167	*/
3168	PGSTPT pPTSrc;
3169	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
3170	AssertRCReturn(rc, rc);
3171
3172	if (SHW_PDE_IS_P(*pPdeDst))
3173	{
3174	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
3175	const GSTPTE PteSrc = *pPteSrc;
3176
3177	/*
3178	* Map shadow page table.
3179	*/
3180	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3181	if (pShwPage)
3182	{
3183	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3184	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3185	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
3186	{
3187	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
3188	{
3189	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
3190	SHWPTE PteDst = *pPteDst;
3191
3192	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
3193	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3194
3195	Assert(PteSrc.u & X86_PTE_RW);
3196
3197	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
3198	* entry will not harm; write access will simply fault again and
3199	* take this path to only invalidate the entry.
3200	*/
3201	if (RT_LIKELY(pPage))
3202	{
3203	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3204	{
3205	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
3206	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
3207	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
3208	SHW_PTE_SET_RO(PteDst);
3209	}
3210	else
3211	{
3212	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
3213	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
3214	{
3215	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
3216	AssertRC(rc);
3217	}
3218	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
3219	SHW_PTE_SET_RW(PteDst);
3220	else
3221	{
3222	/* Still applies to shared pages. */
3223	Assert(!PGM_PAGE_IS_ZERO(pPage));
3224	SHW_PTE_SET_RO(PteDst);
3225	}
3226	}
3227	}
3228	else
3229	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
3230
3231	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
3232	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
3233	PGM_INVL_PG(pVCpu, GCPtrPage);
3234	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3235	}
3236
3237	# ifdef IN_RING0
3238	/* Check for stale TLB entry; only applies to the SMP guest case. */
3239	if ( pVM->cCpus > 1
3240	&& SHW_PTE_IS_RW(*pPteDst)
3241	&& SHW_PTE_IS_A(*pPteDst))
3242	{
3243	/* Stale TLB entry. */
3244	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3245	PGM_INVL_PG(pVCpu, GCPtrPage);
3246	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3247	}
3248	# endif
3249	}
3250	}
3251	else
3252	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
3253	}
3254
3255	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3256	}
3257
3258	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
3259
3260	/**
3261	* Sync a shadow page table.
3262	*
3263	* The shadow page table is not present in the shadow PDE.
3264	*
3265	* Handles mapping conflicts.
3266	*
3267	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
3268	* conflict), and Trap0eHandler.
3269	*
3270	* A precondition for this method is that the shadow PDE is not present. The
3271	* caller must take the PGM lock before checking this and continue to hold it
3272	* when calling this method.
3273	*
3274	* @returns VBox status code.
3275	* @param pVCpu The cross context virtual CPU structure.
3276	* @param iPDSrc Page directory index.
3277	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
3278	* Assume this is a temporary mapping.
3279	* @param GCPtrPage GC Pointer of the page that caused the fault
3280	*/
3281	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
3282	{
3283	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3284	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3285
3286	#if 0 /* rarely useful; leave for debugging. */
3287	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
3288	#endif
3289	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
3290
3291	PGM_LOCK_ASSERT_OWNER(pVM);
3292
3293	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3294	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3295	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3296	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3297	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3298	int rc = VINF_SUCCESS;
3299
3300	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3301
3302	/*
3303	* Some input validation first.
3304	*/
3305	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
3306
3307	/*
3308	* Get the relevant shadow PDE entry.
3309	*/
3310	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3311	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
3312	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3313
3314	/* Fetch the pgm pool shadow descriptor. */
3315	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3316	Assert(pShwPde);
3317
3318	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3319	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3320	PPGMPOOLPAGE pShwPde = NULL;
3321	PX86PDPAE pPDDst;
3322	PSHWPDE pPdeDst;
3323
3324	/* Fetch the pgm pool shadow descriptor. */
3325	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3326	AssertRCSuccessReturn(rc, rc);
3327	Assert(pShwPde);
3328
3329	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3330	pPdeDst = &pPDDst->a[iPDDst];
3331
3332	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3333	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3334	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3335	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3336	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
3337	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3338	AssertRCSuccessReturn(rc, rc);
3339	Assert(pPDDst);
3340	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3341
3342	# endif
3343	SHWPDE PdeDst = *pPdeDst;
3344
3345	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3346	/* Fetch the pgm pool shadow descriptor. */
3347	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3348	Assert(pShwPde);
3349	# endif
3350
3351	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
3352
3353	/*
3354	* Sync the page directory entry.
3355	*/
3356	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3357	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
3358	if ( (PdeSrc.u & X86_PDE_P)
3359	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
3360	{
3361	/*
3362	* Allocate & map the page table.
3363	*/
3364	PSHWPT pPTDst;
3365	PPGMPOOLPAGE pShwPage;
3366	RTGCPHYS GCPhys;
3367	if (fPageTable)
3368	{
3369	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
3370	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3371	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3372	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
3373	# endif
3374	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
3375	pShwPde->idx, iPDDst, false /fLockPage/,
3376	&pShwPage);
3377	}
3378	else
3379	{
3380	PGMPOOLACCESS enmAccess;
3381	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
3382	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
3383	# else
3384	const bool fNoExecute = false;
3385	# endif
3386
3387	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3388	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3389	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3390	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
3391	# endif
3392	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3393	if (PdeSrc.u & X86_PDE_US)
3394	{
3395	if (PdeSrc.u & X86_PDE_RW)
3396	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
3397	else
3398	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
3399	}
3400	else
3401	{
3402	if (PdeSrc.u & X86_PDE_RW)
3403	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3404	else
3405	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3406	}
3407	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3408	pShwPde->idx, iPDDst, false /fLockPage/,
3409	&pShwPage);
3410	}
3411	if (rc == VINF_SUCCESS)
3412	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3413	else if (rc == VINF_PGM_CACHED_PAGE)
3414	{
3415	/*
3416	* The PT was cached, just hook it up.
3417	*/
3418	if (fPageTable)
3419	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3420	else
3421	{
3422	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3423	/* (see explanation and assumptions further down.) */
3424	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3425	{
3426	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3427	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3428	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3429	}
3430	}
3431	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3432	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3433	return VINF_SUCCESS;
3434	}
3435	else
3436	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3437	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
3438	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
3439	* irrelevant at this point. */
3440	PdeDst.u &= X86_PDE_AVL_MASK;
3441	PdeDst.u \|= pShwPage->Core.Key;
3442
3443	/*
3444	* Page directory has been accessed (this is a fault situation, remember).
3445	*/
3446	/** @todo
3447	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
3448	* fault situation. What's more, the Trap0eHandler has already set the
3449	* accessed bit. So, it's actually just VerifyAccessSyncPage which
3450	* might need setting the accessed flag.
3451	*
3452	* The best idea is to leave this change to the caller and add an
3453	* assertion that it's set already. */
3454	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
3455	if (fPageTable)
3456	{
3457	/*
3458	* Page table - 4KB.
3459	*
3460	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
3461	*/
3462	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
3463	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
3464	PGSTPT pPTSrc;
3465	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
3466	if (RT_SUCCESS(rc))
3467	{
3468	/*
3469	* Start by syncing the page directory entry so CSAM's TLB trick works.
3470	*/
3471	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
3472	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3473	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3474	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3475
3476	/*
3477	* Directory/page user or supervisor privilege: (same goes for read/write)
3478	*
3479	* Directory Page Combined
3480	* U/S U/S U/S
3481	* 0 0 0
3482	* 0 1 0
3483	* 1 0 0
3484	* 1 1 1
3485	*
3486	* Simple AND operation. Table listed for completeness.
3487	*
3488	*/
3489	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
3490	# ifdef PGM_SYNC_N_PAGES
3491	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3492	unsigned iPTDst = iPTBase;
3493	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
3494	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
3495	iPTDst = 0;
3496	else
3497	iPTDst -= PGM_SYNC_NR_PAGES / 2;
3498	# else /* !PGM_SYNC_N_PAGES */
3499	unsigned iPTDst = 0;
3500	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
3501	# endif /* !PGM_SYNC_N_PAGES */
3502	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
3503	\| ((RTGCPTR)iPTDst << GUEST_PAGE_SHIFT);
3504	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3505	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3506	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
3507	# else
3508	const unsigned offPTSrc = 0;
3509	# endif
3510	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += GUEST_PAGE_SIZE)
3511	{
3512	const unsigned iPTSrc = iPTDst + offPTSrc;
3513	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
3514	if (PteSrc.u & X86_PTE_P)
3515	{
3516	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
3517	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
3518	GCPtrCur,
3519	PteSrc.u & X86_PTE_P,
3520	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
3521	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
3522	(uint64_t)PteSrc.u,
3523	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
3524	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
3525	}
3526	/* else: the page table was cleared by the pool */
3527	} /* for PTEs */
3528	}
3529	}
3530	else
3531	{
3532	/*
3533	* Big page - 2/4MB.
3534	*
3535	* We'll walk the ram range list in parallel and optimize lookups.
3536	* We will only sync one shadow page table at a time.
3537	*/
3538	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
3539
3540	/**
3541	* @todo It might be more efficient to sync only a part of the 4MB
3542	* page (similar to what we do for 4KB PDs).
3543	*/
3544
3545	/*
3546	* Start by syncing the page directory entry.
3547	*/
3548	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
3549	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3550
3551	/*
3552	* If the page is not flagged as dirty and is writable, then make it read-only
3553	* at PD level, so we can set the dirty bit when the page is modified.
3554	*
3555	* ASSUMES that page access handlers are implemented on page table entry level.
3556	* Thus we will first catch the dirty access and set PDE.D and restart. If
3557	* there is an access handler, we'll trap again and let it work on the problem.
3558	*/
3559	/** @todo move the above stuff to a section in the PGM documentation. */
3560	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3561	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3562	{
3563	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3564	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3565	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3566	}
3567	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3568	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3569
3570	/*
3571	* Fill the shadow page table.
3572	*/
3573	/* Get address and flags from the source PDE. */
3574	SHWPTE PteDstBase;
3575	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3576
3577	/* Loop thru the entries in the shadow PT. */
3578	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3579	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3580	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
3581	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3582	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3583	unsigned iPTDst = 0;
3584	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3585	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3586	{
3587	if (pRam && GCPhys >= pRam->GCPhys)
3588	{
3589	# ifndef PGM_WITH_A20
3590	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT;
3591	# endif
3592	do
3593	{
3594	/* Make shadow PTE. */
3595	# ifdef PGM_WITH_A20
3596	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT];
3597	# else
3598	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3599	# endif
3600	SHWPTE PteDst;
3601
3602	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3603	/* Try to make the page writable if necessary. */
3604	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3605	&& ( PGM_PAGE_IS_ZERO(pPage)
3606	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3607	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3608	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3609	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3610	# endif
3611	# ifdef VBOX_WITH_PAGE_SHARING
3612	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3613	# endif
3614	&& !PGM_PAGE_IS_BALLOONED(pPage))
3615	)
3616	)
3617	{
3618	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3619	AssertRCReturn(rc, rc);
3620	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3621	break;
3622	}
3623	# endif
3624
3625	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3626	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, SHW_PTE_GET_U(PteDstBase), &PteDst);
3627	else if (PGM_PAGE_IS_BALLOONED(pPage))
3628	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3629	else
3630	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3631
3632	/* Only map writable pages writable. */
3633	if ( SHW_PTE_IS_P_RW(PteDst)
3634	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3635	{
3636	/* Still applies to shared pages. */
3637	Assert(!PGM_PAGE_IS_ZERO(pPage));
3638	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3639	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3640	}
3641
3642	if (SHW_PTE_IS_P(PteDst))
3643	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3644
3645	/* commit it (not atomic, new table) */
3646	pPTDst->a[iPTDst] = PteDst;
3647	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3648	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3649	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3650
3651	/* advance */
3652	GCPhys += GUEST_PAGE_SIZE;
3653	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3654	# ifndef PGM_WITH_A20
3655	iHCPage++;
3656	# endif
3657	iPTDst++;
3658	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3659	&& GCPhys <= pRam->GCPhysLast);
3660
3661	/* Advance ram range list. */
3662	while (pRam && GCPhys > pRam->GCPhysLast)
3663	pRam = pRam->CTX_SUFF(pNext);
3664	}
3665	else if (pRam)
3666	{
3667	Log(("Invalid pages at %RGp\n", GCPhys));
3668	do
3669	{
3670	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3671	GCPhys += GUEST_PAGE_SIZE;
3672	iPTDst++;
3673	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3674	&& GCPhys < pRam->GCPhys);
3675	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3676	}
3677	else
3678	{
3679	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3680	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3681	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3682	}
3683	} /* while more PTEs */
3684	} /* 4KB / 4MB */
3685	}
3686	else
3687	AssertRelease(!SHW_PDE_IS_P(PdeDst));
3688
3689	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3690	if (RT_FAILURE(rc))
3691	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3692	return rc;
3693
3694	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3695	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
3696	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3697	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3698	NOREF(iPDSrc); NOREF(pPDSrc);
3699
3700	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3701
3702	/*
3703	* Validate input a little bit.
3704	*/
3705	int rc = VINF_SUCCESS;
3706	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3707	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3708	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3709
3710	/* Fetch the pgm pool shadow descriptor. */
3711	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3712	Assert(pShwPde);
3713
3714	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3715	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3716	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3717	PX86PDPAE pPDDst;
3718	PSHWPDE pPdeDst;
3719
3720	/* Fetch the pgm pool shadow descriptor. */
3721	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3722	AssertRCSuccessReturn(rc, rc);
3723	Assert(pShwPde);
3724
3725	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3726	pPdeDst = &pPDDst->a[iPDDst];
3727
3728	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3729	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3730	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3731	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3732	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3733	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3734	AssertRCSuccessReturn(rc, rc);
3735	Assert(pPDDst);
3736	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3737
3738	/* Fetch the pgm pool shadow descriptor. */
3739	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3740	Assert(pShwPde);
3741
3742	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3743	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3744	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3745	PEPTPD pPDDst;
3746	PEPTPDPT pPdptDst;
3747
3748	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3749	if (rc != VINF_SUCCESS)
3750	{
3751	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3752	AssertRC(rc);
3753	return rc;
3754	}
3755	Assert(pPDDst);
3756	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3757
3758	/* Fetch the pgm pool shadow descriptor. */
3759	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
3760	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3761	Assert(pShwPde);
3762	# endif
3763	SHWPDE PdeDst = *pPdeDst;
3764
3765	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3766
3767	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3768	if (BTH_IS_NP_ACTIVE(pVM))
3769	{
3770	Assert(!VM_IS_NEM_ENABLED(pVM));
3771
3772	/* Check if we allocated a big page before for this 2 MB range. */
3773	PPGMPAGE pPage;
3774	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3775	if (RT_SUCCESS(rc))
3776	{
3777	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3778	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3779	{
3780	if (PGM_A20_IS_ENABLED(pVCpu))
3781	{
3782	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3783	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3784	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3785	}
3786	else
3787	{
3788	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3789	pVM->pgm.s.cLargePagesDisabled++;
3790	}
3791	}
3792	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3793	&& PGM_A20_IS_ENABLED(pVCpu))
3794	{
3795	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3796	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3797	if (RT_SUCCESS(rc))
3798	{
3799	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3800	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3801	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3802	}
3803	}
3804	else if ( PGMIsUsingLargePages(pVM)
3805	&& PGM_A20_IS_ENABLED(pVCpu))
3806	{
3807	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3808	if (RT_SUCCESS(rc))
3809	{
3810	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3811	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3812	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3813	}
3814	else
3815	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3816	}
3817
3818	if (HCPhys != NIL_RTHCPHYS)
3819	{
3820	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3821	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
3822	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
3823	# else
3824	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
3825	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
3826	# endif
3827	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3828
3829	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3830	/* Add a reference to the first page only. */
3831	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3832
3833	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3834	return VINF_SUCCESS;
3835	}
3836	}
3837	}
3838	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3839
3840	/*
3841	* Allocate & map the page table.
3842	*/
3843	PSHWPT pPTDst;
3844	PPGMPOOLPAGE pShwPage;
3845	RTGCPHYS GCPhys;
3846
3847	/* Virtual address = physical address */
3848	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3849	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3850	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3851	&pShwPage);
3852	if ( rc == VINF_SUCCESS
3853	\|\| rc == VINF_PGM_CACHED_PAGE)
3854	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3855	else
3856	{
3857	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3858	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3859	}
3860
3861	if (rc == VINF_SUCCESS)
3862	{
3863	/* New page table; fully set it up. */
3864	Assert(pPTDst);
3865
3866	/* Mask away the page offset. */
3867	GCPtrPage &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
3868
3869	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3870	{
3871	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3872	\| (iPTDst << GUEST_PAGE_SHIFT));
3873
3874	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3875	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3876	GCPtrCurPage,
3877	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3878	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3879
3880	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3881	break;
3882	}
3883	}
3884	else
3885	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3886
3887	/* Save the new PDE. */
3888	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3889	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
3890	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
3891	# else
3892	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
3893	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
3894	# endif
3895	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3896
3897	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3898	if (RT_FAILURE(rc))
3899	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3900	return rc;
3901
3902	#else
3903	NOREF(iPDSrc); NOREF(pPDSrc);
3904	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3905	return VERR_PGM_NOT_USED_IN_MODE;
3906	#endif
3907	}
3908
3909
3910
3911	/**
3912	* Prefetch a page/set of pages.
3913	*
3914	* Typically used to sync commonly used pages before entering raw mode
3915	* after a CR3 reload.
3916	*
3917	* @returns VBox status code.
3918	* @param pVCpu The cross context virtual CPU structure.
3919	* @param GCPtrPage Page to invalidate.
3920	*/
3921	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
3922	{
3923	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3924	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3925	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3926	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3927	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3928	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3929	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3930	/*
3931	* Check that all Guest levels thru the PDE are present, getting the
3932	* PD and PDE in the processes.
3933	*/
3934	int rc = VINF_SUCCESS;
3935	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3936	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3937	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3938	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3939	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3940	unsigned iPDSrc;
3941	X86PDPE PdpeSrc;
3942	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3943	if (!pPDSrc)
3944	return VINF_SUCCESS; /* not present */
3945	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3946	unsigned iPDSrc;
3947	PX86PML4E pPml4eSrc;
3948	X86PDPE PdpeSrc;
3949	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3950	if (!pPDSrc)
3951	return VINF_SUCCESS; /* not present */
3952	# endif
3953	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3954	# else
3955	PGSTPD pPDSrc = NULL;
3956	const unsigned iPDSrc = 0;
3957	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
3958	# endif
3959
3960	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
3961	{
3962	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3963	PGM_LOCK_VOID(pVM);
3964
3965	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3966	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3967	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3968	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3969	PX86PDPAE pPDDst;
3970	X86PDEPAE PdeDst;
3971	# if PGM_GST_TYPE != PGM_TYPE_PAE
3972	X86PDPE PdpeSrc;
3973
3974	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3975	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3976	# endif
3977	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3978	if (rc != VINF_SUCCESS)
3979	{
3980	PGM_UNLOCK(pVM);
3981	AssertRC(rc);
3982	return rc;
3983	}
3984	Assert(pPDDst);
3985	PdeDst = pPDDst->a[iPDDst];
3986
3987	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3988	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3989	PX86PDPAE pPDDst;
3990	X86PDEPAE PdeDst;
3991
3992	# if PGM_GST_TYPE == PGM_TYPE_PROT
3993	/* AMD-V nested paging */
3994	X86PML4E Pml4eSrc;
3995	X86PDPE PdpeSrc;
3996	PX86PML4E pPml4eSrc = &Pml4eSrc;
3997
3998	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3999	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4000	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4001	# endif
4002
4003	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4004	if (rc != VINF_SUCCESS)
4005	{
4006	PGM_UNLOCK(pVM);
4007	AssertRC(rc);
4008	return rc;
4009	}
4010	Assert(pPDDst);
4011	PdeDst = pPDDst->a[iPDDst];
4012	# endif
4013	if (!(PdeDst.u & X86_PDE_P))
4014	{
4015	/** @todo r=bird: This guy will set the A bit on the PDE,
4016	* probably harmless. */
4017	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4018	}
4019	else
4020	{
4021	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
4022	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
4023	* makes no sense to prefetch more than one page.
4024	*/
4025	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4026	if (RT_SUCCESS(rc))
4027	rc = VINF_SUCCESS;
4028	}
4029	PGM_UNLOCK(pVM);
4030	}
4031	return rc;
4032
4033	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4034	NOREF(pVCpu); NOREF(GCPtrPage);
4035	return VINF_SUCCESS; /* ignore */
4036	#else
4037	AssertCompile(0);
4038	#endif
4039	}
4040
4041
4042
4043
4044	/**
4045	* Syncs a page during a PGMVerifyAccess() call.
4046	*
4047	* @returns VBox status code (informational included).
4048	* @param pVCpu The cross context virtual CPU structure.
4049	* @param GCPtrPage The address of the page to sync.
4050	* @param fPage The effective guest page flags.
4051	* @param uErr The trap error code.
4052	* @remarks This will normally never be called on invalid guest page
4053	* translation entries.
4054	*/
4055	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
4056	{
4057	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4058
4059	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
4060	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
4061
4062	Assert(!pVM->pgm.s.fNestedPaging);
4063	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4064	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4065	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4066	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4067	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4068	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4069	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4070
4071	/*
4072	* Get guest PD and index.
4073	*/
4074	/** @todo Performance: We've done all this a jiffy ago in the
4075	* PGMGstGetPage call. */
4076	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4077	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4078	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4079	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4080
4081	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4082	unsigned iPDSrc = 0;
4083	X86PDPE PdpeSrc;
4084	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4085	if (RT_UNLIKELY(!pPDSrc))
4086	{
4087	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4088	return VINF_EM_RAW_GUEST_TRAP;
4089	}
4090
4091	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4092	unsigned iPDSrc = 0; /* shut up gcc */
4093	PX86PML4E pPml4eSrc = NULL; /* ditto */
4094	X86PDPE PdpeSrc;
4095	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4096	if (RT_UNLIKELY(!pPDSrc))
4097	{
4098	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4099	return VINF_EM_RAW_GUEST_TRAP;
4100	}
4101	# endif
4102
4103	# else /* !PGM_WITH_PAGING */
4104	PGSTPD pPDSrc = NULL;
4105	const unsigned iPDSrc = 0;
4106	# endif /* !PGM_WITH_PAGING */
4107	int rc = VINF_SUCCESS;
4108
4109	PGM_LOCK_VOID(pVM);
4110
4111	/*
4112	* First check if the shadow pd is present.
4113	*/
4114	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4115	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
4116
4117	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4118	PX86PDEPAE pPdeDst;
4119	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4120	PX86PDPAE pPDDst;
4121	# if PGM_GST_TYPE != PGM_TYPE_PAE
4122	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4123	X86PDPE PdpeSrc;
4124	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4125	# endif
4126	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4127	if (rc != VINF_SUCCESS)
4128	{
4129	PGM_UNLOCK(pVM);
4130	AssertRC(rc);
4131	return rc;
4132	}
4133	Assert(pPDDst);
4134	pPdeDst = &pPDDst->a[iPDDst];
4135
4136	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4137	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4138	PX86PDPAE pPDDst;
4139	PX86PDEPAE pPdeDst;
4140
4141	# if PGM_GST_TYPE == PGM_TYPE_PROT
4142	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4143	X86PML4E Pml4eSrc;
4144	X86PDPE PdpeSrc;
4145	PX86PML4E pPml4eSrc = &Pml4eSrc;
4146	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4147	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4148	# endif
4149
4150	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4151	if (rc != VINF_SUCCESS)
4152	{
4153	PGM_UNLOCK(pVM);
4154	AssertRC(rc);
4155	return rc;
4156	}
4157	Assert(pPDDst);
4158	pPdeDst = &pPDDst->a[iPDDst];
4159	# endif
4160
4161	if (!(pPdeDst->u & X86_PDE_P))
4162	{
4163	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4164	if (rc != VINF_SUCCESS)
4165	{
4166	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4167	PGM_UNLOCK(pVM);
4168	AssertRC(rc);
4169	return rc;
4170	}
4171	}
4172
4173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4174	/* Check for dirty bit fault */
4175	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
4176	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
4177	Log(("PGMVerifyAccess: success (dirty)\n"));
4178	else
4179	# endif
4180	{
4181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4182	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4183	# else
4184	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4185	# endif
4186
4187	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
4188	if (uErr & X86_TRAP_PF_US)
4189	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
4190	else /* supervisor */
4191	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
4192
4193	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4194	if (RT_SUCCESS(rc))
4195	{
4196	/* Page was successfully synced */
4197	Log2(("PGMVerifyAccess: success (sync)\n"));
4198	rc = VINF_SUCCESS;
4199	}
4200	else
4201	{
4202	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
4203	rc = VINF_EM_RAW_GUEST_TRAP;
4204	}
4205	}
4206	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4207	PGM_UNLOCK(pVM);
4208	return rc;
4209
4210	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4211
4212	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
4213	return VERR_PGM_NOT_USED_IN_MODE;
4214	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4215	}
4216
4217
4218	/**
4219	* Syncs the paging hierarchy starting at CR3.
4220	*
4221	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
4222	* informational status codes.
4223	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
4224	* the VMM into guest context.
4225	* @param pVCpu The cross context virtual CPU structure.
4226	* @param cr0 Guest context CR0 register.
4227	* @param cr3 Guest context CR3 register. Not subjected to the A20
4228	* mask.
4229	* @param cr4 Guest context CR4 register.
4230	* @param fGlobal Including global page directories or not
4231	*/
4232	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
4233	{
4234	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4235	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
4236
4237	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
4238
4239	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
4240	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4241	PGM_LOCK_VOID(pVM);
4242	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4243	if (pPool->cDirtyPages)
4244	pgmPoolResetDirtyPages(pVM);
4245	PGM_UNLOCK(pVM);
4246	# endif
4247	#endif /* !NESTED && !EPT */
4248
4249	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4250	/*
4251	* Nested / EPT / None - No work.
4252	*/
4253	return VINF_SUCCESS;
4254
4255	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4256	/*
4257	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
4258	* out the shadow parts when the guest modifies its tables.
4259	*/
4260	return VINF_SUCCESS;
4261
4262	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4263
4264	return VINF_SUCCESS;
4265	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4266	}
4267
4268
4269
4270
4271	#ifdef VBOX_STRICT
4272
4273	/**
4274	* Checks that the shadow page table is in sync with the guest one.
4275	*
4276	* @returns The number of errors.
4277	* @param pVCpu The cross context virtual CPU structure.
4278	* @param cr3 Guest context CR3 register.
4279	* @param cr4 Guest context CR4 register.
4280	* @param GCPtr Where to start. Defaults to 0.
4281	* @param cb How much to check. Defaults to everything.
4282	*/
4283	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
4284	{
4285	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
4286	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4287	return 0;
4288	#else
4289	unsigned cErrors = 0;
4290	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4291	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
4292
4293	# if PGM_GST_TYPE == PGM_TYPE_PAE
4294	/** @todo currently broken; crashes below somewhere */
4295	AssertFailed();
4296	# endif
4297
4298	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
4299	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4300	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4301
4302	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
4303	PPGMCPU pPGM = &pVCpu->pgm.s;
4304	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
4305	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
4306	# ifndef IN_RING0
4307	RTHCPHYS HCPhys; /* general usage. */
4308	# endif
4309	int rc;
4310
4311	/*
4312	* Check that the Guest CR3 and all its mappings are correct.
4313	*/
4314	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
4315	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
4316	false);
4317	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
4318	# if 0
4319	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4320	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
4321	# else
4322	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
4323	# endif
4324	AssertRCReturn(rc, 1);
4325	HCPhys = NIL_RTHCPHYS;
4326	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
4327	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
4328	# endif
4329	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
4330	pgmGstGet32bitPDPtr(pVCpu);
4331	RTGCPHYS GCPhys;
4332	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
4333	AssertRCReturn(rc, 1);
4334	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
4335	# endif
4336	# endif /* !IN_RING0 */
4337
4338	/*
4339	* Get and check the Shadow CR3.
4340	*/
4341	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4342	unsigned cPDEs = X86_PG_ENTRIES;
4343	unsigned cIncrement = X86_PG_ENTRIES * GUEST_PAGE_SIZE;
4344	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4345	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4346	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
4347	# else
4348	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4349	# endif
4350	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4351	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4352	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4353	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4354	# endif
4355	if (cb != ~(RTGCPTR)0)
4356	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
4357
4358	/** @todo call the other two PGMAssert() functions. /
4359
4360	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4361	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4362
4363	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
4364	{
4365	PPGMPOOLPAGE pShwPdpt = NULL;
4366	PX86PML4E pPml4eSrc;
4367	PX86PML4E pPml4eDst;
4368	RTGCPHYS GCPhysPdptSrc;
4369
4370	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
4371	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4372
4373	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
4374	if (!(pPml4eDst->u & X86_PML4E_P))
4375	{
4376	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4377	continue;
4378	}
4379
4380	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
4381	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
4382
4383	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
4384	{
4385	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4386	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4387	cErrors++;
4388	continue;
4389	}
4390
4391	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
4392	{
4393	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
4394	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4395	cErrors++;
4396	continue;
4397	}
4398
4399	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
4400	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
4401	{
4402	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4403	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4404	cErrors++;
4405	continue;
4406	}
4407	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4408	{
4409	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4410
4411	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
4412	/*
4413	* Check the PDPTEs too.
4414	*/
4415	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
4416
4417	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
4418	{
4419	unsigned iPDSrc = 0; /* initialized to shut up gcc */
4420	PPGMPOOLPAGE pShwPde = NULL;
4421	PX86PDPE pPdpeDst;
4422	RTGCPHYS GCPhysPdeSrc;
4423	X86PDPE PdpeSrc;
4424	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
4425	# if PGM_GST_TYPE == PGM_TYPE_PAE
4426	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
4427	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
4428	# else
4429	PX86PML4E pPml4eSrcIgn;
4430	PX86PDPT pPdptDst;
4431	PX86PDPAE pPDDst;
4432	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
4433
4434	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
4435	if (rc != VINF_SUCCESS)
4436	{
4437	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
4438	GCPtr += 512 * _2M;
4439	continue; /* next PDPTE */
4440	}
4441	Assert(pPDDst);
4442	# endif
4443	Assert(iPDSrc == 0);
4444
4445	pPdpeDst = &pPdptDst->a[iPdpt];
4446
4447	if (!(pPdpeDst->u & X86_PDPE_P))
4448	{
4449	GCPtr += 512 * _2M;
4450	continue; /* next PDPTE */
4451	}
4452
4453	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
4454	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
4455
4456	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
4457	{
4458	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4459	GCPtr += 512 * _2M;
4460	cErrors++;
4461	continue;
4462	}
4463
4464	if (GCPhysPdeSrc != pShwPde->GCPhys)
4465	{
4466	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4467	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4468	# else
4469	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4470	# endif
4471	GCPtr += 512 * _2M;
4472	cErrors++;
4473	continue;
4474	}
4475
4476	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4477	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
4478	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
4479	{
4480	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4481	GCPtr += 512 * _2M;
4482	cErrors++;
4483	continue;
4484	}
4485	# endif
4486
4487	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4488	{
4489	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4490	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4491	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4492	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4493	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4494	# endif
4495	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4496	/*
4497	* Iterate the shadow page directory.
4498	*/
4499	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4500	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4501
4502	for (;
4503	iPDDst < cPDEs;
4504	iPDDst++, GCPtr += cIncrement)
4505	{
4506	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4507	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4508	# else
4509	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4510	# endif
4511	if ( (PdeDst.u & X86_PDE_P)
4512	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
4513	{
4514	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4515	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4516	if (!pPoolPage)
4517	{
4518	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4519	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4520	cErrors++;
4521	continue;
4522	}
4523	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4524
4525	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4526	{
4527	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4528	GCPtr, (uint64_t)PdeDst.u));
4529	cErrors++;
4530	}
4531
4532	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4533	{
4534	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4535	GCPtr, (uint64_t)PdeDst.u));
4536	cErrors++;
4537	}
4538
4539	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4540	if (!(PdeSrc.u & X86_PDE_P))
4541	{
4542	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4543	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4544	cErrors++;
4545	continue;
4546	}
4547
4548	if ( !(PdeSrc.u & X86_PDE_PS)
4549	\|\| !fBigPagesSupported)
4550	{
4551	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4552	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4553	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
4554	# endif
4555	}
4556	else
4557	{
4558	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4559	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4560	{
4561	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4562	GCPtr, (uint64_t)PdeSrc.u));
4563	cErrors++;
4564	continue;
4565	}
4566	# endif
4567	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4568	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4569	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4570	# endif
4571	}
4572
4573	if ( pPoolPage->enmKind
4574	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4575	{
4576	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4577	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4578	cErrors++;
4579	}
4580
4581	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4582	if (!pPhysPage)
4583	{
4584	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4585	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4586	cErrors++;
4587	continue;
4588	}
4589
4590	if (GCPhysGst != pPoolPage->GCPhys)
4591	{
4592	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4593	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4594	cErrors++;
4595	continue;
4596	}
4597
4598	if ( !(PdeSrc.u & X86_PDE_PS)
4599	\|\| !fBigPagesSupported)
4600	{
4601	/*
4602	* Page Table.
4603	*/
4604	const GSTPT *pPTSrc;
4605	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(GUEST_PAGE_SIZE - 1)),
4606	&pPTSrc);
4607	if (RT_FAILURE(rc))
4608	{
4609	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4610	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4611	cErrors++;
4612	continue;
4613	}
4614	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4615	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4616	{
4617	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4618	// (This problem will go away when/if we shadow multiple CR3s.)
4619	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4620	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4621	cErrors++;
4622	continue;
4623	}
4624	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4625	{
4626	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4627	GCPtr, (uint64_t)PdeDst.u));
4628	cErrors++;
4629	continue;
4630	}
4631
4632	/* iterate the page table. */
4633	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4634	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4635	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4636	# else
4637	const unsigned offPTSrc = 0;
4638	# endif
4639	for (unsigned iPT = 0, off = 0;
4640	iPT < RT_ELEMENTS(pPTDst->a);
4641	iPT++, off += GUEST_PAGE_SIZE)
4642	{
4643	const SHWPTE PteDst = pPTDst->a[iPT];
4644
4645	/* skip not-present and dirty tracked entries. */
4646	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4647	continue;
4648	Assert(SHW_PTE_IS_P(PteDst));
4649
4650	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4651	if (!(PteSrc.u & X86_PTE_P))
4652	{
4653	# ifdef IN_RING3
4654	PGMAssertHandlerAndFlagsInSync(pVM);
4655	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4656	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4657	0, 0, UINT64_MAX, 99, NULL);
4658	# endif
4659	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4660	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4661	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4662	cErrors++;
4663	continue;
4664	}
4665
4666	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4667	# if 1 /** @todo sync accessed bit properly... */
4668	fIgnoreFlags \|= X86_PTE_A;
4669	# endif
4670
4671	/* match the physical addresses */
4672	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4673	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4674
4675	# ifdef IN_RING3
4676	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4677	if (RT_FAILURE(rc))
4678	{
4679	# if 0
4680	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4681	{
4682	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4683	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4684	cErrors++;
4685	continue;
4686	}
4687	# endif
4688	}
4689	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4690	{
4691	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4692	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4693	cErrors++;
4694	continue;
4695	}
4696	# endif
4697
4698	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4699	if (!pPhysPage)
4700	{
4701	# if 0
4702	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4703	{
4704	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4705	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4706	cErrors++;
4707	continue;
4708	}
4709	# endif
4710	if (SHW_PTE_IS_RW(PteDst))
4711	{
4712	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4713	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4714	cErrors++;
4715	}
4716	fIgnoreFlags \|= X86_PTE_RW;
4717	}
4718	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4719	{
4720	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4721	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4722	cErrors++;
4723	continue;
4724	}
4725
4726	/* flags */
4727	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
4728	{
4729	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4730	{
4731	if (SHW_PTE_IS_RW(PteDst))
4732	{
4733	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4734	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4735	cErrors++;
4736	continue;
4737	}
4738	fIgnoreFlags \|= X86_PTE_RW;
4739	}
4740	else
4741	{
4742	if ( SHW_PTE_IS_P(PteDst)
4743	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4744	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4745	# endif
4746	)
4747	{
4748	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4749	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4750	cErrors++;
4751	continue;
4752	}
4753	fIgnoreFlags \|= X86_PTE_P;
4754	}
4755	}
4756	else
4757	{
4758	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
4759	{
4760	if (SHW_PTE_IS_RW(PteDst))
4761	{
4762	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4763	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4764	cErrors++;
4765	continue;
4766	}
4767	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4768	{
4769	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4770	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4771	cErrors++;
4772	continue;
4773	}
4774	if (SHW_PTE_IS_D(PteDst))
4775	{
4776	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4777	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4778	cErrors++;
4779	}
4780	# if 0 /** @todo sync access bit properly... */
4781	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4782	{
4783	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4784	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4785	cErrors++;
4786	}
4787	fIgnoreFlags \|= X86_PTE_RW;
4788	# else
4789	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4790	# endif
4791	}
4792	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4793	{
4794	/* access bit emulation (not implemented). */
4795	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
4796	{
4797	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4798	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4799	cErrors++;
4800	continue;
4801	}
4802	if (!SHW_PTE_IS_A(PteDst))
4803	{
4804	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4805	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4806	cErrors++;
4807	}
4808	fIgnoreFlags \|= X86_PTE_P;
4809	}
4810	# ifdef DEBUG_sandervl
4811	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4812	# endif
4813	}
4814
4815	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4816	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4817	)
4818	{
4819	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4820	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4821	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4822	cErrors++;
4823	continue;
4824	}
4825	} /* foreach PTE */
4826	}
4827	else
4828	{
4829	/*
4830	* Big Page.
4831	*/
4832	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4833	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
4834	{
4835	if (PdeDst.u & X86_PDE_RW)
4836	{
4837	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4838	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4839	cErrors++;
4840	continue;
4841	}
4842	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4843	{
4844	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4845	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4846	cErrors++;
4847	continue;
4848	}
4849	# if 0 /** @todo sync access bit properly... */
4850	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4851	{
4852	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4853	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4854	cErrors++;
4855	}
4856	fIgnoreFlags \|= X86_PTE_RW;
4857	# else
4858	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4859	# endif
4860	}
4861	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4862	{
4863	/* access bit emulation (not implemented). */
4864	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
4865	{
4866	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4867	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4868	cErrors++;
4869	continue;
4870	}
4871	if (!SHW_PDE_IS_A(PdeDst))
4872	{
4873	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4874	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4875	cErrors++;
4876	}
4877	fIgnoreFlags \|= X86_PTE_P;
4878	}
4879
4880	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4881	{
4882	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4883	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4884	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4885	cErrors++;
4886	}
4887
4888	/* iterate the page table. */
4889	for (unsigned iPT = 0, off = 0;
4890	iPT < RT_ELEMENTS(pPTDst->a);
4891	iPT++, off += GUEST_PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + GUEST_PAGE_SIZE))
4892	{
4893	const SHWPTE PteDst = pPTDst->a[iPT];
4894
4895	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4896	{
4897	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4898	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4899	cErrors++;
4900	}
4901
4902	/* skip not-present entries. */
4903	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4904	continue;
4905
4906	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4907
4908	/* match the physical addresses */
4909	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4910
4911	# ifdef IN_RING3
4912	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4913	if (RT_FAILURE(rc))
4914	{
4915	# if 0
4916	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4917	{
4918	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4919	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4920	cErrors++;
4921	}
4922	# endif
4923	}
4924	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4925	{
4926	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4927	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4928	cErrors++;
4929	continue;
4930	}
4931	# endif
4932	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4933	if (!pPhysPage)
4934	{
4935	# if 0 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4936	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4937	{
4938	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4939	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4940	cErrors++;
4941	continue;
4942	}
4943	# endif
4944	if (SHW_PTE_IS_RW(PteDst))
4945	{
4946	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4947	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4948	cErrors++;
4949	}
4950	fIgnoreFlags \|= X86_PTE_RW;
4951	}
4952	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4953	{
4954	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4955	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4956	cErrors++;
4957	continue;
4958	}
4959
4960	/* flags */
4961	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4962	{
4963	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4964	{
4965	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4966	{
4967	if ( SHW_PTE_IS_RW(PteDst)
4968	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
4969	{
4970	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4971	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4972	cErrors++;
4973	continue;
4974	}
4975	fIgnoreFlags \|= X86_PTE_RW;
4976	}
4977	}
4978	else
4979	{
4980	if ( SHW_PTE_IS_P(PteDst)
4981	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage)
4982	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4983	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4984	# endif
4985	)
4986	{
4987	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4988	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4989	cErrors++;
4990	continue;
4991	}
4992	fIgnoreFlags \|= X86_PTE_P;
4993	}
4994	}
4995
4996	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4997	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4998	)
4999	{
5000	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
5001	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
5002	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5003	cErrors++;
5004	continue;
5005	}
5006	} /* for each PTE */
5007	}
5008	}
5009	/* not present */
5010
5011	} /* for each PDE */
5012
5013	} /* for each PDPTE */
5014
5015	} /* for each PML4E */
5016
5017	# ifdef DEBUG
5018	if (cErrors)
5019	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
5020	# endif
5021	# endif /* GST is in {32BIT, PAE, AMD64} */
5022	return cErrors;
5023	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
5024	}
5025	#endif /* VBOX_STRICT */
5026
5027
5028	/**
5029	* Sets up the CR3 for shadow paging
5030	*
5031	* @returns Strict VBox status code.
5032	* @retval VINF_SUCCESS.
5033	*
5034	* @param pVCpu The cross context virtual CPU structure.
5035	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
5036	* already applied.)
5037	*/
5038	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
5039	{
5040	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5041	int rc = VINF_SUCCESS;
5042
5043	/* Update guest paging info. */
5044	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5045	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
5046	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
5047
5048	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
5049	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5050
5051	# if PGM_GST_TYPE == PGM_TYPE_PAE
5052	if ( !pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped)
5053	\|\| pVCpu->pgm.s.GCPhysPaeCR3 != GCPhysCR3)
5054	# endif
5055	{
5056	/*
5057	* Map the page CR3 points at.
5058	*/
5059	RTHCPTR HCPtrGuestCR3;
5060	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
5061	if (RT_SUCCESS(rc))
5062	{
5063	# if PGM_GST_TYPE == PGM_TYPE_32BIT
5064	# ifdef IN_RING3
5065	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
5066	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
5067	# else
5068	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
5069	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
5070	# endif
5071
5072	# elif PGM_GST_TYPE == PGM_TYPE_PAE
5073	# ifdef IN_RING3
5074	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
5075	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
5076	# else
5077	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
5078	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
5079	# endif
5080
5081	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
5082	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5083	/*
5084	* When EPT is enabled by the nested-hypervisor and the nested-guest is in PAE mode,
5085	* the guest-CPU context would've already been updated with the 4 PAE PDPEs specified
5086	* in the virtual VMCS. The PDPEs can differ from those in guest memory referenced by
5087	* the translated nested-guest CR3. We -MUST- use the PDPEs provided in the virtual VMCS
5088	* rather than those in guest memory.
5089	*
5090	* See Intel spec. 26.3.2.4 "Loading Page-Directory-Pointer-Table Entries".
5091	*/
5092	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
5093	CPUMGetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5094	else
5095	#endif
5096	{
5097	/* Update CPUM with the PAE PDPEs referenced by CR3. */
5098	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
5099	CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5100	}
5101
5102	/*
5103	* Map the 4 PAE PDPEs.
5104	*/
5105	rc = PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
5106	if (RT_SUCCESS(rc))
5107	{
5108	# ifdef IN_RING3
5109	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
5110	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5111	# else
5112	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5113	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
5114	# endif
5115	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
5116	}
5117
5118	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
5119	# ifdef IN_RING3
5120	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
5121	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
5122	# else
5123	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
5124	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
5125	# endif
5126	# endif
5127	}
5128	else
5129	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
5130	}
5131	#endif
5132
5133	/*
5134	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
5135	*/
5136	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5137	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5138	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
5139	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
5140	&& PGM_GST_TYPE != PGM_TYPE_PROT))
5141
5142	Assert(!pVM->pgm.s.fNestedPaging);
5143	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5144
5145	/*
5146	* Update the shadow root page as well since that's not fixed.
5147	*/
5148	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5149	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
5150	PPGMPOOLPAGE pNewShwPageCR3;
5151
5152	PGM_LOCK_VOID(pVM);
5153
5154	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5155	if (pPool->cDirtyPages)
5156	pgmPoolResetDirtyPages(pVM);
5157	# endif
5158
5159	Assert(!(GCPhysCR3 >> (GUEST_PAGE_SHIFT + 32))); /** @todo what is this for? */
5160	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
5161	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
5162	AssertFatalRC(rc2);
5163
5164	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
5165	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
5166
5167	/* Set the current hypervisor CR3. */
5168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
5169
5170	/* Clean up the old CR3 root. */
5171	if ( pOldShwPageCR3
5172	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
5173	{
5174	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
5175
5176	/* Mark the page as unlocked; allow flushing again. */
5177	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
5178
5179	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
5180	}
5181	PGM_UNLOCK(pVM);
5182	# else
5183	NOREF(GCPhysCR3);
5184	# endif
5185
5186	return rc;
5187	}
5188
5189	/**
5190	* Unmaps the shadow CR3.
5191	*
5192	* @returns VBox status, no specials.
5193	* @param pVCpu The cross context virtual CPU structure.
5194	*/
5195	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
5196	{
5197	LogFlow(("UnmapCR3\n"));
5198
5199	int rc = VINF_SUCCESS;
5200	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5201
5202	/*
5203	* Update guest paging info.
5204	*/
5205	#if PGM_GST_TYPE == PGM_TYPE_32BIT
5206	pVCpu->pgm.s.pGst32BitPdR3 = 0;
5207	pVCpu->pgm.s.pGst32BitPdR0 = 0;
5208
5209	#elif PGM_GST_TYPE == PGM_TYPE_PAE
5210	pVCpu->pgm.s.pGstPaePdptR3 = 0;
5211	pVCpu->pgm.s.pGstPaePdptR0 = 0;
5212	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
5213	{
5214	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
5215	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
5216	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
5217	}
5218
5219	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
5220	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
5221	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
5222
5223	#else /* prot/real mode stub */
5224	/* nothing to do */
5225	#endif
5226
5227	/*
5228	* PAE PDPEs (and CR3) might have been mapped via PGMGstMapPaePdpesAtCr3()
5229	* prior to switching to PAE in pfnMapCr3(), so we need to clear them here.
5230	*/
5231	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5232	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5233	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
5234
5235	/*
5236	* Update shadow paging info.
5237	*/
5238	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5239	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5240	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
5241	# if PGM_GST_TYPE != PGM_TYPE_REAL
5242	Assert(!pVM->pgm.s.fNestedPaging);
5243	# endif
5244	PGM_LOCK_VOID(pVM);
5245
5246	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
5247	{
5248	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5249
5250	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5251	if (pPool->cDirtyPages)
5252	pgmPoolResetDirtyPages(pVM);
5253	# endif
5254
5255	/* Mark the page as unlocked; allow flushing again. */
5256	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
5257
5258	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
5259	pVCpu->pgm.s.pShwPageCR3R3 = 0;
5260	pVCpu->pgm.s.pShwPageCR3R0 = 0;
5261	}
5262
5263	PGM_UNLOCK(pVM);
5264	#endif
5265
5266	return rc;
5267	}
5268

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 97441

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