VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 4295

Last change on this file since 4295 was 4071, checked in by vboxsync, 17 years ago

Biggest check-in ever. New source code headers for all (C) innotek files.
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1/* $Id: PGMAllBth.h 4071 2007-08-07 17:07:59Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4 *
5 * This file is a big challenge!
6 */
7
8/*
9 * Copyright (C) 2006-2007 innotek GmbH
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License as published by the Free Software Foundation,
15 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16 * distribution. VirtualBox OSE is distributed in the hope that it will
17 * be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/*******************************************************************************
21* Internal Functions *
22*******************************************************************************/
23__BEGIN_DECLS
24PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage);
29PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32#ifdef VBOX_STRICT
33PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34#endif
35#ifdef PGMPOOL_WITH_USER_TRACKING
36DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37#endif
38__END_DECLS
39
40
41/**
42 * #PF Handler for raw-mode guest execution.
43 *
44 * @returns VBox status code (appropriate for trap handling and GC return).
45 * @param pVM VM Handle.
46 * @param uErr The trap error code.
47 * @param pRegFrame Trap register frame.
48 * @param pvFault The fault address.
49 */
50PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
51{
52#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
53
54# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
55# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
56# endif
57
58# if PGM_SHW_TYPE == PGM_TYPE_PAE
59 /*
60 * Hide the instruction fetch trap indicator for now.
61 */
62 /** @todo NXE will change this and we must fix NXE in the switcher too! */
63 if (uErr & X86_TRAP_PF_ID)
64 {
65 uErr &= ~X86_TRAP_PF_ID;
66 TRPMSetErrorCode(pVM, uErr);
67 }
68# endif
69
70 /*
71 * Get PDs.
72 */
73 int rc;
74# if PGM_WITH_PAGING(PGM_GST_TYPE)
75 PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
76 const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
77# else
78 PVBOXPD pPDSrc = NULL;
79 const unsigned iPDSrc = 0;
80# endif
81
82 const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
83# if PGM_SHW_TYPE == PGM_TYPE_32BIT
84 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
85# else /* PAE */
86 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
87# endif
88
89# if PGM_WITH_PAGING(PGM_GST_TYPE)
90 /* Determine current privilege level */
91 uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
92
93# ifdef PGM_SYNC_DIRTY_BIT
94 /*
95 * If we successfully correct the write protection fault due to dirty bit
96 * tracking, or this page fault is a genuine one, then return immediately.
97 */
98 STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
99 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
100 STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
101 if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
102 || rc == VINF_EM_RAW_GUEST_TRAP)
103 {
104 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
105 = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
106 LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
107 return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
108 }
109# endif
110
111 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
112# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
113
114 /*
115 * A common case is the not-present error caused by lazy page table syncing.
116 *
117 * It is IMPORTANT that we weed out any access to non-present shadow PDEs here
118 * so we can safely assume that the shadow PT is present when calling SyncPage later.
119 *
120 * On failure, we ASSUME that SyncPT is out of memory or detected some kind
121 * of mapping conflict and defer to SyncCR3 in R3.
122 * (Again, we do NOT support access handlers for non-present guest pages.)
123 *
124 */
125# if PGM_WITH_PAGING(PGM_GST_TYPE)
126 VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
127# else
128 VBOXPDE PdeSrc;
129 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
130 PdeSrc.n.u1Present = 1;
131 PdeSrc.n.u1Write = 1;
132 PdeSrc.n.u1Accessed = 1;
133 PdeSrc.n.u1User = 1;
134# endif
135 if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
136 && !pPDDst->a[iPDDst].n.u1Present
137 && PdeSrc.n.u1Present
138 )
139
140 {
141 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
142 STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
143 LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
144 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
145 if (VBOX_SUCCESS(rc))
146 {
147 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
148 return rc;
149 }
150 Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
151 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
152 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
153 return VINF_PGM_SYNC_CR3;
154 }
155
156# if PGM_WITH_PAGING(PGM_GST_TYPE)
157 /*
158 * Check if this address is within any of our mappings.
159 *
160 * This is *very* fast and it's gonna save us a bit of effort below and prevent
161 * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
162 * (BTW, it's impossible to have physical access handlers in a mapping.)
163 */
164 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
165 {
166 STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
167 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
168 for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
169 {
170 if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
171 break;
172 if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
173 {
174 /*
175 * The first thing we check is if we've got an undetected conflict.
176 */
177 if (!pVM->pgm.s.fMappingsFixed)
178 {
179 unsigned iPT = pMapping->cPTs;
180 while (iPT-- > 0)
181 if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
182 {
183 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
184 Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
185 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
186 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
187 return VINF_PGM_SYNC_CR3;
188 }
189 }
190
191 /*
192 * Check if the fault address is in a virtual page access handler range.
193 */
194 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
195 if ( pCur
196 && pCur->enmType != PGMVIRTHANDLERTYPE_EIP
197 && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
198 && ( uErr & X86_TRAP_PF_RW
199 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
200 && pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** r=bird: <- this is probably wrong. */
201 {
202# ifdef IN_GC
203 STAM_PROFILE_START(&pCur->Stat, h);
204 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
205 STAM_PROFILE_STOP(&pCur->Stat, h);
206# else
207 AssertFailed();
208 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
209# endif
210 STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
211 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
212 return rc;
213 }
214
215 /*
216 * Check if the EIP is in a virtual page access handler range.
217 */
218 if (cpl == 0)
219 {
220 RTGCPTR pvEIP;
221 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
222 if (VBOX_SUCCESS(rc))
223 {
224 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
225 if ( pCur
226 && pCur->enmType == PGMVIRTHANDLERTYPE_EIP
227 && (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
228 {
229# ifdef IN_GC
230 STAM_PROFILE_START(&pCur->Stat, h);
231 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
232 STAM_PROFILE_STOP(&pCur->Stat, h);
233# else
234 AssertFailed();
235 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
236# endif
237 STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
238 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
239 return rc;
240 }
241 }
242 }
243
244 /*
245 * Pretend we're not here and let the guest handle the trap.
246 */
247 TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
248 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
249 LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
250 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
251 return VINF_EM_RAW_GUEST_TRAP;
252 }
253 }
254 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
255 } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
256# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
257
258 /*
259 * Check if this fault address is flagged for special treatment,
260 * which means we'll have to figure out the physical address and
261 * check flags associated with it.
262 *
263 * ASSUME that we can limit any special access handling to pages
264 * in page tables which the guest believes to be present.
265 */
266 if (PdeSrc.n.u1Present)
267 {
268 RTGCPHYS GCPhys = ~0U;
269
270# if PGM_WITH_PAGING(PGM_GST_TYPE)
271 uint32_t cr4 = CPUMGetGuestCR4(pVM);
272 if ( PdeSrc.b.u1Size
273 && (cr4 & X86_CR4_PSE))
274 GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK)
275 | ((RTGCPHYS)pvFault & (PAGE_OFFSET_MASK_BIG ^ PAGE_OFFSET_MASK));
276 else
277 {
278 PVBOXPT pPTSrc;
279# ifdef IN_GC
280 rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & X86_PDE_PG_MASK, (void **)&pPTSrc);
281# else
282 pPTSrc = (PVBOXPT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & X86_PDE_PG_MASK, sizeof(*pPTSrc));
283 if (pPTSrc == 0)
284 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
285# endif
286 if (VBOX_SUCCESS(rc))
287 {
288 unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & PTE_MASK;
289 if (pPTSrc->a[iPTESrc].n.u1Present)
290 GCPhys = pPTSrc->a[iPTESrc].u & X86_PTE_PG_MASK;
291 }
292 }
293# else
294 /* No paging so the fault address is the physical address */
295 GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
296# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
297
298 /*
299 * If we have a GC address we'll check if it has any flags set.
300 */
301 if (GCPhys != ~0U)
302 {
303 STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
304
305 RTHCPHYS HCPhys;
306 rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPhys);
307 if (VBOX_SUCCESS(rc))
308 {
309 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_HANDLER | MM_RAM_FLAGS_VIRTUAL_HANDLER))
310 {
311 if (HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER)
312 {
313 /*
314 * Physical page access handler.
315 */
316 const RTGCPHYS GCPhysFault = GCPhys | ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
317 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
318 if (pCur)
319 {
320# ifdef PGM_SYNC_N_PAGES
321 /*
322 * If the region is write protected and we got a page not present fault, then sync
323 * the pages. If the fault was caused by a read, then restart the instruction.
324 * In case of write access continue to the GC write handler.
325 *
326 * ASSUMES that there is only one handler per page or that they have similar write properties.
327 */
328 if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
329 && !(uErr & X86_TRAP_PF_P))
330 {
331 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
332 if ( VBOX_FAILURE(rc)
333 || !(uErr & X86_TRAP_PF_RW)
334 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
335 {
336 AssertRC(rc);
337 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
338 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
339 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
340 return rc;
341 }
342 }
343# endif
344
345 AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
346 || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
347 ("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
348
349#if defined(IN_GC) || defined(IN_RING0)
350 if (CTXALLSUFF(pCur->pfnHandler))
351 {
352 STAM_PROFILE_START(&pCur->Stat, h);
353 rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
354 STAM_PROFILE_STOP(&pCur->Stat, h);
355 }
356 else
357#endif
358 rc = VINF_EM_RAW_EMULATE_INSTR;
359 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
360 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
361 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
362 return rc;
363 }
364 }
365# if PGM_WITH_PAGING(PGM_GST_TYPE)
366 else
367 {
368# ifdef PGM_SYNC_N_PAGES
369 /*
370 * If the region is write protected and we got a page not present fault, then sync
371 * the pages. If the fault was caused by a read, then restart the instruction.
372 * In case of write access continue to the GC write handler.
373 */
374 if ( (HCPhys & (MM_RAM_FLAGS_VIRTUAL_WRITE | MM_RAM_FLAGS_VIRTUAL_ALL)) == MM_RAM_FLAGS_VIRTUAL_WRITE
375 && !(uErr & X86_TRAP_PF_P))
376 {
377 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
378 if ( VBOX_FAILURE(rc)
379 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
380 || !(uErr & X86_TRAP_PF_RW))
381 {
382 AssertRC(rc);
383 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
384 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
385 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
386 return rc;
387 }
388 }
389# endif
390 /*
391 * Ok, it's an virtual page access handler.
392 *
393 * Since it's faster to search by address, we'll do that first
394 * and then retry by GCPhys if that fails.
395 */
396 /** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
397 /** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
398 * page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
399 */
400 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
401 if (pCur)
402 {
403 AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
404 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
405 || !(uErr & X86_TRAP_PF_P)
406 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
407 ("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
408
409 if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
410 && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
411 && ( uErr & X86_TRAP_PF_RW
412 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
413 && pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
414 {
415# ifdef IN_GC
416 STAM_PROFILE_START(&pCur->Stat, h);
417 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
418 STAM_PROFILE_STOP(&pCur->Stat, h);
419# else
420 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
421# endif
422 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
423 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
424 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
425 return rc;
426 }
427 /* Unhandled part of a monitored page */
428 }
429 else
430 {
431 /* Check by physical address. */
432 PPGMVIRTHANDLER pCur;
433 unsigned iPage;
434 rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
435 &pCur, &iPage);
436 Assert(VBOX_SUCCESS(rc) || !pCur);
437 if ( pCur
438 && pCur->enmType != PGMVIRTHANDLERTYPE_EIP
439 && ( uErr & X86_TRAP_PF_RW
440 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
441 && pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) )
442 {
443 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
444# ifdef IN_GC
445 RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
446 Assert(off < pCur->cb);
447 STAM_PROFILE_START(&pCur->Stat, h);
448 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
449 STAM_PROFILE_STOP(&pCur->Stat, h);
450# else
451 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
452# endif
453 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
454 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
455 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
456 return rc;
457 }
458 }
459 }
460# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
461
462 /*
463 * There is a handled area of the page, but this fault doesn't belong to it.
464 * We must emulate the instruction.
465 *
466 * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
467 * we first check if this was a page-not-present fault for a page with only
468 * write access handlers. Restart the instruction if it wasn't a write access.
469 */
470 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
471
472 if ( !(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL))
473 && !(uErr & X86_TRAP_PF_P))
474 {
475 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
476 if ( VBOX_FAILURE(rc)
477 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
478 || !(uErr & X86_TRAP_PF_RW))
479 {
480 AssertRC(rc);
481 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
482 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
483 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
484 return rc;
485 }
486 }
487
488 /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
489 * It's writing to an unhandled part of the LDT page several million times.
490 */
491 rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
492 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%VHp%s%s\n",
493 rc, HCPhys, HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER ? " phys" : "",
494 HCPhys & MM_RAM_FLAGS_VIRTUAL_HANDLER ? " virt" : ""));
495 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
496 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
497 return rc;
498 } /* if any kind of handler */
499
500# if PGM_WITH_PAGING(PGM_GST_TYPE)
501 if (uErr & X86_TRAP_PF_P)
502 {
503 /*
504 * The page isn't marked, but it might still be monitored by a virtual page access handler.
505 * (ASSUMES no temporary disabling of virtual handlers.)
506 */
507 /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
508 * we should correct both the shadow page table and physical memory flags, and not only check for
509 * accesses within the handler region but for access to pages with virtual handlers. */
510 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
511 if (pCur)
512 {
513 AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
514 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
515 || !(uErr & X86_TRAP_PF_P)
516 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
517 ("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
518
519 if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
520 && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
521 && ( uErr & X86_TRAP_PF_RW
522 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
523 && pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
524 {
525# ifdef IN_GC
526 STAM_PROFILE_START(&pCur->Stat, h);
527 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
528 STAM_PROFILE_STOP(&pCur->Stat, h);
529# else
530 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
531# endif
532 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
533 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
534 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
535 return rc;
536 }
537 }
538 }
539# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
540 }
541 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
542
543# ifdef PGM_OUT_OF_SYNC_IN_GC
544 /*
545 * We are here only if page is present in Guest page tables and trap is not handled
546 * by our handlers.
547 * Check it for page out-of-sync situation.
548 */
549 STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
550
551 if (!(uErr & X86_TRAP_PF_P))
552 {
553 /*
554 * Page is not present in our page tables.
555 * Try to sync it!
556 * BTW, fPageShw is invalid in this branch!
557 */
558 if (uErr & X86_TRAP_PF_US)
559 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
560 else /* supervisor */
561 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
562
563# if defined(LOG_ENABLED) && !defined(IN_RING0)
564 RTGCPHYS GCPhys;
565 uint64_t fPageGst;
566 PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
567 Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
568 pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
569# endif /* LOG_ENABLED */
570
571# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
572 if (cpl == 0)
573 {
574 uint64_t fPageGst;
575 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
576 if ( VBOX_SUCCESS(rc)
577 && !(fPageGst & X86_PTE_US))
578 {
579 /* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
580 if ( pvFault == (RTGCPTR)pRegFrame->eip
581 || (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
582# ifdef CSAM_DETECT_NEW_CODE_PAGES
583 || ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
584 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
585# endif /* CSAM_DETECT_NEW_CODE_PAGES */
586 )
587 {
588 LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
589 rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
590 if (rc != VINF_SUCCESS)
591 {
592 /*
593 * CSAM needs to perform a job in ring 3.
594 *
595 * Sync the page before going to the host context; otherwise we'll end up in a loop if
596 * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
597 */
598 LogFlow(("CSAM ring 3 job\n"));
599 int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
600 AssertRC(rc2);
601
602 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
603 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
604 return rc;
605 }
606 }
607# ifdef CSAM_DETECT_NEW_CODE_PAGES
608 else
609 if ( uErr == X86_TRAP_PF_RW
610 && pRegFrame->ecx >= 0x100 /* early check for movswd count */
611 && pRegFrame->ecx < 0x10000
612 )
613 {
614 /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
615 * to detect loading of new code pages.
616 */
617
618 /*
619 * Decode the instruction.
620 */
621 RTGCPTR PC;
622 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
623 if (rc == VINF_SUCCESS)
624 {
625 DISCPUSTATE Cpu;
626 uint32_t cbOp;
627 rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
628
629 /* For now we'll restrict this to rep movsw/d instructions */
630 if ( rc == VINF_SUCCESS
631 && Cpu.pCurInstr->opcode == OP_MOVSWD
632 && (Cpu.prefix & PREFIX_REP))
633 {
634 CSAMMarkPossibleCodePage(pVM, pvFault);
635 }
636 }
637 }
638# endif /* CSAM_DETECT_NEW_CODE_PAGES */
639
640 /*
641 * Mark this page as safe.
642 */
643 /** @todo not correct for pages that contain both code and data!! */
644 Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
645 CSAMMarkPage(pVM, pvFault, true);
646 }
647 }
648# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
649 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
650 if (VBOX_SUCCESS(rc))
651 {
652 /* The page was successfully synced, return to the guest. */
653 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
654 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
655 return VINF_SUCCESS;
656 }
657 }
658 else
659 {
660 /*
661 * A side effect of not flushing global PDEs are out of sync pages due
662 * to physical monitored regions, that are no longer valid.
663 * Assume for now it only applies to the read/write flag
664 */
665 if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
666 {
667 if (uErr & X86_TRAP_PF_US)
668 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
669 else /* supervisor */
670 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
671
672
673 /*
674 * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
675 */
676 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
677 if (VBOX_SUCCESS(rc))
678 {
679 /*
680 * Page was successfully synced, return to guest.
681 */
682# ifdef VBOX_STRICT
683 RTGCPHYS GCPhys;
684 uint64_t fPageGst;
685 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
686 Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
687 LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
688
689 uint64_t fPageShw;
690 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
691 Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
692# endif /* VBOX_STRICT */
693 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
694 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
695 return VINF_SUCCESS;
696 }
697 }
698
699# if PGM_WITH_PAGING(PGM_GST_TYPE)
700# ifdef VBOX_STRICT
701 /*
702 * Check for VMM page flags vs. Guest page flags consistency.
703 * Currently only for debug purposes.
704 */
705 if (VBOX_SUCCESS(rc))
706 {
707 /* Get guest page flags. */
708 uint64_t fPageGst;
709 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
710 if (VBOX_SUCCESS(rc))
711 {
712 uint64_t fPageShw;
713 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
714
715 /*
716 * Compare page flags.
717 * Note: we have AVL, A, D bits desynched.
718 */
719 AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)),
720 ("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
721 }
722 else
723 AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
724 }
725 else
726 AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
727# endif /* VBOX_STRICT */
728# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729 }
730 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
731# endif /* PGM_OUT_OF_SYNC_IN_GC */
732 }
733 else
734 {
735 /*
736 * Page not present in Guest OS or invalid page table address.
737 * This is potential virtual page access handler food.
738 *
739 * For the present we'll say that our access handlers don't
740 * work for this case - we've already discarded the page table
741 * not present case which is identical to this.
742 *
743 * When we perchance find we need this, we will probably have AVL
744 * trees (offset based) to operate on and we can measure their speed
745 * agains mapping a page table and probably rearrange this handling
746 * a bit. (Like, searching virtual ranges before checking the
747 * physical address.)
748 */
749 }
750 }
751
752
753# if PGM_WITH_PAGING(PGM_GST_TYPE)
754 /*
755 * Check if it's in a EIP based virtual page access handler range.
756 * This is only used for supervisor pages in flat mode.
757 */
758 /** @todo this stuff is completely broken by the out-of-sync stuff. since we don't use this stuff, that's not really a problem yet. */
759 STAM_PROFILE_START(&pVM->pgm.s.StatEIPHandlers, d);
760 if (cpl == 0)
761 {
762 RTGCPTR pvEIP;
763 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
764 if ( VBOX_SUCCESS(rc)
765 && pvEIP == (RTGCPTR)pRegFrame->eip)
766 {
767 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
768 if ( pCur
769 && pCur->enmType == PGMVIRTHANDLERTYPE_EIP
770 && (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
771 {
772 LogFlow(("EIP handler\n"));
773# ifdef IN_GC
774 STAM_PROFILE_START(&pCur->Stat, h);
775 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
776 STAM_PROFILE_STOP(&pCur->Stat, h);
777# else
778 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
779# endif
780 STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
781 return rc;
782 }
783 }
784 }
785 STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
786
787 /*
788 * Conclusion, this is a guest trap.
789 */
790 LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
791 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
792 return VINF_EM_RAW_GUEST_TRAP;
793# else
794 /* present, but not a monitored page; perhaps the guest is probing physical memory */
795 return VINF_EM_RAW_EMULATE_INSTR;
796# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
797
798
799#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
800
801 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
802 return VERR_INTERNAL_ERROR;
803#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
804}
805
806
807/**
808 * Emulation of the invlpg instruction.
809 *
810 *
811 * @returns VBox status code.
812 *
813 * @param pVM VM handle.
814 * @param GCPtrPage Page to invalidate.
815 *
816 * @remark ASSUMES that the guest is updating before invalidating. This order
817 * isn't required by the CPU, so this is speculative and could cause
818 * trouble.
819 *
820 * @todo Flush page or page directory only if necessary!
821 * @todo Add a #define for simply invalidating the page.
822 */
823PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
824{
825#if PGM_GST_TYPE == PGM_TYPE_32BIT
826
827 LogFlow(("InvalidatePage %x\n", GCPtrPage));
828# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
829 /*
830 * Get the shadow PD entry and skip out if this PD isn't present.
831 * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
832 */
833 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
834# if PGM_SHW_TYPE == PGM_TYPE_32BIT
835 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
836# else
837 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
838# endif
839 const SHWPDE PdeDst = *pPdeDst;
840 if (!PdeDst.n.u1Present)
841 {
842 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
843 return VINF_SUCCESS;
844 }
845
846 /*
847 * Get the guest PD entry and calc big page.
848 */
849 PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
850 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
851 VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
852 const uint32_t cr4 = CPUMGetGuestCR4(pVM);
853 const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
854
855# ifdef IN_RING3
856 /*
857 * If a CR3 Sync is pending we may ignore the invalidate page operation
858 * depending on the kind of sync and if it's a global page or not.
859 * This doesn't make sense in GC/R0 so we'll skip it entirely there.
860 */
861# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
862 if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
863 || ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
864 && fIsBigPage
865 && PdeSrc.b.u1Global
866 && (cr4 & X86_CR4_PGE)
867 )
868 )
869# else
870 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
871# endif
872 {
873 STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
874 return VINF_SUCCESS;
875 }
876# endif /* IN_RING3 */
877
878
879 /*
880 * Deal with the Guest PDE.
881 */
882 int rc = VINF_SUCCESS;
883 if (PdeSrc.n.u1Present)
884 {
885 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
886 {
887 /*
888 * Conflict - Let SyncPT deal with it to avoid duplicate code.
889 */
890 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
891 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
892 }
893 else if ( PdeSrc.n.u1User != PdeDst.n.u1User
894 || (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
895 {
896 /*
897 * Mark not present so we can resync the PDE when it's used.
898 */
899 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
900 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
901 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
902 pPdeDst->u = 0;
903 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
904 PGM_INVL_GUEST_TLBS();
905 }
906# ifdef PGM_SYNC_ACCESSED_BIT
907 else if (!PdeSrc.n.u1Accessed)
908 {
909 /*
910 * Mark not present so we can set the accessed bit.
911 */
912 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
913 pPdeDst->u = 0;
914 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
915 PGM_INVL_GUEST_TLBS();
916 }
917# endif
918 else if (!fIsBigPage)
919 {
920 /*
921 * 4KB - page.
922 */
923 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
924 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
925# if PGM_SHW_TYPE != PGM_TYPE_32BIT
926 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
927# endif
928 if (pShwPage->GCPhys == GCPhys)
929 {
930#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
931 const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
932 PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
933 if (pPT->a[iPTEDst].n.u1Present)
934 {
935# ifdef PGMPOOL_WITH_USER_TRACKING
936 /* This is very unlikely with caching/monitoring enabled. */
937 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
938# endif
939 pPT->a[iPTEDst].u = 0;
940 }
941#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
942 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
943 if (VBOX_SUCCESS(rc))
944 rc = VINF_SUCCESS;
945#endif
946 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
947 PGM_INVL_PG(GCPtrPage);
948 }
949 else
950 {
951 /*
952 * The page table address changed.
953 */
954 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
955 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
956 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
957 pPdeDst->u = 0;
958 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
959 PGM_INVL_GUEST_TLBS();
960 }
961 }
962 else
963 {
964 /*
965 * 4MB - page.
966 */
967 /* Before freeing the page, check if anything really changed. */
968 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
969 RTGCPHYS GCPhys = PdeSrc.u & X86_PDE4M_PG_MASK;
970# if PGM_SHW_TYPE != PGM_TYPE_32BIT
971 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
972# endif
973 if ( pShwPage->GCPhys == GCPhys
974 && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
975 {
976 /* ASSUMES a the given bits are identical for 4M and normal PDEs */
977 /** @todo PAT */
978# ifdef PGM_SYNC_DIRTY_BIT
979 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
980 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
981 && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
982 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
983# else
984 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
985 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD)))
986# endif
987 {
988 LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
989 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
990 return VINF_SUCCESS;
991 }
992 }
993
994 /*
995 * Ok, the page table is present and it's been changed in the guest.
996 * If we're in host context, we'll just mark it as not present taking the lazy approach.
997 * We could do this for some flushes in GC too, but we need an algorithm for
998 * deciding which 4MB pages containing code likely to be executed very soon.
999 */
1000 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1001 pPdeDst->u = 0;
1002 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1003 DUMP_PDE_BIG("PGMInvalidatePage", iPDSrc, PdeSrc);
1004 PGM_INVL_BIG_PG(GCPtrPage);
1005 }
1006 }
1007 else
1008 {
1009 /*
1010 * Page directory is not present, mark shadow PDE not present.
1011 */
1012 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1013 {
1014 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1015 pPdeDst->u = 0;
1016 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1017 PGM_INVL_PG(GCPtrPage);
1018 }
1019 else
1020 {
1021 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1022 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1023 }
1024 }
1025
1026 return rc;
1027
1028# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1029# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
1030# endif
1031 return VINF_SUCCESS;
1032
1033#elif PGM_GST_TYPE == PGM_TYPE_PAE
1034# if PGM_SHW_TYPE == PGM_TYPE_PAE
1035//# error not implemented
1036 return VERR_INTERNAL_ERROR;
1037
1038# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1039# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
1040# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1041
1042#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1043# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1044//# error not implemented
1045 return VERR_INTERNAL_ERROR;
1046
1047# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1048# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
1049# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1050
1051#else /* guest real and protected mode */
1052 /* There's no such thing when paging is disabled. */
1053 return VINF_SUCCESS;
1054#endif
1055}
1056
1057
1058#ifdef PGMPOOL_WITH_USER_TRACKING
1059/**
1060 * Update the tracking of shadowed pages.
1061 *
1062 * @param pVM The VM handle.
1063 * @param pShwPage The shadow page.
1064 * @param HCPhys The physical page we is being dereferenced.
1065 */
1066DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1067{
1068# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1069 STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1070 LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1071
1072 /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
1073 * 1. have a medium sized HCPhys -> GCPhys cache (hash?)
1074 * 2. write protect all shadowed pages. I.e. implement caching.
1075 */
1076 /*
1077 * Find the guest address.
1078 */
1079 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTXSUFF(pRamRanges);
1080 pRam;
1081 pRam = pRam->CTXSUFF(pNext))
1082 {
1083 unsigned iPage = pRam->cb >> PAGE_SHIFT;
1084 while (iPage-- > 0)
1085 {
1086 if ((pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) == HCPhys)
1087 {
1088 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1089 pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aHCPhys[iPage]);
1090 pShwPage->cPresent--;
1091 pPool->cPresent--;
1092 STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1093 return;
1094 }
1095 }
1096 }
1097
1098 for (;;)
1099 AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1100# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1101 pShwPage->cPresent--;
1102 pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1103# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1104}
1105
1106
1107/**
1108 * Update the tracking of shadowed pages.
1109 *
1110 * @param pVM The VM handle.
1111 * @param pShwPage The shadow page.
1112 * @param u16 The top 16-bit of the *pHCPhys.
1113 * @param pHCPhys Pointer to the ram range physical page entry.
1114 * @param iPTDst The index into the shadow table.
1115 */
1116DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PRTHCPHYS pHCPhys, const unsigned iPTDst)
1117{
1118# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1119 /*
1120 * We're making certain assumptions about the placement of cRef and idx.
1121 */
1122 Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1123 Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1124
1125 /*
1126 * Just deal with the simple first time here.
1127 */
1128 if (!u16)
1129 {
1130 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1131 u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) | pShwPage->idx;
1132 }
1133 else
1134 u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1135
1136 /* write back, trying to be clever... */
1137 Log2(("SyncPageWorkerTrackAddRef: u16=%#x *pHCPhys=%VHp->%VHp iPTDst=%#x\n",
1138 u16, *pHCPhys, (*pHCPhys & MM_RAM_FLAGS_NO_REFS_MASK) | ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1139 *((uint16_t *)pHCPhys + 3) = u16;
1140# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1141
1142 /* update statistics. */
1143 pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1144 pShwPage->cPresent++;
1145 if (pShwPage->iFirstPresent > iPTDst)
1146 pShwPage->iFirstPresent = iPTDst;
1147}
1148#endif /* PGMPOOL_WITH_USER_TRACKING */
1149
1150
1151/**
1152 * Creates a 4K shadow page for a guest page.
1153 *
1154 * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1155 * physical address. The PdeSrc argument only the flags are used. No page structured
1156 * will be mapped in this function.
1157 *
1158 * @param pVM VM handle.
1159 * @param pPteDst Destination page table entry.
1160 * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1161 * Can safely assume that only the flags are being used.
1162 * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1163 * @param pShwPage Pointer to the shadow page.
1164 * @param iPTDst The index into the shadow table.
1165 *
1166 * @remark Not used for 2/4MB pages!
1167 */
1168DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, VBOXPDE PdeSrc, VBOXPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1169{
1170 if (PteSrc.n.u1Present)
1171 {
1172 /*
1173 * Find the ram range.
1174 */
1175 PRTHCPHYS pHCPhys;
1176 int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, PteSrc.u & X86_PTE_PG_MASK, &pHCPhys);
1177 if (VBOX_SUCCESS(rc))
1178 {
1179 /** @todo investiage PWT, PCD and PAT. */
1180 /*
1181 * Make page table entry.
1182 */
1183 const RTHCPHYS HCPhys = *pHCPhys;
1184 SHWPTE PteDst;
1185 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
1186 {
1187 /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1188 if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL)))
1189 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1190 | (HCPhys & X86_PTE_PAE_PG_MASK);
1191 else
1192 PteDst.u = 0;
1193 /** @todo count these two kinds. */
1194 }
1195 else
1196 {
1197#ifdef PGM_SYNC_DIRTY_BIT
1198# ifdef PGM_SYNC_ACCESSED_BIT
1199 /*
1200 * If the page or page directory entry is not marked accessed,
1201 * we mark the page not present.
1202 */
1203 if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
1204 {
1205 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1206 PteDst.u = 0;
1207 }
1208 else
1209# endif
1210 /*
1211 * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1212 * when the page is modified.
1213 */
1214 if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1215 {
1216 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1217 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1218 | (HCPhys & X86_PTE_PAE_PG_MASK)
1219 | PGM_PTFLAGS_TRACK_DIRTY;
1220 }
1221 else
1222 {
1223 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1224 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1225 | (HCPhys & X86_PTE_PAE_PG_MASK);
1226 }
1227#endif
1228 }
1229
1230#ifdef PGMPOOL_WITH_USER_TRACKING
1231 /*
1232 * Keep user track up to date.
1233 */
1234 if (PteDst.n.u1Present)
1235 {
1236 if (!pPteDst->n.u1Present)
1237 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1238 else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1239 {
1240 Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1241 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1242 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1243 }
1244 }
1245 else if (pPteDst->n.u1Present)
1246 {
1247 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1248 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1249 }
1250#endif /* PGMPOOL_WITH_USER_TRACKING */
1251
1252 /*
1253 * Update statistics and commit the entry.
1254 */
1255 if (!PteSrc.n.u1Global)
1256 pShwPage->fSeenNonGlobal = true;
1257 *pPteDst = PteDst;
1258 }
1259 /* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1260 /** @todo count these. */
1261 }
1262 else
1263 {
1264 /*
1265 * Page not-present.
1266 */
1267#ifdef PGMPOOL_WITH_USER_TRACKING
1268 /* Keep user track up to date. */
1269 if (pPteDst->n.u1Present)
1270 {
1271 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1272 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1273 }
1274#endif /* PGMPOOL_WITH_USER_TRACKING */
1275 pPteDst->u = 0;
1276 /** @todo count these. */
1277 }
1278}
1279
1280
1281/**
1282 * Syncs a guest OS page.
1283 *
1284 * There are no conflicts at this point, neither is there any need for
1285 * page table allocations.
1286 *
1287 * @returns VBox status code.
1288 * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1289 * @param pVM VM handle.
1290 * @param PdeSrc Page directory entry of the guest.
1291 * @param GCPtrPage Guest context page address.
1292 * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1293 * @param uErr Fault error (X86_TRAP_PF_*).
1294 */
1295PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1296{
1297 LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1298
1299#if PGM_GST_TYPE == PGM_TYPE_32BIT
1300
1301# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1302# error "Invalid shadow mode for 32-bit guest mode!"
1303# endif
1304
1305 /*
1306 * Assert preconditions.
1307 */
1308# if GC_ARCH_BITS != 32
1309 Assert(GCPtrPage < _4G); //???
1310# endif
1311 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & X86_PD_MASK]);
1312 Assert(PdeSrc.n.u1Present);
1313 Assert(cPages);
1314
1315 /*
1316 * Get the shadow PDE, find the shadow page table in the pool.
1317 */
1318 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1319# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1320 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1321# else /* PAE */
1322 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1323# endif
1324 Assert(PdeDst.n.u1Present);
1325 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1326
1327 /*
1328 * Check that the page is present and that the shadow PDE isn't out of sync.
1329 */
1330 const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1331 RTGCPHYS GCPhys;
1332 if (!fBigPage)
1333 {
1334 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1335# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1336 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
1337# endif
1338 }
1339 else
1340 {
1341 GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1342# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1343 GCPhys |= GCPtrPage & X86_PAGE_2M_SIZE;
1344# endif
1345 }
1346 if ( pShwPage->GCPhys == GCPhys
1347 && PdeSrc.n.u1Present
1348 && (PdeSrc.n.u1User == PdeDst.n.u1User)
1349 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
1350 )
1351 {
1352# ifdef PGM_SYNC_ACCESSED_BIT
1353 /*
1354 * Check that the PDE is marked accessed already.
1355 * Since we set the accessed bit *before* getting here on a #PF, this
1356 * check is only meant for dealing with non-#PF'ing paths.
1357 */
1358 if (PdeSrc.n.u1Accessed)
1359# endif
1360 {
1361 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1362 if (!fBigPage)
1363 {
1364 /*
1365 * 4KB Page - Map the guest page table.
1366 */
1367 PVBOXPT pPTSrc;
1368 int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & X86_PDE_PG_MASK, &pPTSrc);
1369 if (VBOX_SUCCESS(rc))
1370 {
1371# ifdef PGM_SYNC_N_PAGES
1372 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1373 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1374 {
1375 /*
1376 * This code path is currently only taken when the caller is PGMTrap0eHandler
1377 * for non-present pages!
1378 *
1379 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1380 * deal with locality.
1381 */
1382 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1383# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1384 const unsigned offPTSrc = 0;
1385# else
1386 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1387# endif
1388 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1389 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1390 iPTDst = 0;
1391 else
1392 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1393 for (; iPTDst < iPTDstEnd; iPTDst++)
1394 {
1395 if (!pPTDst->a[iPTDst].n.u1Present)
1396 {
1397 VBOXPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1398 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1399 NOREF(GCPtrCurPage);
1400#ifndef IN_RING0
1401 /*
1402 * Assuming kernel code will be marked as supervisor - and not as user level
1403 * and executed using a conforming code selector - And marked as readonly.
1404 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
1405 */
1406 if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW | X86_PTE_US))
1407 || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1408 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1409 || PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
1410 MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE)
1411 )
1412#endif
1413 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1414 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1415 GCPtrCurPage, PteSrc.n.u1Present,
1416 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1417 PteSrc.n.u1User & PdeSrc.n.u1User,
1418 (uint64_t)PteSrc.u,
1419 (uint64_t)pPTDst->a[iPTDst].u,
1420 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1421 }
1422 }
1423 }
1424 else
1425# endif /* PGM_SYNC_N_PAGES */
1426 {
1427 const unsigned iPTSrc = (GCPtrPage >> X86_PT_SHIFT) & X86_PT_MASK;
1428 VBOXPTE PteSrc = pPTSrc->a[iPTSrc];
1429 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1430 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1431 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1432 GCPtrPage, PteSrc.n.u1Present,
1433 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1434 PteSrc.n.u1User & PdeSrc.n.u1User,
1435 (uint64_t)PteSrc.u,
1436 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1437 }
1438 }
1439 else /* MMIO or invalid page: emulated in #PF handler. */
1440 Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1441 }
1442 else
1443 {
1444 /*
1445 * 4/2MB page - lazy syncing shadow 4K pages.
1446 * (There are many causes of getting here, it's no longer only CSAM.)
1447 */
1448 /* Calculate the GC physical address of this 4KB shadow page. */
1449 RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & PAGE_OFFSET_MASK_BIG);
1450 /* Find ram range. */
1451 PRTHCPHYS pHCPhys;
1452 int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, GCPhys, &pHCPhys);
1453 if (VBOX_SUCCESS(rc))
1454 {
1455 /*
1456 * Make shadow PTE entry.
1457 */
1458 RTHCPHYS HCPhys = *pHCPhys;
1459 SHWPTE PteDst;
1460 PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1461 | (HCPhys & X86_PTE_PAE_PG_MASK);
1462 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
1463 {
1464 if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL)))
1465 PteDst.n.u1Write = 0;
1466 else
1467 PteDst.u = 0;
1468 }
1469 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1470# ifdef PGMPOOL_WITH_USER_TRACKING
1471 if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1472 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1473# endif
1474 pPTDst->a[iPTDst] = PteDst;
1475
1476
1477# ifdef PGM_SYNC_DIRTY_BIT
1478 /*
1479 * If the page is not flagged as dirty and is writable, then make it read-only
1480 * at PD level, so we can set the dirty bit when the page is modified.
1481 *
1482 * ASSUMES that page access handlers are implemented on page table entry level.
1483 * Thus we will first catch the dirty access and set PDE.D and restart. If
1484 * there is an access handler, we'll trap again and let it work on the problem.
1485 */
1486 /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1487 * As for invlpg, it simply frees the whole shadow PT.
1488 * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1489 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1490 {
1491 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1492 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1493 PdeDst.n.u1Write = 0;
1494 }
1495 else
1496 {
1497 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1498 PdeDst.n.u1Write = PdeSrc.n.u1Write;
1499 }
1500# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1501 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1502# else /* PAE */
1503 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1504# endif
1505# endif /* PGM_SYNC_DIRTY_BIT */
1506 Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1507 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1508 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1509 }
1510 }
1511 return VINF_SUCCESS;
1512 }
1513# ifdef PGM_SYNC_ACCESSED_BIT
1514 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1515#endif
1516 }
1517 else
1518 {
1519 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1520 Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1521 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1522 }
1523
1524 /*
1525 * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1526 * Yea, I'm lazy.
1527 */
1528 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1529# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1530 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1531# else /* PAE */
1532 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1533# endif
1534 PGM_INVL_GUEST_TLBS();
1535 return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1536
1537#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
1538
1539# ifdef PGM_SYNC_N_PAGES
1540 /*
1541 * Get the shadow PDE, find the shadow page table in the pool.
1542 */
1543 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1544# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1545 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1546# else /* PAE */
1547 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1548# endif
1549 Assert(PdeDst.n.u1Present);
1550 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1551 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1552
1553# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1554 const unsigned offPTSrc = 0;
1555# else
1556 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1557# endif
1558
1559 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1560 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1561 {
1562 /*
1563 * This code path is currently only taken when the caller is PGMTrap0eHandler
1564 * for non-present pages!
1565 *
1566 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1567 * deal with locality.
1568 */
1569 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1570 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1571 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1572 iPTDst = 0;
1573 else
1574 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1575 for (; iPTDst < iPTDstEnd; iPTDst++)
1576 {
1577 if (!pPTDst->a[iPTDst].n.u1Present)
1578 {
1579 VBOXPTE PteSrc;
1580
1581 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1582
1583 /* Fake the page table entry */
1584 PteSrc.u = GCPtrCurPage;
1585 PteSrc.n.u1Present = 1;
1586 PteSrc.n.u1Dirty = 1;
1587 PteSrc.n.u1Accessed = 1;
1588 PteSrc.n.u1Write = 1;
1589 PteSrc.n.u1User = 1;
1590
1591 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1592
1593 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1594 GCPtrCurPage, PteSrc.n.u1Present,
1595 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1596 PteSrc.n.u1User & PdeSrc.n.u1User,
1597 (uint64_t)PteSrc.u,
1598 (uint64_t)pPTDst->a[iPTDst].u,
1599 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1600 }
1601 }
1602 }
1603 else
1604# endif /* PGM_SYNC_N_PAGES */
1605 {
1606 VBOXPTE PteSrc;
1607 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1608 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1609
1610 /* Fake the page table entry */
1611 PteSrc.u = GCPtrCurPage;
1612 PteSrc.n.u1Present = 1;
1613 PteSrc.n.u1Dirty = 1;
1614 PteSrc.n.u1Accessed = 1;
1615 PteSrc.n.u1Write = 1;
1616 PteSrc.n.u1User = 1;
1617 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1618
1619 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1620 GCPtrPage, PteSrc.n.u1Present,
1621 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1622 PteSrc.n.u1User & PdeSrc.n.u1User,
1623 (uint64_t)PteSrc.u,
1624 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1625 }
1626 return VINF_SUCCESS;
1627
1628#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1629 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1630 return VERR_INTERNAL_ERROR;
1631#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1632}
1633
1634
1635
1636#if PGM_WITH_PAGING(PGM_GST_TYPE)
1637
1638# ifdef PGM_SYNC_DIRTY_BIT
1639
1640/**
1641 * Investigate page fault and handle write protection page faults caused by
1642 * dirty bit tracking.
1643 *
1644 * @returns VBox status code.
1645 * @param pVM VM handle.
1646 * @param uErr Page fault error code.
1647 * @param pPdeDst Shadow page directory entry.
1648 * @param pPdeSrc Guest page directory entry.
1649 * @param GCPtrPage Guest context page address.
1650 */
1651PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1652{
1653 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1654 LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1655
1656 /*
1657 * Real page fault?
1658 */
1659 if ( (uErr & X86_TRAP_PF_RSVD)
1660 || !pPdeSrc->n.u1Present
1661 || ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1662 || ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1663 {
1664# ifdef IN_GC
1665 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1666# endif
1667 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1668 LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1669
1670 if (pPdeSrc->n.u1Present)
1671 {
1672 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1673 * See the 2nd case below as well.
1674 */
1675 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1676 {
1677 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1678 }
1679 else
1680 {
1681 /*
1682 * Map the guest page table.
1683 */
1684 PVBOXPT pPTSrc;
1685 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1686 if (VBOX_SUCCESS(rc))
1687 {
1688 PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1689 const VBOXPTE PteSrc = *pPteSrc;
1690 if (pPteSrc->n.u1Present)
1691 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1692 }
1693 AssertRC(rc);
1694 }
1695 }
1696 return VINF_EM_RAW_GUEST_TRAP;
1697 }
1698
1699 /*
1700 * First check the easy case where the page directory has been marked read-only to track
1701 * the dirty bit of an emulated BIG page
1702 */
1703 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1704 {
1705 /* Mark guest page directory as accessed */
1706 pPdeSrc->b.u1Accessed = 1;
1707
1708 /*
1709 * Only write protection page faults are relevant here.
1710 */
1711 if (uErr & X86_TRAP_PF_RW)
1712 {
1713 /* Mark guest page directory as dirty (BIG page only). */
1714 pPdeSrc->b.u1Dirty = 1;
1715
1716 if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1717 {
1718 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1719
1720 Assert(pPdeSrc->b.u1Write);
1721
1722 pPdeDst->n.u1Write = 1;
1723 pPdeDst->n.u1Accessed = 1;
1724 pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1725 PGM_INVL_BIG_PG(GCPtrPage);
1726 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1727 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1728 }
1729 }
1730 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1731 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1732 }
1733 /* else: 4KB page table */
1734
1735 /*
1736 * Map the guest page table.
1737 */
1738 PVBOXPT pPTSrc;
1739 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1740 if (VBOX_SUCCESS(rc))
1741 {
1742 /*
1743 * Real page fault?
1744 */
1745 PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1746 const VBOXPTE PteSrc = *pPteSrc;
1747 if ( !PteSrc.n.u1Present
1748 || ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1749 || ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1750 )
1751 {
1752# ifdef IN_GC
1753 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1754# endif
1755 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1756 LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1757
1758 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1759 * See the 2nd case above as well.
1760 */
1761 if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1762 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1763
1764 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1765 return VINF_EM_RAW_GUEST_TRAP;
1766 }
1767 LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1768
1769 /*
1770 * Set the accessed bits in the page directory and the page table.
1771 */
1772 pPdeSrc->n.u1Accessed = 1;
1773 pPteSrc->n.u1Accessed = 1;
1774
1775 /*
1776 * Only write protection page faults are relevant here.
1777 */
1778 if (uErr & X86_TRAP_PF_RW)
1779 {
1780 /* Write access, so mark guest entry as dirty. */
1781# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1782 if (!pPteSrc->n.u1Dirty)
1783 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1784 else
1785 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1786# endif
1787 pPteSrc->n.u1Dirty = 1;
1788
1789 if (pPdeDst->n.u1Present)
1790 {
1791 /* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1792 * Our individual shadow handlers will provide more information and force a fatal exit.
1793 */
1794 if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1795 {
1796 LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1797 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1798 return VINF_SUCCESS;
1799 }
1800
1801 /*
1802 * Map shadow page table.
1803 */
1804 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1805 if (pShwPage)
1806 {
1807 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1808 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1809 if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1810 && (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1811 {
1812 LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1813# ifdef VBOX_STRICT
1814 RTHCPHYS HCPhys;
1815 rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, pPteSrc->u & X86_PTE_PG_MASK, &HCPhys);
1816 if (VBOX_SUCCESS(rc))
1817 AssertMsg(!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE)),
1818 ("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1819# endif
1820 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1821
1822 Assert(pPteSrc->n.u1Write);
1823
1824 pPteDst->n.u1Write = 1;
1825 pPteDst->n.u1Dirty = 1;
1826 pPteDst->n.u1Accessed = 1;
1827 pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1828 PGM_INVL_PG(GCPtrPage);
1829
1830 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1831 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1832 }
1833 }
1834 else
1835 AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1836 }
1837 }
1838/** @todo Optimize accessed bit emulation? */
1839# ifdef VBOX_STRICT
1840 /*
1841 * Sanity check.
1842 */
1843 else if ( !pPteSrc->n.u1Dirty
1844 && (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1845 && pPdeDst->n.u1Present)
1846 {
1847 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1848 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1849 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1850 if ( pPteDst->n.u1Present
1851 && pPteDst->n.u1Write)
1852 LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1853 }
1854# endif /* VBOX_STRICT */
1855 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1856 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1857 }
1858 AssertRC(rc);
1859 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1860 return rc;
1861}
1862
1863# endif
1864
1865#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1866
1867
1868/**
1869 * Sync a shadow page table.
1870 *
1871 * The shadow page table is not present. This includes the case where
1872 * there is a conflict with a mapping.
1873 *
1874 * @returns VBox status code.
1875 * @param pVM VM handle.
1876 * @param iPD Page directory index.
1877 * @param pPDSrc Source page directory (i.e. Guest OS page directory).
1878 * Assume this is a temporary mapping.
1879 * @param GCPtrPage GC Pointer of the page that caused the fault
1880 */
1881PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage)
1882{
1883 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1884 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1885 LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1886
1887#if PGM_GST_TYPE == PGM_TYPE_32BIT
1888
1889# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1890# error "Invalid shadow mode for 32-bit guest mode!"
1891# endif
1892
1893 /*
1894 * Validate input a little bit.
1895 */
1896 Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1897# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1898 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1899# else
1900 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1901# endif
1902 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1903 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1904 SHWPDE PdeDst = *pPdeDst;
1905
1906 /*
1907 * Check for conflicts.
1908 * GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1909 * HC: Simply resolve the conflict.
1910 */
1911 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1912 {
1913 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1914# ifndef IN_RING3
1915 Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1916 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1917 return VERR_ADDRESS_CONFLICT;
1918# else
1919 PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1920 Assert(pMapping);
1921 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1922 if (VBOX_FAILURE(rc))
1923 {
1924 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1925 return rc;
1926 }
1927 PdeDst = *pPdeDst;
1928# endif
1929 }
1930 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1931
1932 /*
1933 * Sync page directory entry.
1934 */
1935 int rc = VINF_SUCCESS;
1936 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1937 if (PdeSrc.n.u1Present)
1938 {
1939 /*
1940 * Allocate & map the page table.
1941 */
1942 PSHWPT pPTDst;
1943 const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1944 PPGMPOOLPAGE pShwPage;
1945 RTGCPHYS GCPhys;
1946 if (fPageTable)
1947 {
1948 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1949# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1950 GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
1951# endif
1952 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1953 }
1954 else
1955 {
1956 GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1957# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1958 GCPhys |= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
1959# endif
1960 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1961 }
1962 if (rc == VINF_SUCCESS)
1963 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1964 else if (rc == VINF_PGM_CACHED_PAGE)
1965 {
1966 /*
1967 * The PT was cached, just hook it up.
1968 */
1969 if (fPageTable)
1970 PdeDst.u = pShwPage->Core.Key
1971 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1972 else
1973 {
1974 PdeDst.u = pShwPage->Core.Key
1975 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1976# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1977 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1978 {
1979 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1980 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1981 PdeDst.b.u1Write = 0;
1982 }
1983# endif
1984 }
1985 *pPdeDst = PdeDst;
1986 return VINF_SUCCESS;
1987 }
1988 else if (rc == VERR_PGM_POOL_FLUSHED)
1989 return VINF_PGM_SYNC_CR3;
1990 else
1991 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1992 PdeDst.u &= X86_PDE_AVL_MASK;
1993 PdeDst.u |= pShwPage->Core.Key;
1994
1995# ifdef PGM_SYNC_DIRTY_BIT
1996 /*
1997 * Page directory has been accessed (this is a fault situation, remember).
1998 */
1999 pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2000# endif
2001 if (fPageTable)
2002 {
2003 /*
2004 * Page table - 4KB.
2005 *
2006 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2007 */
2008 Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2009 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2010 PGSTPT pPTSrc;
2011 rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2012 if (VBOX_SUCCESS(rc))
2013 {
2014 /*
2015 * Start by syncing the page directory entry so CSAM's TLB trick works.
2016 */
2017 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK))
2018 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2019 *pPdeDst = PdeDst;
2020
2021 /*
2022 * Directory/page user or supervisor privilege: (same goes for read/write)
2023 *
2024 * Directory Page Combined
2025 * U/S U/S U/S
2026 * 0 0 0
2027 * 0 1 0
2028 * 1 0 0
2029 * 1 1 1
2030 *
2031 * Simple AND operation. Table listed for completeness.
2032 *
2033 */
2034 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2035# ifdef PGM_SYNC_N_PAGES
2036 unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2037 unsigned iPTDst = iPTBase;
2038 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2039 if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2040 iPTDst = 0;
2041 else
2042 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2043# else /* !PGM_SYNC_N_PAGES */
2044 unsigned iPTDst = 0;
2045 const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2046# endif /* !PGM_SYNC_N_PAGES */
2047# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2048 const unsigned offPTSrc = 0;
2049# else
2050 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2051# endif
2052 for (; iPTDst < iPTDstEnd; iPTDst++)
2053 {
2054 const unsigned iPTSrc = iPTDst + offPTSrc;
2055 const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2056
2057 if (PteSrc.n.u1Present) /* we've already cleared it above */
2058 {
2059#ifndef IN_RING0
2060 /*
2061 * Assuming kernel code will be marked as supervisor - and not as user level
2062 * and executed using a conforming code selector - And marked as readonly.
2063 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2064 */
2065 if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
2066 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)))
2067 || PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
2068 MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE)
2069 )
2070#endif
2071 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2072 Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2073 (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)),
2074 PteSrc.n.u1Present,
2075 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2076 PteSrc.n.u1User & PdeSrc.n.u1User,
2077 (uint64_t)PteSrc.u,
2078 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2079 (PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2080 }
2081 } /* for PTEs */
2082 }
2083 }
2084 else
2085 {
2086 /*
2087 * Big page - 2/4MB.
2088 *
2089 * We'll walk the ram range list in parallel and optimize lookups.
2090 * We will only sync on shadow page table at a time.
2091 */
2092 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2093
2094 /**
2095 * @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2096 */
2097
2098 /*
2099 * Start by syncing the page directory entry.
2100 */
2101 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2102 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2103
2104# ifdef PGM_SYNC_DIRTY_BIT
2105 /*
2106 * If the page is not flagged as dirty and is writable, then make it read-only
2107 * at PD level, so we can set the dirty bit when the page is modified.
2108 *
2109 * ASSUMES that page access handlers are implemented on page table entry level.
2110 * Thus we will first catch the dirty access and set PDE.D and restart. If
2111 * there is an access handler, we'll trap again and let it work on the problem.
2112 */
2113 /** @todo move the above stuff to a section in the PGM documentation. */
2114 Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2115 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2116 {
2117 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2118 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2119 PdeDst.b.u1Write = 0;
2120 }
2121# endif /* PGM_SYNC_DIRTY_BIT */
2122 *pPdeDst = PdeDst;
2123
2124 /*
2125 * Fill the shadow page table.
2126 */
2127 /* Get address and flags from the source PDE. */
2128 SHWPTE PteDstBase;
2129 PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
2130
2131 /* Loop thru the entries in the shadow PT. */
2132 const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2133 Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2134 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2135 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2136 PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
2137 unsigned iPTDst = 0;
2138 while (iPTDst < ELEMENTS(pPTDst->a))
2139 {
2140 /* Advance ram range list. */
2141 while (pRam && GCPhys > pRam->GCPhysLast)
2142 pRam = CTXSUFF(pRam->pNext);
2143 if (pRam && GCPhys >= pRam->GCPhys)
2144 {
2145 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2146 do
2147 {
2148 /* Make shadow PTE. */
2149 RTHCPHYS HCPhys = pRam->aHCPhys[iHCPage];
2150 SHWPTE PteDst;
2151
2152 /* Make sure the RAM has already been allocated. */
2153 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2154 {
2155 if (RT_UNLIKELY(!(pRam->aHCPhys[iHCPage] & X86_PTE_PAE_PG_MASK)))
2156 {
2157# ifdef IN_RING3
2158 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2159# else
2160 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2161# endif
2162 if (rc != VINF_SUCCESS)
2163 return rc;
2164
2165 HCPhys = pRam->aHCPhys[iHCPage];
2166 }
2167 }
2168
2169 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
2170 {
2171 if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL)))
2172 {
2173 PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) | PteDstBase.u;
2174 PteDst.n.u1Write = 0;
2175 }
2176 else
2177 PteDst.u = 0;
2178 }
2179# ifndef IN_RING0
2180 /*
2181 * Assuming kernel code will be marked as supervisor and not as user level and executed
2182 * using a conforming code selector. Don't check for readonly, as that implies the whole
2183 * 4MB can be code or readonly data. Linux enables write access for its large pages.
2184 */
2185 else if ( !PdeSrc.n.u1User
2186 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))))
2187 PteDst.u = 0;
2188# endif
2189 else
2190 PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) | PteDstBase.u;
2191# ifdef PGMPOOL_WITH_USER_TRACKING
2192 if (PteDst.n.u1Present)
2193 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, &pRam->aHCPhys[iHCPage], iPTDst);
2194# endif
2195 /* commit it */
2196 pPTDst->a[iPTDst] = PteDst;
2197 Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2198 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2199 PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2200
2201 /* advance */
2202 GCPhys += PAGE_SIZE;
2203 iHCPage++;
2204 iPTDst++;
2205 } while ( iPTDst < ELEMENTS(pPTDst->a)
2206 && GCPhys <= pRam->GCPhysLast);
2207 }
2208 else if (pRam)
2209 {
2210 Log(("Invalid pages at %VGp\n", GCPhys));
2211 do
2212 {
2213 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2214 GCPhys += PAGE_SIZE;
2215 iPTDst++;
2216 } while ( iPTDst < ELEMENTS(pPTDst->a)
2217 && GCPhys < pRam->GCPhys);
2218 }
2219 else
2220 {
2221 Log(("Invalid pages at %VGp (2)\n", GCPhys));
2222 for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2223 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2224 }
2225 } /* while more PTEs */
2226 } /* 4KB / 4MB */
2227 }
2228 else
2229 AssertRelease(!PdeDst.n.u1Present);
2230
2231 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2232# ifdef IN_GC
2233 if (VBOX_FAILURE(rc))
2234 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2235# endif
2236 return rc;
2237
2238#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
2239
2240 int rc = VINF_SUCCESS;
2241
2242 /*
2243 * Validate input a little bit.
2244 */
2245# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2246 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2247# else
2248 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2249# endif
2250 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2251 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2252 SHWPDE PdeDst = *pPdeDst;
2253
2254 Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2255 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2256
2257 VBOXPDE PdeSrc;
2258 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2259 PdeSrc.n.u1Present = 1;
2260 PdeSrc.n.u1Write = 1;
2261 PdeSrc.n.u1Accessed = 1;
2262 PdeSrc.n.u1User = 1;
2263
2264 /*
2265 * Allocate & map the page table.
2266 */
2267 PSHWPT pPTDst;
2268 PPGMPOOLPAGE pShwPage;
2269 RTGCPHYS GCPhys;
2270
2271 /* Virtual address = physical address */
2272 GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2273 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2274
2275 if ( rc == VINF_SUCCESS
2276 || rc == VINF_PGM_CACHED_PAGE)
2277 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2278 else
2279 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2280
2281 PdeDst.u &= X86_PDE_AVL_MASK;
2282 PdeDst.u |= pShwPage->Core.Key;
2283 PdeDst.n.u1Present = 1;
2284 *pPdeDst = PdeDst;
2285
2286 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2287 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2288 return rc;
2289
2290#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2291
2292 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2293 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2294 return VERR_INTERNAL_ERROR;
2295#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2296}
2297
2298
2299
2300/**
2301 * Prefetch a page/set of pages.
2302 *
2303 * Typically used to sync commonly used pages before entering raw mode
2304 * after a CR3 reload.
2305 *
2306 * @returns VBox status code.
2307 * @param pVM VM handle.
2308 * @param GCPtrPage Page to invalidate.
2309 */
2310PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2311{
2312#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2313
2314# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2315# error "Invalid shadow mode for 32-bit guest mode!"
2316# endif
2317
2318 /*
2319 * Check that all Guest levels thru the PDE are present, getting the
2320 * PD and PDE in the processes.
2321 */
2322 int rc = VINF_SUCCESS;
2323# if PGM_WITH_PAGING(PGM_GST_TYPE)
2324 PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2325 const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2326# else
2327 PVBOXPD pPDSrc = NULL;
2328 const unsigned iPDSrc = 0;
2329# endif
2330
2331# if PGM_WITH_PAGING(PGM_GST_TYPE)
2332 const VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2333# else
2334 VBOXPDE PdeSrc;
2335 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2336 PdeSrc.n.u1Present = 1;
2337 PdeSrc.n.u1Write = 1;
2338 PdeSrc.n.u1Accessed = 1;
2339 PdeSrc.n.u1User = 1;
2340# endif
2341
2342# ifdef PGM_SYNC_ACCESSED_BIT
2343 if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2344# else
2345 if (PdeSrc.n.u1Present)
2346# endif
2347 {
2348# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2349 const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2350# else
2351 const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2352# endif
2353 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2354 {
2355 if (!PdeDst.n.u1Present)
2356 /** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2357 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2358 else
2359 {
2360 /** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2361 * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2362 * makes no sense to prefetch more than one page.
2363 */
2364 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2365 if (VBOX_SUCCESS(rc))
2366 rc = VINF_SUCCESS;
2367 }
2368 }
2369 }
2370 return rc;
2371
2372#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2373
2374 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2375 return VERR_INTERNAL_ERROR;
2376#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2377}
2378
2379
2380
2381
2382/**
2383 * Syncs a page during a PGMVerifyAccess() call.
2384 *
2385 * @returns VBox status code (informational included).
2386 * @param GCPtrPage The address of the page to sync.
2387 * @param fPage The effective guest page flags.
2388 * @param uErr The trap error code.
2389 */
2390PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2391{
2392 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2393
2394#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2395
2396# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2397# error "Invalid shadow mode for 32-bit guest mode!"
2398# endif
2399
2400#ifndef IN_RING0
2401 if (!(fPage & X86_PTE_US))
2402 {
2403 /*
2404 * Mark this page as safe.
2405 */
2406 /** @todo not correct for pages that contain both code and data!! */
2407 Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2408 CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2409 }
2410#endif
2411 /*
2412 * Get guest PD and index.
2413 */
2414 unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2415 PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2416 int rc = VINF_SUCCESS;
2417
2418 /*
2419 * First check if the shadow pd is present.
2420 */
2421# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2422 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2423# else
2424 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2425# endif
2426 if (!pPdeDst->n.u1Present)
2427 {
2428 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2429 AssertRC(rc);
2430 if (rc != VINF_SUCCESS)
2431 return rc;
2432 }
2433
2434# if PGM_WITH_PAGING(PGM_GST_TYPE)
2435 /* Check for dirty bit fault */
2436 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2437 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2438 Log(("PGMVerifyAccess: success (dirty)\n"));
2439 else
2440 {
2441 VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2442#else
2443 {
2444 VBOXPDE PdeSrc;
2445 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2446 PdeSrc.n.u1Present = 1;
2447 PdeSrc.n.u1Write = 1;
2448 PdeSrc.n.u1Accessed = 1;
2449 PdeSrc.n.u1User = 1;
2450
2451#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2452 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2453 if (uErr & X86_TRAP_PF_US)
2454 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2455 else /* supervisor */
2456 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2457
2458 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2459 if (VBOX_SUCCESS(rc))
2460 {
2461 /* Page was successfully synced */
2462 Log(("PGMVerifyAccess: success (sync)\n"));
2463 rc = VINF_SUCCESS;
2464 }
2465 else
2466 {
2467 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2468 return VINF_EM_RAW_GUEST_TRAP;
2469 }
2470 }
2471 return rc;
2472
2473#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2474
2475 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2476 return VERR_INTERNAL_ERROR;
2477#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2478}
2479
2480
2481#if PGM_GST_TYPE == PGM_TYPE_32BIT
2482# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2483/**
2484 * Figures out which kind of shadow page this guest PDE warrants.
2485 *
2486 * @returns Shadow page kind.
2487 * @param pPdeSrc The guest PDE in question.
2488 * @param cr4 The current guest cr4 value.
2489 */
2490DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const VBOXPDE *pPdeSrc, uint32_t cr4)
2491{
2492 if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE))
2493 return BTH_PGMPOOLKIND_PT_FOR_PT;
2494 //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
2495 //{
2496 // case 0:
2497 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2498 // case X86_PDE4M_RW:
2499 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2500 // case X86_PDE4M_US:
2501 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2502 // case X86_PDE4M_RW | X86_PDE4M_US:
2503 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2504# if 0
2505 // case X86_PDE4M_PAE_NX:
2506 // return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2507 // case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
2508 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2509 // case X86_PDE4M_US | X86_PDE4M_PAE_NX:
2510 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2511 // case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
2512 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2513# endif
2514 return BTH_PGMPOOLKIND_PT_FOR_BIG;
2515 //}
2516}
2517# endif
2518#endif
2519
2520#undef MY_STAM_COUNTER_INC
2521#define MY_STAM_COUNTER_INC(a) do { } while (0)
2522
2523
2524/**
2525 * Syncs the paging hierarchy starting at CR3.
2526 *
2527 * @returns VBox status code, no specials.
2528 * @param pVM The virtual machine.
2529 * @param cr0 Guest context CR0 register
2530 * @param cr3 Guest context CR3 register
2531 * @param cr4 Guest context CR4 register
2532 * @param fGlobal Including global page directories or not
2533 */
2534PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2535{
2536#if PGM_GST_TYPE == PGM_TYPE_32BIT
2537# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2538 if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2539 fGlobal = true; /* Change this CR3 reload to be a global one. */
2540# endif
2541#endif
2542
2543 /*
2544 * Update page access handlers.
2545 * The virtual are always flushed, while the physical are only on demand.
2546 * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2547 * have to look into that later because it will have a bad influence on the performance.
2548 * @note SvL: There's no need for that. Just invalidate the virtual range(s).
2549 * bird: Yes, but that won't work for aliases.
2550 */
2551 /** @todo this MUST go away. See #1557. */
2552 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2553 PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2554 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2555
2556#ifdef PGMPOOL_WITH_MONITORING
2557 /*
2558 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2559 * Occationally we will have to clear all the shadow page tables because we wanted
2560 * to monitor a page which was mapped by too many shadowed page tables. This operation
2561 * sometimes refered to as a 'lightweight flush'.
2562 */
2563 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2564 pgmPoolMonitorModifiedClearAll(pVM);
2565 else
2566 {
2567# ifdef IN_RING3
2568 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2569 pgmPoolClearAll(pVM);
2570# else
2571 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2572 return VINF_PGM_SYNC_CR3;
2573# endif
2574 }
2575#endif
2576
2577 Assert(fGlobal || (cr4 & X86_CR4_PGE));
2578 MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2579
2580#if PGM_GST_TYPE == PGM_TYPE_32BIT
2581# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2582 /*
2583 * Get page directory addresses.
2584 */
2585# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2586 PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2587# else
2588 PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2589# endif
2590 PVBOXPD pPDSrc = pVM->pgm.s.CTXSUFF(pGuestPD);
2591
2592 Assert(pPDSrc);
2593#ifndef IN_GC
2594 Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2595#endif
2596
2597 /*
2598 * Iterate the page directory.
2599 */
2600 PPGMMAPPING pMapping;
2601 unsigned iPdNoMapping;
2602 const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2603 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2604
2605 /* Only check mappings if they are supposed to be put into the shadow page table. */
2606 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2607 {
2608 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2609 iPdNoMapping = (pMapping) ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2610 }
2611 else
2612 {
2613 pMapping = 0;
2614 iPdNoMapping = ~0U;
2615 }
2616
2617 for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2618 {
2619# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2620 Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2621# else
2622 Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2623# endif
2624 register VBOXPDE PdeSrc = pPDSrc->a[iPD];
2625 if ( PdeSrc.n.u1Present
2626 && (PdeSrc.n.u1User || fRawR0Enabled))
2627 {
2628 /*
2629 * Check for conflicts with GC mappings.
2630 */
2631 if (iPD == iPdNoMapping)
2632 {
2633 if (pVM->pgm.s.fMappingsFixed)
2634 {
2635 /* It's fixed, just skip the mapping. */
2636 const unsigned cPTs = pMapping->cPTs;
2637 iPD += cPTs - 1;
2638 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2639 pMapping = pMapping->CTXALLSUFF(pNext);
2640 iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2641 continue;
2642 }
2643
2644#ifdef IN_RING3
2645 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2646 if (VBOX_FAILURE(rc))
2647 return rc;
2648
2649 /*
2650 * Update iPdNoMapping and pMapping.
2651 */
2652 pMapping = pVM->pgm.s.pMappingsR3;
2653 while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2654 pMapping = pMapping->pNextR3;
2655 iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2656#else
2657 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2658 return VINF_PGM_SYNC_CR3;
2659#endif
2660 }
2661
2662 /*
2663 * Sync page directory entry.
2664 *
2665 * The current approach is to allocated the page table but to set
2666 * the entry to not-present and postpone the page table synching till
2667 * it's actually used.
2668 */
2669# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2670 const unsigned iPdShw = iPD; NOREF(iPdShw);
2671# else
2672 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2673# endif
2674 {
2675 SHWPDE PdeDst = *pPDEDst;
2676 if (PdeDst.n.u1Present)
2677 {
2678 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2679 RTGCPHYS GCPhys;
2680 if ( !PdeSrc.b.u1Size
2681 || !(cr4 & X86_CR4_PSE))
2682 {
2683 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2684# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2685 GCPhys |= i * (PAGE_SIZE / 2);
2686# endif
2687 }
2688 else
2689 {
2690 GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
2691# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2692 GCPhys |= i * X86_PAGE_2M_SIZE;
2693# endif
2694 }
2695
2696 if ( pShwPage->GCPhys == GCPhys
2697 && pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2698 && ( pShwPage->fCached
2699 || ( !fGlobal
2700 && ( false
2701# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2702 || ( (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2703 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */
2704 || ( !pShwPage->fSeenNonGlobal
2705 && (cr4 & X86_CR4_PGE))
2706# endif
2707 )
2708 )
2709 )
2710 && ( (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW))
2711 || ( (cr4 & X86_CR4_PSE)
2712 && ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY)
2713 == ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS))
2714 )
2715 )
2716 {
2717# ifdef VBOX_WITH_STATISTICS
2718 if ( !fGlobal
2719 && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2720 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE))
2721 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2722 else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2723 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2724 else
2725 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2726# endif /* VBOX_WITH_STATISTICS */
2727/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2728 * The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2729//# ifdef PGMPOOL_WITH_CACHE
2730// pgmPoolCacheUsed(pPool, pShwPage);
2731//# endif
2732 }
2733 else
2734 {
2735 pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2736 pPDEDst->u = 0;
2737 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2738 }
2739 }
2740 else
2741 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2742 pPDEDst++;
2743 }
2744 }
2745 else if (iPD != iPdNoMapping)
2746 {
2747 /*
2748 * Check if there is any page directory to mark not present here.
2749 */
2750# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2751 const unsigned iPdShw = iPD; NOREF(iPdShw);
2752# else
2753 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2754# endif
2755 {
2756 if (pPDEDst->n.u1Present)
2757 {
2758 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2759 pPDEDst->u = 0;
2760 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2761 }
2762 pPDEDst++;
2763 }
2764 }
2765 else
2766 {
2767 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2768 const unsigned cPTs = pMapping->cPTs;
2769 if (pVM->pgm.s.fMappingsFixed)
2770 {
2771 /* It's fixed, just skip the mapping. */
2772 pMapping = pMapping->CTXALLSUFF(pNext);
2773 iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2774 }
2775 else
2776 {
2777 /*
2778 * Check for conflicts for subsequent pagetables
2779 * and advance to the next mapping.
2780 */
2781 iPdNoMapping = ~0U;
2782 unsigned iPT = cPTs;
2783 while (iPT-- > 1)
2784 {
2785 if ( pPDSrc->a[iPD + iPT].n.u1Present
2786 && (pPDSrc->a[iPD + iPT].n.u1User || fRawR0Enabled))
2787 {
2788# ifdef IN_RING3
2789 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2790 if (VBOX_FAILURE(rc))
2791 return rc;
2792
2793 /*
2794 * Update iPdNoMapping and pMapping.
2795 */
2796 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2797 while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2798 pMapping = pMapping->CTXALLSUFF(pNext);
2799 iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2800 break;
2801# else
2802 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2803 return VINF_PGM_SYNC_CR3;
2804# endif
2805 }
2806 }
2807 if (iPdNoMapping == ~0U && pMapping)
2808 {
2809 pMapping = pMapping->CTXALLSUFF(pNext);
2810 if (pMapping)
2811 iPdNoMapping = pMapping->GCPtr >> PGDIR_SHIFT;
2812 }
2813 }
2814 /* advance. */
2815 iPD += cPTs - 1;
2816 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2817 }
2818
2819 } /* for iPD */
2820# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2821# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2822# endif
2823
2824 return VINF_SUCCESS;
2825
2826#elif PGM_GST_TYPE == PGM_TYPE_PAE
2827# if PGM_SHW_TYPE == PGM_TYPE_PAE
2828//# error not implemented
2829 return VERR_INTERNAL_ERROR;
2830
2831# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2832# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2833# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2834
2835#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2836# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2837//# error not implemented
2838 return VERR_INTERNAL_ERROR;
2839
2840# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2841# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2842# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2843
2844#else /* guest real and protected mode */
2845
2846 return VINF_SUCCESS;
2847#endif
2848}
2849
2850
2851
2852
2853#ifdef VBOX_STRICT
2854#ifdef IN_GC
2855# undef AssertMsgFailed
2856# define AssertMsgFailed Log
2857#endif
2858#ifdef IN_RING3
2859# include <VBox/dbgf.h>
2860
2861/**
2862 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2863 *
2864 * @returns VBox status code (VINF_SUCCESS).
2865 * @param pVM The VM handle.
2866 * @param cr3 The root of the hierarchy.
2867 * @param crr The cr4, only PAE and PSE is currently used.
2868 * @param fLongMode Set if long mode, false if not long mode.
2869 * @param cMaxDepth Number of levels to dump.
2870 * @param pHlp Pointer to the output functions.
2871 */
2872__BEGIN_DECLS
2873PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2874__END_DECLS
2875
2876#endif
2877
2878/**
2879 * Checks that the shadow page table is in sync with the guest one.
2880 *
2881 * @returns The number of errors.
2882 * @param pVM The virtual machine.
2883 * @param cr3 Guest context CR3 register
2884 * @param cr4 Guest context CR4 register
2885 * @param GCPtr Where to start. Defaults to 0.
2886 * @param cb How much to check. Defaults to everything.
2887 */
2888PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2889{
2890 unsigned cErrors = 0;
2891
2892#if PGM_GST_TYPE == PGM_TYPE_32BIT
2893
2894# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2895# error "Invalid shadow mode for 32-bit guest paging."
2896# endif
2897
2898 PPGM pPGM = &pVM->pgm.s;
2899 RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2900 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2901 RTHCPHYS HCPhys; /* general usage. */
2902 int rc;
2903
2904 /*
2905 * Check that the Guest CR3 and all it's mappings are correct.
2906 */
2907 AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
2908 ("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2909 false);
2910 rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2911 AssertRCReturn(rc, 1);
2912 rc = PGMRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
2913 AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2914# ifndef IN_GC
2915 RTGCPHYS GCPhys;
2916 rc = PGMPhysHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2917 AssertRCReturn(rc, 1);
2918 AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2919# endif
2920 const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2921
2922 /*
2923 * Get and check the Shadow CR3.
2924 */
2925# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2926 const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2927 unsigned cPDEs = ELEMENTS(pPDDst->a);
2928# else
2929 const X86PDPAE *pPDDst = pPGM->CTXMID(ap,PaePDs[0]); /* use it as a 2048 entry PD */
2930 unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2931# endif
2932 if (cb != ~(RTGCUINTPTR)0)
2933 cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2934
2935/** @todo call the other two PGMAssert*() functions. */
2936
2937 /*
2938 * Iterate the shadow page directory.
2939 */
2940 GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2941 unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2942 cPDEs += iPDDst;
2943 for (;
2944 iPDDst < cPDEs;
2945 iPDDst++, GCPtr += _4G / cPDEs)
2946 {
2947 const SHWPDE PdeDst = pPDDst->a[iPDDst];
2948 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2949 {
2950 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2951 if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2952 {
2953 AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2954 cErrors++;
2955 continue;
2956 }
2957 }
2958 else if ( (PdeDst.u & X86_PDE_P)
2959 || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
2960 )
2961 {
2962 HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2963 PPGMPOOLPAGE pPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2964 if (!pPage)
2965 {
2966 AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2967 HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2968 cErrors++;
2969 continue;
2970 }
2971 const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2972
2973 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD))
2974 {
2975 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2976 GCPtr, (uint64_t)PdeDst.u));
2977 cErrors++;
2978 }
2979
2980 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D))
2981 {
2982 AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2983 GCPtr, (uint64_t)PdeDst.u));
2984 cErrors++;
2985 }
2986
2987 const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2988 if (!PdeSrc.n.u1Present)
2989 {
2990 AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2991 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2992 cErrors++;
2993 continue;
2994 }
2995
2996 if ( !PdeSrc.b.u1Size
2997 || !(cr4 & X86_CR4_PSE))
2998 {
2999 GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3000# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3001 GCPhysGst |= (iPDDst & 1) * (PAGE_SIZE / 2);
3002# endif
3003 }
3004 else
3005 {
3006 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3007 {
3008 AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3009 GCPtr, (uint64_t)PdeSrc.u));
3010 cErrors++;
3011 continue;
3012 }
3013 GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
3014# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3015 GCPhysGst |= GCPtr & BIT(X86_PAGE_2M_SHIFT);
3016# endif
3017 }
3018
3019 if ( pPage->enmKind
3020 != (!PdeSrc.b.u1Size || !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3021 {
3022 AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3023 pPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3024 cErrors++;
3025 }
3026
3027 rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3028 if (VBOX_FAILURE(rc))
3029 {
3030 AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3031 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3032 cErrors++;
3033 continue;
3034 }
3035
3036 if (GCPhysGst != pPage->GCPhys)
3037 {
3038 AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3039 GCPhysGst, pPage->GCPhys, GCPtr));
3040 cErrors++;
3041 continue;
3042 }
3043
3044 if ( !PdeSrc.b.u1Size
3045 || !(cr4 & X86_CR4_PSE))
3046 {
3047 /*
3048 * Page Table.
3049 */
3050 const GSTPT *pPTSrc;
3051 rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3052 if (VBOX_FAILURE(rc))
3053 {
3054 AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3055 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3056 cErrors++;
3057 continue;
3058 }
3059 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
3060 != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
3061 {
3062 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3063 // (This problem will go away when/if we shadow multiple CR3s.)
3064 AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3065 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3066 cErrors++;
3067 continue;
3068 }
3069 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3070 {
3071 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3072 GCPtr, (uint64_t)PdeDst.u));
3073 cErrors++;
3074 continue;
3075 }
3076
3077 /* iterate the page table. */
3078# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3079 const unsigned offPTSrc = 0;
3080# else
3081 const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3082# endif
3083 for (unsigned iPT = 0, off = 0;
3084 iPT < ELEMENTS(pPTDst->a);
3085 iPT++, off += PAGE_SIZE)
3086 {
3087 const SHWPTE PteDst = pPTDst->a[iPT];
3088
3089 /* skip not-present entries. */
3090 if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3091 continue;
3092 Assert(PteDst.n.u1Present);
3093
3094 const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3095 if (!PteSrc.n.u1Present)
3096 {
3097#ifdef IN_RING3
3098 PGMAssertHandlerAndFlagsInSync(pVM);
3099 PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3100#endif
3101 AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3102 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3103 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3104 cErrors++;
3105 continue;
3106 }
3107
3108 uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3109# if 1 /** @todo sync accessed bit properly... */
3110 fIgnoreFlags |= X86_PTE_A;
3111# endif
3112
3113 /* match the physical addresses */
3114 HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3115 GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3116
3117# ifdef IN_RING3
3118 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3119 if (VBOX_FAILURE(rc))
3120 {
3121 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3122 {
3123 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3124 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3125 cErrors++;
3126 continue;
3127 }
3128 }
3129 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3130 {
3131 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3132 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3133 cErrors++;
3134 continue;
3135 }
3136# endif
3137
3138 rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3139 if (VBOX_FAILURE(rc))
3140 {
3141# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3142 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3143 {
3144 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3145 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3146 cErrors++;
3147 continue;
3148 }
3149# endif
3150 if (PteDst.n.u1Write)
3151 {
3152 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3153 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3154 cErrors++;
3155 }
3156 fIgnoreFlags |= X86_PTE_RW;
3157 }
3158 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3159 {
3160 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3161 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3162 cErrors++;
3163 continue;
3164 }
3165
3166 /* flags */
3167 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
3168 {
3169 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
3170 {
3171 if (PteDst.n.u1Write)
3172 {
3173 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3174 GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3175 cErrors++;
3176 continue;
3177 }
3178 fIgnoreFlags |= X86_PTE_RW;
3179 }
3180 else
3181 {
3182 if (PteDst.n.u1Present)
3183 {
3184 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3185 GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3186 cErrors++;
3187 continue;
3188 }
3189 fIgnoreFlags |= X86_PTE_P;
3190 }
3191 }
3192 else
3193 {
3194 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3195 {
3196 if (PteDst.n.u1Write)
3197 {
3198 AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3199 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3200 cErrors++;
3201 continue;
3202 }
3203 if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3204 {
3205 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3206 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3207 cErrors++;
3208 continue;
3209 }
3210 if (PteDst.n.u1Dirty)
3211 {
3212 AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3213 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3214 cErrors++;
3215 }
3216# if 0 /** @todo sync access bit properly... */
3217 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3218 {
3219 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3220 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3221 cErrors++;
3222 }
3223 fIgnoreFlags |= X86_PTE_RW;
3224# else
3225 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3226# endif
3227 }
3228 else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3229 {
3230 /* access bit emulation (not implemented). */
3231 if (PteSrc.n.u1Accessed || PteDst.n.u1Present)
3232 {
3233 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3234 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3235 cErrors++;
3236 continue;
3237 }
3238 if (!PteDst.n.u1Accessed)
3239 {
3240 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3241 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3242 cErrors++;
3243 }
3244 fIgnoreFlags |= X86_PTE_P;
3245 }
3246# ifdef DEBUG_sandervl
3247 fIgnoreFlags |= X86_PTE_D | X86_PTE_A;
3248# endif
3249 }
3250
3251 if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3252 && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3253 )
3254 {
3255 AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3256 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3257 fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3258 cErrors++;
3259 continue;
3260 }
3261 } /* foreach PTE */
3262 }
3263 else
3264 {
3265 /*
3266 * Big Page.
3267 */
3268 uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | X86_PDE_PAE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
3269 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3270 {
3271 if (PdeDst.n.u1Write)
3272 {
3273 AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3274 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3275 cErrors++;
3276 continue;
3277 }
3278 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3279 {
3280 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3281 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3282 cErrors++;
3283 continue;
3284 }
3285# if 0 /** @todo sync access bit properly... */
3286 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3287 {
3288 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3289 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3290 cErrors++;
3291 }
3292 fIgnoreFlags |= X86_PTE_RW;
3293# else
3294 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3295# endif
3296 }
3297 else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3298 {
3299 /* access bit emulation (not implemented). */
3300 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
3301 {
3302 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3303 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3304 cErrors++;
3305 continue;
3306 }
3307 if (!PdeDst.n.u1Accessed)
3308 {
3309 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3310 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3311 cErrors++;
3312 }
3313 fIgnoreFlags |= X86_PTE_P;
3314 }
3315
3316 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3317 {
3318 AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3319 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3320 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3321 cErrors++;
3322 }
3323
3324 /* iterate the page table. */
3325 for (unsigned iPT = 0, off = 0;
3326 iPT < ELEMENTS(pPTDst->a);
3327 iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3328 {
3329 const SHWPTE PteDst = pPTDst->a[iPT];
3330
3331 if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3332 {
3333 AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3334 GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3335 cErrors++;
3336 }
3337
3338 /* skip not-present entries. */
3339 if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3340 continue;
3341
3342 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3343
3344 /* match the physical addresses */
3345 HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3346
3347# ifdef IN_RING3
3348 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3349 if (VBOX_FAILURE(rc))
3350 {
3351 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3352 {
3353 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3354 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3355 cErrors++;
3356 }
3357 }
3358 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3359 {
3360 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3361 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3362 cErrors++;
3363 continue;
3364 }
3365# endif
3366
3367 rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3368 if (VBOX_FAILURE(rc))
3369 {
3370# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3371 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3372 {
3373 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3374 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3375 cErrors++;
3376 continue;
3377 }
3378# endif
3379 if (PteDst.n.u1Write)
3380 {
3381 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3382 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3383 cErrors++;
3384 }
3385 fIgnoreFlags |= X86_PTE_RW;
3386 }
3387 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3388 {
3389 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3390 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3391 cErrors++;
3392 continue;
3393 }
3394
3395 /* flags */
3396 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL | MM_RAM_FLAGS_VIRTUAL_ALL | MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
3397 {
3398 if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE | MM_RAM_FLAGS_VIRTUAL_WRITE))
3399 {
3400 if (!(HCPhys & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF))
3401 {
3402 if (PteDst.n.u1Write)
3403 {
3404 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3405 GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3406 cErrors++;
3407 continue;
3408 }
3409 fIgnoreFlags |= X86_PTE_RW;
3410 }
3411 }
3412 else
3413 {
3414 if (PteDst.n.u1Present)
3415 {
3416 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3417 GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3418 cErrors++;
3419 continue;
3420 }
3421 fIgnoreFlags |= X86_PTE_P;
3422 }
3423 }
3424
3425 if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3426 && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3427 )
3428 {
3429 AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3430 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3431 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3432 cErrors++;
3433 continue;
3434 }
3435 } /* foreach PTE */
3436 }
3437 }
3438 /* not present */
3439
3440 } /* forearch PDE */
3441
3442# ifdef DEBUG
3443 if (cErrors)
3444 LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3445# endif
3446
3447#elif PGM_GST_TYPE == PGM_TYPE_PAE
3448//# error not implemented
3449
3450
3451#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3452//# error not implemented
3453
3454/*#else: guest real and protected mode */
3455#endif
3456 return cErrors;
3457}
3458#endif /* VBOX_STRICT */
3459
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