PGMAllBth.h@ 41774

Last change on this file since 41774 was 41774, checked in by vboxsync, 12 years ago
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1	/* $Id: PGMAllBth.h 41774 2012-06-16 14:44:06Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
108	{
109	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
110	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
112	return VINF_EM_RAW_EMULATE_INSTR;
113	}
114	# endif
115
116	/*
117	* Calc the error code for the guest trap.
118	*/
119	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
120	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
121	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
122	if (pGstWalk->Core.fBadPhysAddr)
123	{
124	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
125	Assert(!pGstWalk->Core.fNotPresent);
126	}
127	else if (!pGstWalk->Core.fNotPresent)
128	uNewErr \|= X86_TRAP_PF_P;
129	TRPMSetErrorCode(pVCpu, uNewErr);
130
131	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
132	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
136
137
138	/**
139	* Deal with a guest page fault.
140	*
141	* The caller has taken the PGM lock.
142	*
143	* @returns Strict VBox status code.
144	*
145	* @param pVCpu The current CPU.
146	* @param uErr The error code.
147	* @param pRegFrame The register frame.
148	* @param pvFault The fault address.
149	* @param pPage The guest page at @a pvFault.
150	* @param pGstWalk The guest page table walk result.
151	* @param pfLockTaken PGM lock taken here or not (out). This is true
152	* when we're called.
153	*/
154	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
155	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
156	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	, PGSTPTWALK pGstWalk
158	# endif
159	)
160	{
161	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
163	#endif
164	PVM pVM = pVCpu->CTX_SUFF(pVM);
165	int rc;
166
167	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
168	{
169	/*
170	* Physical page access handler.
171	*/
172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
173	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
174	# else
175	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
176	# endif
177	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
178	if (pCur)
179	{
180	# ifdef PGM_SYNC_N_PAGES
181	/*
182	* If the region is write protected and we got a page not present fault, then sync
183	* the pages. If the fault was caused by a read, then restart the instruction.
184	* In case of write access continue to the GC write handler.
185	*
186	* ASSUMES that there is only one handler per page or that they have similar write properties.
187	*/
188	if ( !(uErr & X86_TRAP_PF_P)
189	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
190	{
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
193	# else
194	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
195	# endif
196	if ( RT_FAILURE(rc)
197	\|\| !(uErr & X86_TRAP_PF_RW)
198	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
199	{
200	AssertRC(rc);
201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
202	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
203	return rc;
204	}
205	}
206	# endif
207	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
208	/*
209	* If the access was not thru a #PF(RSVD\|...) resync the page.
210	*/
211	if ( !(uErr & X86_TRAP_PF_RSVD)
212	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
213	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
214	&& pGstWalk->Core.fEffectiveRW
215	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
216	# endif
217	)
218	{
219	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
220	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
221	# else
222	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
223	# endif
224	if ( RT_FAILURE(rc)
225	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
226	{
227	AssertRC(rc);
228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
229	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
230	return rc;
231	}
232	}
233	# endif
234
235	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
236	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
237	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
238	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
239	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
241	else
242	{
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
244	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
245	}
246
247	if (pCur->CTX_SUFF(pfnHandler))
248	{
249	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250	void *pvUser = pCur->CTX_SUFF(pvUser);
251	# ifdef IN_RING0
252	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
253	# else
254	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
255	# endif
256
257	STAM_PROFILE_START(&pCur->Stat, h);
258	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
259	{
260	pgmUnlock(pVM);
261	*pfLockTaken = false;
262	}
263
264	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
265
266	# ifdef VBOX_WITH_STATISTICS
267	pgmLock(pVM);
268	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	pgmUnlock(pVM);
272	# endif
273	}
274	else
275	rc = VINF_EM_RAW_EMULATE_INSTR;
276
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
278	return rc;
279	}
280	}
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
282	else
283	{
284	# ifdef PGM_SYNC_N_PAGES
285	/*
286	* If the region is write protected and we got a page not present fault, then sync
287	* the pages. If the fault was caused by a read, then restart the instruction.
288	* In case of write access continue to the GC write handler.
289	*/
290	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
291	&& !(uErr & X86_TRAP_PF_P))
292	{
293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
294	if ( RT_FAILURE(rc)
295	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
296	\|\| !(uErr & X86_TRAP_PF_RW))
297	{
298	AssertRC(rc);
299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
300	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
301	return rc;
302	}
303	}
304	# endif
305	/*
306	* Ok, it's an virtual page access handler.
307	*
308	* Since it's faster to search by address, we'll do that first
309	* and then retry by GCPhys if that fails.
310	*/
311	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
312	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
313	* out of sync, because the page was changed without us noticing it (not-present -> present
314	* without invlpg or mov cr3, xxx).
315	*/
316	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
317	if (pCur)
318	{
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rc;
352	}
353	/* Unhandled part of a monitored page */
354	}
355	else
356	{
357	/* Check by physical address. */
358	unsigned iPage;
359	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
360	Assert(RT_SUCCESS(rc) \|\| !pCur);
361	if ( pCur
362	&& ( uErr & X86_TRAP_PF_RW
363	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
364	{
365	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
366	# ifdef IN_RC
367	STAM_PROFILE_START(&pCur->Stat, h);
368	RTGCPTR GCPtrStart = pCur->Core.Key;
369	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
370	pgmUnlock(pVM);
371	*pfLockTaken = false;
372
373	RTGCPTR off = (iPage << PAGE_SHIFT)
374	+ (pvFault & PAGE_OFFSET_MASK)
375	- (GCPtrStart & PAGE_OFFSET_MASK);
376	Assert(off < pCur->cb);
377	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
378
379	# ifdef VBOX_WITH_STATISTICS
380	pgmLock(pVM);
381	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
382	if (pCur)
383	STAM_PROFILE_STOP(&pCur->Stat, h);
384	pgmUnlock(pVM);
385	# endif
386	# else
387	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
388	# endif
389	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
390	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
391	return rc;
392	}
393	}
394	}
395	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
396
397	/*
398	* There is a handled area of the page, but this fault doesn't belong to it.
399	* We must emulate the instruction.
400	*
401	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
402	* we first check if this was a page-not-present fault for a page with only
403	* write access handlers. Restart the instruction if it wasn't a write access.
404	*/
405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
406
407	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
408	&& !(uErr & X86_TRAP_PF_P))
409	{
410	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
411	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
412	# else
413	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
414	# endif
415	if ( RT_FAILURE(rc)
416	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
417	\|\| !(uErr & X86_TRAP_PF_RW))
418	{
419	AssertRC(rc);
420	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
422	return rc;
423	}
424	}
425
426	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
427	* It's writing to an unhandled part of the LDT page several million times.
428	*/
429	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
430	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
431	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
432	return rc;
433	} /* if any kind of handler */
434
435
436	/**
437	* #PF Handler for raw-mode guest execution.
438	*
439	* @returns VBox status code (appropriate for trap handling and GC return).
440	*
441	* @param pVCpu VMCPU Handle.
442	* @param uErr The trap error code.
443	* @param pRegFrame Trap register frame.
444	* @param pvFault The fault address.
445	* @param pfLockTaken PGM lock taken here or not (out)
446	*/
447	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
448	{
449	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
450
451	*pfLockTaken = false;
452
453	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
454	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
455	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
456	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
457	int rc;
458
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	/*
461	* Walk the guest page translation tables and check if it's a guest fault.
462	*/
463	GSTPTWALK GstWalk;
464	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
465	if (RT_FAILURE_NP(rc))
466	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
467
468	/* assert some GstWalk sanity. */
469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
470	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
471	# endif
472	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
473	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
474	# endif
475	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
476	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
477	Assert(GstWalk.Core.fSucceeded);
478
479	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
480	{
481	if ( ( (uErr & X86_TRAP_PF_RW)
482	&& !GstWalk.Core.fEffectiveRW
483	&& ( (uErr & X86_TRAP_PF_US)
484	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
485	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
486	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
487	)
488	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
489	}
490
491	/*
492	* Set the accessed and dirty flags.
493	*/
494	# if PGM_GST_TYPE == PGM_TYPE_AMD64
495	GstWalk.Pml4e.u \|= X86_PML4E_A;
496	GstWalk.pPml4e->u \|= X86_PML4E_A;
497	GstWalk.Pdpe.u \|= X86_PDPE_A;
498	GstWalk.pPdpe->u \|= X86_PDPE_A;
499	# endif
500	if (GstWalk.Core.fBigPage)
501	{
502	Assert(GstWalk.Pde.b.u1Size);
503	if (uErr & X86_TRAP_PF_RW)
504	{
505	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
506	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
507	}
508	else
509	{
510	GstWalk.Pde.u \|= X86_PDE4M_A;
511	GstWalk.pPde->u \|= X86_PDE4M_A;
512	}
513	}
514	else
515	{
516	Assert(!GstWalk.Pde.b.u1Size);
517	GstWalk.Pde.u \|= X86_PDE_A;
518	GstWalk.pPde->u \|= X86_PDE_A;
519	if (uErr & X86_TRAP_PF_RW)
520	{
521	# ifdef VBOX_WITH_STATISTICS
522	if (!GstWalk.Pte.n.u1Dirty)
523	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
524	else
525	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
526	# endif
527	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
528	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
529	}
530	else
531	{
532	GstWalk.Pte.u \|= X86_PTE_A;
533	GstWalk.pPte->u \|= X86_PTE_A;
534	}
535	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
536	}
537	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
538	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
539	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
540	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
541	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542
543	/* Take the big lock now. */
544	*pfLockTaken = true;
545	pgmLock(pVM);
546
547	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
548	/*
549	* If it is a reserved bit fault we know that it is an MMIO (access
550	* handler) related fault and can skip some 200 lines of code.
551	*/
552	if (uErr & X86_TRAP_PF_RSVD)
553	{
554	Assert(uErr & X86_TRAP_PF_P);
555	PPGMPAGE pPage;
556	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
557	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
558	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
560	pfLockTaken, &GstWalk));
561	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
562	# else
563	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
566	pfLockTaken));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
568	# endif
569	AssertRC(rc);
570	PGM_INVL_PG(pVCpu, pvFault);
571	return rc; /* Restart with the corrected entry. */
572	}
573	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
574
575	/*
576	* Fetch the guest PDE, PDPE and PML4E.
577	*/
578	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
579	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
580	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
583	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PAE
586	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
587	# else
588	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
589	# endif
590	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
591
592	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
593	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
594	PX86PDPAE pPDDst;
595	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
596	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
597	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
598	# else
599	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
600	# endif
601	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
602
603	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
604	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
605	PEPTPD pPDDst;
606	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
607	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
608	# endif
609	Assert(pPDDst);
610
611	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
612	/*
613	* Dirty page handling.
614	*
615	* If we successfully correct the write protection fault due to dirty bit
616	* tracking, then return immediately.
617	*/
618	if (uErr & X86_TRAP_PF_RW) /* write fault? */
619	{
620	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
621	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
622	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
623	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
624	{
625	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
626	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
627	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
628	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
629	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
630	return VINF_SUCCESS;
631	}
632	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
633	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
634	}
635
636	# if 0 /* rarely useful; leave for debugging. */
637	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
638	# endif
639	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
640
641	/*
642	* A common case is the not-present error caused by lazy page table syncing.
643	*
644	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
645	* here so we can safely assume that the shadow PT is present when calling
646	* SyncPage later.
647	*
648	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
649	* of mapping conflict and defer to SyncCR3 in R3.
650	* (Again, we do NOT support access handlers for non-present guest pages.)
651	*
652	*/
653	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
654	Assert(GstWalk.Pde.n.u1Present);
655	# endif
656	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
657	&& !pPDDst->a[iPDDst].n.u1Present)
658	{
659	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
662	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
663	# else
664	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
665	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
666	# endif
667	if (RT_SUCCESS(rc))
668	return rc;
669	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
670	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
671	return VINF_PGM_SYNC_CR3;
672	}
673
674	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
675	/*
676	* Check if this address is within any of our mappings.
677	*
678	* This is very fast and it's gonna save us a bit of effort below and prevent
679	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
680	* (BTW, it's impossible to have physical access handlers in a mapping.)
681	*/
682	if (pgmMapAreMappingsEnabled(pVM))
683	{
684	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
685	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
686	{
687	if (pvFault < pMapping->GCPtr)
688	break;
689	if (pvFault - pMapping->GCPtr < pMapping->cb)
690	{
691	/*
692	* The first thing we check is if we've got an undetected conflict.
693	*/
694	if (pgmMapAreMappingsFloating(pVM))
695	{
696	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
697	while (iPT-- > 0)
698	if (GstWalk.pPde[iPT].n.u1Present)
699	{
700	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
701	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
702	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
703	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
704	return VINF_PGM_SYNC_CR3;
705	}
706	}
707
708	/*
709	* Check if the fault address is in a virtual page access handler range.
710	*/
711	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
712	if ( pCur
713	&& pvFault - pCur->Core.Key < pCur->cb
714	&& uErr & X86_TRAP_PF_RW)
715	{
716	# ifdef IN_RC
717	STAM_PROFILE_START(&pCur->Stat, h);
718	pgmUnlock(pVM);
719	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
720	pgmLock(pVM);
721	STAM_PROFILE_STOP(&pCur->Stat, h);
722	# else
723	AssertFailed();
724	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
725	# endif
726	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return rc;
729	}
730
731	/*
732	* Pretend we're not here and let the guest handle the trap.
733	*/
734	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
736	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
737	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
738	return VINF_EM_RAW_GUEST_TRAP;
739	}
740	}
741	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
742	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
743
744	/*
745	* Check if this fault address is flagged for special treatment,
746	* which means we'll have to figure out the physical address and
747	* check flags associated with it.
748	*
749	* ASSUME that we can limit any special access handling to pages
750	* in page tables which the guest believes to be present.
751	*/
752	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
753	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
754	# else
755	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
756	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
757	PPGMPAGE pPage;
758	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
759	if (RT_FAILURE(rc))
760	{
761	/*
762	* When the guest accesses invalid physical memory (e.g. probing
763	* of RAM or accessing a remapped MMIO range), then we'll fall
764	* back to the recompiler to emulate the instruction.
765	*/
766	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
767	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
768	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
769	return VINF_EM_RAW_EMULATE_INSTR;
770	}
771
772	/*
773	* Any handlers for this page?
774	*/
775	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
776	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
777	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
778	&GstWalk));
779	# else
780	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
781	# endif
782
783	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
784
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
786	if (uErr & X86_TRAP_PF_P)
787	{
788	/*
789	* The page isn't marked, but it might still be monitored by a virtual page access handler.
790	* (ASSUMES no temporary disabling of virtual handlers.)
791	*/
792	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
793	* we should correct both the shadow page table and physical memory flags, and not only check for
794	* accesses within the handler region but for access to pages with virtual handlers. */
795	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
796	if (pCur)
797	{
798	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
799	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
800	\|\| !(uErr & X86_TRAP_PF_P)
801	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
802	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
803
804	if ( pvFault - pCur->Core.Key < pCur->cb
805	&& ( uErr & X86_TRAP_PF_RW
806	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
807	{
808	# ifdef IN_RC
809	STAM_PROFILE_START(&pCur->Stat, h);
810	pgmUnlock(pVM);
811	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
812	pgmLock(pVM);
813	STAM_PROFILE_STOP(&pCur->Stat, h);
814	# else
815	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
816	# endif
817	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
818	return rc;
819	}
820	}
821	}
822	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
823
824	/*
825	* We are here only if page is present in Guest page tables and
826	* trap is not handled by our handlers.
827	*
828	* Check it for page out-of-sync situation.
829	*/
830	if (!(uErr & X86_TRAP_PF_P))
831	{
832	/*
833	* Page is not present in our page tables. Try to sync it!
834	*/
835	if (uErr & X86_TRAP_PF_US)
836	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
837	else /* supervisor */
838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
839
840	if (PGM_PAGE_IS_BALLOONED(pPage))
841	{
842	/* Emulate reads from ballooned pages as they are not present in
843	our shadow page tables. (Required for e.g. Solaris guests; soft
844	ecc, random nr generator.) */
845	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
846	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
847	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
848	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
849	return rc;
850	}
851
852	# if defined(LOG_ENABLED) && !defined(IN_RING0)
853	RTGCPHYS GCPhys2;
854	uint64_t fPageGst2;
855	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
856	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
857	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
858	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
859	# else
860	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
861	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
862	# endif
863	# endif /* LOG_ENABLED */
864
865	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
866	if ( !GstWalk.Core.fEffectiveUS
867	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
868	{
869	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
870	if ( pvFault == (RTGCPTR)pRegFrame->eip
871	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
872	# ifdef CSAM_DETECT_NEW_CODE_PAGES
873	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
874	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
875	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
876	)
877	{
878	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
879	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
880	if (rc != VINF_SUCCESS)
881	{
882	/*
883	* CSAM needs to perform a job in ring 3.
884	*
885	* Sync the page before going to the host context; otherwise we'll end up in a loop if
886	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
887	*/
888	LogFlow(("CSAM ring 3 job\n"));
889	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
890	AssertRC(rc2);
891
892	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
893	return rc;
894	}
895	}
896	# ifdef CSAM_DETECT_NEW_CODE_PAGES
897	else if ( uErr == X86_TRAP_PF_RW
898	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
899	&& pRegFrame->ecx < 0x10000)
900	{
901	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
902	* to detect loading of new code pages.
903	*/
904
905	/*
906	* Decode the instruction.
907	*/
908	RTGCPTR PC;
909	rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
910	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
911	if (rc == VINF_SUCCESS)
912	{
913	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
914	uint32_t cbOp;
915	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
916
917	/* For now we'll restrict this to rep movsw/d instructions */
918	if ( rc == VINF_SUCCESS
919	&& pDis->pCurInstr->opcode == OP_MOVSWD
920	&& (pDis->prefix & DISPREFIX_REP))
921	{
922	CSAMMarkPossibleCodePage(pVM, pvFault);
923	}
924	}
925	}
926	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
927
928	/*
929	* Mark this page as safe.
930	*/
931	/** @todo not correct for pages that contain both code and data!! */
932	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
933	CSAMMarkPage(pVM, pvFault, true);
934	}
935	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
936	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
937	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
938	# else
939	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
940	# endif
941	if (RT_SUCCESS(rc))
942	{
943	/* The page was successfully synced, return to the guest. */
944	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
945	return VINF_SUCCESS;
946	}
947	}
948	else /* uErr & X86_TRAP_PF_P: */
949	{
950	/*
951	* Write protected pages are made writable when the guest makes the
952	* first write to it. This happens for pages that are shared, write
953	* monitored or not yet allocated.
954	*
955	* We may also end up here when CR0.WP=0 in the guest.
956	*
957	* Also, a side effect of not flushing global PDEs are out of sync
958	* pages due to physical monitored regions, that are no longer valid.
959	* Assume for now it only applies to the read/write flag.
960	*/
961	if (uErr & X86_TRAP_PF_RW)
962	{
963	/*
964	* Check if it is a read-only page.
965	*/
966	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
967	{
968	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
969	Assert(!PGM_PAGE_IS_ZERO(pPage));
970	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
971	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
972
973	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
974	if (rc != VINF_SUCCESS)
975	{
976	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
977	return rc;
978	}
979	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
980	return VINF_EM_NO_MEMORY;
981	}
982
983	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
984	/*
985	* Check to see if we need to emulate the instruction if CR0.WP=0.
986	*/
987	if ( !GstWalk.Core.fEffectiveRW
988	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
989	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
990	{
991	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
992	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
993	if (RT_SUCCESS(rc))
994	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
995	else
996	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
997	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
998	return rc;
999	}
1000	# endif
1001	/// @todo count the above case; else
1002	if (uErr & X86_TRAP_PF_US)
1003	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1004	else /* supervisor */
1005	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1006
1007	/*
1008	* Sync the page.
1009	*
1010	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1011	* page is not present, which is not true in this case.
1012	*/
1013	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1014	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1015	# else
1016	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1017	# endif
1018	if (RT_SUCCESS(rc))
1019	{
1020	/*
1021	* Page was successfully synced, return to guest but invalidate
1022	* the TLB first as the page is very likely to be in it.
1023	*/
1024	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1025	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1026	# else
1027	PGM_INVL_PG(pVCpu, pvFault);
1028	# endif
1029	# ifdef VBOX_STRICT
1030	RTGCPHYS GCPhys2;
1031	uint64_t fPageGst;
1032	if (!pVM->pgm.s.fNestedPaging)
1033	{
1034	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1035	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1036	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1037	}
1038	uint64_t fPageShw;
1039	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1040	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1041	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1042	# endif /* VBOX_STRICT */
1043	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1044	return VINF_SUCCESS;
1045	}
1046	}
1047	/** @todo else: why are we here? */
1048
1049	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1050	/*
1051	* Check for VMM page flags vs. Guest page flags consistency.
1052	* Currently only for debug purposes.
1053	*/
1054	if (RT_SUCCESS(rc))
1055	{
1056	/* Get guest page flags. */
1057	uint64_t fPageGst;
1058	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1059	if (RT_SUCCESS(rc))
1060	{
1061	uint64_t fPageShw;
1062	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1063
1064	/*
1065	* Compare page flags.
1066	* Note: we have AVL, A, D bits desynced.
1067	*/
1068	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1069	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1070	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1071	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1072	}
1073	else
1074	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1075	}
1076	else
1077	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1078	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1079	}
1080
1081
1082	/*
1083	* If we get here it is because something failed above, i.e. most like guru
1084	* meditiation time.
1085	*/
1086	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1087	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1088	return rc;
1089
1090	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1091	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1092	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1093	return VERR_PGM_NOT_USED_IN_MODE;
1094	# endif
1095	}
1096	#endif /* !IN_RING3 */
1097
1098
1099	/**
1100	* Emulation of the invlpg instruction.
1101	*
1102	*
1103	* @returns VBox status code.
1104	*
1105	* @param pVCpu The VMCPU handle.
1106	* @param GCPtrPage Page to invalidate.
1107	*
1108	* @remark ASSUMES that the guest is updating before invalidating. This order
1109	* isn't required by the CPU, so this is speculative and could cause
1110	* trouble.
1111	* @remark No TLB shootdown is done on any other VCPU as we assume that
1112	* invlpg emulation is the only reason for calling this function.
1113	* (The guest has to shoot down TLB entries on other CPUs itself)
1114	* Currently true, but keep in mind!
1115	*
1116	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1117	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1118	*/
1119	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1120	{
1121	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1122	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1123	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1124	int rc;
1125	PVM pVM = pVCpu->CTX_SUFF(pVM);
1126	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1127
1128	PGM_LOCK_ASSERT_OWNER(pVM);
1129
1130	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1131
1132	/*
1133	* Get the shadow PD entry and skip out if this PD isn't present.
1134	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1135	*/
1136	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1137	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1138	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1139
1140	/* Fetch the pgm pool shadow descriptor. */
1141	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1142	Assert(pShwPde);
1143
1144	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1145	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1146	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1147
1148	/* If the shadow PDPE isn't present, then skip the invalidate. */
1149	if (!pPdptDst->a[iPdpt].n.u1Present)
1150	{
1151	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1152	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1153	return VINF_SUCCESS;
1154	}
1155
1156	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1157	PPGMPOOLPAGE pShwPde = NULL;
1158	PX86PDPAE pPDDst;
1159
1160	/* Fetch the pgm pool shadow descriptor. */
1161	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1162	AssertRCSuccessReturn(rc, rc);
1163	Assert(pShwPde);
1164
1165	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1166	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1167
1168	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1169	/* PML4 */
1170	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1171	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1172	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1173	PX86PDPAE pPDDst;
1174	PX86PDPT pPdptDst;
1175	PX86PML4E pPml4eDst;
1176	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1177	if (rc != VINF_SUCCESS)
1178	{
1179	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1180	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1181	return VINF_SUCCESS;
1182	}
1183	Assert(pPDDst);
1184
1185	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1186	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1187
1188	if (!pPdpeDst->n.u1Present)
1189	{
1190	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1191	return VINF_SUCCESS;
1192	}
1193
1194	/* Fetch the pgm pool shadow descriptor. */
1195	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1196	Assert(pShwPde);
1197
1198	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1199
1200	const SHWPDE PdeDst = *pPdeDst;
1201	if (!PdeDst.n.u1Present)
1202	{
1203	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1204	return VINF_SUCCESS;
1205	}
1206
1207	/*
1208	* Get the guest PD entry and calc big page.
1209	*/
1210	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1211	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1212	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1213	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1214	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1215	unsigned iPDSrc = 0;
1216	# if PGM_GST_TYPE == PGM_TYPE_PAE
1217	X86PDPE PdpeSrcIgn;
1218	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1219	# else /* AMD64 */
1220	PX86PML4E pPml4eSrcIgn;
1221	X86PDPE PdpeSrcIgn;
1222	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1223	# endif
1224	GSTPDE PdeSrc;
1225
1226	if (pPDSrc)
1227	PdeSrc = pPDSrc->a[iPDSrc];
1228	else
1229	PdeSrc.u = 0;
1230	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1231	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1232
1233	# ifdef IN_RING3
1234	/*
1235	* If a CR3 Sync is pending we may ignore the invalidate page operation
1236	* depending on the kind of sync and if it's a global page or not.
1237	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1238	*/
1239	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1240	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1241	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1242	&& fIsBigPage
1243	&& PdeSrc.b.u1Global
1244	)
1245	)
1246	# else
1247	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1248	# endif
1249	{
1250	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1251	return VINF_SUCCESS;
1252	}
1253	# endif /* IN_RING3 */
1254
1255	/*
1256	* Deal with the Guest PDE.
1257	*/
1258	rc = VINF_SUCCESS;
1259	if (PdeSrc.n.u1Present)
1260	{
1261	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1262	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1263	# ifndef PGM_WITHOUT_MAPPING
1264	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1265	{
1266	/*
1267	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1268	*/
1269	Assert(pgmMapAreMappingsEnabled(pVM));
1270	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1271	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1272	}
1273	else
1274	# endif /* !PGM_WITHOUT_MAPPING */
1275	if (!fIsBigPage)
1276	{
1277	/*
1278	* 4KB - page.
1279	*/
1280	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1281	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1282
1283	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1284	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1285	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1286	# endif
1287	if (pShwPage->GCPhys == GCPhys)
1288	{
1289	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1290	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1291
1292	PGSTPT pPTSrc;
1293	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1294	if (RT_SUCCESS(rc))
1295	{
1296	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1297	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1298	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1299	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1300	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1301	GCPtrPage, PteSrc.n.u1Present,
1302	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1303	PteSrc.n.u1User & PdeSrc.n.u1User,
1304	(uint64_t)PteSrc.u,
1305	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1306	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1307	}
1308	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1309	PGM_INVL_PG(pVCpu, GCPtrPage);
1310	}
1311	else
1312	{
1313	/*
1314	* The page table address changed.
1315	*/
1316	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1317	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1318	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1319	ASMAtomicWriteSize(pPdeDst, 0);
1320	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1321	PGM_INVL_VCPU_TLBS(pVCpu);
1322	}
1323	}
1324	else
1325	{
1326	/*
1327	* 2/4MB - page.
1328	*/
1329	/* Before freeing the page, check if anything really changed. */
1330	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1331	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1332	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1333	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1334	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1335	# endif
1336	if ( pShwPage->GCPhys == GCPhys
1337	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1338	{
1339	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1340	/** @todo This test is wrong as it cannot check the G bit!
1341	* FIXME */
1342	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1343	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1344	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1345	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1346	{
1347	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1348	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1349	return VINF_SUCCESS;
1350	}
1351	}
1352
1353	/*
1354	* Ok, the page table is present and it's been changed in the guest.
1355	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1356	* We could do this for some flushes in GC too, but we need an algorithm for
1357	* deciding which 4MB pages containing code likely to be executed very soon.
1358	*/
1359	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1360	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1361	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1362	ASMAtomicWriteSize(pPdeDst, 0);
1363	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1364	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1365	}
1366	}
1367	else
1368	{
1369	/*
1370	* Page directory is not present, mark shadow PDE not present.
1371	*/
1372	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1373	{
1374	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1375	ASMAtomicWriteSize(pPdeDst, 0);
1376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1377	PGM_INVL_PG(pVCpu, GCPtrPage);
1378	}
1379	else
1380	{
1381	Assert(pgmMapAreMappingsEnabled(pVM));
1382	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1383	}
1384	}
1385	return rc;
1386
1387	#else /* guest real and protected mode */
1388	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1389	NOREF(pVCpu); NOREF(GCPtrPage);
1390	return VINF_SUCCESS;
1391	#endif
1392	}
1393
1394
1395	/**
1396	* Update the tracking of shadowed pages.
1397	*
1398	* @param pVCpu The VMCPU handle.
1399	* @param pShwPage The shadow page.
1400	* @param HCPhys The physical page we is being dereferenced.
1401	* @param iPte Shadow PTE index
1402	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1403	*/
1404	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1405	RTGCPHYS GCPhysPage)
1406	{
1407	PVM pVM = pVCpu->CTX_SUFF(pVM);
1408
1409	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1410	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1411	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1412
1413	/* Use the hint we retrieved from the cached guest PT. */
1414	if (pShwPage->fDirty)
1415	{
1416	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1417
1418	Assert(pShwPage->cPresent);
1419	Assert(pPool->cPresent);
1420	pShwPage->cPresent--;
1421	pPool->cPresent--;
1422
1423	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1424	AssertRelease(pPhysPage);
1425	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1426	return;
1427	}
1428	# else
1429	NOREF(GCPhysPage);
1430	# endif
1431
1432	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1433	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1434
1435	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1436	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1437	* 2. write protect all shadowed pages. I.e. implement caching.
1438	*/
1439	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1440
1441	/*
1442	* Find the guest address.
1443	*/
1444	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1445	pRam;
1446	pRam = pRam->CTX_SUFF(pNext))
1447	{
1448	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1449	while (iPage-- > 0)
1450	{
1451	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1452	{
1453	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1454
1455	Assert(pShwPage->cPresent);
1456	Assert(pPool->cPresent);
1457	pShwPage->cPresent--;
1458	pPool->cPresent--;
1459
1460	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1461	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1462	return;
1463	}
1464	}
1465	}
1466
1467	for (;;)
1468	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1469	}
1470
1471
1472	/**
1473	* Update the tracking of shadowed pages.
1474	*
1475	* @param pVCpu The VMCPU handle.
1476	* @param pShwPage The shadow page.
1477	* @param u16 The top 16-bit of the pPage->HCPhys.
1478	* @param pPage Pointer to the guest page. this will be modified.
1479	* @param iPTDst The index into the shadow table.
1480	*/
1481	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1482	{
1483	PVM pVM = pVCpu->CTX_SUFF(pVM);
1484
1485	/*
1486	* Just deal with the simple first time here.
1487	*/
1488	if (!u16)
1489	{
1490	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1491	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1492	/* Save the page table index. */
1493	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1494	}
1495	else
1496	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1497
1498	/* write back */
1499	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1500	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1501
1502	/* update statistics. */
1503	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1504	pShwPage->cPresent++;
1505	if (pShwPage->iFirstPresent > iPTDst)
1506	pShwPage->iFirstPresent = iPTDst;
1507	}
1508
1509
1510	/**
1511	* Modifies a shadow PTE to account for access handlers.
1512	*
1513	* @param pVM The VM handle.
1514	* @param pPage The page in question.
1515	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1516	* A (accessed) bit so it can be emulated correctly.
1517	* @param pPteDst The shadow PTE (output). This is temporary storage and
1518	* does not need to be set atomically.
1519	*/
1520	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1521	{
1522	NOREF(pVM);
1523	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1524	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1525	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1526	{
1527	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1528	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1529	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1530	pPteDst->n.u1Present = 1;
1531	pPteDst->n.u1Execute = 1;
1532	pPteDst->n.u1IgnorePAT = 1;
1533	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1534	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1535	#else
1536	if (fPteSrc & X86_PTE_A)
1537	{
1538	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1539	SHW_PTE_SET_RO(*pPteDst);
1540	}
1541	else
1542	SHW_PTE_SET(*pPteDst, 0);
1543	#endif
1544	}
1545	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1546	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1547	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1548	&& ( BTH_IS_NP_ACTIVE(pVM)
1549	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1550	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1551	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1552	# endif
1553	)
1554	{
1555	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1556	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1557	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1558	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1559	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1560	pPteDst->n.u1Present = 0;
1561	pPteDst->n.u1Write = 1;
1562	pPteDst->n.u1Execute = 0;
1563	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1564	pPteDst->n.u3EMT = 7;
1565	# else
1566	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1567	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1568	# endif
1569	}
1570	# endif
1571	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1572	else
1573	{
1574	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1575	SHW_PTE_SET(*pPteDst, 0);
1576	}
1577	/** @todo count these kinds of entries. */
1578	}
1579
1580
1581	/**
1582	* Creates a 4K shadow page for a guest page.
1583	*
1584	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1585	* physical address. The PdeSrc argument only the flags are used. No page
1586	* structured will be mapped in this function.
1587	*
1588	* @param pVCpu The VMCPU handle.
1589	* @param pPteDst Destination page table entry.
1590	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1591	* Can safely assume that only the flags are being used.
1592	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1593	* @param pShwPage Pointer to the shadow page.
1594	* @param iPTDst The index into the shadow table.
1595	*
1596	* @remark Not used for 2/4MB pages!
1597	*/
1598	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1599	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1600	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1601	#else
1602	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1603	#endif
1604	{
1605	PVM pVM = pVCpu->CTX_SUFF(pVM);
1606	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1607
1608	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1609	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1610	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1611
1612	if (pShwPage->fDirty)
1613	{
1614	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1615	PGSTPT pGstPT;
1616
1617	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1618	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1619	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1620	pGstPT->a[iPTDst].u = PteSrc.u;
1621	}
1622	#else
1623	Assert(!pShwPage->fDirty);
1624	#endif
1625
1626	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1627	if ( PteSrc.n.u1Present
1628	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1629	#endif
1630	{
1631	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1632	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1633	# endif
1634	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1635
1636	/*
1637	* Find the ram range.
1638	*/
1639	PPGMPAGE pPage;
1640	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1641	if (RT_SUCCESS(rc))
1642	{
1643	/* Ignore ballooned pages.
1644	Don't return errors or use a fatal assert here as part of a
1645	shadow sync range might included ballooned pages. */
1646	if (PGM_PAGE_IS_BALLOONED(pPage))
1647	{
1648	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1649	return;
1650	}
1651
1652	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1653	/* Make the page writable if necessary. */
1654	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1655	&& ( PGM_PAGE_IS_ZERO(pPage)
1656	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1657	\|\| ( PteSrc.n.u1Write
1658	# else
1659	\|\| ( 1
1660	# endif
1661	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1662	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1663	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1664	# endif
1665	# ifdef VBOX_WITH_PAGE_SHARING
1666	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1667	# endif
1668	)
1669	)
1670	)
1671	{
1672	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1673	AssertRC(rc);
1674	}
1675	#endif
1676
1677	/*
1678	* Make page table entry.
1679	*/
1680	SHWPTE PteDst;
1681	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1682	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1683	# else
1684	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1685	# endif
1686	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1687	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1688	else
1689	{
1690	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1691	/*
1692	* If the page or page directory entry is not marked accessed,
1693	* we mark the page not present.
1694	*/
1695	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1696	{
1697	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1698	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1699	SHW_PTE_SET(PteDst, 0);
1700	}
1701	/*
1702	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1703	* when the page is modified.
1704	*/
1705	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1706	{
1707	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1708	SHW_PTE_SET(PteDst,
1709	fGstShwPteFlags
1710	\| PGM_PAGE_GET_HCPHYS(pPage)
1711	\| PGM_PTFLAGS_TRACK_DIRTY);
1712	SHW_PTE_SET_RO(PteDst);
1713	}
1714	else
1715	#endif
1716	{
1717	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1718	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1719	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1720	PteDst.n.u1Present = 1;
1721	PteDst.n.u1Write = 1;
1722	PteDst.n.u1Execute = 1;
1723	PteDst.n.u1IgnorePAT = 1;
1724	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1725	/* PteDst.n.u1Size = 0 */
1726	#else
1727	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1728	#endif
1729	}
1730
1731	/*
1732	* Make sure only allocated pages are mapped writable.
1733	*/
1734	if ( SHW_PTE_IS_P_RW(PteDst)
1735	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1736	{
1737	/* Still applies to shared pages. */
1738	Assert(!PGM_PAGE_IS_ZERO(pPage));
1739	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1740	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1741	}
1742	}
1743
1744	/*
1745	* Keep user track up to date.
1746	*/
1747	if (SHW_PTE_IS_P(PteDst))
1748	{
1749	if (!SHW_PTE_IS_P(*pPteDst))
1750	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1751	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1752	{
1753	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1754	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1755	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1756	}
1757	}
1758	else if (SHW_PTE_IS_P(*pPteDst))
1759	{
1760	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1761	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1762	}
1763
1764	/*
1765	* Update statistics and commit the entry.
1766	*/
1767	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1768	if (!PteSrc.n.u1Global)
1769	pShwPage->fSeenNonGlobal = true;
1770	#endif
1771	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1772	return;
1773	}
1774
1775	/** @todo count these three different kinds. */
1776	Log2(("SyncPageWorker: invalid address in Pte\n"));
1777	}
1778	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1779	else if (!PteSrc.n.u1Present)
1780	Log2(("SyncPageWorker: page not present in Pte\n"));
1781	else
1782	Log2(("SyncPageWorker: invalid Pte\n"));
1783	#endif
1784
1785	/*
1786	* The page is not present or the PTE is bad. Replace the shadow PTE by
1787	* an empty entry, making sure to keep the user tracking up to date.
1788	*/
1789	if (SHW_PTE_IS_P(*pPteDst))
1790	{
1791	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1792	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1793	}
1794	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1795	}
1796
1797
1798	/**
1799	* Syncs a guest OS page.
1800	*
1801	* There are no conflicts at this point, neither is there any need for
1802	* page table allocations.
1803	*
1804	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1805	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1806	*
1807	* @returns VBox status code.
1808	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1809	* @param pVCpu The VMCPU handle.
1810	* @param PdeSrc Page directory entry of the guest.
1811	* @param GCPtrPage Guest context page address.
1812	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1813	* @param uErr Fault error (X86_TRAP_PF_*).
1814	*/
1815	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1816	{
1817	PVM pVM = pVCpu->CTX_SUFF(pVM);
1818	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1819	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1820
1821	PGM_LOCK_ASSERT_OWNER(pVM);
1822
1823	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1824	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1825	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1826	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1827	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1828
1829	/*
1830	* Assert preconditions.
1831	*/
1832	Assert(PdeSrc.n.u1Present);
1833	Assert(cPages);
1834	# if 0 /* rarely useful; leave for debugging. */
1835	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1836	# endif
1837
1838	/*
1839	* Get the shadow PDE, find the shadow page table in the pool.
1840	*/
1841	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1842	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1843	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1844
1845	/* Fetch the pgm pool shadow descriptor. */
1846	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1847	Assert(pShwPde);
1848
1849	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1850	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1851	PPGMPOOLPAGE pShwPde = NULL;
1852	PX86PDPAE pPDDst;
1853
1854	/* Fetch the pgm pool shadow descriptor. */
1855	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1856	AssertRCSuccessReturn(rc2, rc2);
1857	Assert(pShwPde);
1858
1859	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1860	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1861
1862	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1863	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1864	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1865	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1866	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1867
1868	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1869	AssertRCSuccessReturn(rc2, rc2);
1870	Assert(pPDDst && pPdptDst);
1871	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1872	# endif
1873	SHWPDE PdeDst = *pPdeDst;
1874
1875	/*
1876	* - In the guest SMP case we could have blocked while another VCPU reused
1877	* this page table.
1878	* - With W7-64 we may also take this path when the the A bit is cleared on
1879	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1880	* relevant TLB entries. If we're write monitoring any page mapped by
1881	* the modified entry, we may end up here with a "stale" TLB entry.
1882	*/
1883	if (!PdeDst.n.u1Present)
1884	{
1885	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1886	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1887	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1888	if (uErr & X86_TRAP_PF_P)
1889	PGM_INVL_PG(pVCpu, GCPtrPage);
1890	return VINF_SUCCESS; /* force the instruction to be executed again. */
1891	}
1892
1893	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1894	Assert(pShwPage);
1895
1896	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1897	/* Fetch the pgm pool shadow descriptor. */
1898	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1899	Assert(pShwPde);
1900	# endif
1901
1902	/*
1903	* Check that the page is present and that the shadow PDE isn't out of sync.
1904	*/
1905	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1906	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1907	RTGCPHYS GCPhys;
1908	if (!fBigPage)
1909	{
1910	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1911	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1912	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1913	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1914	# endif
1915	}
1916	else
1917	{
1918	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1919	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1920	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1921	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1922	# endif
1923	}
1924	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1925	if ( fPdeValid
1926	&& pShwPage->GCPhys == GCPhys
1927	&& PdeSrc.n.u1Present
1928	&& PdeSrc.n.u1User == PdeDst.n.u1User
1929	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1930	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1931	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1932	# endif
1933	)
1934	{
1935	/*
1936	* Check that the PDE is marked accessed already.
1937	* Since we set the accessed bit before getting here on a #PF, this
1938	* check is only meant for dealing with non-#PF'ing paths.
1939	*/
1940	if (PdeSrc.n.u1Accessed)
1941	{
1942	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1943	if (!fBigPage)
1944	{
1945	/*
1946	* 4KB Page - Map the guest page table.
1947	*/
1948	PGSTPT pPTSrc;
1949	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1950	if (RT_SUCCESS(rc))
1951	{
1952	# ifdef PGM_SYNC_N_PAGES
1953	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1954	if ( cPages > 1
1955	&& !(uErr & X86_TRAP_PF_P)
1956	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1957	{
1958	/*
1959	* This code path is currently only taken when the caller is PGMTrap0eHandler
1960	* for non-present pages!
1961	*
1962	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1963	* deal with locality.
1964	*/
1965	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1966	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1967	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1968	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1969	# else
1970	const unsigned offPTSrc = 0;
1971	# endif
1972	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1973	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1974	iPTDst = 0;
1975	else
1976	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1977
1978	for (; iPTDst < iPTDstEnd; iPTDst++)
1979	{
1980	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1981
1982	if ( pPteSrc->n.u1Present
1983	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1984	{
1985	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1986	NOREF(GCPtrCurPage);
1987	#ifndef IN_RING0
1988	/*
1989	* Assuming kernel code will be marked as supervisor - and not as user level
1990	* and executed using a conforming code selector - And marked as readonly.
1991	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1992	*/
1993	PPGMPAGE pPage;
1994	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1995	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1996	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1997	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
1998	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1999	)
2000	#endif /* else: CSAM not active */
2001	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2002	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2003	GCPtrCurPage, pPteSrc->n.u1Present,
2004	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2005	pPteSrc->n.u1User & PdeSrc.n.u1User,
2006	(uint64_t)pPteSrc->u,
2007	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2008	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2009	}
2010	}
2011	}
2012	else
2013	# endif /* PGM_SYNC_N_PAGES */
2014	{
2015	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2016	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2017	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2018	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2019	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2020	GCPtrPage, PteSrc.n.u1Present,
2021	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2022	PteSrc.n.u1User & PdeSrc.n.u1User,
2023	(uint64_t)PteSrc.u,
2024	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2025	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2026	}
2027	}
2028	else /* MMIO or invalid page: emulated in #PF handler. */
2029	{
2030	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2031	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2032	}
2033	}
2034	else
2035	{
2036	/*
2037	* 4/2MB page - lazy syncing shadow 4K pages.
2038	* (There are many causes of getting here, it's no longer only CSAM.)
2039	*/
2040	/* Calculate the GC physical address of this 4KB shadow page. */
2041	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2042	/* Find ram range. */
2043	PPGMPAGE pPage;
2044	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2045	if (RT_SUCCESS(rc))
2046	{
2047	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2048
2049	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2050	/* Try to make the page writable if necessary. */
2051	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2052	&& ( PGM_PAGE_IS_ZERO(pPage)
2053	\|\| ( PdeSrc.n.u1Write
2054	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2055	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2056	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2057	# endif
2058	# ifdef VBOX_WITH_PAGE_SHARING
2059	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2060	# endif
2061	)
2062	)
2063	)
2064	{
2065	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2066	AssertRC(rc);
2067	}
2068	# endif
2069
2070	/*
2071	* Make shadow PTE entry.
2072	*/
2073	SHWPTE PteDst;
2074	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2075	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2076	else
2077	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2078
2079	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2080	if ( SHW_PTE_IS_P(PteDst)
2081	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2082	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2083
2084	/* Make sure only allocated pages are mapped writable. */
2085	if ( SHW_PTE_IS_P_RW(PteDst)
2086	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2087	{
2088	/* Still applies to shared pages. */
2089	Assert(!PGM_PAGE_IS_ZERO(pPage));
2090	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2091	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2092	}
2093
2094	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2095
2096	/*
2097	* If the page is not flagged as dirty and is writable, then make it read-only
2098	* at PD level, so we can set the dirty bit when the page is modified.
2099	*
2100	* ASSUMES that page access handlers are implemented on page table entry level.
2101	* Thus we will first catch the dirty access and set PDE.D and restart. If
2102	* there is an access handler, we'll trap again and let it work on the problem.
2103	*/
2104	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2105	* As for invlpg, it simply frees the whole shadow PT.
2106	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2107	if ( !PdeSrc.b.u1Dirty
2108	&& PdeSrc.b.u1Write)
2109	{
2110	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2111	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2112	PdeDst.n.u1Write = 0;
2113	}
2114	else
2115	{
2116	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2117	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2118	}
2119	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2120	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2121	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2122	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2123	}
2124	else
2125	{
2126	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2127	/** @todo must wipe the shadow page table entry in this
2128	* case. */
2129	}
2130	}
2131	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2132	return VINF_SUCCESS;
2133	}
2134
2135	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2136	}
2137	else if (fPdeValid)
2138	{
2139	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2140	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2141	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2142	}
2143	else
2144	{
2145	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2146	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2147	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2148	}
2149
2150	/*
2151	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2152	* Yea, I'm lazy.
2153	*/
2154	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2155	ASMAtomicWriteSize(pPdeDst, 0);
2156
2157	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2158	PGM_INVL_VCPU_TLBS(pVCpu);
2159	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2160
2161
2162	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2163	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2164	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2165	&& !defined(IN_RC)
2166	NOREF(PdeSrc);
2167
2168	# ifdef PGM_SYNC_N_PAGES
2169	/*
2170	* Get the shadow PDE, find the shadow page table in the pool.
2171	*/
2172	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2173	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2174
2175	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2176	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2177
2178	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2179	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2180	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2181	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2182	X86PDEPAE PdeDst;
2183	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2184
2185	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2186	AssertRCSuccessReturn(rc, rc);
2187	Assert(pPDDst && pPdptDst);
2188	PdeDst = pPDDst->a[iPDDst];
2189	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2190	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2191	PEPTPD pPDDst;
2192	EPTPDE PdeDst;
2193
2194	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2195	if (rc != VINF_SUCCESS)
2196	{
2197	AssertRC(rc);
2198	return rc;
2199	}
2200	Assert(pPDDst);
2201	PdeDst = pPDDst->a[iPDDst];
2202	# endif
2203	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2204	if (!PdeDst.n.u1Present)
2205	{
2206	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2207	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2208	return VINF_SUCCESS; /* force the instruction to be executed again. */
2209	}
2210
2211	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2212	if (PdeDst.n.u1Size)
2213	{
2214	Assert(pVM->pgm.s.fNestedPaging);
2215	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2216	return VINF_SUCCESS;
2217	}
2218
2219	/* Mask away the page offset. */
2220	GCPtrPage &= ~((RTGCPTR)0xfff);
2221
2222	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2223	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2224
2225	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2226	if ( cPages > 1
2227	&& !(uErr & X86_TRAP_PF_P)
2228	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2229	{
2230	/*
2231	* This code path is currently only taken when the caller is PGMTrap0eHandler
2232	* for non-present pages!
2233	*
2234	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2235	* deal with locality.
2236	*/
2237	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2238	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2239	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2240	iPTDst = 0;
2241	else
2242	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2243	for (; iPTDst < iPTDstEnd; iPTDst++)
2244	{
2245	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2246	{
2247	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2248	\| (iPTDst << PAGE_SHIFT));
2249
2250	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2251	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2252	GCPtrCurPage,
2253	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2254	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2255
2256	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2257	break;
2258	}
2259	else
2260	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2261	}
2262	}
2263	else
2264	# endif /* PGM_SYNC_N_PAGES */
2265	{
2266	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2267	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2268	\| (iPTDst << PAGE_SHIFT));
2269
2270	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2271
2272	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2273	GCPtrPage,
2274	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2275	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2276	}
2277	return VINF_SUCCESS;
2278
2279	#else
2280	NOREF(PdeSrc);
2281	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2282	return VERR_PGM_NOT_USED_IN_MODE;
2283	#endif
2284	}
2285
2286
2287	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2288
2289	/**
2290	* CheckPageFault helper for returning a page fault indicating a non-present
2291	* (NP) entry in the page translation structures.
2292	*
2293	* @returns VINF_EM_RAW_GUEST_TRAP.
2294	* @param pVCpu The virtual CPU to operate on.
2295	* @param uErr The error code of the shadow fault. Corrections to
2296	* TRPM's copy will be made if necessary.
2297	* @param GCPtrPage For logging.
2298	* @param uPageFaultLevel For logging.
2299	*/
2300	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2301	{
2302	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2303	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2304	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2305	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2306	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2307
2308	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2309	return VINF_EM_RAW_GUEST_TRAP;
2310	}
2311
2312
2313	/**
2314	* CheckPageFault helper for returning a page fault indicating a reserved bit
2315	* (RSVD) error in the page translation structures.
2316	*
2317	* @returns VINF_EM_RAW_GUEST_TRAP.
2318	* @param pVCpu The virtual CPU to operate on.
2319	* @param uErr The error code of the shadow fault. Corrections to
2320	* TRPM's copy will be made if necessary.
2321	* @param GCPtrPage For logging.
2322	* @param uPageFaultLevel For logging.
2323	*/
2324	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2325	{
2326	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2327	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2328	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2329
2330	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2331	return VINF_EM_RAW_GUEST_TRAP;
2332	}
2333
2334
2335	/**
2336	* CheckPageFault helper for returning a page protection fault (P).
2337	*
2338	* @returns VINF_EM_RAW_GUEST_TRAP.
2339	* @param pVCpu The virtual CPU to operate on.
2340	* @param uErr The error code of the shadow fault. Corrections to
2341	* TRPM's copy will be made if necessary.
2342	* @param GCPtrPage For logging.
2343	* @param uPageFaultLevel For logging.
2344	*/
2345	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2346	{
2347	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2348	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2349	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2350	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2351
2352	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2353	return VINF_EM_RAW_GUEST_TRAP;
2354	}
2355
2356
2357	/**
2358	* Handle dirty bit tracking faults.
2359	*
2360	* @returns VBox status code.
2361	* @param pVCpu The VMCPU handle.
2362	* @param uErr Page fault error code.
2363	* @param pPdeSrc Guest page directory entry.
2364	* @param pPdeDst Shadow page directory entry.
2365	* @param GCPtrPage Guest context page address.
2366	*/
2367	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2368	RTGCPTR GCPtrPage)
2369	{
2370	PVM pVM = pVCpu->CTX_SUFF(pVM);
2371	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2372	NOREF(uErr);
2373
2374	PGM_LOCK_ASSERT_OWNER(pVM);
2375
2376	/*
2377	* Handle big page.
2378	*/
2379	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2380	{
2381	if ( pPdeDst->n.u1Present
2382	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2383	{
2384	SHWPDE PdeDst = *pPdeDst;
2385
2386	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2387	Assert(pPdeSrc->b.u1Write);
2388
2389	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2390	* fault again and take this path to only invalidate the entry (see below).
2391	*/
2392	PdeDst.n.u1Write = 1;
2393	PdeDst.n.u1Accessed = 1;
2394	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2395	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2396	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2397	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2398	}
2399
2400	# ifdef IN_RING0
2401	/* Check for stale TLB entry; only applies to the SMP guest case. */
2402	if ( pVM->cCpus > 1
2403	&& pPdeDst->n.u1Write
2404	&& pPdeDst->n.u1Accessed)
2405	{
2406	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2407	if (pShwPage)
2408	{
2409	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2410	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2411	if (SHW_PTE_IS_P_RW(*pPteDst))
2412	{
2413	/* Stale TLB entry. */
2414	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2415	PGM_INVL_PG(pVCpu, GCPtrPage);
2416	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2417	}
2418	}
2419	}
2420	# endif /* IN_RING0 */
2421	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2422	}
2423
2424	/*
2425	* Map the guest page table.
2426	*/
2427	PGSTPT pPTSrc;
2428	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2429	if (RT_FAILURE(rc))
2430	{
2431	AssertRC(rc);
2432	return rc;
2433	}
2434
2435	if (pPdeDst->n.u1Present)
2436	{
2437	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2438	const GSTPTE PteSrc = *pPteSrc;
2439
2440	#ifndef IN_RING0
2441	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2442	* Our individual shadow handlers will provide more information and force a fatal exit.
2443	*/
2444	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2445	{
2446	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2447	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2448	}
2449	#endif
2450	/*
2451	* Map shadow page table.
2452	*/
2453	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2454	if (pShwPage)
2455	{
2456	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2457	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2458	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2459	{
2460	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2461	{
2462	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2463	SHWPTE PteDst = *pPteDst;
2464
2465	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2466	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2467
2468	Assert(PteSrc.n.u1Write);
2469
2470	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2471	* entry will not harm; write access will simply fault again and
2472	* take this path to only invalidate the entry.
2473	*/
2474	if (RT_LIKELY(pPage))
2475	{
2476	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2477	{
2478	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2479	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2480	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2481	SHW_PTE_SET_RO(PteDst);
2482	}
2483	else
2484	{
2485	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2486	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2487	{
2488	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2489	AssertRC(rc);
2490	}
2491	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2492	SHW_PTE_SET_RW(PteDst);
2493	else
2494	{
2495	/* Still applies to shared pages. */
2496	Assert(!PGM_PAGE_IS_ZERO(pPage));
2497	SHW_PTE_SET_RO(PteDst);
2498	}
2499	}
2500	}
2501	else
2502	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2503
2504	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2505	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2506	PGM_INVL_PG(pVCpu, GCPtrPage);
2507	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2508	}
2509
2510	# ifdef IN_RING0
2511	/* Check for stale TLB entry; only applies to the SMP guest case. */
2512	if ( pVM->cCpus > 1
2513	&& SHW_PTE_IS_RW(*pPteDst)
2514	&& SHW_PTE_IS_A(*pPteDst))
2515	{
2516	/* Stale TLB entry. */
2517	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2518	PGM_INVL_PG(pVCpu, GCPtrPage);
2519	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2520	}
2521	# endif
2522	}
2523	}
2524	else
2525	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2526	}
2527
2528	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2529	}
2530
2531	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2532
2533
2534	/**
2535	* Sync a shadow page table.
2536	*
2537	* The shadow page table is not present in the shadow PDE.
2538	*
2539	* Handles mapping conflicts.
2540	*
2541	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2542	* conflict), and Trap0eHandler.
2543	*
2544	* A precondition for this method is that the shadow PDE is not present. The
2545	* caller must take the PGM lock before checking this and continue to hold it
2546	* when calling this method.
2547	*
2548	* @returns VBox status code.
2549	* @param pVCpu The VMCPU handle.
2550	* @param iPD Page directory index.
2551	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2552	* Assume this is a temporary mapping.
2553	* @param GCPtrPage GC Pointer of the page that caused the fault
2554	*/
2555	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2556	{
2557	PVM pVM = pVCpu->CTX_SUFF(pVM);
2558	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2559
2560	#if 0 /* rarely useful; leave for debugging. */
2561	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2562	#endif
2563	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2564
2565	PGM_LOCK_ASSERT_OWNER(pVM);
2566
2567	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2568	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2569	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2570	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2571	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2572
2573	int rc = VINF_SUCCESS;
2574
2575	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2576
2577	/*
2578	* Some input validation first.
2579	*/
2580	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2581
2582	/*
2583	* Get the relevant shadow PDE entry.
2584	*/
2585	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2586	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2587	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2588
2589	/* Fetch the pgm pool shadow descriptor. */
2590	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2591	Assert(pShwPde);
2592
2593	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2594	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2595	PPGMPOOLPAGE pShwPde = NULL;
2596	PX86PDPAE pPDDst;
2597	PSHWPDE pPdeDst;
2598
2599	/* Fetch the pgm pool shadow descriptor. */
2600	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2601	AssertRCSuccessReturn(rc, rc);
2602	Assert(pShwPde);
2603
2604	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2605	pPdeDst = &pPDDst->a[iPDDst];
2606
2607	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2608	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2609	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2610	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2611	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2612	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2613	AssertRCSuccessReturn(rc, rc);
2614	Assert(pPDDst);
2615	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2616	# endif
2617	SHWPDE PdeDst = *pPdeDst;
2618
2619	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2620	/* Fetch the pgm pool shadow descriptor. */
2621	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2622	Assert(pShwPde);
2623	# endif
2624
2625	# ifndef PGM_WITHOUT_MAPPINGS
2626	/*
2627	* Check for conflicts.
2628	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2629	* R3: Simply resolve the conflict.
2630	*/
2631	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2632	{
2633	Assert(pgmMapAreMappingsEnabled(pVM));
2634	# ifndef IN_RING3
2635	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2636	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2637	return VERR_ADDRESS_CONFLICT;
2638
2639	# else /* IN_RING3 */
2640	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2641	Assert(pMapping);
2642	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2643	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2644	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2645	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2646	# else
2647	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2648	# endif
2649	if (RT_FAILURE(rc))
2650	{
2651	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2652	return rc;
2653	}
2654	PdeDst = *pPdeDst;
2655	# endif /* IN_RING3 */
2656	}
2657	# endif /* !PGM_WITHOUT_MAPPINGS */
2658	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2659
2660	/*
2661	* Sync the page directory entry.
2662	*/
2663	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2664	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2665	if ( PdeSrc.n.u1Present
2666	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2667	{
2668	/*
2669	* Allocate & map the page table.
2670	*/
2671	PSHWPT pPTDst;
2672	PPGMPOOLPAGE pShwPage;
2673	RTGCPHYS GCPhys;
2674	if (fPageTable)
2675	{
2676	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2677	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2678	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2679	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2680	# endif
2681	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2682	pShwPde->idx, iPDDst, false /fLockPage/,
2683	&pShwPage);
2684	}
2685	else
2686	{
2687	PGMPOOLACCESS enmAccess;
2688	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2689	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2690	# else
2691	const bool fNoExecute = false;
2692	# endif
2693
2694	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2695	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2696	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2697	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2698	# endif
2699	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2700	if (PdeSrc.n.u1User)
2701	{
2702	if (PdeSrc.n.u1Write)
2703	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2704	else
2705	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2706	}
2707	else
2708	{
2709	if (PdeSrc.n.u1Write)
2710	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2711	else
2712	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2713	}
2714	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2715	pShwPde->idx, iPDDst, false /fLockPage/,
2716	&pShwPage);
2717	}
2718	if (rc == VINF_SUCCESS)
2719	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2720	else if (rc == VINF_PGM_CACHED_PAGE)
2721	{
2722	/*
2723	* The PT was cached, just hook it up.
2724	*/
2725	if (fPageTable)
2726	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2727	else
2728	{
2729	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2730	/* (see explanation and assumptions further down.) */
2731	if ( !PdeSrc.b.u1Dirty
2732	&& PdeSrc.b.u1Write)
2733	{
2734	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2735	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2736	PdeDst.b.u1Write = 0;
2737	}
2738	}
2739	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2740	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2741	return VINF_SUCCESS;
2742	}
2743	else if (rc == VERR_PGM_POOL_FLUSHED)
2744	{
2745	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2746	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2747	return VINF_PGM_SYNC_CR3;
2748	}
2749	else
2750	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2751	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2752	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2753	* irrelevant at this point. */
2754	PdeDst.u &= X86_PDE_AVL_MASK;
2755	PdeDst.u \|= pShwPage->Core.Key;
2756
2757	/*
2758	* Page directory has been accessed (this is a fault situation, remember).
2759	*/
2760	/** @todo
2761	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2762	* fault situation. What's more, the Trap0eHandler has already set the
2763	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2764	* might need setting the accessed flag.
2765	*
2766	* The best idea is to leave this change to the caller and add an
2767	* assertion that it's set already. */
2768	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2769	if (fPageTable)
2770	{
2771	/*
2772	* Page table - 4KB.
2773	*
2774	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2775	*/
2776	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2777	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2778	PGSTPT pPTSrc;
2779	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2780	if (RT_SUCCESS(rc))
2781	{
2782	/*
2783	* Start by syncing the page directory entry so CSAM's TLB trick works.
2784	*/
2785	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2786	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2787	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2788	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2789
2790	/*
2791	* Directory/page user or supervisor privilege: (same goes for read/write)
2792	*
2793	* Directory Page Combined
2794	* U/S U/S U/S
2795	* 0 0 0
2796	* 0 1 0
2797	* 1 0 0
2798	* 1 1 1
2799	*
2800	* Simple AND operation. Table listed for completeness.
2801	*
2802	*/
2803	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2804	# ifdef PGM_SYNC_N_PAGES
2805	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2806	unsigned iPTDst = iPTBase;
2807	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2808	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2809	iPTDst = 0;
2810	else
2811	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2812	# else /* !PGM_SYNC_N_PAGES */
2813	unsigned iPTDst = 0;
2814	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2815	# endif /* !PGM_SYNC_N_PAGES */
2816	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2817	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2818	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2819	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2820	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2821	# else
2822	const unsigned offPTSrc = 0;
2823	# endif
2824	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2825	{
2826	const unsigned iPTSrc = iPTDst + offPTSrc;
2827	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2828
2829	if (PteSrc.n.u1Present)
2830	{
2831	# ifndef IN_RING0
2832	/*
2833	* Assuming kernel code will be marked as supervisor - and not as user level
2834	* and executed using a conforming code selector - And marked as readonly.
2835	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2836	*/
2837	PPGMPAGE pPage;
2838	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2839	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2840	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2841	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2842	)
2843	# endif
2844	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2845	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2846	GCPtrCur,
2847	PteSrc.n.u1Present,
2848	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2849	PteSrc.n.u1User & PdeSrc.n.u1User,
2850	(uint64_t)PteSrc.u,
2851	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2852	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2853	}
2854	/* else: the page table was cleared by the pool */
2855	} /* for PTEs */
2856	}
2857	}
2858	else
2859	{
2860	/*
2861	* Big page - 2/4MB.
2862	*
2863	* We'll walk the ram range list in parallel and optimize lookups.
2864	* We will only sync one shadow page table at a time.
2865	*/
2866	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2867
2868	/**
2869	* @todo It might be more efficient to sync only a part of the 4MB
2870	* page (similar to what we do for 4KB PDs).
2871	*/
2872
2873	/*
2874	* Start by syncing the page directory entry.
2875	*/
2876	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2877	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2878
2879	/*
2880	* If the page is not flagged as dirty and is writable, then make it read-only
2881	* at PD level, so we can set the dirty bit when the page is modified.
2882	*
2883	* ASSUMES that page access handlers are implemented on page table entry level.
2884	* Thus we will first catch the dirty access and set PDE.D and restart. If
2885	* there is an access handler, we'll trap again and let it work on the problem.
2886	*/
2887	/** @todo move the above stuff to a section in the PGM documentation. */
2888	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2889	if ( !PdeSrc.b.u1Dirty
2890	&& PdeSrc.b.u1Write)
2891	{
2892	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2893	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2894	PdeDst.b.u1Write = 0;
2895	}
2896	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2897	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2898
2899	/*
2900	* Fill the shadow page table.
2901	*/
2902	/* Get address and flags from the source PDE. */
2903	SHWPTE PteDstBase;
2904	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2905
2906	/* Loop thru the entries in the shadow PT. */
2907	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2908	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2909	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2910	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2911	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2912	unsigned iPTDst = 0;
2913	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2914	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2915	{
2916	if (pRam && GCPhys >= pRam->GCPhys)
2917	{
2918	# ifndef PGM_WITH_A20
2919	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2920	# endif
2921	do
2922	{
2923	/* Make shadow PTE. */
2924	# ifdef PGM_WITH_A20
2925	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2926	# else
2927	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2928	# endif
2929	SHWPTE PteDst;
2930
2931	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2932	/* Try to make the page writable if necessary. */
2933	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2934	&& ( PGM_PAGE_IS_ZERO(pPage)
2935	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2936	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2937	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2938	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2939	# endif
2940	# ifdef VBOX_WITH_PAGE_SHARING
2941	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2942	# endif
2943	&& !PGM_PAGE_IS_BALLOONED(pPage))
2944	)
2945	)
2946	{
2947	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2948	AssertRCReturn(rc, rc);
2949	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2950	break;
2951	}
2952	# endif
2953
2954	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2955	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2956	else if (PGM_PAGE_IS_BALLOONED(pPage))
2957	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2958	# ifndef IN_RING0
2959	/*
2960	* Assuming kernel code will be marked as supervisor and not as user level and executed
2961	* using a conforming code selector. Don't check for readonly, as that implies the whole
2962	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2963	*/
2964	else if ( !PdeSrc.n.u1User
2965	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2966	SHW_PTE_SET(PteDst, 0);
2967	# endif
2968	else
2969	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2970
2971	/* Only map writable pages writable. */
2972	if ( SHW_PTE_IS_P_RW(PteDst)
2973	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2974	{
2975	/* Still applies to shared pages. */
2976	Assert(!PGM_PAGE_IS_ZERO(pPage));
2977	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2978	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2979	}
2980
2981	if (SHW_PTE_IS_P(PteDst))
2982	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2983
2984	/* commit it (not atomic, new table) */
2985	pPTDst->a[iPTDst] = PteDst;
2986	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2987	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2988	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2989
2990	/* advance */
2991	GCPhys += PAGE_SIZE;
2992	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2993	# ifndef PGM_WITH_A20
2994	iHCPage++;
2995	# endif
2996	iPTDst++;
2997	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2998	&& GCPhys <= pRam->GCPhysLast);
2999
3000	/* Advance ram range list. */
3001	while (pRam && GCPhys > pRam->GCPhysLast)
3002	pRam = pRam->CTX_SUFF(pNext);
3003	}
3004	else if (pRam)
3005	{
3006	Log(("Invalid pages at %RGp\n", GCPhys));
3007	do
3008	{
3009	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3010	GCPhys += PAGE_SIZE;
3011	iPTDst++;
3012	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3013	&& GCPhys < pRam->GCPhys);
3014	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3015	}
3016	else
3017	{
3018	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3019	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3020	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3021	}
3022	} /* while more PTEs */
3023	} /* 4KB / 4MB */
3024	}
3025	else
3026	AssertRelease(!PdeDst.n.u1Present);
3027
3028	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3029	if (RT_FAILURE(rc))
3030	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3031	return rc;
3032
3033	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3034	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3035	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3036	&& !defined(IN_RC)
3037	NOREF(iPDSrc); NOREF(pPDSrc);
3038
3039	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3040
3041	/*
3042	* Validate input a little bit.
3043	*/
3044	int rc = VINF_SUCCESS;
3045	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3046	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3047	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3048
3049	/* Fetch the pgm pool shadow descriptor. */
3050	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3051	Assert(pShwPde);
3052
3053	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3054	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3055	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3056	PX86PDPAE pPDDst;
3057	PSHWPDE pPdeDst;
3058
3059	/* Fetch the pgm pool shadow descriptor. */
3060	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3061	AssertRCSuccessReturn(rc, rc);
3062	Assert(pShwPde);
3063
3064	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3065	pPdeDst = &pPDDst->a[iPDDst];
3066
3067	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3068	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3069	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3070	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3071	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3072	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3073	AssertRCSuccessReturn(rc, rc);
3074	Assert(pPDDst);
3075	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3076
3077	/* Fetch the pgm pool shadow descriptor. */
3078	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3079	Assert(pShwPde);
3080
3081	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3082	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3083	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3084	PEPTPD pPDDst;
3085	PEPTPDPT pPdptDst;
3086
3087	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3088	if (rc != VINF_SUCCESS)
3089	{
3090	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3091	AssertRC(rc);
3092	return rc;
3093	}
3094	Assert(pPDDst);
3095	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3096
3097	/* Fetch the pgm pool shadow descriptor. */
3098	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3099	Assert(pShwPde);
3100	# endif
3101	SHWPDE PdeDst = *pPdeDst;
3102
3103	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3104	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3105
3106	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3107	if (BTH_IS_NP_ACTIVE(pVM))
3108	{
3109	/* Check if we allocated a big page before for this 2 MB range. */
3110	PPGMPAGE pPage;
3111	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3112	if (RT_SUCCESS(rc))
3113	{
3114	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3115	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3116	{
3117	if (PGM_A20_IS_ENABLED(pVCpu))
3118	{
3119	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3120	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3121	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3122	}
3123	else
3124	{
3125	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3126	pVM->pgm.s.cLargePagesDisabled++;
3127	}
3128	}
3129	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3130	&& PGM_A20_IS_ENABLED(pVCpu))
3131	{
3132	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3133	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3134	if (RT_SUCCESS(rc))
3135	{
3136	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3137	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3138	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3139	}
3140	}
3141	else if ( PGMIsUsingLargePages(pVM)
3142	&& PGM_A20_IS_ENABLED(pVCpu))
3143	{
3144	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3145	if (RT_SUCCESS(rc))
3146	{
3147	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3148	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3149	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3150	}
3151	else
3152	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3153	}
3154
3155	if (HCPhys != NIL_RTHCPHYS)
3156	{
3157	PdeDst.u &= X86_PDE_AVL_MASK;
3158	PdeDst.u \|= HCPhys;
3159	PdeDst.n.u1Present = 1;
3160	PdeDst.n.u1Write = 1;
3161	PdeDst.b.u1Size = 1;
3162	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3163	PdeDst.n.u1Execute = 1;
3164	PdeDst.b.u1IgnorePAT = 1;
3165	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3166	# else
3167	PdeDst.n.u1User = 1;
3168	# endif
3169	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3170
3171	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3172	/* Add a reference to the first page only. */
3173	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3174
3175	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3176	return VINF_SUCCESS;
3177	}
3178	}
3179	}
3180	# endif /* HC_ARCH_BITS == 64 */
3181
3182	/*
3183	* Allocate & map the page table.
3184	*/
3185	PSHWPT pPTDst;
3186	PPGMPOOLPAGE pShwPage;
3187	RTGCPHYS GCPhys;
3188
3189	/* Virtual address = physical address */
3190	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3191	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3192	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3193	&pShwPage);
3194	if ( rc == VINF_SUCCESS
3195	\|\| rc == VINF_PGM_CACHED_PAGE)
3196	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3197	else
3198	{
3199	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3200	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3201	}
3202
3203	if (rc == VINF_SUCCESS)
3204	{
3205	/* New page table; fully set it up. */
3206	Assert(pPTDst);
3207
3208	/* Mask away the page offset. */
3209	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3210
3211	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3212	{
3213	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3214	\| (iPTDst << PAGE_SHIFT));
3215
3216	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3217	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3218	GCPtrCurPage,
3219	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3220	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3221
3222	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3223	break;
3224	}
3225	}
3226	else
3227	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3228
3229	/* Save the new PDE. */
3230	PdeDst.u &= X86_PDE_AVL_MASK;
3231	PdeDst.u \|= pShwPage->Core.Key;
3232	PdeDst.n.u1Present = 1;
3233	PdeDst.n.u1Write = 1;
3234	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3235	PdeDst.n.u1Execute = 1;
3236	# else
3237	PdeDst.n.u1User = 1;
3238	PdeDst.n.u1Accessed = 1;
3239	# endif
3240	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3241
3242	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3243	if (RT_FAILURE(rc))
3244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3245	return rc;
3246
3247	#else
3248	NOREF(iPDSrc); NOREF(pPDSrc);
3249	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3250	return VERR_PGM_NOT_USED_IN_MODE;
3251	#endif
3252	}
3253
3254
3255
3256	/**
3257	* Prefetch a page/set of pages.
3258	*
3259	* Typically used to sync commonly used pages before entering raw mode
3260	* after a CR3 reload.
3261	*
3262	* @returns VBox status code.
3263	* @param pVCpu The VMCPU handle.
3264	* @param GCPtrPage Page to invalidate.
3265	*/
3266	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3267	{
3268	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3269	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3270	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3271	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3272	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3273	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3274	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3275
3276	/*
3277	* Check that all Guest levels thru the PDE are present, getting the
3278	* PD and PDE in the processes.
3279	*/
3280	int rc = VINF_SUCCESS;
3281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3282	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3283	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3284	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3285	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3286	unsigned iPDSrc;
3287	X86PDPE PdpeSrc;
3288	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3289	if (!pPDSrc)
3290	return VINF_SUCCESS; /* not present */
3291	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3292	unsigned iPDSrc;
3293	PX86PML4E pPml4eSrc;
3294	X86PDPE PdpeSrc;
3295	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3296	if (!pPDSrc)
3297	return VINF_SUCCESS; /* not present */
3298	# endif
3299	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3300	# else
3301	PGSTPD pPDSrc = NULL;
3302	const unsigned iPDSrc = 0;
3303	GSTPDE PdeSrc;
3304
3305	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3306	PdeSrc.n.u1Present = 1;
3307	PdeSrc.n.u1Write = 1;
3308	PdeSrc.n.u1Accessed = 1;
3309	PdeSrc.n.u1User = 1;
3310	# endif
3311
3312	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3313	{
3314	PVM pVM = pVCpu->CTX_SUFF(pVM);
3315	pgmLock(pVM);
3316
3317	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3318	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3319	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3320	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3321	PX86PDPAE pPDDst;
3322	X86PDEPAE PdeDst;
3323	# if PGM_GST_TYPE != PGM_TYPE_PAE
3324	X86PDPE PdpeSrc;
3325
3326	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3327	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3328	# endif
3329	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3330	if (rc != VINF_SUCCESS)
3331	{
3332	pgmUnlock(pVM);
3333	AssertRC(rc);
3334	return rc;
3335	}
3336	Assert(pPDDst);
3337	PdeDst = pPDDst->a[iPDDst];
3338
3339	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3340	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3341	PX86PDPAE pPDDst;
3342	X86PDEPAE PdeDst;
3343
3344	# if PGM_GST_TYPE == PGM_TYPE_PROT
3345	/* AMD-V nested paging */
3346	X86PML4E Pml4eSrc;
3347	X86PDPE PdpeSrc;
3348	PX86PML4E pPml4eSrc = &Pml4eSrc;
3349
3350	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3351	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3352	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3353	# endif
3354
3355	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3356	if (rc != VINF_SUCCESS)
3357	{
3358	pgmUnlock(pVM);
3359	AssertRC(rc);
3360	return rc;
3361	}
3362	Assert(pPDDst);
3363	PdeDst = pPDDst->a[iPDDst];
3364	# endif
3365	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3366	{
3367	if (!PdeDst.n.u1Present)
3368	{
3369	/** @todo r=bird: This guy will set the A bit on the PDE,
3370	* probably harmless. */
3371	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3372	}
3373	else
3374	{
3375	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3376	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3377	* makes no sense to prefetch more than one page.
3378	*/
3379	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3380	if (RT_SUCCESS(rc))
3381	rc = VINF_SUCCESS;
3382	}
3383	}
3384	pgmUnlock(pVM);
3385	}
3386	return rc;
3387
3388	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3389	NOREF(pVCpu); NOREF(GCPtrPage);
3390	return VINF_SUCCESS; /* ignore */
3391	#else
3392	AssertCompile(0);
3393	#endif
3394	}
3395
3396
3397
3398
3399	/**
3400	* Syncs a page during a PGMVerifyAccess() call.
3401	*
3402	* @returns VBox status code (informational included).
3403	* @param pVCpu The VMCPU handle.
3404	* @param GCPtrPage The address of the page to sync.
3405	* @param fPage The effective guest page flags.
3406	* @param uErr The trap error code.
3407	* @remarks This will normally never be called on invalid guest page
3408	* translation entries.
3409	*/
3410	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3411	{
3412	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3413
3414	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3415
3416	Assert(!pVM->pgm.s.fNestedPaging);
3417	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3418	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3419	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3420	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3421	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3422	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3423	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3424
3425	# ifndef IN_RING0
3426	if (!(fPage & X86_PTE_US))
3427	{
3428	/*
3429	* Mark this page as safe.
3430	*/
3431	/** @todo not correct for pages that contain both code and data!! */
3432	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3433	CSAMMarkPage(pVM, GCPtrPage, true);
3434	}
3435	# endif
3436
3437	/*
3438	* Get guest PD and index.
3439	*/
3440	/** @todo Performance: We've done all this a jiffy ago in the
3441	* PGMGstGetPage call. */
3442	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3443	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3444	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3445	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3446
3447	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3448	unsigned iPDSrc = 0;
3449	X86PDPE PdpeSrc;
3450	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3451	if (RT_UNLIKELY(!pPDSrc))
3452	{
3453	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3454	return VINF_EM_RAW_GUEST_TRAP;
3455	}
3456
3457	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3458	unsigned iPDSrc = 0; /* shut up gcc */
3459	PX86PML4E pPml4eSrc = NULL; /* ditto */
3460	X86PDPE PdpeSrc;
3461	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3462	if (RT_UNLIKELY(!pPDSrc))
3463	{
3464	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3465	return VINF_EM_RAW_GUEST_TRAP;
3466	}
3467	# endif
3468
3469	# else /* !PGM_WITH_PAGING */
3470	PGSTPD pPDSrc = NULL;
3471	const unsigned iPDSrc = 0;
3472	# endif /* !PGM_WITH_PAGING */
3473	int rc = VINF_SUCCESS;
3474
3475	pgmLock(pVM);
3476
3477	/*
3478	* First check if the shadow pd is present.
3479	*/
3480	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3481	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3482
3483	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3484	PX86PDEPAE pPdeDst;
3485	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3486	PX86PDPAE pPDDst;
3487	# if PGM_GST_TYPE != PGM_TYPE_PAE
3488	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3489	X86PDPE PdpeSrc;
3490	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3491	# endif
3492	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3493	if (rc != VINF_SUCCESS)
3494	{
3495	pgmUnlock(pVM);
3496	AssertRC(rc);
3497	return rc;
3498	}
3499	Assert(pPDDst);
3500	pPdeDst = &pPDDst->a[iPDDst];
3501
3502	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3503	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3504	PX86PDPAE pPDDst;
3505	PX86PDEPAE pPdeDst;
3506
3507	# if PGM_GST_TYPE == PGM_TYPE_PROT
3508	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3509	X86PML4E Pml4eSrc;
3510	X86PDPE PdpeSrc;
3511	PX86PML4E pPml4eSrc = &Pml4eSrc;
3512	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3513	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3514	# endif
3515
3516	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3517	if (rc != VINF_SUCCESS)
3518	{
3519	pgmUnlock(pVM);
3520	AssertRC(rc);
3521	return rc;
3522	}
3523	Assert(pPDDst);
3524	pPdeDst = &pPDDst->a[iPDDst];
3525	# endif
3526
3527	if (!pPdeDst->n.u1Present)
3528	{
3529	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3530	if (rc != VINF_SUCCESS)
3531	{
3532	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3533	pgmUnlock(pVM);
3534	AssertRC(rc);
3535	return rc;
3536	}
3537	}
3538
3539	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3540	/* Check for dirty bit fault */
3541	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3542	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3543	Log(("PGMVerifyAccess: success (dirty)\n"));
3544	else
3545	# endif
3546	{
3547	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3548	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3549	# else
3550	GSTPDE PdeSrc;
3551	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3552	PdeSrc.n.u1Present = 1;
3553	PdeSrc.n.u1Write = 1;
3554	PdeSrc.n.u1Accessed = 1;
3555	PdeSrc.n.u1User = 1;
3556	# endif
3557
3558	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3559	if (uErr & X86_TRAP_PF_US)
3560	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3561	else /* supervisor */
3562	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3563
3564	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3565	if (RT_SUCCESS(rc))
3566	{
3567	/* Page was successfully synced */
3568	Log2(("PGMVerifyAccess: success (sync)\n"));
3569	rc = VINF_SUCCESS;
3570	}
3571	else
3572	{
3573	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3574	rc = VINF_EM_RAW_GUEST_TRAP;
3575	}
3576	}
3577	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3578	pgmUnlock(pVM);
3579	return rc;
3580
3581	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3582
3583	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3584	return VERR_PGM_NOT_USED_IN_MODE;
3585	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3586	}
3587
3588
3589	/**
3590	* Syncs the paging hierarchy starting at CR3.
3591	*
3592	* @returns VBox status code, no specials.
3593	* @param pVCpu The VMCPU handle.
3594	* @param cr0 Guest context CR0 register.
3595	* @param cr3 Guest context CR3 register. Not subjected to the A20
3596	* mask.
3597	* @param cr4 Guest context CR4 register.
3598	* @param fGlobal Including global page directories or not
3599	*/
3600	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3601	{
3602	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3603	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3604
3605	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3606
3607	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3608
3609	pgmLock(pVM);
3610
3611	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3612	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3613	if (pPool->cDirtyPages)
3614	pgmPoolResetDirtyPages(pVM);
3615	# endif
3616
3617	/*
3618	* Update page access handlers.
3619	* The virtual are always flushed, while the physical are only on demand.
3620	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3621	* have to look into that later because it will have a bad influence on the performance.
3622	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3623	* bird: Yes, but that won't work for aliases.
3624	*/
3625	/** @todo this MUST go away. See @bugref{1557}. */
3626	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3627	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3628	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3629	pgmUnlock(pVM);
3630	#endif /* !NESTED && !EPT */
3631
3632	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3633	/*
3634	* Nested / EPT - almost no work.
3635	*/
3636	Assert(!pgmMapAreMappingsEnabled(pVM));
3637	return VINF_SUCCESS;
3638
3639	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3640	/*
3641	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3642	* out the shadow parts when the guest modifies its tables.
3643	*/
3644	Assert(!pgmMapAreMappingsEnabled(pVM));
3645	return VINF_SUCCESS;
3646
3647	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3648
3649	# ifndef PGM_WITHOUT_MAPPINGS
3650	/*
3651	* Check for and resolve conflicts with our guest mappings if they
3652	* are enabled and not fixed.
3653	*/
3654	if (pgmMapAreMappingsFloating(pVM))
3655	{
3656	int rc = pgmMapResolveConflicts(pVM);
3657	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3658	if (rc == VINF_PGM_SYNC_CR3)
3659	{
3660	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3661	return VINF_PGM_SYNC_CR3;
3662	}
3663	}
3664	# else
3665	Assert(!pgmMapAreMappingsEnabled(pVM));
3666	# endif
3667	return VINF_SUCCESS;
3668	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3669	}
3670
3671
3672
3673
3674	#ifdef VBOX_STRICT
3675	# ifdef IN_RC
3676	# undef AssertMsgFailed
3677	# define AssertMsgFailed Log
3678	# endif
3679
3680	/**
3681	* Checks that the shadow page table is in sync with the guest one.
3682	*
3683	* @returns The number of errors.
3684	* @param pVM The virtual machine.
3685	* @param pVCpu The VMCPU handle.
3686	* @param cr3 Guest context CR3 register.
3687	* @param cr4 Guest context CR4 register.
3688	* @param GCPtr Where to start. Defaults to 0.
3689	* @param cb How much to check. Defaults to everything.
3690	*/
3691	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3692	{
3693	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3694	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3695	return 0;
3696	#else
3697	unsigned cErrors = 0;
3698	PVM pVM = pVCpu->CTX_SUFF(pVM);
3699	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3700
3701	# if PGM_GST_TYPE == PGM_TYPE_PAE
3702	/** @todo currently broken; crashes below somewhere */
3703	AssertFailed();
3704	# endif
3705
3706	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3707	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3708	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3709
3710	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3711	PPGMCPU pPGM = &pVCpu->pgm.s;
3712	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3713	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3714	# ifndef IN_RING0
3715	RTHCPHYS HCPhys; /* general usage. */
3716	# endif
3717	int rc;
3718
3719	/*
3720	* Check that the Guest CR3 and all its mappings are correct.
3721	*/
3722	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3723	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3724	false);
3725	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3726	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3727	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3728	# else
3729	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3730	# endif
3731	AssertRCReturn(rc, 1);
3732	HCPhys = NIL_RTHCPHYS;
3733	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3734	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3735	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3736	pgmGstGet32bitPDPtr(pVCpu);
3737	RTGCPHYS GCPhys;
3738	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3739	AssertRCReturn(rc, 1);
3740	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3741	# endif
3742	# endif /* !IN_RING0 */
3743
3744	/*
3745	* Get and check the Shadow CR3.
3746	*/
3747	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3748	unsigned cPDEs = X86_PG_ENTRIES;
3749	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3750	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3751	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3752	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3753	# else
3754	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3755	# endif
3756	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3757	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3758	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3759	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3760	# endif
3761	if (cb != ~(RTGCPTR)0)
3762	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3763
3764	/** @todo call the other two PGMAssert() functions. /
3765
3766	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3767	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3768
3769	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3770	{
3771	PPGMPOOLPAGE pShwPdpt = NULL;
3772	PX86PML4E pPml4eSrc;
3773	PX86PML4E pPml4eDst;
3774	RTGCPHYS GCPhysPdptSrc;
3775
3776	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3777	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3778
3779	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3780	if (!pPml4eDst->n.u1Present)
3781	{
3782	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3783	continue;
3784	}
3785
3786	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3787	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3788
3789	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3790	{
3791	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3792	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3793	cErrors++;
3794	continue;
3795	}
3796
3797	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3798	{
3799	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3800	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3801	cErrors++;
3802	continue;
3803	}
3804
3805	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3806	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3807	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3808	{
3809	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3810	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3811	cErrors++;
3812	continue;
3813	}
3814	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3815	{
3816	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3817
3818	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3819	/*
3820	* Check the PDPTEs too.
3821	*/
3822	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3823
3824	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3825	{
3826	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3827	PPGMPOOLPAGE pShwPde = NULL;
3828	PX86PDPE pPdpeDst;
3829	RTGCPHYS GCPhysPdeSrc;
3830	X86PDPE PdpeSrc;
3831	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3832	# if PGM_GST_TYPE == PGM_TYPE_PAE
3833	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3834	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3835	# else
3836	PX86PML4E pPml4eSrcIgn;
3837	PX86PDPT pPdptDst;
3838	PX86PDPAE pPDDst;
3839	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3840
3841	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3842	if (rc != VINF_SUCCESS)
3843	{
3844	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3845	GCPtr += 512 * _2M;
3846	continue; /* next PDPTE */
3847	}
3848	Assert(pPDDst);
3849	# endif
3850	Assert(iPDSrc == 0);
3851
3852	pPdpeDst = &pPdptDst->a[iPdpt];
3853
3854	if (!pPdpeDst->n.u1Present)
3855	{
3856	GCPtr += 512 * _2M;
3857	continue; /* next PDPTE */
3858	}
3859
3860	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3861	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3862
3863	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3864	{
3865	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3866	GCPtr += 512 * _2M;
3867	cErrors++;
3868	continue;
3869	}
3870
3871	if (GCPhysPdeSrc != pShwPde->GCPhys)
3872	{
3873	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3874	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3875	# else
3876	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3877	# endif
3878	GCPtr += 512 * _2M;
3879	cErrors++;
3880	continue;
3881	}
3882
3883	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3884	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3885	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3886	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3887	{
3888	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3889	GCPtr += 512 * _2M;
3890	cErrors++;
3891	continue;
3892	}
3893	# endif
3894
3895	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3896	{
3897	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3898	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3899	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3900	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3901	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3902	# endif
3903	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3904	/*
3905	* Iterate the shadow page directory.
3906	*/
3907	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3908	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3909
3910	for (;
3911	iPDDst < cPDEs;
3912	iPDDst++, GCPtr += cIncrement)
3913	{
3914	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3915	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3916	# else
3917	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3918	# endif
3919	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3920	{
3921	Assert(pgmMapAreMappingsEnabled(pVM));
3922	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3923	{
3924	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3925	cErrors++;
3926	continue;
3927	}
3928	}
3929	else if ( (PdeDst.u & X86_PDE_P)
3930	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3931	)
3932	{
3933	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3934	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3935	if (!pPoolPage)
3936	{
3937	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3938	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3939	cErrors++;
3940	continue;
3941	}
3942	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3943
3944	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3945	{
3946	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3947	GCPtr, (uint64_t)PdeDst.u));
3948	cErrors++;
3949	}
3950
3951	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3952	{
3953	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3954	GCPtr, (uint64_t)PdeDst.u));
3955	cErrors++;
3956	}
3957
3958	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3959	if (!PdeSrc.n.u1Present)
3960	{
3961	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3962	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3963	cErrors++;
3964	continue;
3965	}
3966
3967	if ( !PdeSrc.b.u1Size
3968	\|\| !fBigPagesSupported)
3969	{
3970	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3971	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3972	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3973	# endif
3974	}
3975	else
3976	{
3977	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3978	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3979	{
3980	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3981	GCPtr, (uint64_t)PdeSrc.u));
3982	cErrors++;
3983	continue;
3984	}
3985	# endif
3986	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3987	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3988	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3989	# endif
3990	}
3991
3992	if ( pPoolPage->enmKind
3993	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3994	{
3995	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3996	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3997	cErrors++;
3998	}
3999
4000	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4001	if (!pPhysPage)
4002	{
4003	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4004	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4005	cErrors++;
4006	continue;
4007	}
4008
4009	if (GCPhysGst != pPoolPage->GCPhys)
4010	{
4011	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4012	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4013	cErrors++;
4014	continue;
4015	}
4016
4017	if ( !PdeSrc.b.u1Size
4018	\|\| !fBigPagesSupported)
4019	{
4020	/*
4021	* Page Table.
4022	*/
4023	const GSTPT *pPTSrc;
4024	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4025	&pPTSrc);
4026	if (RT_FAILURE(rc))
4027	{
4028	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4029	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4030	cErrors++;
4031	continue;
4032	}
4033	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4034	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4035	{
4036	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4037	// (This problem will go away when/if we shadow multiple CR3s.)
4038	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4039	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4040	cErrors++;
4041	continue;
4042	}
4043	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4044	{
4045	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4046	GCPtr, (uint64_t)PdeDst.u));
4047	cErrors++;
4048	continue;
4049	}
4050
4051	/* iterate the page table. */
4052	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4053	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4054	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4055	# else
4056	const unsigned offPTSrc = 0;
4057	# endif
4058	for (unsigned iPT = 0, off = 0;
4059	iPT < RT_ELEMENTS(pPTDst->a);
4060	iPT++, off += PAGE_SIZE)
4061	{
4062	const SHWPTE PteDst = pPTDst->a[iPT];
4063
4064	/* skip not-present and dirty tracked entries. */
4065	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4066	continue;
4067	Assert(SHW_PTE_IS_P(PteDst));
4068
4069	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4070	if (!PteSrc.n.u1Present)
4071	{
4072	# ifdef IN_RING3
4073	PGMAssertHandlerAndFlagsInSync(pVM);
4074	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4075	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4076	0, 0, UINT64_MAX, 99, NULL);
4077	# endif
4078	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4079	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4080	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4081	cErrors++;
4082	continue;
4083	}
4084
4085	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4086	# if 1 /** @todo sync accessed bit properly... */
4087	fIgnoreFlags \|= X86_PTE_A;
4088	# endif
4089
4090	/* match the physical addresses */
4091	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4092	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4093
4094	# ifdef IN_RING3
4095	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4096	if (RT_FAILURE(rc))
4097	{
4098	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4099	{
4100	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4101	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4102	cErrors++;
4103	continue;
4104	}
4105	}
4106	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4107	{
4108	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4109	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4110	cErrors++;
4111	continue;
4112	}
4113	# endif
4114
4115	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4116	if (!pPhysPage)
4117	{
4118	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4119	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4120	{
4121	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4122	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4123	cErrors++;
4124	continue;
4125	}
4126	# endif
4127	if (SHW_PTE_IS_RW(PteDst))
4128	{
4129	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4130	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4131	cErrors++;
4132	}
4133	fIgnoreFlags \|= X86_PTE_RW;
4134	}
4135	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4136	{
4137	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4138	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4139	cErrors++;
4140	continue;
4141	}
4142
4143	/* flags */
4144	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4145	{
4146	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4147	{
4148	if (SHW_PTE_IS_RW(PteDst))
4149	{
4150	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4151	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4152	cErrors++;
4153	continue;
4154	}
4155	fIgnoreFlags \|= X86_PTE_RW;
4156	}
4157	else
4158	{
4159	if ( SHW_PTE_IS_P(PteDst)
4160	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4161	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4162	# endif
4163	)
4164	{
4165	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4166	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4167	cErrors++;
4168	continue;
4169	}
4170	fIgnoreFlags \|= X86_PTE_P;
4171	}
4172	}
4173	else
4174	{
4175	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4176	{
4177	if (SHW_PTE_IS_RW(PteDst))
4178	{
4179	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4180	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4181	cErrors++;
4182	continue;
4183	}
4184	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4185	{
4186	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4187	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4188	cErrors++;
4189	continue;
4190	}
4191	if (SHW_PTE_IS_D(PteDst))
4192	{
4193	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4194	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4195	cErrors++;
4196	}
4197	# if 0 /** @todo sync access bit properly... */
4198	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4199	{
4200	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4201	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4202	cErrors++;
4203	}
4204	fIgnoreFlags \|= X86_PTE_RW;
4205	# else
4206	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4207	# endif
4208	}
4209	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4210	{
4211	/* access bit emulation (not implemented). */
4212	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4213	{
4214	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4215	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4216	cErrors++;
4217	continue;
4218	}
4219	if (!SHW_PTE_IS_A(PteDst))
4220	{
4221	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4222	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4223	cErrors++;
4224	}
4225	fIgnoreFlags \|= X86_PTE_P;
4226	}
4227	# ifdef DEBUG_sandervl
4228	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4229	# endif
4230	}
4231
4232	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4233	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4234	)
4235	{
4236	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4237	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4238	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4239	cErrors++;
4240	continue;
4241	}
4242	} /* foreach PTE */
4243	}
4244	else
4245	{
4246	/*
4247	* Big Page.
4248	*/
4249	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4250	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4251	{
4252	if (PdeDst.n.u1Write)
4253	{
4254	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4255	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4256	cErrors++;
4257	continue;
4258	}
4259	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4260	{
4261	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4262	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4263	cErrors++;
4264	continue;
4265	}
4266	# if 0 /** @todo sync access bit properly... */
4267	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4268	{
4269	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4270	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4271	cErrors++;
4272	}
4273	fIgnoreFlags \|= X86_PTE_RW;
4274	# else
4275	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4276	# endif
4277	}
4278	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4279	{
4280	/* access bit emulation (not implemented). */
4281	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4282	{
4283	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4284	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4285	cErrors++;
4286	continue;
4287	}
4288	if (!PdeDst.n.u1Accessed)
4289	{
4290	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4291	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4292	cErrors++;
4293	}
4294	fIgnoreFlags \|= X86_PTE_P;
4295	}
4296
4297	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4298	{
4299	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4300	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4301	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4302	cErrors++;
4303	}
4304
4305	/* iterate the page table. */
4306	for (unsigned iPT = 0, off = 0;
4307	iPT < RT_ELEMENTS(pPTDst->a);
4308	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4309	{
4310	const SHWPTE PteDst = pPTDst->a[iPT];
4311
4312	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4313	{
4314	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4315	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4316	cErrors++;
4317	}
4318
4319	/* skip not-present entries. */
4320	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4321	continue;
4322
4323	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4324
4325	/* match the physical addresses */
4326	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4327
4328	# ifdef IN_RING3
4329	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4330	if (RT_FAILURE(rc))
4331	{
4332	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4333	{
4334	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4335	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4336	cErrors++;
4337	}
4338	}
4339	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4340	{
4341	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4342	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4343	cErrors++;
4344	continue;
4345	}
4346	# endif
4347	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4348	if (!pPhysPage)
4349	{
4350	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4351	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4352	{
4353	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4354	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4355	cErrors++;
4356	continue;
4357	}
4358	# endif
4359	if (SHW_PTE_IS_RW(PteDst))
4360	{
4361	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4362	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4363	cErrors++;
4364	}
4365	fIgnoreFlags \|= X86_PTE_RW;
4366	}
4367	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4368	{
4369	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4370	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4371	cErrors++;
4372	continue;
4373	}
4374
4375	/* flags */
4376	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4377	{
4378	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4379	{
4380	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4381	{
4382	if (SHW_PTE_IS_RW(PteDst))
4383	{
4384	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4385	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4386	cErrors++;
4387	continue;
4388	}
4389	fIgnoreFlags \|= X86_PTE_RW;
4390	}
4391	}
4392	else
4393	{
4394	if ( SHW_PTE_IS_P(PteDst)
4395	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4396	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4397	# endif
4398	)
4399	{
4400	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4401	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4402	cErrors++;
4403	continue;
4404	}
4405	fIgnoreFlags \|= X86_PTE_P;
4406	}
4407	}
4408
4409	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4410	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4411	)
4412	{
4413	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4414	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4415	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4416	cErrors++;
4417	continue;
4418	}
4419	} /* for each PTE */
4420	}
4421	}
4422	/* not present */
4423
4424	} /* for each PDE */
4425
4426	} /* for each PDPTE */
4427
4428	} /* for each PML4E */
4429
4430	# ifdef DEBUG
4431	if (cErrors)
4432	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4433	# endif
4434	# endif /* GST is in {32BIT, PAE, AMD64} */
4435	return cErrors;
4436	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4437	}
4438	#endif /* VBOX_STRICT */
4439
4440
4441	/**
4442	* Sets up the CR3 for shadow paging
4443	*
4444	* @returns Strict VBox status code.
4445	* @retval VINF_SUCCESS.
4446	*
4447	* @param pVCpu The VMCPU handle.
4448	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4449	* mask already applied.)
4450	*/
4451	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4452	{
4453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4454
4455	/* Update guest paging info. */
4456	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4457	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4458	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4459
4460	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4461	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4462
4463	/*
4464	* Map the page CR3 points at.
4465	*/
4466	RTHCPTR HCPtrGuestCR3;
4467	RTHCPHYS HCPhysGuestCR3;
4468	pgmLock(pVM);
4469	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4470	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4471	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4472	/** @todo this needs some reworking wrt. locking? */
4473	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4474	HCPtrGuestCR3 = NIL_RTHCPTR;
4475	int rc = VINF_SUCCESS;
4476	# else
4477	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4478	# endif
4479	pgmUnlock(pVM);
4480	if (RT_SUCCESS(rc))
4481	{
4482	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4483	if (RT_SUCCESS(rc))
4484	{
4485	# ifdef IN_RC
4486	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4487	# endif
4488	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4489	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4490	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4491	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4492	# endif
4493	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4494
4495	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4496	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4497	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4498	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4499	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4500	# endif
4501	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4502	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4503
4504	/*
4505	* Map the 4 PDs too.
4506	*/
4507	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4508	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4509	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4510	{
4511	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4512	if (pGuestPDPT->a[i].n.u1Present)
4513	{
4514	RTHCPTR HCPtr;
4515	RTHCPHYS HCPhys;
4516	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4517	pgmLock(pVM);
4518	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4519	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4520	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4521	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4522	HCPtr = NIL_RTHCPTR;
4523	int rc2 = VINF_SUCCESS;
4524	# else
4525	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4526	# endif
4527	pgmUnlock(pVM);
4528	if (RT_SUCCESS(rc2))
4529	{
4530	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4531	AssertRCReturn(rc, rc);
4532
4533	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4534	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4535	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4536	# endif
4537	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4538	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4539	# ifdef IN_RC
4540	PGM_INVL_PG(pVCpu, GCPtr);
4541	# endif
4542	continue;
4543	}
4544	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4545	}
4546
4547	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4548	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4549	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4550	# endif
4551	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4552	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4553	# ifdef IN_RC
4554	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4555	# endif
4556	}
4557
4558	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4559	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4560	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4561	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4562	# endif
4563	# endif
4564	}
4565	else
4566	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4567	}
4568	else
4569	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4570
4571	#else /* prot/real stub */
4572	int rc = VINF_SUCCESS;
4573	#endif
4574
4575	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4576	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4577	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4578	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4579	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4580	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4581
4582	Assert(!pVM->pgm.s.fNestedPaging);
4583	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4584
4585	/*
4586	* Update the shadow root page as well since that's not fixed.
4587	*/
4588	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4589	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4590	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4591	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4592	PPGMPOOLPAGE pNewShwPageCR3;
4593
4594	pgmLock(pVM);
4595
4596	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4597	if (pPool->cDirtyPages)
4598	pgmPoolResetDirtyPages(pVM);
4599	# endif
4600
4601	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4602	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4603	SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/,
4604	&pNewShwPageCR3);
4605	AssertFatalRC(rc);
4606	rc = VINF_SUCCESS;
4607
4608	# ifdef IN_RC
4609	/*
4610	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4611	* state will be inconsistent! Flush important things now while
4612	* we still can and then make sure there are no ring-3 calls.
4613	*/
4614	# ifdef VBOX_WITH_REM
4615	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4616	# endif
4617	VMMRZCallRing3Disable(pVCpu);
4618	# endif
4619
4620	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4621	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4622	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4623	# ifdef IN_RING0
4624	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4625	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4626	# elif defined(IN_RC)
4627	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4628	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4629	# else
4630	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4631	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4632	# endif
4633
4634	# ifndef PGM_WITHOUT_MAPPINGS
4635	/*
4636	* Apply all hypervisor mappings to the new CR3.
4637	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4638	* make sure we check for conflicts in the new CR3 root.
4639	*/
4640	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4641	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4642	# endif
4643	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4644	AssertRCReturn(rc, rc);
4645	# endif
4646
4647	/* Set the current hypervisor CR3. */
4648	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4649	SELMShadowCR3Changed(pVM, pVCpu);
4650
4651	# ifdef IN_RC
4652	/* NOTE: The state is consistent again. */
4653	VMMRZCallRing3Enable(pVCpu);
4654	# endif
4655
4656	/* Clean up the old CR3 root. */
4657	if ( pOldShwPageCR3
4658	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4659	{
4660	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4661	# ifndef PGM_WITHOUT_MAPPINGS
4662	/* Remove the hypervisor mappings from the shadow page table. */
4663	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4664	# endif
4665	/* Mark the page as unlocked; allow flushing again. */
4666	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4667
4668	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4669	}
4670	pgmUnlock(pVM);
4671	# else
4672	NOREF(GCPhysCR3);
4673	# endif
4674
4675	return rc;
4676	}
4677
4678	/**
4679	* Unmaps the shadow CR3.
4680	*
4681	* @returns VBox status, no specials.
4682	* @param pVCpu The VMCPU handle.
4683	*/
4684	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4685	{
4686	LogFlow(("UnmapCR3\n"));
4687
4688	int rc = VINF_SUCCESS;
4689	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4690
4691	/*
4692	* Update guest paging info.
4693	*/
4694	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4695	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4696	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4697	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4698	# endif
4699	pVCpu->pgm.s.pGst32BitPdRC = 0;
4700
4701	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4702	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4703	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4704	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4705	# endif
4706	pVCpu->pgm.s.pGstPaePdptRC = 0;
4707	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4708	{
4709	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4710	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4711	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4712	# endif
4713	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4714	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4715	}
4716
4717	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4718	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4719	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4720	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4721	# endif
4722
4723	#else /* prot/real mode stub */
4724	/* nothing to do */
4725	#endif
4726
4727	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4728	/*
4729	* Update shadow paging info.
4730	*/
4731	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4732	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4733	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4734
4735	# if PGM_GST_TYPE != PGM_TYPE_REAL
4736	Assert(!pVM->pgm.s.fNestedPaging);
4737	# endif
4738
4739	pgmLock(pVM);
4740
4741	# ifndef PGM_WITHOUT_MAPPINGS
4742	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4743	/* Remove the hypervisor mappings from the shadow page table. */
4744	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4745	# endif
4746
4747	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4748	{
4749	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4750
4751	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4752
4753	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4754	if (pPool->cDirtyPages)
4755	pgmPoolResetDirtyPages(pVM);
4756	# endif
4757
4758	/* Mark the page as unlocked; allow flushing again. */
4759	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4760
4761	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4762	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4763	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4764	pVCpu->pgm.s.pShwPageCR3RC = 0;
4765	pVCpu->pgm.s.iShwUser = 0;
4766	pVCpu->pgm.s.iShwUserTable = 0;
4767	}
4768	pgmUnlock(pVM);
4769	# endif
4770	#endif /* !IN_RC*/
4771
4772	return rc;
4773	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 41774

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