PGMAllBth.h@ 101002

Last change on this file since 101002 was 101002, checked in by vboxsync, 18 months ago
VMM: Nested VMX: bugref:10318 Naming consistency nits.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 236.2 KB

Line
1	/* $Id: PGMAllBth.h 101002 2023-09-01 14:03:12Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#ifdef _MSC_VER
36	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
37	* real/prot-guest+RC mode. */
38	# pragma warning(disable: 4505)
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	RT_C_DECLS_BEGIN
46	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
47	#ifndef IN_RING3
48	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken);
49	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
50	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
51	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
52	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
53	unsigned iPte, PCPGMPTWALKGST pGstWalkAll);
54	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
55	uint32_t uErr, PPGMPTWALKGST pGstWalkAll);
56	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll);
57	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
58	#endif
59	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
60	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
61	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
62	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
63	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
64	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
65	#else
66	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
67	#endif
68	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
69	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
70	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
71	#ifdef VBOX_STRICT
72	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
73	#endif
74	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
75	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
76
77	#ifdef IN_RING3
78	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
79	#endif
80	RT_C_DECLS_END
81
82
83
84
85	/*
86	* Filter out some illegal combinations of guest and shadow paging, so we can
87	* remove redundant checks inside functions.
88	*/
89	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
90	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
91	# error "Invalid combination; PAE guest implies PAE shadow"
92	#endif
93
94	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
95	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
96	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
97	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
98	#endif
99
100	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
101	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
102	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
103	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
104	#endif
105
106	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
107	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
108	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
109	#endif
110
111
112	/**
113	* Enters the shadow+guest mode.
114	*
115	* @returns VBox status code.
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param GCPhysCR3 The physical address from the CR3 register.
118	*/
119	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
120	{
121	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
122	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
123	*/
124	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
125	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
126	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
127	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
128	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
129
130	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
131
132	Assert(!pVM->pgm.s.fNestedPaging);
133
134	PGM_LOCK_VOID(pVM);
135	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
136	* but any calls to GC need a proper shadow page setup as well.
137	*/
138	/* Free the previous root mapping if still active. */
139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
140	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
141	if (pOldShwPageCR3)
142	{
143	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
144
145	/* Mark the page as unlocked; allow flushing again. */
146	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
147
148	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
149	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
150	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
151	}
152
153	/* construct a fake address. */
154	GCPhysCR3 = RT_BIT_64(63);
155	PPGMPOOLPAGE pNewShwPageCR3;
156	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
157	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
158	&pNewShwPageCR3);
159	AssertRCReturn(rc, rc);
160
161	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
162	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
163
164	/* Mark the page as locked; disallow flushing. */
165	pgmPoolLockPage(pPool, pNewShwPageCR3);
166
167	/* Set the current hypervisor CR3. */
168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
169
170	PGM_UNLOCK(pVM);
171	return rc;
172	#else
173	NOREF(pVCpu); NOREF(GCPhysCR3);
174	return VINF_SUCCESS;
175	#endif
176	}
177
178
179	#ifndef IN_RING3
180
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	/**
183	* Deal with a guest page fault.
184	*
185	* @returns Strict VBox status code.
186	* @retval VINF_EM_RAW_GUEST_TRAP
187	* @retval VINF_EM_RAW_EMULATE_INSTR
188	*
189	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
190	* @param pWalk The guest page table walk result.
191	* @param uErr The error code.
192	*/
193	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
194	{
195	/*
196	* Calc the error code for the guest trap.
197	*/
198	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
199	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
200	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
201	if ( pWalk->fRsvdError
202	\|\| pWalk->fBadPhysAddr)
203	{
204	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
205	Assert(!pWalk->fNotPresent);
206	}
207	else if (!pWalk->fNotPresent)
208	uNewErr \|= X86_TRAP_PF_P;
209	TRPMSetErrorCode(pVCpu, uNewErr);
210
211	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
212	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
213	return VINF_EM_RAW_GUEST_TRAP;
214	}
215	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
216
217
218	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
219	/**
220	* Deal with a guest page fault.
221	*
222	* The caller has taken the PGM lock.
223	*
224	* @returns Strict VBox status code.
225	*
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param uErr The error code.
228	* @param pCtx Pointer to the register context for the CPU.
229	* @param pvFault The fault address.
230	* @param pPage The guest page at @a pvFault.
231	* @param pWalk The guest page table walk result.
232	* @param pGstWalk The guest paging-mode specific walk information.
233	* @param pfLockTaken PGM lock taken here or not (out). This is true
234	* when we're called.
235	*/
236	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
237	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
238	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
239	, PPGMPTWALK pWalk
240	, PGSTPTWALK pGstWalk
241	# endif
242	)
243	{
244	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
245	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
246	# endif
247	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
248	VBOXSTRICTRC rcStrict;
249
250	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
251	{
252	/*
253	* Physical page access handler.
254	*/
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
257	# else
258	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
259	# endif
260	PPGMPHYSHANDLER pCur;
261	rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysFault, &pCur);
262	if (RT_SUCCESS(rcStrict))
263	{
264	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
265
266	# ifdef PGM_SYNC_N_PAGES
267	/*
268	* If the region is write protected and we got a page not present fault, then sync
269	* the pages. If the fault was caused by a read, then restart the instruction.
270	* In case of write access continue to the GC write handler.
271	*
272	* ASSUMES that there is only one handler per page or that they have similar write properties.
273	*/
274	if ( !(uErr & X86_TRAP_PF_P)
275	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
276	{
277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
278	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
279	# else
280	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
281	# endif
282	if ( RT_FAILURE(rcStrict)
283	\|\| !(uErr & X86_TRAP_PF_RW)
284	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
285	{
286	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
288	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
289	return rcStrict;
290	}
291	}
292	# endif
293	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
294	/*
295	* If the access was not thru a #PF(RSVD\|...) resync the page.
296	*/
297	if ( !(uErr & X86_TRAP_PF_RSVD)
298	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
299	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
300	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
301	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
302	# endif
303	)
304	{
305	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
306	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
307	# else
308	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
309	# endif
310	if ( RT_FAILURE(rcStrict)
311	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
312	{
313	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
314	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
315	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
316	return rcStrict;
317	}
318	}
319	# endif
320
321	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
322	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
323	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
324	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
325	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
326	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
327	else
328	{
329	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
330	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
331	}
332
333	if (pCurType->pfnPfHandler)
334	{
335	STAM_PROFILE_START(&pCur->Stat, h);
336
337	if (pCurType->fKeepPgmLock)
338	{
339	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault,
340	!pCurType->fRing0DevInsIdx ? pCur->uUser
341	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
342
343	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
344	}
345	else
346	{
347	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
348	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
349	PGM_UNLOCK(pVM);
350	*pfLockTaken = false;
351
352	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser);
353
354	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
355	}
356	}
357	else
358	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
359
360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
361	return rcStrict;
362	}
363	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
364	}
365
366	/*
367	* There is a handled area of the page, but this fault doesn't belong to it.
368	* We must emulate the instruction.
369	*
370	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
371	* we first check if this was a page-not-present fault for a page with only
372	* write access handlers. Restart the instruction if it wasn't a write access.
373	*/
374	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
375
376	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
380	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
381	# else
382	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
383	# endif
384	if ( RT_FAILURE(rcStrict)
385	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
386	\|\| !(uErr & X86_TRAP_PF_RW))
387	{
388	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
389	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
390	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
391	return rcStrict;
392	}
393	}
394
395	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
396	* It's writing to an unhandled part of the LDT page several million times.
397	*/
398	rcStrict = PGMInterpretInstruction(pVCpu, pvFault);
399	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
400	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
401	return rcStrict;
402	} /* if any kind of handler */
403	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
404
405
406	/**
407	* \#PF Handler for raw-mode guest execution.
408	*
409	* @returns VBox status code (appropriate for trap handling and GC return).
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param uErr The trap error code.
413	* @param pCtx Pointer to the register context for the CPU.
414	* @param pvFault The fault address.
415	* @param pfLockTaken PGM lock taken here or not (out)
416	*/
417	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)
418	{
419	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
420
421	*pfLockTaken = false;
422
423	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
424	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
425	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
426	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
427	&& PGM_SHW_TYPE != PGM_TYPE_NONE
428	int rc;
429
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	/*
432	* Walk the guest page translation tables and check if it's a guest fault.
433	*/
434	PGMPTWALK Walk;
435	GSTPTWALK GstWalk;
436	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
437	if (RT_FAILURE_NP(rc))
438	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
439
440	/* assert some GstWalk sanity. */
441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
442	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
443	# endif
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
445	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
446	# endif
447	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
448	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
449	Assert(Walk.fSucceeded);
450	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
451
452	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
453	{
454	if ( ( (uErr & X86_TRAP_PF_RW)
455	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
456	&& ( (uErr & X86_TRAP_PF_US)
457	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
458	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
459	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
460	)
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
462	}
463
464	/* Take the big lock now before we update flags. */
465	*pfLockTaken = true;
466	PGM_LOCK_VOID(pVM);
467
468	/*
469	* Set the accessed and dirty flags.
470	*/
471	/** @todo Should probably use cmpxchg logic here as we're potentially racing
472	* other CPUs in SMP configs. (the lock isn't enough, since we take it
473	* after walking and the page tables could be stale already) */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
476	{
477	GstWalk.Pml4e.u \|= X86_PML4E_A;
478	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
479	}
480	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
481	{
482	GstWalk.Pdpe.u \|= X86_PDPE_A;
483	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
484	}
485	# endif
486	if (Walk.fBigPage)
487	{
488	Assert(GstWalk.Pde.u & X86_PDE_PS);
489	if (uErr & X86_TRAP_PF_RW)
490	{
491	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
492	{
493	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
494	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
495	}
496	}
497	else
498	{
499	if (!(GstWalk.Pde.u & X86_PDE4M_A))
500	{
501	GstWalk.Pde.u \|= X86_PDE4M_A;
502	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
503	}
504	}
505	}
506	else
507	{
508	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
509	if (!(GstWalk.Pde.u & X86_PDE_A))
510	{
511	GstWalk.Pde.u \|= X86_PDE_A;
512	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
513	}
514
515	if (uErr & X86_TRAP_PF_RW)
516	{
517	# ifdef VBOX_WITH_STATISTICS
518	if (GstWalk.Pte.u & X86_PTE_D)
519	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
520	else
521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
522	# endif
523	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
524	{
525	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
526	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
527	}
528	}
529	else
530	{
531	if (!(GstWalk.Pte.u & X86_PTE_A))
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
535	}
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	#if 0
540	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	#endif
544
545	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	PGM_LOCK_VOID(pVM);
551	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
554	/*
555	* If it is a reserved bit fault we know that it is an MMIO (access
556	* handler) related fault and can skip some 200 lines of code.
557	*/
558	if (uErr & X86_TRAP_PF_RSVD)
559	{
560	Assert(uErr & X86_TRAP_PF_P);
561	PPGMPAGE pPage;
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage,
566	pfLockTaken, &Walk, &GstWalk));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
568	# else
569	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
570	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
571	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.u & X86_PDE_P);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
665	{
666	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	/*
682	* Check if this fault address is flagged for special treatment,
683	* which means we'll have to figure out the physical address and
684	* check flags associated with it.
685	*
686	* ASSUME that we can limit any special access handling to pages
687	* in page tables which the guest believes to be present.
688	*/
689	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
690	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
691	# else
692	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK);
693	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
694	PPGMPAGE pPage;
695	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
696	if (RT_FAILURE(rc))
697	{
698	/*
699	* When the guest accesses invalid physical memory (e.g. probing
700	* of RAM or accessing a remapped MMIO range), then we'll fall
701	* back to the recompiler to emulate the instruction.
702	*/
703	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
704	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
705	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
706	return VINF_EM_RAW_EMULATE_INSTR;
707	}
708
709	/*
710	* Any handlers for this page?
711	*/
712	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
713	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
714	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken,
715	&Walk, &GstWalk));
716	# else
717	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
718	# endif
719
720	/*
721	* We are here only if page is present in Guest page tables and
722	* trap is not handled by our handlers.
723	*
724	* Check it for page out-of-sync situation.
725	*/
726	if (!(uErr & X86_TRAP_PF_P))
727	{
728	/*
729	* Page is not present in our page tables. Try to sync it!
730	*/
731	if (uErr & X86_TRAP_PF_US)
732	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
733	else /* supervisor */
734	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
735
736	if (PGM_PAGE_IS_BALLOONED(pPage))
737	{
738	/* Emulate reads from ballooned pages as they are not present in
739	our shadow page tables. (Required for e.g. Solaris guests; soft
740	ecc, random nr generator.) */
741	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
742	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
743	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
744	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
745	return rc;
746	}
747
748	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
749	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
750	# else
751	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
752	# endif
753	if (RT_SUCCESS(rc))
754	{
755	/* The page was successfully synced, return to the guest. */
756	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
757	return VINF_SUCCESS;
758	}
759	}
760	else /* uErr & X86_TRAP_PF_P: */
761	{
762	/*
763	* Write protected pages are made writable when the guest makes the
764	* first write to it. This happens for pages that are shared, write
765	* monitored or not yet allocated.
766	*
767	* We may also end up here when CR0.WP=0 in the guest.
768	*
769	* Also, a side effect of not flushing global PDEs are out of sync
770	* pages due to physical monitored regions, that are no longer valid.
771	* Assume for now it only applies to the read/write flag.
772	*/
773	if (uErr & X86_TRAP_PF_RW)
774	{
775	/*
776	* Check if it is a read-only page.
777	*/
778	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
779	{
780	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
781	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
782	Assert(!PGM_PAGE_IS_ZERO(pPage));
783	# endif
784	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
785	# ifdef PGM_WITH_PAGE_ZEROING_DETECTION
786	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
787	&& (pvFault & X86_PAGE_OFFSET_MASK) == 0
788	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
789	{
790	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
791	return VINF_SUCCESS;
792	}
793	# endif
794	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
795
796	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
797	if (rc != VINF_SUCCESS)
798	{
799	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
800	return rc;
801	}
802	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
803	return VINF_EM_NO_MEMORY;
804	}
805
806	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
807	/*
808	* Check to see if we need to emulate the instruction if CR0.WP=0.
809	*/
810	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
811	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
812	&& CPUMGetGuestCPL(pVCpu) < 3)
813	{
814	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
815
816	/*
817	* The Netware WP0+RO+US hack.
818	*
819	* Netware sometimes(/always?) runs with WP0. It has been observed doing
820	* excessive write accesses to pages which are mapped with US=1 and RW=0
821	* while WP=0. This causes a lot of exits and extremely slow execution.
822	* To avoid trapping and emulating every write here, we change the shadow
823	* page table entry to map it as US=0 and RW=1 until user mode tries to
824	* access it again (see further below). We count these shadow page table
825	* changes so we can avoid having to clear the page pool every time the WP
826	* bit changes to 1 (see PGMCr0WpEnabled()).
827	*/
828	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
829	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
830	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
831	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
832	{
833	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
834	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
835	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
836	{
837	PGM_INVL_PG(pVCpu, pvFault);
838	pVCpu->pgm.s.cNetwareWp0Hacks++;
839	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
840	return rc;
841	}
842	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
843	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
844	}
845	# endif
846
847	/* Interpret the access. */
848	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
849	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
850	if (RT_SUCCESS(rc))
851	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
852	else
853	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
854	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
855	return rc;
856	}
857	# endif
858	/// @todo count the above case; else
859	if (uErr & X86_TRAP_PF_US)
860	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
861	else /* supervisor */
862	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
863
864	/*
865	* Sync the page.
866	*
867	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
868	* page is not present, which is not true in this case.
869	*/
870	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
871	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
872	# else
873	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
874	# endif
875	if (RT_SUCCESS(rc))
876	{
877	/*
878	* Page was successfully synced, return to guest but invalidate
879	* the TLB first as the page is very likely to be in it.
880	*/
881	# if PGM_SHW_TYPE == PGM_TYPE_EPT
882	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
883	# else
884	PGM_INVL_PG(pVCpu, pvFault);
885	# endif
886	# ifdef VBOX_STRICT
887	PGMPTWALK GstPageWalk;
888	GstPageWalk.GCPhys = RTGCPHYS_MAX;
889	if (!pVM->pgm.s.fNestedPaging)
890	{
891	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
892	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
893	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
894	}
895	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
896	uint64_t fPageShw = 0;
897	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
898	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
899	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
900	# endif
901	# endif /* VBOX_STRICT */
902	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
903	return VINF_SUCCESS;
904	}
905	}
906	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
907	/*
908	* Check for Netware WP0+RO+US hack from above and undo it when user
909	* mode accesses the page again.
910	*/
911	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
912	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
913	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
914	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
915	&& CPUMGetGuestCPL(pVCpu) == 3
916	&& pVM->cCpus == 1
917	)
918	{
919	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
920	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
921	if (RT_SUCCESS(rc))
922	{
923	PGM_INVL_PG(pVCpu, pvFault);
924	pVCpu->pgm.s.cNetwareWp0Hacks--;
925	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
926	return VINF_SUCCESS;
927	}
928	}
929	# endif /* PGM_WITH_PAGING */
930
931	/** @todo else: why are we here? */
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
934	/*
935	* Check for VMM page flags vs. Guest page flags consistency.
936	* Currently only for debug purposes.
937	*/
938	if (RT_SUCCESS(rc))
939	{
940	/* Get guest page flags. */
941	PGMPTWALK GstPageWalk;
942	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
943	if (RT_SUCCESS(rc2))
944	{
945	uint64_t fPageShw = 0;
946	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
947
948	#if 0
949	/*
950	* Compare page flags.
951	* Note: we have AVL, A, D bits desynced.
952	*/
953	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
954	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
955	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
956	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
957	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
958	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
959	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
960	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
961	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
962	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
963	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
964
965	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
966	01:01:15.625516 00:08:43.268051 Location :
967	e:\vbox\svn\trunk\srcPage flags mismatch!
968	pvFault=fffff801b0d7b000
969	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
970	GCPhys=0000000019b52000
971	fPageShw=0
972	fPageGst=77b0000000000121
973	rc=0
974	#endif
975
976	}
977	else
978	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
979	}
980	else
981	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
982	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
983	}
984
985
986	/*
987	* If we get here it is because something failed above, i.e. most like guru
988	* meditiation time.
989	*/
990	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
991	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip));
992	return rc;
993
994	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
995	NOREF(uErr); NOREF(pCtx); NOREF(pvFault);
996	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
997	return VERR_PGM_NOT_USED_IN_MODE;
998	# endif
999	}
1000
1001
1002	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
1003	/**
1004	* Deals with a nested-guest \#PF fault for a guest-physical page with a handler.
1005	*
1006	* @returns Strict VBox status code.
1007	* @param pVCpu The cross context virtual CPU structure.
1008	* @param uErr The error code.
1009	* @param pCtx Pointer to the register context for the CPU.
1010	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1011	* @param pPage The guest page at @a GCPhysNestedFault.
1012	* @param GCPhysFault The guest-physical address of the fault.
1013	* @param pGstWalkAll The guest page walk result.
1014	* @param pfLockTaken Where to store whether the PGM is still held when
1015	* this function completes.
1016	*
1017	* @note The caller has taken the PGM lock.
1018	*/
1019	static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
1020	RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
1021	RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
1022	bool *pfLockTaken)
1023	{
1024	# if PGM_GST_TYPE == PGM_TYPE_PROT \
1025	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1026
1027	/** @todo Assert uErr isn't X86_TRAP_PF_RSVD and remove release checks. */
1028	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysFault);
1029	AssertMsgReturn(PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage), ("%RGp %RGp uErr=%u\n", GCPhysNestedFault, GCPhysFault, uErr),
1030	VERR_PGM_HANDLER_IPE_1);
1031
1032	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1033	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1034	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1035
1036	/*
1037	* Physical page access handler.
1038	*/
1039	PPGMPHYSHANDLER pCur;
1040	VBOXSTRICTRC rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysPage, &pCur);
1041	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
1042
1043	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
1044	Assert(pCurType);
1045
1046	/*
1047	* If the region is write protected and we got a page not present fault, then sync
1048	* the pages. If the fault was caused by a read, then restart the instruction.
1049	* In case of write access continue to the GC write handler.
1050	*/
1051	if ( !(uErr & X86_TRAP_PF_P)
1052	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1053	{
1054	Log7Func(("Syncing Monitored: GCPhysNestedPage=%RGp GCPhysPage=%RGp uErr=%#x\n", GCPhysNestedPage, GCPhysPage, uErr));
1055	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1056	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1057	if ( RT_FAILURE(rcStrict)
1058	\|\| !(uErr & X86_TRAP_PF_RW))
1059	{
1060	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1061	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1062	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1063	return rcStrict;
1064	}
1065	}
1066	else if ( !(uErr & X86_TRAP_PF_RSVD)
1067	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE)
1068	{
1069	/*
1070	* If the access was NOT through an EPT misconfig (i.e. RSVD), sync the page.
1071	* This can happen for the VMX APIC-access page.
1072	*/
1073	Log7Func(("Syncing MMIO: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1074	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1075	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1076	if (RT_FAILURE(rcStrict))
1077	{
1078	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1079	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1080	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1081	return rcStrict;
1082	}
1083	}
1084
1085	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
1086	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
1087	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
1088	GCPhysNestedFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
1089	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1090	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
1091	else
1092	{
1093	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
1094	if (uErr & X86_TRAP_PF_RSVD)
1095	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
1096	}
1097
1098	if (pCurType->pfnPfHandler)
1099	{
1100	STAM_PROFILE_START(&pCur->Stat, h);
1101	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
1102	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
1103
1104	if (pCurType->fKeepPgmLock)
1105	{
1106	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1107	STAM_PROFILE_STOP(&pCur->Stat, h);
1108	}
1109	else
1110	{
1111	PGM_UNLOCK(pVM);
1112	*pfLockTaken = false;
1113	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1114	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
1115	}
1116	}
1117	else
1118	{
1119	AssertMsgFailed(("What's going on here!? Fault falls outside handler range!?\n"));
1120	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
1121	}
1122
1123	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
1124	return rcStrict;
1125
1126	# else
1127	RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
1128	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1129	return VERR_PGM_NOT_USED_IN_MODE;
1130	# endif
1131	}
1132	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1133
1134
1135	/**
1136	* Nested \#PF handler for nested-guest hardware-assisted execution using nested
1137	* paging.
1138	*
1139	* @returns VBox status code (appropriate for trap handling and GC return).
1140	* @param pVCpu The cross context virtual CPU structure.
1141	* @param uErr The fault error (X86_TRAP_PF_*).
1142	* @param pCtx Pointer to the register context for the CPU.
1143	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1144	* @param fIsLinearAddrValid Whether translation of a nested-guest linear address
1145	* caused this fault. If @c false, GCPtrNestedFault
1146	* must be 0.
1147	* @param GCPtrNestedFault The nested-guest linear address of this fault.
1148	* @param pWalk The guest page table walk result.
1149	* @param pfLockTaken Where to store whether the PGM lock is still held
1150	* when this function completes.
1151	*/
1152	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1153	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
1154	{
1155	*pfLockTaken = false;
1156	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \
1157	&& PGM_GST_TYPE == PGM_TYPE_PROT \
1158	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1159
1160	Assert(CPUMIsGuestVmxEptPagingEnabled(pVCpu));
1161	Assert(PGM_A20_IS_ENABLED(pVCpu));
1162
1163	/* We don't support mode-based execute control for EPT yet. */
1164	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
1165	Assert(!(uErr & X86_TRAP_PF_US));
1166
1167	/* Take the big lock now. */
1168	*pfLockTaken = true;
1169	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1170	PGM_LOCK_VOID(pVM);
1171
1172	/*
1173	* Walk the guest EPT tables and check if it's an EPT violation or misconfiguration.
1174	*/
1175	if (fIsLinearAddrValid)
1176	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n",
1177	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
1178	else
1179	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n",
1180	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr));
1181	PGMPTWALKGST GstWalkAll;
1182	int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
1183	if (RT_FAILURE(rc))
1184	return rc;
1185
1186	Assert(GstWalkAll.enmType == PGMPTWALKGSTTYPE_EPT);
1187	Assert(pWalk->fSucceeded);
1188	Assert(pWalk->fEffective & (PGM_PTATTRS_EPT_R_MASK \| PGM_PTATTRS_EPT_W_MASK \| PGM_PTATTRS_EPT_X_SUPER_MASK));
1189	Assert(pWalk->fIsSlat);
1190
1191	# ifdef DEBUG_ramshankar
1192	/* Paranoia. */
1193	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_R_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_R_MASK));
1194	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_W_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_W_MASK));
1195	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_NX_MASK) == !RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_X_SUPER_MASK));
1196	# endif
1197
1198	Log7Func(("SLAT: GCPhysNestedFault=%RGp -> GCPhys=%#RGp\n", GCPhysNestedFault, pWalk->GCPhys));
1199
1200	/*
1201	* Check page-access permissions.
1202	*/
1203	if ( ((uErr & X86_TRAP_PF_RW) && !(pWalk->fEffective & PGM_PTATTRS_W_MASK))
1204	\|\| ((uErr & X86_TRAP_PF_ID) && (pWalk->fEffective & PGM_PTATTRS_NX_MASK)))
1205	{
1206	Log7Func(("Permission failed! GCPtrNested=%RGv GCPhysNested=%RGp uErr=%#x fEffective=%#RX64\n", GCPtrNestedFault,
1207	GCPhysNestedFault, uErr, pWalk->fEffective));
1208	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
1209	return VERR_ACCESS_DENIED;
1210	}
1211
1212	PGM_A20_ASSERT_MASKED(pVCpu, pWalk->GCPhys);
1213	RTGCPHYS const GCPhysPage = pWalk->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1214	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1215
1216	/*
1217	* If we were called via an EPT misconfig, it should've already resulted in a nested-guest VM-exit.
1218	*/
1219	AssertMsgReturn(!(uErr & X86_TRAP_PF_RSVD),
1220	("Unexpected EPT misconfig VM-exit. GCPhysPage=%RGp GCPhysNestedPage=%RGp\n", GCPhysPage, GCPhysNestedPage),
1221	VERR_PGM_MAPPING_IPE);
1222
1223	/*
1224	* Fetch and sync the nested-guest EPT page directory pointer.
1225	*/
1226	PEPTPD pEptPd;
1227	rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL /ppPdpt/, &pEptPd, &GstWalkAll);
1228	AssertRCReturn(rc, rc);
1229	Assert(pEptPd);
1230
1231	/*
1232	* A common case is the not-present error caused by lazy page table syncing.
1233	*
1234	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
1235	* here so we can safely assume that the shadow PT is present when calling
1236	* NestedSyncPage later.
1237	*
1238	* NOTE: It's possible we will be syncing the VMX APIC-access page here.
1239	* In that case, we would sync the page but will NOT go ahead with emulating
1240	* the APIC-access VM-exit through IEM. However, once the page is mapped in
1241	* the shadow tables, subsequent APIC-access VM-exits for the nested-guest
1242	* will be triggered by hardware. Maybe calling the IEM #PF handler can be
1243	* considered as an optimization later.
1244	*/
1245	unsigned const iPde = (GCPhysNestedPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1246	if ( !(uErr & X86_TRAP_PF_P)
1247	&& !(pEptPd->a[iPde].u & EPT_PRESENT_MASK))
1248	{
1249	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
1250	Log7Func(("NestedSyncPT: Lazy. GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1251	rc = PGM_BTH_NAME(NestedSyncPT)(pVCpu, GCPhysNestedPage, GCPhysPage, &GstWalkAll);
1252	if (RT_SUCCESS(rc))
1253	return rc;
1254	AssertMsgFailedReturn(("NestedSyncPT: %RGv failed! rc=%Rrc\n", GCPhysNestedPage, rc), VERR_PGM_MAPPING_IPE);
1255	}
1256
1257	/*
1258	* Check if this fault address is flagged for special treatment.
1259	* This handles faults on an MMIO or write-monitored page.
1260	*
1261	* If this happens to be the VMX APIC-access page, we don't treat is as MMIO
1262	* but rather sync it further below (as a regular guest page) which lets
1263	* hardware-assisted execution trigger the APIC-access VM-exits of the
1264	* nested-guest directly.
1265	*/
1266	PPGMPAGE pPage;
1267	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1268	if (RT_FAILURE(rc))
1269	{
1270	/*
1271	* We failed to get the physical page which means it's a reserved/invalid
1272	* page address (not MMIO even). This can typically be observed with
1273	* Microsoft Hyper-V enabled Windows guests. We must fall back to emulating
1274	* the instruction, see @bugref{10318#c7}.
1275	*/
1276	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
1277	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
1278	return VINF_EM_RAW_EMULATE_INSTR;
1279	}
1280	/* Check if this is an MMIO page and NOT the VMX APIC-access page. */
1281	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1282	{
1283	Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
1284	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault,
1285	pPage, pWalk->GCPhys, &GstWalkAll,
1286	pfLockTaken));
1287	}
1288
1289	/*
1290	* We are here only if page is present in nested-guest page tables but the
1291	* trap is not handled by our handlers. Check for page out-of-sync situation.
1292	*/
1293	if (!(uErr & X86_TRAP_PF_P))
1294	{
1295	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
1296	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
1298
1299	Log7Func(("SyncPage: Not-Present: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedFault, GCPhysPage));
1300	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, PGM_SYNC_NR_PAGES, uErr, &GstWalkAll);
1301	if (RT_SUCCESS(rc))
1302	{
1303	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
1304	return VINF_SUCCESS;
1305	}
1306	}
1307	else if (uErr & X86_TRAP_PF_RW)
1308	{
1309	/*
1310	* Write protected pages are made writable when the guest makes the
1311	* first write to it. This happens for pages that are shared, write
1312	* monitored or not yet allocated.
1313	*
1314	* We may also end up here when CR0.WP=0 in the guest.
1315	*
1316	* Also, a side effect of not flushing global PDEs are out of sync
1317	* pages due to physical monitored regions, that are no longer valid.
1318	* Assume for now it only applies to the read/write flag.
1319	*/
1320	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1321	{
1322	/* This is a read-only page. */
1323	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhysPage));
1324	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
1325	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
1326	&& (GCPhysNestedFault & X86_PAGE_OFFSET_MASK) == 0
1327	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
1328	{
1329	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
1330	return VINF_SUCCESS;
1331	}
1332	#endif
1333	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
1334
1335	Log7Func(("Calling pgmPhysPageMakeWritable for GCPhysPage=%RGp\n", GCPhysPage));
1336	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1337	if (rc != VINF_SUCCESS)
1338	{
1339	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1340	return rc;
1341	}
1342	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
1343	return VINF_EM_NO_MEMORY;
1344	}
1345
1346	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1347	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1348
1349	/*
1350	* Sync the write-protected page.
1351	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1352	* page is not present, which is not true in this case.
1353	*/
1354	Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
1355	pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
1356	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
1357	if (RT_SUCCESS(rc))
1358	{
1359	HMInvalidatePhysPage(pVM, GCPhysPage);
1360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
1361	return VINF_SUCCESS;
1362	}
1363	}
1364
1365	/*
1366	* If we get here it is because something failed above => guru meditation time?
1367	*/
1368	LogRelMaxFunc(32, ("rc=%Rrc GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n",
1369	rc, GCPhysNestedFault, GCPhysPage, (uint32_t)uErr, pCtx->cs.Sel, pCtx->rip));
1370	return VERR_PGM_MAPPING_IPE;
1371
1372	# else /* !VBOX_WITH_NESTED_HWVIRT_VMX_EPT \|\| PGM_GST_TYPE != PGM_TYPE_PROT \|\| PGM_SHW_TYPE != PGM_TYPE_EPT */
1373	RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
1374	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1375	return VERR_PGM_NOT_USED_IN_MODE;
1376	# endif
1377	}
1378
1379	#endif /* !IN_RING3 */
1380
1381
1382	/**
1383	* Emulation of the invlpg instruction.
1384	*
1385	*
1386	* @returns VBox status code.
1387	*
1388	* @param pVCpu The cross context virtual CPU structure.
1389	* @param GCPtrPage Page to invalidate.
1390	*
1391	* @remark ASSUMES that the guest is updating before invalidating. This order
1392	* isn't required by the CPU, so this is speculative and could cause
1393	* trouble.
1394	* @remark No TLB shootdown is done on any other VCPU as we assume that
1395	* invlpg emulation is the only reason for calling this function.
1396	* (The guest has to shoot down TLB entries on other CPUs itself)
1397	* Currently true, but keep in mind!
1398	*
1399	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1400	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1401	*/
1402	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1403	{
1404	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1405	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1406	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1407	int rc;
1408	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1409	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1410
1411	PGM_LOCK_ASSERT_OWNER(pVM);
1412
1413	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1414
1415	/*
1416	* Get the shadow PD entry and skip out if this PD isn't present.
1417	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1418	*/
1419	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1420	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1421	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1422
1423	/* Fetch the pgm pool shadow descriptor. */
1424	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1425	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1426	if (!pShwPde)
1427	{
1428	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1429	return VINF_SUCCESS;
1430	}
1431	# else
1432	Assert(pShwPde);
1433	# endif
1434
1435	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1436	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1437	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1438
1439	/* If the shadow PDPE isn't present, then skip the invalidate. */
1440	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1441	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1442	# else
1443	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1444	# endif
1445	{
1446	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1447	PGM_INVL_PG(pVCpu, GCPtrPage);
1448	return VINF_SUCCESS;
1449	}
1450
1451	/* Fetch the pgm pool shadow descriptor. */
1452	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1453	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1454
1455	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1456	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1457	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1458
1459	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1460	/* PML4 */
1461	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1462	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1463	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1464	PX86PDPAE pPDDst;
1465	PX86PDPT pPdptDst;
1466	PX86PML4E pPml4eDst;
1467	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1468	if (rc != VINF_SUCCESS)
1469	{
1470	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1471	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1472	PGM_INVL_PG(pVCpu, GCPtrPage);
1473	return VINF_SUCCESS;
1474	}
1475	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1476	Assert(pPDDst);
1477	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1478
1479	/* Fetch the pgm pool shadow descriptor. */
1480	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1481	Assert(pShwPde);
1482
1483	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1484
1485	const SHWPDE PdeDst = *pPdeDst;
1486	if (!(PdeDst.u & X86_PDE_P))
1487	{
1488	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1489	PGM_INVL_PG(pVCpu, GCPtrPage);
1490	return VINF_SUCCESS;
1491	}
1492
1493	/*
1494	* Get the guest PD entry and calc big page.
1495	*/
1496	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1497	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1498	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1499	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1500	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1501	unsigned iPDSrc = 0;
1502	# if PGM_GST_TYPE == PGM_TYPE_PAE
1503	X86PDPE PdpeSrcIgn;
1504	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1505	# else /* AMD64 */
1506	PX86PML4E pPml4eSrcIgn;
1507	X86PDPE PdpeSrcIgn;
1508	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1509	# endif
1510	GSTPDE PdeSrc;
1511
1512	if (pPDSrc)
1513	PdeSrc = pPDSrc->a[iPDSrc];
1514	else
1515	PdeSrc.u = 0;
1516	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1517	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1518	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1519	if (fWasBigPage != fIsBigPage)
1520	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1521
1522	# ifdef IN_RING3
1523	/*
1524	* If a CR3 Sync is pending we may ignore the invalidate page operation
1525	* depending on the kind of sync and if it's a global page or not.
1526	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1527	*/
1528	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1529	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1530	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1531	&& fIsBigPage
1532	&& (PdeSrc.u & X86_PDE4M_G)
1533	)
1534	)
1535	# else
1536	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1537	# endif
1538	{
1539	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1540	return VINF_SUCCESS;
1541	}
1542	# endif /* IN_RING3 */
1543
1544	/*
1545	* Deal with the Guest PDE.
1546	*/
1547	rc = VINF_SUCCESS;
1548	if (PdeSrc.u & X86_PDE_P)
1549	{
1550	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1551	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1552	if (!fIsBigPage)
1553	{
1554	/*
1555	* 4KB - page.
1556	*/
1557	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1558	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1559
1560	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1561	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1562	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
1563	# endif
1564	if (pShwPage->GCPhys == GCPhys)
1565	{
1566	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1567	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1568
1569	PGSTPT pPTSrc;
1570	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1571	if (RT_SUCCESS(rc))
1572	{
1573	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1574	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1575	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1576	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1577	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1578	GCPtrPage, PteSrc.u & X86_PTE_P,
1579	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1580	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1581	(uint64_t)PteSrc.u,
1582	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1583	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1584	}
1585	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1586	PGM_INVL_PG(pVCpu, GCPtrPage);
1587	}
1588	else
1589	{
1590	/*
1591	* The page table address changed.
1592	*/
1593	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1594	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1595	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1596	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1597	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1598	PGM_INVL_VCPU_TLBS(pVCpu);
1599	}
1600	}
1601	else
1602	{
1603	/*
1604	* 2/4MB - page.
1605	*/
1606	/* Before freeing the page, check if anything really changed. */
1607	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1608	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1609	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1610	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1611	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1612	# endif
1613	if ( pShwPage->GCPhys == GCPhys
1614	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1615	{
1616	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1617	/** @todo This test is wrong as it cannot check the G bit!
1618	* FIXME */
1619	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1620	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1621	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1622	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1623	{
1624	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1625	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1626	return VINF_SUCCESS;
1627	}
1628	}
1629
1630	/*
1631	* Ok, the page table is present and it's been changed in the guest.
1632	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1633	* We could do this for some flushes in GC too, but we need an algorithm for
1634	* deciding which 4MB pages containing code likely to be executed very soon.
1635	*/
1636	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1637	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1638	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1639	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1640	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1641	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1642	}
1643	}
1644	else
1645	{
1646	/*
1647	* Page directory is not present, mark shadow PDE not present.
1648	*/
1649	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1650	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1651	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1652	PGM_INVL_PG(pVCpu, GCPtrPage);
1653	}
1654	return rc;
1655
1656	#else /* guest real and protected mode, nested + ept, none. */
1657	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1658	NOREF(pVCpu); NOREF(GCPtrPage);
1659	return VINF_SUCCESS;
1660	#endif
1661	}
1662
1663	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1664
1665	/**
1666	* Update the tracking of shadowed pages.
1667	*
1668	* @param pVCpu The cross context virtual CPU structure.
1669	* @param pShwPage The shadow page.
1670	* @param HCPhys The physical page we is being dereferenced.
1671	* @param iPte Shadow PTE index
1672	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1673	*/
1674	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1675	RTGCPHYS GCPhysPage)
1676	{
1677	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1678
1679	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1680	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1681	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1682
1683	/* Use the hint we retrieved from the cached guest PT. */
1684	if (pShwPage->fDirty)
1685	{
1686	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1687
1688	Assert(pShwPage->cPresent);
1689	Assert(pPool->cPresent);
1690	pShwPage->cPresent--;
1691	pPool->cPresent--;
1692
1693	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1694	AssertRelease(pPhysPage);
1695	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1696	return;
1697	}
1698	# else
1699	NOREF(GCPhysPage);
1700	# endif
1701
1702	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1703	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1704	* 2. write protect all shadowed pages. I.e. implement caching.
1705	*
1706	* 2023-08-24 bird: If we allow the ZeroPg to enter the shadow page tables,
1707	* this becomes a common occurence and we screw up. A better to the above would
1708	* be to have a parallel table that records the guest physical addresses of the
1709	* pages mapped by the shadow page table... For nested page tables,
1710	* we can easily correleate a table entry to a page entry, so it won't be
1711	* needed for those.
1712	*/
1713	# if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1714	/*
1715	* For non-paged guest tables, EPT and nested tables we can figure out the
1716	* physical page corresponding to the entry and dereference it.
1717	* (This ASSUMES that shadow PTs won't be used ever be used out of place.)
1718	*/
1719	if ( pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_PHYS
1720	\|\| pShwPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PHYS
1721	\|\| pShwPage->enmKind == PGMPOOLKIND_32BIT_PT_FOR_PHYS)
1722	{
1723	RTGCPHYS GCPhysNestedEntry = pShwPage->GCPhys + ((uint32_t)iPte << X86_PAGE_SHIFT);
1724	if (!pShwPage->fA20Enabled)
1725	GCPhysNestedEntry &= ~(uint64_t)RT_BIT_64(20);
1726	PPGMPAGE const pPhysPage = pgmPhysGetPage(pVM, GCPhysNestedEntry);
1727	AssertRelease(pPhysPage);
1728	pgmTrackDerefGCPhys(pVM->pgm.s.CTX_SUFF(pPool), pShwPage, pPhysPage, iPte);
1729	}
1730	else
1731	AssertMsgFailed(("enmKind=%d GCPhys=%RGp\n", pShwPage->enmKind, pShwPage->GCPhys));
1732	# endif
1733
1734	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1735
1736	/*
1737	* Find the guest address.
1738	*/
1739	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1740	LogFlow(("SyncPageWorkerTrackDeref(%d,%d): Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n",
1741	PGM_SHW_TYPE, PGM_GST_TYPE, HCPhys, pShwPage->idx));
1742	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1743	pRam;
1744	pRam = pRam->CTX_SUFF(pNext))
1745	{
1746	unsigned iPage = pRam->cb >> GUEST_PAGE_SHIFT;
1747	while (iPage-- > 0)
1748	{
1749	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1750	{
1751	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1752
1753	Assert(pShwPage->cPresent);
1754	Assert(pPool->cPresent);
1755	pShwPage->cPresent--;
1756	pPool->cPresent--;
1757
1758	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1759	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1760	return;
1761	}
1762	}
1763	}
1764
1765	for (;;)
1766	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1767	}
1768
1769
1770	/**
1771	* Update the tracking of shadowed pages.
1772	*
1773	* @param pVCpu The cross context virtual CPU structure.
1774	* @param pShwPage The shadow page.
1775	* @param u16 The top 16-bit of the pPage->HCPhys.
1776	* @param pPage Pointer to the guest page. this will be modified.
1777	* @param iPTDst The index into the shadow table.
1778	*/
1779	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1780	PPGMPAGE pPage, const unsigned iPTDst)
1781	{
1782	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1783
1784	/*
1785	* Just deal with the simple first time here.
1786	*/
1787	if (!u16)
1788	{
1789	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1790	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1791	/* Save the page table index. */
1792	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1793	}
1794	else
1795	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1796
1797	/* write back */
1798	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x pPage=%p\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst, pPage));
1799	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1800
1801	/* update statistics. */
1802	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1803	pShwPage->cPresent++;
1804	if (pShwPage->iFirstPresent > iPTDst)
1805	pShwPage->iFirstPresent = iPTDst;
1806	}
1807
1808
1809	/**
1810	* Modifies a shadow PTE to account for access handlers.
1811	*
1812	* @param pVM The cross context VM structure.
1813	* @param pVCpu The cross context virtual CPU structure.
1814	* @param pPage The page in question.
1815	* @param GCPhysPage The guest-physical address of the page.
1816	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1817	* A (accessed) bit so it can be emulated correctly.
1818	* @param pPteDst The shadow PTE (output). This is temporary storage and
1819	* does not need to be set atomically.
1820	*/
1821	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PVMCPUCC pVCpu, PCPGMPAGE pPage, RTGCPHYS GCPhysPage, uint64_t fPteSrc,
1822	PSHWPTE pPteDst)
1823	{
1824	RT_NOREF_PV(pVM); RT_NOREF_PV(fPteSrc); RT_NOREF_PV(pVCpu); RT_NOREF_PV(GCPhysPage);
1825
1826	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1827	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1828	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1829	{
1830	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1831	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1832	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1833	# else
1834	if (fPteSrc & X86_PTE_A)
1835	{
1836	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1837	SHW_PTE_SET_RO(*pPteDst);
1838	}
1839	else
1840	SHW_PTE_SET(*pPteDst, 0);
1841	# endif
1842	}
1843	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1844	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1845	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1846	&& ( BTH_IS_NP_ACTIVE(pVM)
1847	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1848	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1849	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1850	# endif
1851	)
1852	{
1853	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1854	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1855	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1856	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1857	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1858	\| EPT_E_WRITE
1859	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1860	\| EPT_E_MEMTYPE_INVALID_3;
1861	# else
1862	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1863	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1864	# endif
1865	}
1866	# endif
1867	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1868	else
1869	{
1870	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1871	SHW_PTE_SET(*pPteDst, 0);
1872	}
1873	/** @todo count these kinds of entries. */
1874	}
1875
1876
1877	/**
1878	* Creates a 4K shadow page for a guest page.
1879	*
1880	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1881	* physical address. The PdeSrc argument only the flags are used. No page
1882	* structured will be mapped in this function.
1883	*
1884	* @param pVCpu The cross context virtual CPU structure.
1885	* @param pPteDst Destination page table entry.
1886	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1887	* Can safely assume that only the flags are being used.
1888	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1889	* @param pShwPage Pointer to the shadow page.
1890	* @param iPTDst The index into the shadow table.
1891	*
1892	* @remark Not used for 2/4MB pages!
1893	*/
1894	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1895	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1896	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1897	# else
1898	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1899	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1900	# endif
1901	{
1902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1903	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1904
1905	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1906	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1907	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1908
1909	if (pShwPage->fDirty)
1910	{
1911	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1912	PGSTPT pGstPT;
1913
1914	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1915	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1916	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1917	pGstPT->a[iPTDst].u = PteSrc.u;
1918	}
1919	# else
1920	Assert(!pShwPage->fDirty);
1921	# endif
1922
1923	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1924	if ( (PteSrc.u & X86_PTE_P)
1925	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1926	# endif
1927	{
1928	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1929	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1930	# endif
1931	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1932
1933	/*
1934	* Find the ram range.
1935	*/
1936	PPGMPAGE pPage;
1937	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1938	if (RT_SUCCESS(rc))
1939	{
1940	/* Ignore ballooned pages.
1941	Don't return errors or use a fatal assert here as part of a
1942	shadow sync range might included ballooned pages. */
1943	if (PGM_PAGE_IS_BALLOONED(pPage))
1944	{
1945	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1946	return;
1947	}
1948
1949	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1950	/* Make the page writable if necessary. */
1951	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1952	&& ( PGM_PAGE_IS_ZERO(pPage)
1953	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1954	\|\| ( (PteSrc.u & X86_PTE_RW)
1955	# else
1956	\|\| ( 1
1957	# endif
1958	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1959	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1960	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1961	# endif
1962	# ifdef VBOX_WITH_PAGE_SHARING
1963	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1964	# endif
1965	)
1966	)
1967	)
1968	{
1969	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1970	AssertRC(rc);
1971	}
1972	# endif
1973
1974	/*
1975	* Make page table entry.
1976	*/
1977	SHWPTE PteDst;
1978	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1979	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1980	# else
1981	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1982	# endif
1983	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1984	{
1985	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1986	/*
1987	* If the page or page directory entry is not marked accessed,
1988	* we mark the page not present.
1989	*/
1990	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1991	{
1992	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1993	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1994	SHW_PTE_SET(PteDst, 0);
1995	}
1996	/*
1997	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1998	* when the page is modified.
1999	*/
2000	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
2001	{
2002	AssertCompile(X86_PTE_RW == X86_PDE_RW);
2003	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
2004	SHW_PTE_SET(PteDst,
2005	fGstShwPteFlags
2006	\| PGM_PAGE_GET_HCPHYS(pPage)
2007	\| PGM_PTFLAGS_TRACK_DIRTY);
2008	SHW_PTE_SET_RO(PteDst);
2009	}
2010	else
2011	# endif
2012	{
2013	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
2014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2015	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
2016	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2017	# else
2018	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
2019	# endif
2020	}
2021
2022	/*
2023	* Make sure only allocated pages are mapped writable.
2024	*/
2025	if ( SHW_PTE_IS_P_RW(PteDst)
2026	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2027	{
2028	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2029	/* Still applies to shared pages. */
2030	Assert(!PGM_PAGE_IS_ZERO(pPage));
2031	# endif
2032	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
2033	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
2034	}
2035	}
2036	else
2037	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhysPage, fGstShwPteFlags, &PteDst);
2038
2039	/*
2040	* Keep user track up to date.
2041	*/
2042	if (SHW_PTE_IS_P(PteDst))
2043	{
2044	if (!SHW_PTE_IS_P(*pPteDst))
2045	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2046	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
2047	{
2048	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
2049	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2050	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2051	}
2052	}
2053	else if (SHW_PTE_IS_P(*pPteDst))
2054	{
2055	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2056	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2057	}
2058
2059	/*
2060	* Update statistics and commit the entry.
2061	*/
2062	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2063	if (!(PteSrc.u & X86_PTE_G))
2064	pShwPage->fSeenNonGlobal = true;
2065	# endif
2066	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2067	return;
2068	}
2069
2070	/** @todo count these three different kinds. */
2071	Log2(("SyncPageWorker: invalid address in Pte\n"));
2072	}
2073	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2074	else if (!(PteSrc.u & X86_PTE_P))
2075	Log2(("SyncPageWorker: page not present in Pte\n"));
2076	else
2077	Log2(("SyncPageWorker: invalid Pte\n"));
2078	# endif
2079
2080	/*
2081	* The page is not present or the PTE is bad. Replace the shadow PTE by
2082	* an empty entry, making sure to keep the user tracking up to date.
2083	*/
2084	if (SHW_PTE_IS_P(*pPteDst))
2085	{
2086	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2087	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2088	}
2089	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
2090	}
2091
2092
2093	/**
2094	* Syncs a guest OS page.
2095	*
2096	* There are no conflicts at this point, neither is there any need for
2097	* page table allocations.
2098	*
2099	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
2100	* When called in AMD64 guest mode, the guest PML4E shall be valid.
2101	*
2102	* @returns VBox status code.
2103	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
2104	* @param pVCpu The cross context virtual CPU structure.
2105	* @param PdeSrc Page directory entry of the guest.
2106	* @param GCPtrPage Guest context page address.
2107	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2108	* @param uErr Fault error (X86_TRAP_PF_*).
2109	*/
2110	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
2111	{
2112	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2113	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2114	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
2115	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
2116
2117	PGM_LOCK_ASSERT_OWNER(pVM);
2118
2119	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2120	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2121	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2122	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
2123
2124	/*
2125	* Assert preconditions.
2126	*/
2127	Assert(PdeSrc.u & X86_PDE_P);
2128	Assert(cPages);
2129	# if 0 /* rarely useful; leave for debugging. */
2130	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
2131	# endif
2132
2133	/*
2134	* Get the shadow PDE, find the shadow page table in the pool.
2135	*/
2136	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2137	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2138	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2139
2140	/* Fetch the pgm pool shadow descriptor. */
2141	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2142	Assert(pShwPde);
2143
2144	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2145	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2146	PPGMPOOLPAGE pShwPde = NULL;
2147	PX86PDPAE pPDDst;
2148
2149	/* Fetch the pgm pool shadow descriptor. */
2150	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2151	AssertRCSuccessReturn(rc2, rc2);
2152	Assert(pShwPde);
2153
2154	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2155	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2156
2157	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2158	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2159	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2160	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2161	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2162
2163	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2164	AssertRCSuccessReturn(rc2, rc2);
2165	Assert(pPDDst && pPdptDst);
2166	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2167	# endif
2168	SHWPDE PdeDst = *pPdeDst;
2169
2170	/*
2171	* - In the guest SMP case we could have blocked while another VCPU reused
2172	* this page table.
2173	* - With W7-64 we may also take this path when the A bit is cleared on
2174	* higher level tables (PDPE/PML4E). The guest does not invalidate the
2175	* relevant TLB entries. If we're write monitoring any page mapped by
2176	* the modified entry, we may end up here with a "stale" TLB entry.
2177	*/
2178	if (!(PdeDst.u & X86_PDE_P))
2179	{
2180	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2181	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
2182	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2183	if (uErr & X86_TRAP_PF_P)
2184	PGM_INVL_PG(pVCpu, GCPtrPage);
2185	return VINF_SUCCESS; /* force the instruction to be executed again. */
2186	}
2187
2188	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2189	Assert(pShwPage);
2190
2191	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2192	/* Fetch the pgm pool shadow descriptor. */
2193	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2194	Assert(pShwPde);
2195	# endif
2196
2197	/*
2198	* Check that the page is present and that the shadow PDE isn't out of sync.
2199	*/
2200	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
2201	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2202	RTGCPHYS GCPhys;
2203	if (!fBigPage)
2204	{
2205	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2206	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2207	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2208	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
2209	# endif
2210	}
2211	else
2212	{
2213	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2214	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2215	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2216	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2217	# endif
2218	}
2219	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2220	if ( fPdeValid
2221	&& pShwPage->GCPhys == GCPhys
2222	&& (PdeSrc.u & X86_PDE_P)
2223	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
2224	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
2225	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2226	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
2227	# endif
2228	)
2229	{
2230	/*
2231	* Check that the PDE is marked accessed already.
2232	* Since we set the accessed bit before getting here on a #PF, this
2233	* check is only meant for dealing with non-#PF'ing paths.
2234	*/
2235	if (PdeSrc.u & X86_PDE_A)
2236	{
2237	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2238	if (!fBigPage)
2239	{
2240	/*
2241	* 4KB Page - Map the guest page table.
2242	*/
2243	PGSTPT pPTSrc;
2244	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2245	if (RT_SUCCESS(rc))
2246	{
2247	# ifdef PGM_SYNC_N_PAGES
2248	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2249	if ( cPages > 1
2250	&& !(uErr & X86_TRAP_PF_P)
2251	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2252	{
2253	/*
2254	* This code path is currently only taken when the caller is PGMTrap0eHandler
2255	* for non-present pages!
2256	*
2257	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2258	* deal with locality.
2259	*/
2260	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2261	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2262	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2263	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2264	# else
2265	const unsigned offPTSrc = 0;
2266	# endif
2267	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2268	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2269	iPTDst = 0;
2270	else
2271	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2272
2273	for (; iPTDst < iPTDstEnd; iPTDst++)
2274	{
2275	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2276
2277	if ( (pPteSrc->u & X86_PTE_P)
2278	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2279	{
2280	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT))
2281	\| ((offPTSrc + iPTDst) << GUEST_PAGE_SHIFT);
2282	NOREF(GCPtrCurPage);
2283	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2284	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2285	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
2286	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
2287	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
2288	(uint64_t)pPteSrc->u,
2289	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2290	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2291	}
2292	}
2293	}
2294	else
2295	# endif /* PGM_SYNC_N_PAGES */
2296	{
2297	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2298	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2299	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2300	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2301	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2302	GCPtrPage, PteSrc.u & X86_PTE_P,
2303	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2304	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2305	(uint64_t)PteSrc.u,
2306	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2307	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2308	}
2309	}
2310	else /* MMIO or invalid page: emulated in #PF handler. */
2311	{
2312	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2313	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2314	}
2315	}
2316	else
2317	{
2318	/*
2319	* 4/2MB page - lazy syncing shadow 4K pages.
2320	* (There are many causes of getting here, it's no longer only CSAM.)
2321	*/
2322	/* Calculate the GC physical address of this 4KB shadow page. */
2323	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2324	/* Find ram range. */
2325	PPGMPAGE pPage;
2326	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2327	if (RT_SUCCESS(rc))
2328	{
2329	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2330
2331	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2332	/* Try to make the page writable if necessary. */
2333	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2334	&& ( PGM_PAGE_IS_ZERO(pPage)
2335	\|\| ( (PdeSrc.u & X86_PDE_RW)
2336	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2337	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2338	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2339	# endif
2340	# ifdef VBOX_WITH_PAGE_SHARING
2341	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2342	# endif
2343	)
2344	)
2345	)
2346	{
2347	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2348	AssertRC(rc);
2349	}
2350	# endif
2351
2352	/*
2353	* Make shadow PTE entry.
2354	*/
2355	SHWPTE PteDst;
2356	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2357	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2358	else
2359	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2360
2361	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2362	if ( SHW_PTE_IS_P(PteDst)
2363	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2364	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2365
2366	/* Make sure only allocated pages are mapped writable. */
2367	if ( SHW_PTE_IS_P_RW(PteDst)
2368	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2369	{
2370	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2371	/* Still applies to shared pages. */
2372	Assert(!PGM_PAGE_IS_ZERO(pPage));
2373	# endif
2374	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2375	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2376	}
2377
2378	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2379
2380	/*
2381	* If the page is not flagged as dirty and is writable, then make it read-only
2382	* at PD level, so we can set the dirty bit when the page is modified.
2383	*
2384	* ASSUMES that page access handlers are implemented on page table entry level.
2385	* Thus we will first catch the dirty access and set PDE.D and restart. If
2386	* there is an access handler, we'll trap again and let it work on the problem.
2387	*/
2388	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2389	* As for invlpg, it simply frees the whole shadow PT.
2390	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2391	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
2392	{
2393	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2394	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2395	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2396	}
2397	else
2398	{
2399	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
2400	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
2401	}
2402	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2403	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2404	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
2405	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2406	}
2407	else
2408	{
2409	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2410	/** @todo must wipe the shadow page table entry in this
2411	* case. */
2412	}
2413	}
2414	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2415	return VINF_SUCCESS;
2416	}
2417
2418	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
2419	}
2420	else if (fPdeValid)
2421	{
2422	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2423	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2424	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2425	}
2426	else
2427	{
2428	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2429	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2430	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2431	}
2432
2433	/*
2434	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2435	* Yea, I'm lazy.
2436	*/
2437	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2438	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2439
2440	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2441	PGM_INVL_VCPU_TLBS(pVCpu);
2442	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2443
2444
2445	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2446	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2447	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2448	NOREF(PdeSrc);
2449
2450	# ifdef PGM_SYNC_N_PAGES
2451	/*
2452	* Get the shadow PDE, find the shadow page table in the pool.
2453	*/
2454	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2455	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2456
2457	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2458	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2459
2460	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2461	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2462	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2463	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2464	X86PDEPAE PdeDst;
2465	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2466
2467	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2468	AssertRCSuccessReturn(rc, rc);
2469	Assert(pPDDst && pPdptDst);
2470	PdeDst = pPDDst->a[iPDDst];
2471
2472	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2473	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2474	PEPTPD pPDDst;
2475	EPTPDE PdeDst;
2476
2477	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2478	if (rc != VINF_SUCCESS)
2479	{
2480	AssertRC(rc);
2481	return rc;
2482	}
2483	Assert(pPDDst);
2484	PdeDst = pPDDst->a[iPDDst];
2485	# endif
2486	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2487	if (!SHW_PDE_IS_P(PdeDst))
2488	{
2489	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2490	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2491	return VINF_SUCCESS; /* force the instruction to be executed again. */
2492	}
2493
2494	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2495	if (SHW_PDE_IS_BIG(PdeDst))
2496	{
2497	Assert(pVM->pgm.s.fNestedPaging);
2498	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2499	return VINF_SUCCESS;
2500	}
2501
2502	/* Mask away the page offset. */
2503	GCPtrPage &= ~((RTGCPTR)0xfff);
2504
2505	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2506	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2507
2508	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2509	if ( cPages > 1
2510	&& !(uErr & X86_TRAP_PF_P)
2511	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2512	{
2513	/*
2514	* This code path is currently only taken when the caller is PGMTrap0eHandler
2515	* for non-present pages!
2516	*
2517	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2518	* deal with locality.
2519	*/
2520	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2521	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2522	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2523	iPTDst = 0;
2524	else
2525	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2526	for (; iPTDst < iPTDstEnd; iPTDst++)
2527	{
2528	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2529	{
2530	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2531	\| (iPTDst << GUEST_PAGE_SHIFT));
2532
2533	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2534	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2535	GCPtrCurPage,
2536	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2537	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2538
2539	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2540	break;
2541	}
2542	else
2543	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n",
2544	(GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << GUEST_PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2545	}
2546	}
2547	else
2548	# endif /* PGM_SYNC_N_PAGES */
2549	{
2550	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2551	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2552	\| (iPTDst << GUEST_PAGE_SHIFT));
2553
2554	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2555
2556	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2557	GCPtrPage,
2558	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2559	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2560	}
2561	return VINF_SUCCESS;
2562
2563	# else
2564	NOREF(PdeSrc);
2565	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2566	return VERR_PGM_NOT_USED_IN_MODE;
2567	# endif
2568	}
2569
2570	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2571
2572	#if !defined(IN_RING3) && defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
2573
2574	/**
2575	* Sync a shadow page for a nested-guest page.
2576	*
2577	* @param pVCpu The cross context virtual CPU structure.
2578	* @param pPte The shadow page table entry.
2579	* @param GCPhysPage The guest-physical address of the page.
2580	* @param pShwPage The shadow page of the page table.
2581	* @param iPte The index of the page table entry.
2582	* @param pGstWalkAll The guest page table walk result.
2583	*
2584	* @note Not to be used for 2/4MB pages!
2585	*/
2586	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
2587	unsigned iPte, PCPGMPTWALKGST pGstWalkAll)
2588	{
2589	/*
2590	* Do not make assumptions about anything other than the final PTE entry in the
2591	* guest page table walk result. For instance, while mapping 2M PDEs as 4K pages,
2592	* the PDE might still be having its leaf bit set.
2593	*
2594	* In the future, we could consider introducing a generic SLAT macro like PSLATPTE
2595	* and using that instead of passing the full SLAT translation result.
2596	*/
2597	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2598	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2599	Assert(!pShwPage->fDirty);
2600	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
2601	AssertMsg(!(pGstWalkAll->u.Ept.Pte.u & EPT_E_LEAF), ("Large page unexpected: %RX64\n", pGstWalkAll->u.Ept.Pte.u));
2602	AssertMsg((pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK) == GCPhysPage,
2603	("PTE address mismatch. GCPhysPage=%RGp Pte=%RX64\n", GCPhysPage, pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK));
2604
2605	/*
2606	* Find the ram range.
2607	*/
2608	PPGMPAGE pPage;
2609	int rc = pgmPhysGetPageEx(pVCpu->CTX_SUFF(pVM), GCPhysPage, &pPage);
2610	if (RT_SUCCESS(rc))
2611	{ /* likely */ }
2612	else
2613	{
2614	/*
2615	* This is a RAM hole/invalid/reserved address (not MMIO).
2616	* Nested Microsoft Hyper-V maps addresses like 0xf0220000 as RW WB memory.
2617	* Shadow a not-present page similar to MMIO, see @bugref{10318#c7}.
2618	*/
2619	Assert(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
2620	if (SHW_PTE_IS_P(*pPte))
2621	{
2622	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2623	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2624	}
2625	Log7Func(("RAM hole/reserved %RGp -> ShwPte=0\n", GCPhysPage));
2626	SHW_PTE_ATOMIC_SET(*pPte, 0);
2627	return;
2628	}
2629
2630	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
2631
2632	/*
2633	* Make page table entry.
2634	*/
2635	SHWPTE Pte;
2636	uint64_t const fGstShwPteFlags = (pGstWalkAll->u.Ept.Pte.u & pVCpu->pgm.s.fGstEptShadowedPteMask)
2637	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2638	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2639	{
2640	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2641	/* If it's the zero page or write to an unallocated page, allocate it to make it writable. */
2642	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2643	&& ( PGM_PAGE_IS_ZERO(pPage)
2644	\|\| ( (pGstWalkAll->u.Ept.Pte.u & EPT_E_WRITE)
2645	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2646	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2647	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2648	# endif
2649	# ifdef VBOX_WITH_PAGE_SHARING
2650	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2651	# endif
2652	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_BALLOONED
2653	)
2654	)
2655	)
2656	{
2657	rc = pgmPhysPageMakeWritable(pVCpu->CTX_SUFF(pVM), pPage, GCPhysPage);
2658	AssertRC(rc);
2659	Log7Func(("made writable (%R[pgmpage]) at %RGp\n", pPage, GCPhysPage));
2660	}
2661	# endif
2662	/** @todo access bit. */
2663	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2664	Log7Func(("regular page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2665
2666	/* Make sure only allocated pages are mapped writable. */
2667	if ( (fGstShwPteFlags & EPT_E_WRITE)
2668	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2669	{
2670	Pte.u &= ~EPT_E_WRITE;
2671	Log7Func(("write-protecting page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2672	}
2673	}
2674	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2675	{
2676	/** @todo access bit. */
2677	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| (fGstShwPteFlags & ~EPT_E_WRITE);
2678	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2679	}
2680	else
2681	{
2682	/** @todo Do MMIO optimizations here too? */
2683	Log7Func(("mmio/all page (%R[pgmpage]) at %RGp -> 0\n", pPage, GCPhysPage));
2684	Pte.u = 0;
2685	}
2686
2687	/* Make sure only allocated pages are mapped writable. */
2688	Assert(!SHW_PTE_IS_P_RW(Pte) \|\| PGM_PAGE_IS_ALLOCATED(pPage));
2689
2690	/*
2691	* Keep user track up to date.
2692	*/
2693	if (SHW_PTE_IS_P(Pte))
2694	{
2695	if (!SHW_PTE_IS_P(*pPte))
2696	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2697	else if (SHW_PTE_GET_HCPHYS(*pPte) != SHW_PTE_GET_HCPHYS(Pte))
2698	{
2699	Log2(("NestedSyncPageWorker: deref! pPte=%RX64 Pte=%RX64\n", SHW_PTE_LOG64(pPte), SHW_PTE_LOG64(Pte)));
2700	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2701	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2702	}
2703	}
2704	else if (SHW_PTE_IS_P(*pPte))
2705	{
2706	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2707	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2708	}
2709
2710	/*
2711	* Commit the entry.
2712	*/
2713	SHW_PTE_ATOMIC_SET2(*pPte, Pte);
2714	return;
2715	}
2716
2717
2718	/**
2719	* Syncs a nested-guest page.
2720	*
2721	* There are no conflicts at this point, neither is there any need for
2722	* page table allocations.
2723	*
2724	* @returns VBox status code.
2725	* @param pVCpu The cross context virtual CPU structure.
2726	* @param GCPhysNestedPage The nested-guest physical address of the page being
2727	* synced.
2728	* @param GCPhysPage The guest-physical address of the page being synced.
2729	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2730	* @param uErr The page fault error (X86_TRAP_PF_XXX).
2731	* @param pGstWalkAll The guest page table walk result.
2732	*/
2733	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
2734	uint32_t uErr, PPGMPTWALKGST pGstWalkAll)
2735	{
2736	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2737	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2738	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2739
2740	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2741	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2742	Log7Func(("GCPhysNestedPage=%RGv GCPhysPage=%RGp cPages=%u uErr=%#x\n", GCPhysNestedPage, GCPhysPage, cPages, uErr));
2743	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages);
2744
2745	PGM_LOCK_ASSERT_OWNER(pVM);
2746
2747	/*
2748	* Get the shadow PDE, find the shadow page table in the pool.
2749	*/
2750	unsigned const iPde = ((GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK);
2751	PEPTPD pPd;
2752	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL, &pPd, pGstWalkAll);
2753	if (RT_SUCCESS(rc))
2754	{ /* likely */ }
2755	else
2756	{
2757	Log(("Failed to fetch EPT PD for %RGp (%RGp) rc=%Rrc\n", GCPhysNestedPage, GCPhysPage, rc));
2758	return rc;
2759	}
2760	Assert(pPd);
2761	EPTPDE Pde = pPd->a[iPde];
2762
2763	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2764	if (!SHW_PDE_IS_P(Pde))
2765	{
2766	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)Pde.u));
2767	Log7Func(("CPU%d: SyncPage: Pde at %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2768	return VINF_SUCCESS; /* force the instruction to be executed again. */
2769	}
2770
2771	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2772	if (SHW_PDE_IS_BIG(Pde))
2773	{
2774	Log7Func(("CPU%d: SyncPage: %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2775	return VINF_SUCCESS;
2776	}
2777
2778	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, Pde.u & EPT_PDE_PG_MASK);
2779	PEPTPT pPt = (PEPTPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2780
2781	/*
2782	* If we've shadowed a guest EPT PDE that maps a 2M page using a 4K table,
2783	* then sync the 4K sub-page in the 2M range.
2784	*/
2785	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2786	{
2787	Assert(!SHW_PDE_IS_BIG(Pde));
2788
2789	Assert(pGstWalkAll->u.Ept.Pte.u == 0);
2790	Assert((Pde.u & EPT_PRESENT_MASK) == (pGstWalkAll->u.Ept.Pde.u & EPT_PRESENT_MASK));
2791	Assert(pShwPage->GCPhys == (pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK));
2792
2793	#if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
2794	PPGMPAGE pPage;
2795	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage); AssertRC(rc);
2796	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
2797	Assert(pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB);
2798	#endif
2799	uint64_t const fGstShwPteFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask & ~EPT_E_LEAF)
2800	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2801	pGstWalkAll->u.Ept.Pte.u = GCPhysPage \| fGstShwPteFlags;
2802
2803	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2804	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2805	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2806
2807	/* Restore modifications did to the guest-walk result above in case callers might inspect them later. */
2808	pGstWalkAll->u.Ept.Pte.u = 0;
2809	return VINF_SUCCESS;
2810	}
2811
2812	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2813	# ifdef PGM_SYNC_N_PAGES
2814	if ( cPages > 1
2815	&& !(uErr & X86_TRAP_PF_P)
2816	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2817	{
2818	/*
2819	* This code path is currently only taken for non-present pages!
2820	*
2821	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2822	* deal with locality.
2823	*/
2824	unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2825	unsigned const iPteEnd = RT_MIN(iPte + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPt->a));
2826	if (iPte < PGM_SYNC_NR_PAGES / 2)
2827	iPte = 0;
2828	else
2829	iPte -= PGM_SYNC_NR_PAGES / 2;
2830	for (; iPte < iPteEnd; iPte++)
2831	{
2832	if (!SHW_PTE_IS_P(pPt->a[iPte]))
2833	{
2834	PGMPTWALKGST GstWalkPt;
2835	PGMPTWALK WalkPt;
2836	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2837	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2838	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt,
2839	&GstWalkPt);
2840	if (RT_SUCCESS(rc))
2841	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], WalkPt.GCPhys, pShwPage, iPte, &GstWalkPt);
2842	else
2843	{
2844	/*
2845	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2846	* Ensure the shadow tables entry is not-present.
2847	*/
2848	/** @todo Potential room for optimization (explained in NestedSyncPT). */
2849	AssertMsg(!pPt->a[iPte].u, ("%RX64\n", pPt->a[iPte].u));
2850	}
2851	Log7Func(("Many: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2852	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2853	break;
2854	}
2855	else
2856	{
2857	# ifdef VBOX_STRICT
2858	/* Paranoia - Verify address of the page is what it should be. */
2859	PGMPTWALKGST GstWalkPt;
2860	PGMPTWALK WalkPt;
2861	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2862	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2863	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt, &GstWalkPt);
2864	AssertRC(rc);
2865	PPGMPAGE pPage;
2866	rc = pgmPhysGetPageEx(pVM, WalkPt.GCPhys, &pPage);
2867	AssertRC(rc);
2868	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2869	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp HCPhys=%RHp Shw=%RHp\n",
2870	GCPhysNestedPage, WalkPt.GCPhys, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2871	# endif
2872	Log7Func(("Many3: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2873	}
2874	}
2875	}
2876	else
2877	# endif /* PGM_SYNC_N_PAGES */
2878	{
2879	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2880	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2881	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2882	}
2883
2884	return VINF_SUCCESS;
2885	}
2886
2887
2888	/**
2889	* Sync a shadow page table for a nested-guest page table.
2890	*
2891	* The shadow page table is not present in the shadow PDE.
2892	*
2893	* Handles mapping conflicts.
2894	*
2895	* A precondition for this method is that the shadow PDE is not present. The
2896	* caller must take the PGM lock before checking this and continue to hold it
2897	* when calling this method.
2898	*
2899	* @returns VBox status code.
2900	* @param pVCpu The cross context virtual CPU structure.
2901	* @param GCPhysNestedPage The nested-guest physical page address of the page
2902	* being synced.
2903	* @param GCPhysPage The guest-physical address of the page being synced.
2904	* @param pGstWalkAll The guest page table walk result.
2905	*/
2906	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll)
2907	{
2908	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2909	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2910	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2911
2912	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2913	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2914
2915	Log7Func(("GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
2916
2917	PGM_LOCK_ASSERT_OWNER(pVM);
2918	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2919
2920	PEPTPD pPd;
2921	PEPTPDPT pPdpt;
2922	unsigned const iPde = (GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK;
2923	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, &pPdpt, &pPd, pGstWalkAll);
2924	if (RT_SUCCESS(rc))
2925	{ /* likely */ }
2926	else
2927	{
2928	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2929	AssertRC(rc);
2930	return rc;
2931	}
2932	Assert(pPd);
2933	PSHWPDE pPde = &pPd->a[iPde];
2934
2935	unsigned const iPdpt = (GCPhysNestedPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2936	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdpt->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2937	Assert(pShwPde->enmKind == PGMPOOLKIND_EPT_PD_FOR_EPT_PD);
2938
2939	SHWPDE Pde = *pPde;
2940	Assert(!SHW_PDE_IS_P(Pde)); /* We're only supposed to call SyncPT on PDE!P and conflicts. */
2941
2942	# ifdef PGM_WITH_LARGE_PAGES
2943	Assert(BTH_IS_NP_ACTIVE(pVM));
2944
2945	/*
2946	* Check if the guest is mapping a 2M page.
2947	*/
2948	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2949	{
2950	PPGMPAGE pPage;
2951	rc = pgmPhysGetPageEx(pVM, GCPhysPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2952	AssertRCReturn(rc, rc);
2953
2954	/* A20 is always enabled in VMX root and non-root operation. */
2955	Assert(PGM_A20_IS_ENABLED(pVCpu));
2956
2957	/*
2958	* Check if we have or can get a 2M backing page here.
2959	*/
2960	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2961	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2962	{
2963	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2964	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2965	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2966	}
2967	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2968	{
2969	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2970	rc = pgmPhysRecheckLargePage(pVM, GCPhysPage, pPage);
2971	if (RT_SUCCESS(rc))
2972	{
2973	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2974	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2975	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2976	}
2977	}
2978	else if (PGMIsUsingLargePages(pVM))
2979	{
2980	rc = pgmPhysAllocLargePage(pVM, GCPhysPage);
2981	if (RT_SUCCESS(rc))
2982	{
2983	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2984	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2985	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2986	}
2987	}
2988
2989	/*
2990	* If we have a 2M backing page, we can map the guest's 2M page right away.
2991	*/
2992	uint64_t const fGstShwBigPdeFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask)
2993	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2994	if (HCPhys != NIL_RTHCPHYS)
2995	{
2996	Pde.u = HCPhys \| fGstShwBigPdeFlags;
2997	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzBigPdeMask));
2998	Assert(Pde.u & EPT_E_LEAF);
2999	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3000
3001	/* Add a reference to the first page only. */
3002	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPde);
3003
3004	Assert(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED);
3005
3006	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3007	Log7Func(("GstPde=%RGp ShwPde=%RX64 [2M]\n", pGstWalkAll->u.Ept.Pde.u, Pde.u));
3008	return VINF_SUCCESS;
3009	}
3010
3011	/*
3012	* We didn't get a perfect 2M fit. Split the 2M page into 4K pages.
3013	* The page ought not to be marked as a big (2M) page at this point.
3014	*/
3015	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
3016
3017	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3018	PGMPOOLACCESS enmAccess;
3019	{
3020	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_USER_EXECUTE)); /* Mode-based execute control for EPT not supported. */
3021	bool const fNoExecute = !(pGstWalkAll->u.Ept.Pde.u & EPT_E_EXECUTE);
3022	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_WRITE)
3023	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3024	else
3025	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3026	}
3027
3028	/*
3029	* Allocate & map a 4K shadow table to cover the 2M guest page.
3030	*/
3031	PPGMPOOLPAGE pShwPage;
3032	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK;
3033	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_2MB, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3034	pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3035	if ( rc == VINF_SUCCESS
3036	\|\| rc == VINF_PGM_CACHED_PAGE)
3037	{ /* likely */ }
3038	else
3039	{
3040	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3041	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3042	}
3043
3044	PSHWPT pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3045	Assert(pPt);
3046	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3047	if (rc == VINF_SUCCESS)
3048	{
3049	/* The 4K PTEs shall inherit the flags of the 2M PDE page sans the leaf bit. */
3050	uint64_t const fGstShwPteFlags = fGstShwBigPdeFlags & ~EPT_E_LEAF;
3051
3052	/* Sync each 4K pages in the 2M range. */
3053	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++)
3054	{
3055	RTGCPHYS const GCPhysSubPage = GCPhysPt \| (iPte << GUEST_PAGE_SHIFT);
3056	pGstWalkAll->u.Ept.Pte.u = GCPhysSubPage \| fGstShwPteFlags;
3057	Assert(!(pGstWalkAll->u.Ept.Pte.u & pVCpu->pgm.s.fGstEptMbzPteMask));
3058	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysSubPage, pShwPage, iPte, pGstWalkAll);
3059	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [2M->4K]\n", pGstWalkAll->u.Ept.Pte, pPt->a[iPte].u, iPte));
3060	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3061	break;
3062	}
3063
3064	/* Restore modifications did to the guest-walk result above in case callers might inspect them later. */
3065	pGstWalkAll->u.Ept.Pte.u = 0;
3066	}
3067	else
3068	{
3069	Assert(rc == VINF_PGM_CACHED_PAGE);
3070	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3071	/* Paranoia - Verify address of each of the subpages are what they should be. */
3072	RTGCPHYS GCPhysSubPage = GCPhysPt;
3073	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++, GCPhysSubPage += GUEST_PAGE_SIZE)
3074	{
3075	PPGMPAGE pSubPage;
3076	rc = pgmPhysGetPageEx(pVM, GCPhysSubPage, &pSubPage);
3077	AssertRC(rc);
3078	AssertMsg( PGM_PAGE_GET_HCPHYS(pSubPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte])
3079	\|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3080	("PGM 2M page and shadow PTE conflict. GCPhysSubPage=%RGp Page=%RHp Shw=%RHp\n",
3081	GCPhysSubPage, PGM_PAGE_GET_HCPHYS(pSubPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3082	}
3083	# endif
3084	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3085	}
3086
3087	/* Save the new PDE. */
3088	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3089	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3090	Assert(!(Pde.u & EPT_E_LEAF));
3091	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3092	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3093	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3094	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3095	return rc;
3096	}
3097	# endif /* PGM_WITH_LARGE_PAGES */
3098
3099	/*
3100	* Allocate & map the shadow page table.
3101	*/
3102	PSHWPT pPt;
3103	PPGMPOOLPAGE pShwPage;
3104
3105	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE_PG_MASK;
3106	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_PT, PGMPOOLACCESS_DONTCARE,
3107	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3108	if ( rc == VINF_SUCCESS
3109	\|\| rc == VINF_PGM_CACHED_PAGE)
3110	{ /* likely */ }
3111	else
3112	{
3113	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3114	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3115	}
3116
3117	pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3118	Assert(pPt);
3119	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3120
3121	if (rc == VINF_SUCCESS)
3122	{
3123	/* Sync the page we've already translated through SLAT. */
3124	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3125	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
3126	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3127
3128	/* Sync the rest of page table (expensive but might be cheaper than nested-guest VM-exits in hardware). */
3129	for (unsigned iPteCur = 0; iPteCur < RT_ELEMENTS(pPt->a); iPteCur++)
3130	{
3131	if (iPteCur != iPte)
3132	{
3133	PGMPTWALKGST GstWalkPt;
3134	PGMPTWALK WalkPt;
3135	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
3136	GCPhysNestedPage \|= (iPteCur << GUEST_PAGE_SHIFT);
3137	int const rc2 = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/,
3138	&WalkPt, &GstWalkPt);
3139	if (RT_SUCCESS(rc2))
3140	{
3141	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPteCur], WalkPt.GCPhys, pShwPage, iPteCur, &GstWalkPt);
3142	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", GstWalkPt.u.Ept.Pte.u, pPt->a[iPteCur].u, iPteCur));
3143	}
3144	else
3145	{
3146	/*
3147	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
3148	* Ensure the shadow tables entry is not-present.
3149	*/
3150	/** @todo We currently don't configure these to cause EPT misconfigs but rather trap
3151	* them using EPT violations and walk the guest EPT tables to determine
3152	* whether they are EPT misconfigs VM-exits for the nested-hypervisor. We
3153	* could optimize this by using a specific combination of reserved bits
3154	* which we could immediately identify as EPT misconfigs of the
3155	* nested-hypervisor without having to walk its EPT tables. However, tracking
3156	* non-present entries might be tricky...
3157	*/
3158	AssertMsg(!pPt->a[iPteCur].u, ("%RX64\n", pPt->a[iPteCur].u));
3159	}
3160	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3161	break;
3162	}
3163	}
3164	}
3165	else
3166	{
3167	Assert(rc == VINF_PGM_CACHED_PAGE);
3168	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3169	/* Paranoia - Verify address of the page is what it should be. */
3170	PPGMPAGE pPage;
3171	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
3172	AssertRC(rc);
3173	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3174	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]) \|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3175	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp Page=%RHp Shw=%RHp\n",
3176	GCPhysNestedPage, GCPhysPage, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3177	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [cache]\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3178	# endif
3179	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3180	}
3181
3182	/* Save the new PDE. */
3183	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3184	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF));
3185	Assert(!(pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3186	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3187	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3188	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3189
3190	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3191	return rc;
3192	}
3193
3194	#endif /* !IN_RING3 && VBOX_WITH_NESTED_HWVIRT_VMX_EPT && PGM_SHW_TYPE == PGM_TYPE_EPT*/
3195	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3196
3197	/**
3198	* Handle dirty bit tracking faults.
3199	*
3200	* @returns VBox status code.
3201	* @param pVCpu The cross context virtual CPU structure.
3202	* @param uErr Page fault error code.
3203	* @param pPdeSrc Guest page directory entry.
3204	* @param pPdeDst Shadow page directory entry.
3205	* @param GCPtrPage Guest context page address.
3206	*/
3207	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
3208	RTGCPTR GCPtrPage)
3209	{
3210	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3211	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3212	NOREF(uErr);
3213
3214	PGM_LOCK_ASSERT_OWNER(pVM);
3215
3216	/*
3217	* Handle big page.
3218	*/
3219	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
3220	{
3221	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3222	{
3223	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3224	Assert(pPdeSrc->u & X86_PDE_RW);
3225
3226	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
3227	* fault again and take this path to only invalidate the entry (see below). */
3228	SHWPDE PdeDst = *pPdeDst;
3229	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
3230	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
3231	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3232	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
3233	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3234	}
3235
3236	# ifdef IN_RING0
3237	/* Check for stale TLB entry; only applies to the SMP guest case. */
3238	if ( pVM->cCpus > 1
3239	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
3240	{
3241	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3242	if (pShwPage)
3243	{
3244	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3245	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3246	if (SHW_PTE_IS_P_RW(*pPteDst))
3247	{
3248	/* Stale TLB entry. */
3249	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3250	PGM_INVL_PG(pVCpu, GCPtrPage);
3251	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3252	}
3253	}
3254	}
3255	# endif /* IN_RING0 */
3256	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3257	}
3258
3259	/*
3260	* Map the guest page table.
3261	*/
3262	PGSTPT pPTSrc;
3263	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
3264	AssertRCReturn(rc, rc);
3265
3266	if (SHW_PDE_IS_P(*pPdeDst))
3267	{
3268	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
3269	const GSTPTE PteSrc = *pPteSrc;
3270
3271	/*
3272	* Map shadow page table.
3273	*/
3274	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3275	if (pShwPage)
3276	{
3277	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3278	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3279	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
3280	{
3281	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
3282	{
3283	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
3284	SHWPTE PteDst = *pPteDst;
3285
3286	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
3287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3288
3289	Assert(PteSrc.u & X86_PTE_RW);
3290
3291	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
3292	* entry will not harm; write access will simply fault again and
3293	* take this path to only invalidate the entry.
3294	*/
3295	if (RT_LIKELY(pPage))
3296	{
3297	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3298	{
3299	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
3300	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
3301	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
3302	SHW_PTE_SET_RO(PteDst);
3303	}
3304	else
3305	{
3306	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
3307	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
3308	{
3309	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
3310	AssertRC(rc);
3311	}
3312	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
3313	SHW_PTE_SET_RW(PteDst);
3314	else
3315	{
3316	/* Still applies to shared pages. */
3317	Assert(!PGM_PAGE_IS_ZERO(pPage));
3318	SHW_PTE_SET_RO(PteDst);
3319	}
3320	}
3321	}
3322	else
3323	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
3324
3325	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
3326	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
3327	PGM_INVL_PG(pVCpu, GCPtrPage);
3328	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3329	}
3330
3331	# ifdef IN_RING0
3332	/* Check for stale TLB entry; only applies to the SMP guest case. */
3333	if ( pVM->cCpus > 1
3334	&& SHW_PTE_IS_RW(*pPteDst)
3335	&& SHW_PTE_IS_A(*pPteDst))
3336	{
3337	/* Stale TLB entry. */
3338	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3339	PGM_INVL_PG(pVCpu, GCPtrPage);
3340	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3341	}
3342	# endif
3343	}
3344	}
3345	else
3346	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
3347	}
3348
3349	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3350	}
3351
3352	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
3353
3354	/**
3355	* Sync a shadow page table.
3356	*
3357	* The shadow page table is not present in the shadow PDE.
3358	*
3359	* Handles mapping conflicts.
3360	*
3361	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
3362	* conflict), and Trap0eHandler.
3363	*
3364	* A precondition for this method is that the shadow PDE is not present. The
3365	* caller must take the PGM lock before checking this and continue to hold it
3366	* when calling this method.
3367	*
3368	* @returns VBox status code.
3369	* @param pVCpu The cross context virtual CPU structure.
3370	* @param iPDSrc Page directory index.
3371	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
3372	* Assume this is a temporary mapping.
3373	* @param GCPtrPage GC Pointer of the page that caused the fault
3374	*/
3375	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
3376	{
3377	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3378	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3379
3380	#if 0 /* rarely useful; leave for debugging. */
3381	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
3382	#endif
3383	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
3384
3385	PGM_LOCK_ASSERT_OWNER(pVM);
3386
3387	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3388	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3389	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3390	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3391	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3392	int rc = VINF_SUCCESS;
3393
3394	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3395
3396	/*
3397	* Some input validation first.
3398	*/
3399	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
3400
3401	/*
3402	* Get the relevant shadow PDE entry.
3403	*/
3404	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3405	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
3406	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3407
3408	/* Fetch the pgm pool shadow descriptor. */
3409	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3410	Assert(pShwPde);
3411
3412	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3413	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3414	PPGMPOOLPAGE pShwPde = NULL;
3415	PX86PDPAE pPDDst;
3416	PSHWPDE pPdeDst;
3417
3418	/* Fetch the pgm pool shadow descriptor. */
3419	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3420	AssertRCSuccessReturn(rc, rc);
3421	Assert(pShwPde);
3422
3423	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3424	pPdeDst = &pPDDst->a[iPDDst];
3425
3426	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3427	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3428	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3429	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3430	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
3431	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3432	AssertRCSuccessReturn(rc, rc);
3433	Assert(pPDDst);
3434	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3435
3436	# endif
3437	SHWPDE PdeDst = *pPdeDst;
3438
3439	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3440	/* Fetch the pgm pool shadow descriptor. */
3441	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3442	Assert(pShwPde);
3443	# endif
3444
3445	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
3446
3447	/*
3448	* Sync the page directory entry.
3449	*/
3450	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3451	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
3452	if ( (PdeSrc.u & X86_PDE_P)
3453	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
3454	{
3455	/*
3456	* Allocate & map the page table.
3457	*/
3458	PSHWPT pPTDst;
3459	PPGMPOOLPAGE pShwPage;
3460	RTGCPHYS GCPhys;
3461	if (fPageTable)
3462	{
3463	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
3464	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3465	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3466	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
3467	# endif
3468	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
3469	pShwPde->idx, iPDDst, false /fLockPage/,
3470	&pShwPage);
3471	}
3472	else
3473	{
3474	PGMPOOLACCESS enmAccess;
3475	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
3476	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
3477	# else
3478	const bool fNoExecute = false;
3479	# endif
3480
3481	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3482	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3483	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3484	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
3485	# endif
3486	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3487	if (PdeSrc.u & X86_PDE_US)
3488	{
3489	if (PdeSrc.u & X86_PDE_RW)
3490	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
3491	else
3492	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
3493	}
3494	else
3495	{
3496	if (PdeSrc.u & X86_PDE_RW)
3497	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3498	else
3499	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3500	}
3501	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3502	pShwPde->idx, iPDDst, false /fLockPage/,
3503	&pShwPage);
3504	}
3505	if (rc == VINF_SUCCESS)
3506	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3507	else if (rc == VINF_PGM_CACHED_PAGE)
3508	{
3509	/*
3510	* The PT was cached, just hook it up.
3511	*/
3512	if (fPageTable)
3513	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3514	else
3515	{
3516	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3517	/* (see explanation and assumptions further down.) */
3518	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3519	{
3520	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3521	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3522	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3523	}
3524	}
3525	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3526	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3527	return VINF_SUCCESS;
3528	}
3529	else
3530	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3531	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
3532	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
3533	* irrelevant at this point. */
3534	PdeDst.u &= X86_PDE_AVL_MASK;
3535	PdeDst.u \|= pShwPage->Core.Key;
3536
3537	/*
3538	* Page directory has been accessed (this is a fault situation, remember).
3539	*/
3540	/** @todo
3541	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
3542	* fault situation. What's more, the Trap0eHandler has already set the
3543	* accessed bit. So, it's actually just VerifyAccessSyncPage which
3544	* might need setting the accessed flag.
3545	*
3546	* The best idea is to leave this change to the caller and add an
3547	* assertion that it's set already. */
3548	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
3549	if (fPageTable)
3550	{
3551	/*
3552	* Page table - 4KB.
3553	*
3554	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
3555	*/
3556	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
3557	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
3558	PGSTPT pPTSrc;
3559	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
3560	if (RT_SUCCESS(rc))
3561	{
3562	/*
3563	* Start by syncing the page directory entry so CSAM's TLB trick works.
3564	*/
3565	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
3566	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3567	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3568	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3569
3570	/*
3571	* Directory/page user or supervisor privilege: (same goes for read/write)
3572	*
3573	* Directory Page Combined
3574	* U/S U/S U/S
3575	* 0 0 0
3576	* 0 1 0
3577	* 1 0 0
3578	* 1 1 1
3579	*
3580	* Simple AND operation. Table listed for completeness.
3581	*
3582	*/
3583	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
3584	# ifdef PGM_SYNC_N_PAGES
3585	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3586	unsigned iPTDst = iPTBase;
3587	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
3588	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
3589	iPTDst = 0;
3590	else
3591	iPTDst -= PGM_SYNC_NR_PAGES / 2;
3592	# else /* !PGM_SYNC_N_PAGES */
3593	unsigned iPTDst = 0;
3594	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
3595	# endif /* !PGM_SYNC_N_PAGES */
3596	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
3597	\| ((RTGCPTR)iPTDst << GUEST_PAGE_SHIFT);
3598	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3599	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3600	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
3601	# else
3602	const unsigned offPTSrc = 0;
3603	# endif
3604	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += GUEST_PAGE_SIZE)
3605	{
3606	const unsigned iPTSrc = iPTDst + offPTSrc;
3607	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
3608	if (PteSrc.u & X86_PTE_P)
3609	{
3610	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
3611	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
3612	GCPtrCur,
3613	PteSrc.u & X86_PTE_P,
3614	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
3615	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
3616	(uint64_t)PteSrc.u,
3617	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
3618	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
3619	}
3620	/* else: the page table was cleared by the pool */
3621	} /* for PTEs */
3622	}
3623	}
3624	else
3625	{
3626	/*
3627	* Big page - 2/4MB.
3628	*
3629	* We'll walk the ram range list in parallel and optimize lookups.
3630	* We will only sync one shadow page table at a time.
3631	*/
3632	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
3633
3634	/**
3635	* @todo It might be more efficient to sync only a part of the 4MB
3636	* page (similar to what we do for 4KB PDs).
3637	*/
3638
3639	/*
3640	* Start by syncing the page directory entry.
3641	*/
3642	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
3643	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3644
3645	/*
3646	* If the page is not flagged as dirty and is writable, then make it read-only
3647	* at PD level, so we can set the dirty bit when the page is modified.
3648	*
3649	* ASSUMES that page access handlers are implemented on page table entry level.
3650	* Thus we will first catch the dirty access and set PDE.D and restart. If
3651	* there is an access handler, we'll trap again and let it work on the problem.
3652	*/
3653	/** @todo move the above stuff to a section in the PGM documentation. */
3654	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3655	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3656	{
3657	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3658	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3659	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3660	}
3661	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3662	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3663
3664	/*
3665	* Fill the shadow page table.
3666	*/
3667	/* Get address and flags from the source PDE. */
3668	SHWPTE PteDstBase;
3669	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3670
3671	/* Loop thru the entries in the shadow PT. */
3672	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3673	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3674	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
3675	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3676	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3677	unsigned iPTDst = 0;
3678	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3679	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3680	{
3681	if (pRam && GCPhys >= pRam->GCPhys)
3682	{
3683	# ifndef PGM_WITH_A20
3684	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT;
3685	# endif
3686	do
3687	{
3688	/* Make shadow PTE. */
3689	# ifdef PGM_WITH_A20
3690	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT];
3691	# else
3692	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3693	# endif
3694	SHWPTE PteDst;
3695
3696	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3697	/* Try to make the page writable if necessary. */
3698	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3699	&& ( PGM_PAGE_IS_ZERO(pPage)
3700	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3701	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3702	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3703	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3704	# endif
3705	# ifdef VBOX_WITH_PAGE_SHARING
3706	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3707	# endif
3708	&& !PGM_PAGE_IS_BALLOONED(pPage))
3709	)
3710	)
3711	{
3712	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3713	AssertRCReturn(rc, rc);
3714	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3715	break;
3716	}
3717	# endif
3718
3719	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3720	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, SHW_PTE_GET_U(PteDstBase), &PteDst);
3721	else if (PGM_PAGE_IS_BALLOONED(pPage))
3722	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3723	else
3724	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3725
3726	/* Only map writable pages writable. */
3727	if ( SHW_PTE_IS_P_RW(PteDst)
3728	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3729	{
3730	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3731	/* Still applies to shared pages. */
3732	Assert(!PGM_PAGE_IS_ZERO(pPage));
3733	# endif
3734	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3735	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3736	}
3737
3738	if (SHW_PTE_IS_P(PteDst))
3739	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3740
3741	/* commit it (not atomic, new table) */
3742	pPTDst->a[iPTDst] = PteDst;
3743	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3744	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3745	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3746
3747	/* advance */
3748	GCPhys += GUEST_PAGE_SIZE;
3749	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3750	# ifndef PGM_WITH_A20
3751	iHCPage++;
3752	# endif
3753	iPTDst++;
3754	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3755	&& GCPhys <= pRam->GCPhysLast);
3756
3757	/* Advance ram range list. */
3758	while (pRam && GCPhys > pRam->GCPhysLast)
3759	pRam = pRam->CTX_SUFF(pNext);
3760	}
3761	else if (pRam)
3762	{
3763	Log(("Invalid pages at %RGp\n", GCPhys));
3764	do
3765	{
3766	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3767	GCPhys += GUEST_PAGE_SIZE;
3768	iPTDst++;
3769	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3770	&& GCPhys < pRam->GCPhys);
3771	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3772	}
3773	else
3774	{
3775	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3776	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3777	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3778	}
3779	} /* while more PTEs */
3780	} /* 4KB / 4MB */
3781	}
3782	else
3783	AssertRelease(!SHW_PDE_IS_P(PdeDst));
3784
3785	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3786	if (RT_FAILURE(rc))
3787	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3788	return rc;
3789
3790	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3791	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
3792	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3793	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3794	NOREF(iPDSrc); NOREF(pPDSrc);
3795
3796	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3797
3798	/*
3799	* Validate input a little bit.
3800	*/
3801	int rc = VINF_SUCCESS;
3802	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3803	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3804	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3805
3806	/* Fetch the pgm pool shadow descriptor. */
3807	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3808	Assert(pShwPde);
3809
3810	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3811	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3812	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3813	PX86PDPAE pPDDst;
3814	PSHWPDE pPdeDst;
3815
3816	/* Fetch the pgm pool shadow descriptor. */
3817	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3818	AssertRCSuccessReturn(rc, rc);
3819	Assert(pShwPde);
3820
3821	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3822	pPdeDst = &pPDDst->a[iPDDst];
3823
3824	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3825	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3826	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3827	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3828	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3829	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3830	AssertRCSuccessReturn(rc, rc);
3831	Assert(pPDDst);
3832	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3833
3834	/* Fetch the pgm pool shadow descriptor. */
3835	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3836	Assert(pShwPde);
3837
3838	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3839	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3840	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3841	PEPTPD pPDDst;
3842	PEPTPDPT pPdptDst;
3843
3844	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3845	if (rc != VINF_SUCCESS)
3846	{
3847	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3848	AssertRC(rc);
3849	return rc;
3850	}
3851	Assert(pPDDst);
3852	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3853
3854	/* Fetch the pgm pool shadow descriptor. */
3855	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
3856	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3857	Assert(pShwPde);
3858	# endif
3859	SHWPDE PdeDst = *pPdeDst;
3860
3861	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3862
3863	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3864	if (BTH_IS_NP_ACTIVE(pVM))
3865	{
3866	Assert(!VM_IS_NEM_ENABLED(pVM));
3867
3868	/* Check if we allocated a big page before for this 2 MB range. */
3869	PPGMPAGE pPage;
3870	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3871	if (RT_SUCCESS(rc))
3872	{
3873	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3874	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3875	{
3876	if (PGM_A20_IS_ENABLED(pVCpu))
3877	{
3878	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3879	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3880	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3881	}
3882	else
3883	{
3884	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3885	pVM->pgm.s.cLargePagesDisabled++;
3886	}
3887	}
3888	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3889	&& PGM_A20_IS_ENABLED(pVCpu))
3890	{
3891	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3892	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3893	if (RT_SUCCESS(rc))
3894	{
3895	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3896	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3897	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3898	}
3899	}
3900	# if !defined(VBOX_WITH_NEW_LAZY_PAGE_ALLOC) && !defined(PGM_WITH_PAGE_ZEROING_DETECTION) /* This code is too aggresive! */
3901	else if ( PGMIsUsingLargePages(pVM)
3902	&& PGM_A20_IS_ENABLED(pVCpu))
3903	{
3904	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3905	if (RT_SUCCESS(rc))
3906	{
3907	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3908	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3909	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3910	}
3911	else
3912	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3913	}
3914	# endif
3915
3916	if (HCPhys != NIL_RTHCPHYS)
3917	{
3918	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3919	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
3920	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
3921	# else
3922	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
3923	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
3924	# endif
3925	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3926
3927	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3928	/* Add a reference to the first page only. */
3929	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3930
3931	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3932	return VINF_SUCCESS;
3933	}
3934	}
3935	}
3936	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3937
3938	/*
3939	* Allocate & map the page table.
3940	*/
3941	PSHWPT pPTDst;
3942	PPGMPOOLPAGE pShwPage;
3943	RTGCPHYS GCPhys;
3944
3945	/* Virtual address = physical address */
3946	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3947	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3948	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3949	&pShwPage);
3950	if ( rc == VINF_SUCCESS
3951	\|\| rc == VINF_PGM_CACHED_PAGE)
3952	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3953	else
3954	{
3955	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3956	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3957	}
3958
3959	if (rc == VINF_SUCCESS)
3960	{
3961	/* New page table; fully set it up. */
3962	Assert(pPTDst);
3963
3964	/* Mask away the page offset. */
3965	GCPtrPage &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
3966
3967	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3968	{
3969	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3970	\| (iPTDst << GUEST_PAGE_SHIFT));
3971
3972	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3973	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3974	GCPtrCurPage,
3975	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3976	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3977
3978	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3979	break;
3980	}
3981	}
3982	else
3983	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3984
3985	/* Save the new PDE. */
3986	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3987	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
3988	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
3989	# else
3990	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
3991	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
3992	# endif
3993	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3994
3995	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3996	if (RT_FAILURE(rc))
3997	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3998	return rc;
3999
4000	#else
4001	NOREF(iPDSrc); NOREF(pPDSrc);
4002	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
4003	return VERR_PGM_NOT_USED_IN_MODE;
4004	#endif
4005	}
4006
4007
4008
4009	/**
4010	* Prefetch a page/set of pages.
4011	*
4012	* Typically used to sync commonly used pages before entering raw mode
4013	* after a CR3 reload.
4014	*
4015	* @returns VBox status code.
4016	* @param pVCpu The cross context virtual CPU structure.
4017	* @param GCPtrPage Page to invalidate.
4018	*/
4019	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
4020	{
4021	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4022	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4023	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4024	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4025	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4026	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4027	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4028	/*
4029	* Check that all Guest levels thru the PDE are present, getting the
4030	* PD and PDE in the processes.
4031	*/
4032	int rc = VINF_SUCCESS;
4033	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4034	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4035	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4036	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4037	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4038	unsigned iPDSrc;
4039	X86PDPE PdpeSrc;
4040	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4041	if (!pPDSrc)
4042	return VINF_SUCCESS; /* not present */
4043	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4044	unsigned iPDSrc;
4045	PX86PML4E pPml4eSrc;
4046	X86PDPE PdpeSrc;
4047	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4048	if (!pPDSrc)
4049	return VINF_SUCCESS; /* not present */
4050	# endif
4051	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4052	# else
4053	PGSTPD pPDSrc = NULL;
4054	const unsigned iPDSrc = 0;
4055	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4056	# endif
4057
4058	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
4059	{
4060	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4061	PGM_LOCK_VOID(pVM);
4062
4063	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4064	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
4065	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4066	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4067	PX86PDPAE pPDDst;
4068	X86PDEPAE PdeDst;
4069	# if PGM_GST_TYPE != PGM_TYPE_PAE
4070	X86PDPE PdpeSrc;
4071
4072	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4073	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4074	# endif
4075	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4076	if (rc != VINF_SUCCESS)
4077	{
4078	PGM_UNLOCK(pVM);
4079	AssertRC(rc);
4080	return rc;
4081	}
4082	Assert(pPDDst);
4083	PdeDst = pPDDst->a[iPDDst];
4084
4085	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4086	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4087	PX86PDPAE pPDDst;
4088	X86PDEPAE PdeDst;
4089
4090	# if PGM_GST_TYPE == PGM_TYPE_PROT
4091	/* AMD-V nested paging */
4092	X86PML4E Pml4eSrc;
4093	X86PDPE PdpeSrc;
4094	PX86PML4E pPml4eSrc = &Pml4eSrc;
4095
4096	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4097	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4098	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4099	# endif
4100
4101	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4102	if (rc != VINF_SUCCESS)
4103	{
4104	PGM_UNLOCK(pVM);
4105	AssertRC(rc);
4106	return rc;
4107	}
4108	Assert(pPDDst);
4109	PdeDst = pPDDst->a[iPDDst];
4110	# endif
4111	if (!(PdeDst.u & X86_PDE_P))
4112	{
4113	/** @todo r=bird: This guy will set the A bit on the PDE,
4114	* probably harmless. */
4115	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4116	}
4117	else
4118	{
4119	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
4120	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
4121	* makes no sense to prefetch more than one page.
4122	*/
4123	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4124	if (RT_SUCCESS(rc))
4125	rc = VINF_SUCCESS;
4126	}
4127	PGM_UNLOCK(pVM);
4128	}
4129	return rc;
4130
4131	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4132	NOREF(pVCpu); NOREF(GCPtrPage);
4133	return VINF_SUCCESS; /* ignore */
4134	#else
4135	AssertCompile(0);
4136	#endif
4137	}
4138
4139
4140
4141
4142	/**
4143	* Syncs a page during a PGMVerifyAccess() call.
4144	*
4145	* @returns VBox status code (informational included).
4146	* @param pVCpu The cross context virtual CPU structure.
4147	* @param GCPtrPage The address of the page to sync.
4148	* @param fPage The effective guest page flags.
4149	* @param uErr The trap error code.
4150	* @remarks This will normally never be called on invalid guest page
4151	* translation entries.
4152	*/
4153	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
4154	{
4155	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4156
4157	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
4158	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
4159
4160	Assert(!pVM->pgm.s.fNestedPaging);
4161	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4162	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4163	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4164	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4165	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4166	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4167	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4168
4169	/*
4170	* Get guest PD and index.
4171	*/
4172	/** @todo Performance: We've done all this a jiffy ago in the
4173	* PGMGstGetPage call. */
4174	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4175	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4176	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4177	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4178
4179	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4180	unsigned iPDSrc = 0;
4181	X86PDPE PdpeSrc;
4182	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4183	if (RT_UNLIKELY(!pPDSrc))
4184	{
4185	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4186	return VINF_EM_RAW_GUEST_TRAP;
4187	}
4188
4189	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4190	unsigned iPDSrc = 0; /* shut up gcc */
4191	PX86PML4E pPml4eSrc = NULL; /* ditto */
4192	X86PDPE PdpeSrc;
4193	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4194	if (RT_UNLIKELY(!pPDSrc))
4195	{
4196	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4197	return VINF_EM_RAW_GUEST_TRAP;
4198	}
4199	# endif
4200
4201	# else /* !PGM_WITH_PAGING */
4202	PGSTPD pPDSrc = NULL;
4203	const unsigned iPDSrc = 0;
4204	# endif /* !PGM_WITH_PAGING */
4205	int rc = VINF_SUCCESS;
4206
4207	PGM_LOCK_VOID(pVM);
4208
4209	/*
4210	* First check if the shadow pd is present.
4211	*/
4212	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4213	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
4214
4215	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4216	PX86PDEPAE pPdeDst;
4217	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4218	PX86PDPAE pPDDst;
4219	# if PGM_GST_TYPE != PGM_TYPE_PAE
4220	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4221	X86PDPE PdpeSrc;
4222	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4223	# endif
4224	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4225	if (rc != VINF_SUCCESS)
4226	{
4227	PGM_UNLOCK(pVM);
4228	AssertRC(rc);
4229	return rc;
4230	}
4231	Assert(pPDDst);
4232	pPdeDst = &pPDDst->a[iPDDst];
4233
4234	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4235	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4236	PX86PDPAE pPDDst;
4237	PX86PDEPAE pPdeDst;
4238
4239	# if PGM_GST_TYPE == PGM_TYPE_PROT
4240	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4241	X86PML4E Pml4eSrc;
4242	X86PDPE PdpeSrc;
4243	PX86PML4E pPml4eSrc = &Pml4eSrc;
4244	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4245	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4246	# endif
4247
4248	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4249	if (rc != VINF_SUCCESS)
4250	{
4251	PGM_UNLOCK(pVM);
4252	AssertRC(rc);
4253	return rc;
4254	}
4255	Assert(pPDDst);
4256	pPdeDst = &pPDDst->a[iPDDst];
4257	# endif
4258
4259	if (!(pPdeDst->u & X86_PDE_P))
4260	{
4261	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4262	if (rc != VINF_SUCCESS)
4263	{
4264	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4265	PGM_UNLOCK(pVM);
4266	AssertRC(rc);
4267	return rc;
4268	}
4269	}
4270
4271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4272	/* Check for dirty bit fault */
4273	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
4274	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
4275	Log(("PGMVerifyAccess: success (dirty)\n"));
4276	else
4277	# endif
4278	{
4279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4280	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4281	# else
4282	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4283	# endif
4284
4285	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
4286	if (uErr & X86_TRAP_PF_US)
4287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
4288	else /* supervisor */
4289	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
4290
4291	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4292	if (RT_SUCCESS(rc))
4293	{
4294	/* Page was successfully synced */
4295	Log2(("PGMVerifyAccess: success (sync)\n"));
4296	rc = VINF_SUCCESS;
4297	}
4298	else
4299	{
4300	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
4301	rc = VINF_EM_RAW_GUEST_TRAP;
4302	}
4303	}
4304	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4305	PGM_UNLOCK(pVM);
4306	return rc;
4307
4308	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4309
4310	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
4311	return VERR_PGM_NOT_USED_IN_MODE;
4312	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4313	}
4314
4315
4316	/**
4317	* Syncs the paging hierarchy starting at CR3.
4318	*
4319	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
4320	* informational status codes.
4321	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
4322	* the VMM into guest context.
4323	* @param pVCpu The cross context virtual CPU structure.
4324	* @param cr0 Guest context CR0 register.
4325	* @param cr3 Guest context CR3 register. Not subjected to the A20
4326	* mask.
4327	* @param cr4 Guest context CR4 register.
4328	* @param fGlobal Including global page directories or not
4329	*/
4330	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
4331	{
4332	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4333	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
4334
4335	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
4336
4337	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
4338	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4339	PGM_LOCK_VOID(pVM);
4340	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4341	if (pPool->cDirtyPages)
4342	pgmPoolResetDirtyPages(pVM);
4343	PGM_UNLOCK(pVM);
4344	# endif
4345	#endif /* !NESTED && !EPT */
4346
4347	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4348	/*
4349	* Nested / EPT / None - No work.
4350	*/
4351	return VINF_SUCCESS;
4352
4353	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4354	/*
4355	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
4356	* out the shadow parts when the guest modifies its tables.
4357	*/
4358	return VINF_SUCCESS;
4359
4360	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4361
4362	return VINF_SUCCESS;
4363	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4364	}
4365
4366
4367
4368
4369	#ifdef VBOX_STRICT
4370
4371	/**
4372	* Checks that the shadow page table is in sync with the guest one.
4373	*
4374	* @returns The number of errors.
4375	* @param pVCpu The cross context virtual CPU structure.
4376	* @param cr3 Guest context CR3 register.
4377	* @param cr4 Guest context CR4 register.
4378	* @param GCPtr Where to start. Defaults to 0.
4379	* @param cb How much to check. Defaults to everything.
4380	*/
4381	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
4382	{
4383	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
4384	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4385	return 0;
4386	#else
4387	unsigned cErrors = 0;
4388	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4389	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
4390
4391	# if PGM_GST_TYPE == PGM_TYPE_PAE
4392	/** @todo currently broken; crashes below somewhere */
4393	AssertFailed();
4394	# endif
4395
4396	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
4397	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4398	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4399
4400	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
4401	PPGMCPU pPGM = &pVCpu->pgm.s;
4402	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
4403	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
4404	# ifndef IN_RING0
4405	RTHCPHYS HCPhys; /* general usage. */
4406	# endif
4407	int rc;
4408
4409	/*
4410	* Check that the Guest CR3 and all its mappings are correct.
4411	*/
4412	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
4413	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
4414	false);
4415	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
4416	# if 0
4417	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4418	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
4419	# else
4420	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
4421	# endif
4422	AssertRCReturn(rc, 1);
4423	HCPhys = NIL_RTHCPHYS;
4424	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
4425	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
4426	# endif
4427	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
4428	pgmGstGet32bitPDPtr(pVCpu);
4429	RTGCPHYS GCPhys;
4430	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
4431	AssertRCReturn(rc, 1);
4432	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
4433	# endif
4434	# endif /* !IN_RING0 */
4435
4436	/*
4437	* Get and check the Shadow CR3.
4438	*/
4439	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4440	unsigned cPDEs = X86_PG_ENTRIES;
4441	unsigned cIncrement = X86_PG_ENTRIES * GUEST_PAGE_SIZE;
4442	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4443	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4444	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
4445	# else
4446	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4447	# endif
4448	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4449	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4450	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4451	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4452	# endif
4453	if (cb != ~(RTGCPTR)0)
4454	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
4455
4456	/** @todo call the other two PGMAssert() functions. /
4457
4458	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4459	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4460
4461	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
4462	{
4463	PPGMPOOLPAGE pShwPdpt = NULL;
4464	PX86PML4E pPml4eSrc;
4465	PX86PML4E pPml4eDst;
4466	RTGCPHYS GCPhysPdptSrc;
4467
4468	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
4469	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4470
4471	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
4472	if (!(pPml4eDst->u & X86_PML4E_P))
4473	{
4474	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4475	continue;
4476	}
4477
4478	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
4479	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
4480
4481	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
4482	{
4483	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4484	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4485	cErrors++;
4486	continue;
4487	}
4488
4489	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
4490	{
4491	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
4492	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4493	cErrors++;
4494	continue;
4495	}
4496
4497	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
4498	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
4499	{
4500	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4501	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4502	cErrors++;
4503	continue;
4504	}
4505	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4506	{
4507	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4508
4509	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
4510	/*
4511	* Check the PDPTEs too.
4512	*/
4513	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
4514
4515	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
4516	{
4517	unsigned iPDSrc = 0; /* initialized to shut up gcc */
4518	PPGMPOOLPAGE pShwPde = NULL;
4519	PX86PDPE pPdpeDst;
4520	RTGCPHYS GCPhysPdeSrc;
4521	X86PDPE PdpeSrc;
4522	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
4523	# if PGM_GST_TYPE == PGM_TYPE_PAE
4524	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
4525	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
4526	# else
4527	PX86PML4E pPml4eSrcIgn;
4528	PX86PDPT pPdptDst;
4529	PX86PDPAE pPDDst;
4530	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
4531
4532	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
4533	if (rc != VINF_SUCCESS)
4534	{
4535	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
4536	GCPtr += 512 * _2M;
4537	continue; /* next PDPTE */
4538	}
4539	Assert(pPDDst);
4540	# endif
4541	Assert(iPDSrc == 0);
4542
4543	pPdpeDst = &pPdptDst->a[iPdpt];
4544
4545	if (!(pPdpeDst->u & X86_PDPE_P))
4546	{
4547	GCPtr += 512 * _2M;
4548	continue; /* next PDPTE */
4549	}
4550
4551	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
4552	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
4553
4554	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
4555	{
4556	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4557	GCPtr += 512 * _2M;
4558	cErrors++;
4559	continue;
4560	}
4561
4562	if (GCPhysPdeSrc != pShwPde->GCPhys)
4563	{
4564	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4565	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4566	# else
4567	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4568	# endif
4569	GCPtr += 512 * _2M;
4570	cErrors++;
4571	continue;
4572	}
4573
4574	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4575	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
4576	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
4577	{
4578	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4579	GCPtr += 512 * _2M;
4580	cErrors++;
4581	continue;
4582	}
4583	# endif
4584
4585	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4586	{
4587	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4588	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4589	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4590	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4591	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4592	# endif
4593	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4594	/*
4595	* Iterate the shadow page directory.
4596	*/
4597	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4598	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4599
4600	for (;
4601	iPDDst < cPDEs;
4602	iPDDst++, GCPtr += cIncrement)
4603	{
4604	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4605	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4606	# else
4607	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4608	# endif
4609	if ( (PdeDst.u & X86_PDE_P)
4610	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
4611	{
4612	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4613	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4614	if (!pPoolPage)
4615	{
4616	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4617	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4618	cErrors++;
4619	continue;
4620	}
4621	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4622
4623	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4624	{
4625	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4626	GCPtr, (uint64_t)PdeDst.u));
4627	cErrors++;
4628	}
4629
4630	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4631	{
4632	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4633	GCPtr, (uint64_t)PdeDst.u));
4634	cErrors++;
4635	}
4636
4637	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4638	if (!(PdeSrc.u & X86_PDE_P))
4639	{
4640	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4641	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4642	cErrors++;
4643	continue;
4644	}
4645
4646	if ( !(PdeSrc.u & X86_PDE_PS)
4647	\|\| !fBigPagesSupported)
4648	{
4649	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4650	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4651	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
4652	# endif
4653	}
4654	else
4655	{
4656	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4657	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4658	{
4659	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4660	GCPtr, (uint64_t)PdeSrc.u));
4661	cErrors++;
4662	continue;
4663	}
4664	# endif
4665	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4666	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4667	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4668	# endif
4669	}
4670
4671	if ( pPoolPage->enmKind
4672	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4673	{
4674	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4675	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4676	cErrors++;
4677	}
4678
4679	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4680	if (!pPhysPage)
4681	{
4682	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4683	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4684	cErrors++;
4685	continue;
4686	}
4687
4688	if (GCPhysGst != pPoolPage->GCPhys)
4689	{
4690	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4691	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4692	cErrors++;
4693	continue;
4694	}
4695
4696	if ( !(PdeSrc.u & X86_PDE_PS)
4697	\|\| !fBigPagesSupported)
4698	{
4699	/*
4700	* Page Table.
4701	*/
4702	const GSTPT *pPTSrc;
4703	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(GUEST_PAGE_SIZE - 1)),
4704	&pPTSrc);
4705	if (RT_FAILURE(rc))
4706	{
4707	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4708	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4709	cErrors++;
4710	continue;
4711	}
4712	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4713	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4714	{
4715	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4716	// (This problem will go away when/if we shadow multiple CR3s.)
4717	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4718	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4719	cErrors++;
4720	continue;
4721	}
4722	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4723	{
4724	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4725	GCPtr, (uint64_t)PdeDst.u));
4726	cErrors++;
4727	continue;
4728	}
4729
4730	/* iterate the page table. */
4731	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4732	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4733	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4734	# else
4735	const unsigned offPTSrc = 0;
4736	# endif
4737	for (unsigned iPT = 0, off = 0;
4738	iPT < RT_ELEMENTS(pPTDst->a);
4739	iPT++, off += GUEST_PAGE_SIZE)
4740	{
4741	const SHWPTE PteDst = pPTDst->a[iPT];
4742
4743	/* skip not-present and dirty tracked entries. */
4744	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4745	continue;
4746	Assert(SHW_PTE_IS_P(PteDst));
4747
4748	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4749	if (!(PteSrc.u & X86_PTE_P))
4750	{
4751	# ifdef IN_RING3
4752	PGMAssertHandlerAndFlagsInSync(pVM);
4753	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4754	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4755	0, 0, UINT64_MAX, 99, NULL);
4756	# endif
4757	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4758	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4759	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4760	cErrors++;
4761	continue;
4762	}
4763
4764	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4765	# if 1 /** @todo sync accessed bit properly... */
4766	fIgnoreFlags \|= X86_PTE_A;
4767	# endif
4768
4769	/* match the physical addresses */
4770	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4771	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4772
4773	# ifdef IN_RING3
4774	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4775	if (RT_FAILURE(rc))
4776	{
4777	# if 0
4778	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4779	{
4780	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4781	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4782	cErrors++;
4783	continue;
4784	}
4785	# endif
4786	}
4787	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4788	{
4789	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4790	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4791	cErrors++;
4792	continue;
4793	}
4794	# endif
4795
4796	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4797	if (!pPhysPage)
4798	{
4799	# if 0
4800	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4801	{
4802	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4803	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4804	cErrors++;
4805	continue;
4806	}
4807	# endif
4808	if (SHW_PTE_IS_RW(PteDst))
4809	{
4810	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4811	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4812	cErrors++;
4813	}
4814	fIgnoreFlags \|= X86_PTE_RW;
4815	}
4816	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4817	{
4818	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4819	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4820	cErrors++;
4821	continue;
4822	}
4823
4824	/* flags */
4825	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
4826	{
4827	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4828	{
4829	if (SHW_PTE_IS_RW(PteDst))
4830	{
4831	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4832	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4833	cErrors++;
4834	continue;
4835	}
4836	fIgnoreFlags \|= X86_PTE_RW;
4837	}
4838	else
4839	{
4840	if ( SHW_PTE_IS_P(PteDst)
4841	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4842	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4843	# endif
4844	)
4845	{
4846	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4847	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4848	cErrors++;
4849	continue;
4850	}
4851	fIgnoreFlags \|= X86_PTE_P;
4852	}
4853	}
4854	else
4855	{
4856	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
4857	{
4858	if (SHW_PTE_IS_RW(PteDst))
4859	{
4860	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4861	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4862	cErrors++;
4863	continue;
4864	}
4865	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4866	{
4867	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4868	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4869	cErrors++;
4870	continue;
4871	}
4872	if (SHW_PTE_IS_D(PteDst))
4873	{
4874	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4875	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4876	cErrors++;
4877	}
4878	# if 0 /** @todo sync access bit properly... */
4879	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4880	{
4881	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4882	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4883	cErrors++;
4884	}
4885	fIgnoreFlags \|= X86_PTE_RW;
4886	# else
4887	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4888	# endif
4889	}
4890	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4891	{
4892	/* access bit emulation (not implemented). */
4893	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
4894	{
4895	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4896	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4897	cErrors++;
4898	continue;
4899	}
4900	if (!SHW_PTE_IS_A(PteDst))
4901	{
4902	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4903	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4904	cErrors++;
4905	}
4906	fIgnoreFlags \|= X86_PTE_P;
4907	}
4908	# ifdef DEBUG_sandervl
4909	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4910	# endif
4911	}
4912
4913	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4914	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4915	)
4916	{
4917	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4918	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4919	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4920	cErrors++;
4921	continue;
4922	}
4923	} /* foreach PTE */
4924	}
4925	else
4926	{
4927	/*
4928	* Big Page.
4929	*/
4930	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4931	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
4932	{
4933	if (PdeDst.u & X86_PDE_RW)
4934	{
4935	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4936	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4937	cErrors++;
4938	continue;
4939	}
4940	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4941	{
4942	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4943	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4944	cErrors++;
4945	continue;
4946	}
4947	# if 0 /** @todo sync access bit properly... */
4948	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4949	{
4950	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4951	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4952	cErrors++;
4953	}
4954	fIgnoreFlags \|= X86_PTE_RW;
4955	# else
4956	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4957	# endif
4958	}
4959	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4960	{
4961	/* access bit emulation (not implemented). */
4962	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
4963	{
4964	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4965	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4966	cErrors++;
4967	continue;
4968	}
4969	if (!SHW_PDE_IS_A(PdeDst))
4970	{
4971	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4972	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4973	cErrors++;
4974	}
4975	fIgnoreFlags \|= X86_PTE_P;
4976	}
4977
4978	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4979	{
4980	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4981	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4982	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4983	cErrors++;
4984	}
4985
4986	/* iterate the page table. */
4987	for (unsigned iPT = 0, off = 0;
4988	iPT < RT_ELEMENTS(pPTDst->a);
4989	iPT++, off += GUEST_PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + GUEST_PAGE_SIZE))
4990	{
4991	const SHWPTE PteDst = pPTDst->a[iPT];
4992
4993	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4994	{
4995	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4996	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4997	cErrors++;
4998	}
4999
5000	/* skip not-present entries. */
5001	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
5002	continue;
5003
5004	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
5005
5006	/* match the physical addresses */
5007	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
5008
5009	# ifdef IN_RING3
5010	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
5011	if (RT_FAILURE(rc))
5012	{
5013	# if 0
5014	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5015	{
5016	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5017	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5018	cErrors++;
5019	}
5020	# endif
5021	}
5022	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
5023	{
5024	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5025	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5026	cErrors++;
5027	continue;
5028	}
5029	# endif
5030	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
5031	if (!pPhysPage)
5032	{
5033	# if 0 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
5034	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5035	{
5036	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5037	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5038	cErrors++;
5039	continue;
5040	}
5041	# endif
5042	if (SHW_PTE_IS_RW(PteDst))
5043	{
5044	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5045	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5046	cErrors++;
5047	}
5048	fIgnoreFlags \|= X86_PTE_RW;
5049	}
5050	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
5051	{
5052	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5053	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5054	cErrors++;
5055	continue;
5056	}
5057
5058	/* flags */
5059	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
5060	{
5061	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
5062	{
5063	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
5064	{
5065	if ( SHW_PTE_IS_RW(PteDst)
5066	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
5067	{
5068	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5069	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5070	cErrors++;
5071	continue;
5072	}
5073	fIgnoreFlags \|= X86_PTE_RW;
5074	}
5075	}
5076	else
5077	{
5078	if ( SHW_PTE_IS_P(PteDst)
5079	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage)
5080	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
5081	&& !PGM_PAGE_IS_MMIO(pPhysPage)
5082	# endif
5083	)
5084	{
5085	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5086	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5087	cErrors++;
5088	continue;
5089	}
5090	fIgnoreFlags \|= X86_PTE_P;
5091	}
5092	}
5093
5094	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
5095	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
5096	)
5097	{
5098	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
5099	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
5100	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5101	cErrors++;
5102	continue;
5103	}
5104	} /* for each PTE */
5105	}
5106	}
5107	/* not present */
5108
5109	} /* for each PDE */
5110
5111	} /* for each PDPTE */
5112
5113	} /* for each PML4E */
5114
5115	# ifdef DEBUG
5116	if (cErrors)
5117	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
5118	# endif
5119	# endif /* GST is in {32BIT, PAE, AMD64} */
5120	return cErrors;
5121	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
5122	}
5123	#endif /* VBOX_STRICT */
5124
5125
5126	/**
5127	* Sets up the CR3 for shadow paging
5128	*
5129	* @returns Strict VBox status code.
5130	* @retval VINF_SUCCESS.
5131	*
5132	* @param pVCpu The cross context virtual CPU structure.
5133	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
5134	* already applied.)
5135	*/
5136	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
5137	{
5138	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5139	int rc = VINF_SUCCESS;
5140
5141	/* Update guest paging info. */
5142	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5143	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
5144	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
5145
5146	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
5147	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5148
5149	# if PGM_GST_TYPE == PGM_TYPE_PAE
5150	if ( !pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped)
5151	\|\| pVCpu->pgm.s.GCPhysPaeCR3 != GCPhysCR3)
5152	# endif
5153	{
5154	/*
5155	* Map the page CR3 points at.
5156	*/
5157	RTHCPTR HCPtrGuestCR3;
5158	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
5159	if (RT_SUCCESS(rc))
5160	{
5161	# if PGM_GST_TYPE == PGM_TYPE_32BIT
5162	# ifdef IN_RING3
5163	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
5164	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
5165	# else
5166	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
5167	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
5168	# endif
5169
5170	# elif PGM_GST_TYPE == PGM_TYPE_PAE
5171	# ifdef IN_RING3
5172	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
5173	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
5174	# else
5175	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
5176	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
5177	# endif
5178
5179	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
5180	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5181	/*
5182	* When EPT is enabled by the nested-hypervisor and the nested-guest is in PAE mode,
5183	* the guest-CPU context would've already been updated with the 4 PAE PDPEs specified
5184	* in the virtual VMCS. The PDPEs can differ from those in guest memory referenced by
5185	* the translated nested-guest CR3. We -MUST- use the PDPEs provided in the virtual VMCS
5186	* rather than those in guest memory.
5187	*
5188	* See Intel spec. 26.3.2.4 "Loading Page-Directory-Pointer-Table Entries".
5189	*/
5190	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
5191	CPUMGetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5192	else
5193	#endif
5194	{
5195	/* Update CPUM with the PAE PDPEs referenced by CR3. */
5196	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
5197	CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5198	}
5199
5200	/*
5201	* Map the 4 PAE PDPEs.
5202	*/
5203	rc = PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
5204	if (RT_SUCCESS(rc))
5205	{
5206	# ifdef IN_RING3
5207	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
5208	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5209	# else
5210	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5211	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
5212	# endif
5213	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
5214	}
5215
5216	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
5217	# ifdef IN_RING3
5218	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
5219	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
5220	# else
5221	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
5222	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
5223	# endif
5224	# endif
5225	}
5226	else
5227	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
5228	}
5229	#endif
5230
5231	/*
5232	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
5233	*/
5234	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5235	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5236	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
5237	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
5238	&& PGM_GST_TYPE != PGM_TYPE_PROT))
5239
5240	Assert(!pVM->pgm.s.fNestedPaging);
5241	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5242
5243	/*
5244	* Update the shadow root page as well since that's not fixed.
5245	*/
5246	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5247	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
5248	PPGMPOOLPAGE pNewShwPageCR3;
5249
5250	PGM_LOCK_VOID(pVM);
5251
5252	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5253	if (pPool->cDirtyPages)
5254	pgmPoolResetDirtyPages(pVM);
5255	# endif
5256
5257	Assert(!(GCPhysCR3 >> (GUEST_PAGE_SHIFT + 32))); /** @todo what is this for? */
5258	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
5259	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
5260	AssertFatalRC(rc2);
5261
5262	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
5263	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
5264
5265	/* Set the current hypervisor CR3. */
5266	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
5267
5268	/* Clean up the old CR3 root. */
5269	if ( pOldShwPageCR3
5270	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
5271	{
5272	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
5273
5274	/* Mark the page as unlocked; allow flushing again. */
5275	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
5276
5277	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
5278	}
5279	PGM_UNLOCK(pVM);
5280	# else
5281	NOREF(GCPhysCR3);
5282	# endif
5283
5284	return rc;
5285	}
5286
5287	/**
5288	* Unmaps the shadow CR3.
5289	*
5290	* @returns VBox status, no specials.
5291	* @param pVCpu The cross context virtual CPU structure.
5292	*/
5293	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
5294	{
5295	LogFlow(("UnmapCR3\n"));
5296
5297	int rc = VINF_SUCCESS;
5298	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5299
5300	/*
5301	* Update guest paging info.
5302	*/
5303	#if PGM_GST_TYPE == PGM_TYPE_32BIT
5304	pVCpu->pgm.s.pGst32BitPdR3 = 0;
5305	pVCpu->pgm.s.pGst32BitPdR0 = 0;
5306
5307	#elif PGM_GST_TYPE == PGM_TYPE_PAE
5308	pVCpu->pgm.s.pGstPaePdptR3 = 0;
5309	pVCpu->pgm.s.pGstPaePdptR0 = 0;
5310	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
5311	{
5312	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
5313	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
5314	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
5315	}
5316
5317	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
5318	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
5319	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
5320
5321	#else /* prot/real mode stub */
5322	/* nothing to do */
5323	#endif
5324
5325	/*
5326	* PAE PDPEs (and CR3) might have been mapped via PGMGstMapPaePdpesAtCr3()
5327	* prior to switching to PAE in pfnMapCr3(), so we need to clear them here.
5328	*/
5329	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5330	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5331	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
5332
5333	/*
5334	* Update shadow paging info.
5335	*/
5336	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5337	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5338	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
5339	# if PGM_GST_TYPE != PGM_TYPE_REAL
5340	Assert(!pVM->pgm.s.fNestedPaging);
5341	# endif
5342	PGM_LOCK_VOID(pVM);
5343
5344	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
5345	{
5346	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5347
5348	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5349	if (pPool->cDirtyPages)
5350	pgmPoolResetDirtyPages(pVM);
5351	# endif
5352
5353	/* Mark the page as unlocked; allow flushing again. */
5354	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
5355
5356	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
5357	pVCpu->pgm.s.pShwPageCR3R3 = 0;
5358	pVCpu->pgm.s.pShwPageCR3R0 = 0;
5359	}
5360
5361	PGM_UNLOCK(pVM);
5362	#endif
5363
5364	return rc;
5365	}
5366

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 101002

Download in other formats: