PGMAllBth.h@ 60309

Last change on this file since 60309 was 58126, checked in by vboxsync, 9 years ago
VMM: Fixed almost all the Doxygen warnings.
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1	/* $Id: PGMAllBth.h 58126 2015-10-08 20:59:48Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2015 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	VBOXSTRICTRC rcStrict;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
182
183	# ifdef PGM_SYNC_N_PAGES
184	/*
185	* If the region is write protected and we got a page not present fault, then sync
186	* the pages. If the fault was caused by a read, then restart the instruction.
187	* In case of write access continue to the GC write handler.
188	*
189	* ASSUMES that there is only one handler per page or that they have similar write properties.
190	*/
191	if ( !(uErr & X86_TRAP_PF_P)
192	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
193	{
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# else
197	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
198	# endif
199	if ( RT_FAILURE(rcStrict)
200	\|\| !(uErr & X86_TRAP_PF_RW)
201	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
202	{
203	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
205	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
206	return rcStrict;
207	}
208	}
209	# endif
210	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
211	/*
212	* If the access was not thru a #PF(RSVD\|...) resync the page.
213	*/
214	if ( !(uErr & X86_TRAP_PF_RSVD)
215	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
216	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
217	&& pGstWalk->Core.fEffectiveRW
218	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
219	# endif
220	)
221	{
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# else
225	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
226	# endif
227	if ( RT_FAILURE(rcStrict)
228	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
229	{
230	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
233	return rcStrict;
234	}
235	}
236	# endif
237
238	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
239	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
240	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
241	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
242	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
244	else
245	{
246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
247	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
248	}
249
250	if (pCurType->CTX_SUFF(pfnPfHandler))
251	{
252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
253	void *pvUser = pCur->CTX_SUFF(pvUser);
254
255	STAM_PROFILE_START(&pCur->Stat, h);
256	if (pCur->hType != pPool->hAccessHandlerType)
257	{
258	pgmUnlock(pVM);
259	*pfLockTaken = false;
260	}
261
262	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
263
264	# ifdef VBOX_WITH_STATISTICS
265	pgmLock(pVM);
266	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
267	if (pCur)
268	STAM_PROFILE_STOP(&pCur->Stat, h);
269	pgmUnlock(pVM);
270	# endif
271	}
272	else
273	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
274
275	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
276	return rcStrict;
277	}
278	}
279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
280	else
281	{
282	# ifdef PGM_SYNC_N_PAGES
283	/*
284	* If the region is write protected and we got a page not present fault, then sync
285	* the pages. If the fault was caused by a read, then restart the instruction.
286	* In case of write access continue to the GC write handler.
287	*/
288	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
289	&& !(uErr & X86_TRAP_PF_P))
290	{
291	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
292	if ( RT_FAILURE(rcStrict)
293	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
294	\|\| !(uErr & X86_TRAP_PF_RW))
295	{
296	AssertRC(rcStrict);
297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
298	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
299	return rcStrict;
300	}
301	}
302	# endif
303	/*
304	* Ok, it's an virtual page access handler.
305	*
306	* Since it's faster to search by address, we'll do that first
307	* and then retry by GCPhys if that fails.
308	*/
309	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
310	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
311	* out of sync, because the page was changed without us noticing it (not-present -> present
312	* without invlpg or mov cr3, xxx).
313	*/
314	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
315	if (pCur)
316	{
317	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
318	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
319	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
320	\|\| !(uErr & X86_TRAP_PF_P)
321	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
322	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
323	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
324
325	if ( pvFault - pCur->Core.Key < pCur->cb
326	&& ( uErr & X86_TRAP_PF_RW
327	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
328	{
329	# ifdef IN_RC
330	STAM_PROFILE_START(&pCur->Stat, h);
331	RTGCPTR GCPtrStart = pCur->Core.Key;
332	void *pvUser = pCur->CTX_SUFF(pvUser);
333	pgmUnlock(pVM);
334	*pfLockTaken = false;
335
336	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
337	pvFault - GCPtrStart, pvUser);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rcStrict;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
361	if (pCur)
362	{
363	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
364	if ( uErr & X86_TRAP_PF_RW
365	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
366	{
367	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
368	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
369	# ifdef IN_RC
370	STAM_PROFILE_START(&pCur->Stat, h);
371	RTGCPTR GCPtrStart = pCur->Core.Key;
372	void *pvUser = pCur->CTX_SUFF(pvUser);
373	pgmUnlock(pVM);
374	*pfLockTaken = false;
375
376	RTGCPTR off = (iPage << PAGE_SHIFT)
377	+ (pvFault & PAGE_OFFSET_MASK)
378	- (GCPtrStart & PAGE_OFFSET_MASK);
379	Assert(off < pCur->cb);
380	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
381
382	# ifdef VBOX_WITH_STATISTICS
383	pgmLock(pVM);
384	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
385	if (pCur)
386	STAM_PROFILE_STOP(&pCur->Stat, h);
387	pgmUnlock(pVM);
388	# endif
389	# else
390	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
391	# endif
392	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
393	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
394	return rcStrict;
395	}
396	}
397	}
398	}
399	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
400
401	/*
402	* There is a handled area of the page, but this fault doesn't belong to it.
403	* We must emulate the instruction.
404	*
405	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
406	* we first check if this was a page-not-present fault for a page with only
407	* write access handlers. Restart the instruction if it wasn't a write access.
408	*/
409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
410
411	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
412	&& !(uErr & X86_TRAP_PF_P))
413	{
414	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
415	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# else
417	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	# endif
419	if ( RT_FAILURE(rcStrict)
420	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
421	\|\| !(uErr & X86_TRAP_PF_RW))
422	{
423	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
424	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rcStrict;
427	}
428	}
429
430	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
431	* It's writing to an unhandled part of the LDT page several million times.
432	*/
433	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
434	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
435	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
436	return rcStrict;
437	} /* if any kind of handler */
438
439
440	/**
441	* \#PF Handler for raw-mode guest execution.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	*
445	* @param pVCpu The cross context virtual CPU structure.
446	* @param uErr The trap error code.
447	* @param pRegFrame Trap register frame.
448	* @param pvFault The fault address.
449	* @param pfLockTaken PGM lock taken here or not (out)
450	*/
451	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
452	{
453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
454
455	*pfLockTaken = false;
456
457	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
459	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
460	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
461	int rc;
462
463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
464	/*
465	* Walk the guest page translation tables and check if it's a guest fault.
466	*/
467	GSTPTWALK GstWalk;
468	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
469	if (RT_FAILURE_NP(rc))
470	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
471
472	/* assert some GstWalk sanity. */
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
474	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
475	# endif
476	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
477	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
478	# endif
479	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
480	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
481	Assert(GstWalk.Core.fSucceeded);
482
483	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
484	{
485	if ( ( (uErr & X86_TRAP_PF_RW)
486	&& !GstWalk.Core.fEffectiveRW
487	&& ( (uErr & X86_TRAP_PF_US)
488	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
489	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
490	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
491	)
492	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
493	}
494
495	/*
496	* Set the accessed and dirty flags.
497	*/
498	# if PGM_GST_TYPE == PGM_TYPE_AMD64
499	GstWalk.Pml4e.u \|= X86_PML4E_A;
500	GstWalk.pPml4e->u \|= X86_PML4E_A;
501	GstWalk.Pdpe.u \|= X86_PDPE_A;
502	GstWalk.pPdpe->u \|= X86_PDPE_A;
503	# endif
504	if (GstWalk.Core.fBigPage)
505	{
506	Assert(GstWalk.Pde.b.u1Size);
507	if (uErr & X86_TRAP_PF_RW)
508	{
509	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
510	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	}
512	else
513	{
514	GstWalk.Pde.u \|= X86_PDE4M_A;
515	GstWalk.pPde->u \|= X86_PDE4M_A;
516	}
517	}
518	else
519	{
520	Assert(!GstWalk.Pde.b.u1Size);
521	GstWalk.Pde.u \|= X86_PDE_A;
522	GstWalk.pPde->u \|= X86_PDE_A;
523	if (uErr & X86_TRAP_PF_RW)
524	{
525	# ifdef VBOX_WITH_STATISTICS
526	if (!GstWalk.Pte.n.u1Dirty)
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
528	else
529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
530	# endif
531	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
532	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
533	}
534	else
535	{
536	GstWalk.Pte.u \|= X86_PTE_A;
537	GstWalk.pPte->u \|= X86_PTE_A;
538	}
539	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540	}
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
545	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546
547	/* Take the big lock now. */
548	*pfLockTaken = true;
549	pgmLock(pVM);
550
551	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
552	/*
553	* If it is a reserved bit fault we know that it is an MMIO (access
554	* handler) related fault and can skip some 200 lines of code.
555	*/
556	if (uErr & X86_TRAP_PF_RSVD)
557	{
558	Assert(uErr & X86_TRAP_PF_P);
559	PPGMPAGE pPage;
560	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
561	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
562	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
563	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
564	pfLockTaken, &GstWalk));
565	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
566	# else
567	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
568	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
569	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
570	pfLockTaken));
571	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
572	# endif
573	AssertRC(rc);
574	PGM_INVL_PG(pVCpu, pvFault);
575	return rc; /* Restart with the corrected entry. */
576	}
577	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
578
579	/*
580	* Fetch the guest PDE, PDPE and PML4E.
581	*/
582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
583	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
584	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
587	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PAE
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
591	# else
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
593	# endif
594	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
595
596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
597	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
598	PX86PDPAE pPDDst;
599	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
601	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
602	# else
603	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
604	# endif
605	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
606
607	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
608	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
609	PEPTPD pPDDst;
610	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
611	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
612	# endif
613	Assert(pPDDst);
614
615	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
616	/*
617	* Dirty page handling.
618	*
619	* If we successfully correct the write protection fault due to dirty bit
620	* tracking, then return immediately.
621	*/
622	if (uErr & X86_TRAP_PF_RW) /* write fault? */
623	{
624	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
626	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
627	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
628	{
629	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
630	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
631	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
632	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
633	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
634	return VINF_SUCCESS;
635	}
636	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
637	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
638	}
639
640	# if 0 /* rarely useful; leave for debugging. */
641	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
642	# endif
643	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
644
645	/*
646	* A common case is the not-present error caused by lazy page table syncing.
647	*
648	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
649	* here so we can safely assume that the shadow PT is present when calling
650	* SyncPage later.
651	*
652	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
653	* of mapping conflict and defer to SyncCR3 in R3.
654	* (Again, we do NOT support access handlers for non-present guest pages.)
655	*
656	*/
657	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
658	Assert(GstWalk.Pde.n.u1Present);
659	# endif
660	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
661	&& !pPDDst->a[iPDDst].n.u1Present)
662	{
663	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
665	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
667	# else
668	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
670	# endif
671	if (RT_SUCCESS(rc))
672	return rc;
673	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
674	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
675	return VINF_PGM_SYNC_CR3;
676	}
677
678	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
679	/*
680	* Check if this address is within any of our mappings.
681	*
682	* This is very fast and it's gonna save us a bit of effort below and prevent
683	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
684	* (BTW, it's impossible to have physical access handlers in a mapping.)
685	*/
686	if (pgmMapAreMappingsEnabled(pVM))
687	{
688	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
689	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
690	{
691	if (pvFault < pMapping->GCPtr)
692	break;
693	if (pvFault - pMapping->GCPtr < pMapping->cb)
694	{
695	/*
696	* The first thing we check is if we've got an undetected conflict.
697	*/
698	if (pgmMapAreMappingsFloating(pVM))
699	{
700	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
701	while (iPT-- > 0)
702	if (GstWalk.pPde[iPT].n.u1Present)
703	{
704	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
705	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
706	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
707	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
708	return VINF_PGM_SYNC_CR3;
709	}
710	}
711
712	/*
713	* Check if the fault address is in a virtual page access handler range.
714	*/
715	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
716	pvFault);
717	if ( pCur
718	&& pvFault - pCur->Core.Key < pCur->cb
719	&& uErr & X86_TRAP_PF_RW)
720	{
721	VBOXSTRICTRC rcStrict;
722	# ifdef IN_RC
723	STAM_PROFILE_START(&pCur->Stat, h);
724	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
725	void *pvUser = pCur->CTX_SUFF(pvUser);
726	pgmUnlock(pVM);
727	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
728	pvFault - pCur->Core.Key, pvUser);
729	pgmLock(pVM);
730	STAM_PROFILE_STOP(&pCur->Stat, h);
731	# else
732	AssertFailed();
733	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
734	# endif
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
736	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
737	return VBOXSTRICTRC_TODO(rcStrict);
738	}
739
740	/*
741	* Pretend we're not here and let the guest handle the trap.
742	*/
743	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
744	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
745	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
746	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
747	return VINF_EM_RAW_GUEST_TRAP;
748	}
749	}
750	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
751	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
752
753	/*
754	* Check if this fault address is flagged for special treatment,
755	* which means we'll have to figure out the physical address and
756	* check flags associated with it.
757	*
758	* ASSUME that we can limit any special access handling to pages
759	* in page tables which the guest believes to be present.
760	*/
761	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
762	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
763	# else
764	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
765	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
766	PPGMPAGE pPage;
767	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
768	if (RT_FAILURE(rc))
769	{
770	/*
771	* When the guest accesses invalid physical memory (e.g. probing
772	* of RAM or accessing a remapped MMIO range), then we'll fall
773	* back to the recompiler to emulate the instruction.
774	*/
775	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
776	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
777	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
778	return VINF_EM_RAW_EMULATE_INSTR;
779	}
780
781	/*
782	* Any handlers for this page?
783	*/
784	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
786	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
787	&GstWalk));
788	# else
789	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
790	# endif
791
792	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
793	if (uErr & X86_TRAP_PF_P)
794	{
795	/*
796	* The page isn't marked, but it might still be monitored by a virtual page access handler.
797	* (ASSUMES no temporary disabling of virtual handlers.)
798	*/
799	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
800	* we should correct both the shadow page table and physical memory flags, and not only check for
801	* accesses within the handler region but for access to pages with virtual handlers. */
802	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
803	if (pCur)
804	{
805	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
806	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
807	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
808	\|\| !(uErr & X86_TRAP_PF_P)
809	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
810	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
811	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
812
813	if ( pvFault - pCur->Core.Key < pCur->cb
814	&& ( uErr & X86_TRAP_PF_RW
815	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
816	{
817	VBOXSTRICTRC rcStrict;
818	# ifdef IN_RC
819	STAM_PROFILE_START(&pCur->Stat, h);
820	void *pvUser = pCur->CTX_SUFF(pvUser);
821	pgmUnlock(pVM);
822	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
823	pvFault - pCur->Core.Key, pvUser);
824	pgmLock(pVM);
825	STAM_PROFILE_STOP(&pCur->Stat, h);
826	# else
827	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
828	# endif
829	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
830	return VBOXSTRICTRC_TODO(rcStrict);
831	}
832	}
833	}
834	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
835
836	/*
837	* We are here only if page is present in Guest page tables and
838	* trap is not handled by our handlers.
839	*
840	* Check it for page out-of-sync situation.
841	*/
842	if (!(uErr & X86_TRAP_PF_P))
843	{
844	/*
845	* Page is not present in our page tables. Try to sync it!
846	*/
847	if (uErr & X86_TRAP_PF_US)
848	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
849	else /* supervisor */
850	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
851
852	if (PGM_PAGE_IS_BALLOONED(pPage))
853	{
854	/* Emulate reads from ballooned pages as they are not present in
855	our shadow page tables. (Required for e.g. Solaris guests; soft
856	ecc, random nr generator.) */
857	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
858	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
859	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
860	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
861	return rc;
862	}
863
864	# if defined(LOG_ENABLED) && !defined(IN_RING0)
865	RTGCPHYS GCPhys2;
866	uint64_t fPageGst2;
867	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
868	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
869	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
870	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
871	# else
872	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
873	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
874	# endif
875	# endif /* LOG_ENABLED */
876
877	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
878	if ( !GstWalk.Core.fEffectiveUS
879	&& CSAMIsEnabled(pVM)
880	&& CPUMGetGuestCPL(pVCpu) == 0)
881	{
882	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
883	if ( pvFault == (RTGCPTR)pRegFrame->eip
884	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
885	# ifdef CSAM_DETECT_NEW_CODE_PAGES
886	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
887	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
888	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
889	)
890	{
891	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
892	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
893	if (rc != VINF_SUCCESS)
894	{
895	/*
896	* CSAM needs to perform a job in ring 3.
897	*
898	* Sync the page before going to the host context; otherwise we'll end up in a loop if
899	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
900	*/
901	LogFlow(("CSAM ring 3 job\n"));
902	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
903	AssertRC(rc2);
904
905	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
906	return rc;
907	}
908	}
909	# ifdef CSAM_DETECT_NEW_CODE_PAGES
910	else if ( uErr == X86_TRAP_PF_RW
911	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
912	&& pRegFrame->ecx < 0x10000)
913	{
914	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
915	* to detect loading of new code pages.
916	*/
917
918	/*
919	* Decode the instruction.
920	*/
921	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
922	uint32_t cbOp;
923	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
924
925	/* For now we'll restrict this to rep movsw/d instructions */
926	if ( rc == VINF_SUCCESS
927	&& pDis->pCurInstr->opcode == OP_MOVSWD
928	&& (pDis->prefix & DISPREFIX_REP))
929	{
930	CSAMMarkPossibleCodePage(pVM, pvFault);
931	}
932	}
933	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
934
935	/*
936	* Mark this page as safe.
937	*/
938	/** @todo not correct for pages that contain both code and data!! */
939	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
940	CSAMMarkPage(pVM, pvFault, true);
941	}
942	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
943	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
944	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
945	# else
946	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
947	# endif
948	if (RT_SUCCESS(rc))
949	{
950	/* The page was successfully synced, return to the guest. */
951	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
952	return VINF_SUCCESS;
953	}
954	}
955	else /* uErr & X86_TRAP_PF_P: */
956	{
957	/*
958	* Write protected pages are made writable when the guest makes the
959	* first write to it. This happens for pages that are shared, write
960	* monitored or not yet allocated.
961	*
962	* We may also end up here when CR0.WP=0 in the guest.
963	*
964	* Also, a side effect of not flushing global PDEs are out of sync
965	* pages due to physical monitored regions, that are no longer valid.
966	* Assume for now it only applies to the read/write flag.
967	*/
968	if (uErr & X86_TRAP_PF_RW)
969	{
970	/*
971	* Check if it is a read-only page.
972	*/
973	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
974	{
975	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
976	Assert(!PGM_PAGE_IS_ZERO(pPage));
977	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
978	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
979
980	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
981	if (rc != VINF_SUCCESS)
982	{
983	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
984	return rc;
985	}
986	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
987	return VINF_EM_NO_MEMORY;
988	}
989
990	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
991	/*
992	* Check to see if we need to emulate the instruction if CR0.WP=0.
993	*/
994	if ( !GstWalk.Core.fEffectiveRW
995	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
996	&& CPUMGetGuestCPL(pVCpu) < 3)
997	{
998	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
999
1000	/*
1001	* The Netware WP0+RO+US hack.
1002	*
1003	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1004	* excessive write accesses to pages which are mapped with US=1 and RW=0
1005	* while WP=0. This causes a lot of exits and extremely slow execution.
1006	* To avoid trapping and emulating every write here, we change the shadow
1007	* page table entry to map it as US=0 and RW=1 until user mode tries to
1008	* access it again (see further below). We count these shadow page table
1009	* changes so we can avoid having to clear the page pool every time the WP
1010	* bit changes to 1 (see PGMCr0WpEnabled()).
1011	*/
1012	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1013	if ( GstWalk.Core.fEffectiveUS
1014	&& !GstWalk.Core.fEffectiveRW
1015	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1016	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1017	{
1018	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1019	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1020	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1021	{
1022	PGM_INVL_PG(pVCpu, pvFault);
1023	pVCpu->pgm.s.cNetwareWp0Hacks++;
1024	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1025	return rc;
1026	}
1027	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1028	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1029	}
1030	# endif
1031
1032	/* Interpret the access. */
1033	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1034	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1035	if (RT_SUCCESS(rc))
1036	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1037	else
1038	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1039	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1040	return rc;
1041	}
1042	# endif
1043	/// @todo count the above case; else
1044	if (uErr & X86_TRAP_PF_US)
1045	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1046	else /* supervisor */
1047	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1048
1049	/*
1050	* Sync the page.
1051	*
1052	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1053	* page is not present, which is not true in this case.
1054	*/
1055	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1056	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1057	# else
1058	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1059	# endif
1060	if (RT_SUCCESS(rc))
1061	{
1062	/*
1063	* Page was successfully synced, return to guest but invalidate
1064	* the TLB first as the page is very likely to be in it.
1065	*/
1066	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1067	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1068	# else
1069	PGM_INVL_PG(pVCpu, pvFault);
1070	# endif
1071	# ifdef VBOX_STRICT
1072	RTGCPHYS GCPhys2;
1073	uint64_t fPageGst;
1074	if (!pVM->pgm.s.fNestedPaging)
1075	{
1076	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1077	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1078	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1079	}
1080	uint64_t fPageShw;
1081	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1082	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1083	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1084	# endif /* VBOX_STRICT */
1085	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1086	return VINF_SUCCESS;
1087	}
1088	}
1089	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1090	/*
1091	* Check for Netware WP0+RO+US hack from above and undo it when user
1092	* mode accesses the page again.
1093	*/
1094	else if ( GstWalk.Core.fEffectiveUS
1095	&& !GstWalk.Core.fEffectiveRW
1096	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1097	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1098	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1099	&& CPUMGetGuestCPL(pVCpu) == 3
1100	&& pVM->cCpus == 1
1101	)
1102	{
1103	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1104	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1105	if (RT_SUCCESS(rc))
1106	{
1107	PGM_INVL_PG(pVCpu, pvFault);
1108	pVCpu->pgm.s.cNetwareWp0Hacks--;
1109	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1110	return VINF_SUCCESS;
1111	}
1112	}
1113	# endif /* PGM_WITH_PAGING */
1114
1115	/** @todo else: why are we here? */
1116
1117	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1118	/*
1119	* Check for VMM page flags vs. Guest page flags consistency.
1120	* Currently only for debug purposes.
1121	*/
1122	if (RT_SUCCESS(rc))
1123	{
1124	/* Get guest page flags. */
1125	uint64_t fPageGst;
1126	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1127	if (RT_SUCCESS(rc))
1128	{
1129	uint64_t fPageShw;
1130	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1131
1132	/*
1133	* Compare page flags.
1134	* Note: we have AVL, A, D bits desynced.
1135	*/
1136	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1137	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1138	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1139	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1140	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1141	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1142	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1143	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1144	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1145	}
1146	else
1147	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1148	}
1149	else
1150	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1151	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1152	}
1153
1154
1155	/*
1156	* If we get here it is because something failed above, i.e. most like guru
1157	* meditiation time.
1158	*/
1159	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1160	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1161	return rc;
1162
1163	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1164	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1165	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1166	return VERR_PGM_NOT_USED_IN_MODE;
1167	# endif
1168	}
1169	#endif /* !IN_RING3 */
1170
1171
1172	/**
1173	* Emulation of the invlpg instruction.
1174	*
1175	*
1176	* @returns VBox status code.
1177	*
1178	* @param pVCpu The cross context virtual CPU structure.
1179	* @param GCPtrPage Page to invalidate.
1180	*
1181	* @remark ASSUMES that the guest is updating before invalidating. This order
1182	* isn't required by the CPU, so this is speculative and could cause
1183	* trouble.
1184	* @remark No TLB shootdown is done on any other VCPU as we assume that
1185	* invlpg emulation is the only reason for calling this function.
1186	* (The guest has to shoot down TLB entries on other CPUs itself)
1187	* Currently true, but keep in mind!
1188	*
1189	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1190	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1191	*/
1192	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1193	{
1194	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1195	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1196	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1197	int rc;
1198	PVM pVM = pVCpu->CTX_SUFF(pVM);
1199	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1200
1201	PGM_LOCK_ASSERT_OWNER(pVM);
1202
1203	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1204
1205	/*
1206	* Get the shadow PD entry and skip out if this PD isn't present.
1207	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1208	*/
1209	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1210	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1211	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1212
1213	/* Fetch the pgm pool shadow descriptor. */
1214	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1215	Assert(pShwPde);
1216
1217	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1218	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1219	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1220
1221	/* If the shadow PDPE isn't present, then skip the invalidate. */
1222	if (!pPdptDst->a[iPdpt].n.u1Present)
1223	{
1224	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1225	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1226	PGM_INVL_PG(pVCpu, GCPtrPage);
1227	return VINF_SUCCESS;
1228	}
1229
1230	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1231	PPGMPOOLPAGE pShwPde = NULL;
1232	PX86PDPAE pPDDst;
1233
1234	/* Fetch the pgm pool shadow descriptor. */
1235	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1236	AssertRCSuccessReturn(rc, rc);
1237	Assert(pShwPde);
1238
1239	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1240	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1241
1242	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1243	/* PML4 */
1244	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1245	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1246	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1247	PX86PDPAE pPDDst;
1248	PX86PDPT pPdptDst;
1249	PX86PML4E pPml4eDst;
1250	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1251	if (rc != VINF_SUCCESS)
1252	{
1253	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1254	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1255	PGM_INVL_PG(pVCpu, GCPtrPage);
1256	return VINF_SUCCESS;
1257	}
1258	Assert(pPDDst);
1259
1260	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1261	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1262
1263	if (!pPdpeDst->n.u1Present)
1264	{
1265	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1266	PGM_INVL_PG(pVCpu, GCPtrPage);
1267	return VINF_SUCCESS;
1268	}
1269
1270	/* Fetch the pgm pool shadow descriptor. */
1271	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1272	Assert(pShwPde);
1273
1274	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1275
1276	const SHWPDE PdeDst = *pPdeDst;
1277	if (!PdeDst.n.u1Present)
1278	{
1279	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1280	PGM_INVL_PG(pVCpu, GCPtrPage);
1281	return VINF_SUCCESS;
1282	}
1283
1284	/*
1285	* Get the guest PD entry and calc big page.
1286	*/
1287	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1288	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1289	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1290	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1291	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1292	unsigned iPDSrc = 0;
1293	# if PGM_GST_TYPE == PGM_TYPE_PAE
1294	X86PDPE PdpeSrcIgn;
1295	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1296	# else /* AMD64 */
1297	PX86PML4E pPml4eSrcIgn;
1298	X86PDPE PdpeSrcIgn;
1299	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1300	# endif
1301	GSTPDE PdeSrc;
1302
1303	if (pPDSrc)
1304	PdeSrc = pPDSrc->a[iPDSrc];
1305	else
1306	PdeSrc.u = 0;
1307	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1308	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1309
1310	# ifdef IN_RING3
1311	/*
1312	* If a CR3 Sync is pending we may ignore the invalidate page operation
1313	* depending on the kind of sync and if it's a global page or not.
1314	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1315	*/
1316	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1317	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1318	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1319	&& fIsBigPage
1320	&& PdeSrc.b.u1Global
1321	)
1322	)
1323	# else
1324	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1325	# endif
1326	{
1327	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1328	return VINF_SUCCESS;
1329	}
1330	# endif /* IN_RING3 */
1331
1332	/*
1333	* Deal with the Guest PDE.
1334	*/
1335	rc = VINF_SUCCESS;
1336	if (PdeSrc.n.u1Present)
1337	{
1338	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1339	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1340	# ifndef PGM_WITHOUT_MAPPING
1341	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1342	{
1343	/*
1344	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1345	*/
1346	Assert(pgmMapAreMappingsEnabled(pVM));
1347	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1348	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1349	}
1350	else
1351	# endif /* !PGM_WITHOUT_MAPPING */
1352	if (!fIsBigPage)
1353	{
1354	/*
1355	* 4KB - page.
1356	*/
1357	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1358	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1359
1360	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1361	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1362	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1363	# endif
1364	if (pShwPage->GCPhys == GCPhys)
1365	{
1366	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1367	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1368
1369	PGSTPT pPTSrc;
1370	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1371	if (RT_SUCCESS(rc))
1372	{
1373	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1374	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1375	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1376	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1377	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1378	GCPtrPage, PteSrc.n.u1Present,
1379	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1380	PteSrc.n.u1User & PdeSrc.n.u1User,
1381	(uint64_t)PteSrc.u,
1382	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1383	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1384	}
1385	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1386	PGM_INVL_PG(pVCpu, GCPtrPage);
1387	}
1388	else
1389	{
1390	/*
1391	* The page table address changed.
1392	*/
1393	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1394	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1395	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1396	ASMAtomicWriteSize(pPdeDst, 0);
1397	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1398	PGM_INVL_VCPU_TLBS(pVCpu);
1399	}
1400	}
1401	else
1402	{
1403	/*
1404	* 2/4MB - page.
1405	*/
1406	/* Before freeing the page, check if anything really changed. */
1407	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1408	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1409	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1410	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1411	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1412	# endif
1413	if ( pShwPage->GCPhys == GCPhys
1414	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1415	{
1416	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1417	/** @todo This test is wrong as it cannot check the G bit!
1418	* FIXME */
1419	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1420	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1421	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1422	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1423	{
1424	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1426	return VINF_SUCCESS;
1427	}
1428	}
1429
1430	/*
1431	* Ok, the page table is present and it's been changed in the guest.
1432	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1433	* We could do this for some flushes in GC too, but we need an algorithm for
1434	* deciding which 4MB pages containing code likely to be executed very soon.
1435	*/
1436	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1437	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1438	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1439	ASMAtomicWriteSize(pPdeDst, 0);
1440	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1441	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1442	}
1443	}
1444	else
1445	{
1446	/*
1447	* Page directory is not present, mark shadow PDE not present.
1448	*/
1449	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1450	{
1451	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1452	ASMAtomicWriteSize(pPdeDst, 0);
1453	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1454	PGM_INVL_PG(pVCpu, GCPtrPage);
1455	}
1456	else
1457	{
1458	Assert(pgmMapAreMappingsEnabled(pVM));
1459	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1460	}
1461	}
1462	return rc;
1463
1464	#else /* guest real and protected mode */
1465	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1466	NOREF(pVCpu); NOREF(GCPtrPage);
1467	return VINF_SUCCESS;
1468	#endif
1469	}
1470
1471
1472	/**
1473	* Update the tracking of shadowed pages.
1474	*
1475	* @param pVCpu The cross context virtual CPU structure.
1476	* @param pShwPage The shadow page.
1477	* @param HCPhys The physical page we is being dereferenced.
1478	* @param iPte Shadow PTE index
1479	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1480	*/
1481	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1482	RTGCPHYS GCPhysPage)
1483	{
1484	PVM pVM = pVCpu->CTX_SUFF(pVM);
1485
1486	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1487	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1488	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1489
1490	/* Use the hint we retrieved from the cached guest PT. */
1491	if (pShwPage->fDirty)
1492	{
1493	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1494
1495	Assert(pShwPage->cPresent);
1496	Assert(pPool->cPresent);
1497	pShwPage->cPresent--;
1498	pPool->cPresent--;
1499
1500	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1501	AssertRelease(pPhysPage);
1502	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1503	return;
1504	}
1505	# else
1506	NOREF(GCPhysPage);
1507	# endif
1508
1509	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1510	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1511
1512	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1513	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1514	* 2. write protect all shadowed pages. I.e. implement caching.
1515	*/
1516	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1517
1518	/*
1519	* Find the guest address.
1520	*/
1521	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1522	pRam;
1523	pRam = pRam->CTX_SUFF(pNext))
1524	{
1525	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1526	while (iPage-- > 0)
1527	{
1528	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1529	{
1530	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1531
1532	Assert(pShwPage->cPresent);
1533	Assert(pPool->cPresent);
1534	pShwPage->cPresent--;
1535	pPool->cPresent--;
1536
1537	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1538	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1539	return;
1540	}
1541	}
1542	}
1543
1544	for (;;)
1545	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1546	}
1547
1548
1549	/**
1550	* Update the tracking of shadowed pages.
1551	*
1552	* @param pVCpu The cross context virtual CPU structure.
1553	* @param pShwPage The shadow page.
1554	* @param u16 The top 16-bit of the pPage->HCPhys.
1555	* @param pPage Pointer to the guest page. this will be modified.
1556	* @param iPTDst The index into the shadow table.
1557	*/
1558	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1559	{
1560	PVM pVM = pVCpu->CTX_SUFF(pVM);
1561
1562	/*
1563	* Just deal with the simple first time here.
1564	*/
1565	if (!u16)
1566	{
1567	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1568	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1569	/* Save the page table index. */
1570	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1571	}
1572	else
1573	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1574
1575	/* write back */
1576	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1577	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1578
1579	/* update statistics. */
1580	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1581	pShwPage->cPresent++;
1582	if (pShwPage->iFirstPresent > iPTDst)
1583	pShwPage->iFirstPresent = iPTDst;
1584	}
1585
1586
1587	/**
1588	* Modifies a shadow PTE to account for access handlers.
1589	*
1590	* @param pVM The cross context VM structure.
1591	* @param pPage The page in question.
1592	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1593	* A (accessed) bit so it can be emulated correctly.
1594	* @param pPteDst The shadow PTE (output). This is temporary storage and
1595	* does not need to be set atomically.
1596	*/
1597	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1598	{
1599	NOREF(pVM);
1600	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1601	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1602	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1603	{
1604	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1605	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1606	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1607	pPteDst->n.u1Present = 1;
1608	pPteDst->n.u1Execute = 1;
1609	pPteDst->n.u1IgnorePAT = 1;
1610	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1611	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1612	#else
1613	if (fPteSrc & X86_PTE_A)
1614	{
1615	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1616	SHW_PTE_SET_RO(*pPteDst);
1617	}
1618	else
1619	SHW_PTE_SET(*pPteDst, 0);
1620	#endif
1621	}
1622	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1623	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1624	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1625	&& ( BTH_IS_NP_ACTIVE(pVM)
1626	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1627	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1628	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1629	# endif
1630	)
1631	{
1632	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1633	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1634	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1635	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1636	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1637	pPteDst->n.u1Present = 0;
1638	pPteDst->n.u1Write = 1;
1639	pPteDst->n.u1Execute = 0;
1640	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1641	pPteDst->n.u3EMT = 7;
1642	# else
1643	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1644	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1645	# endif
1646	}
1647	# endif
1648	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1649	else
1650	{
1651	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1652	SHW_PTE_SET(*pPteDst, 0);
1653	}
1654	/** @todo count these kinds of entries. */
1655	}
1656
1657
1658	/**
1659	* Creates a 4K shadow page for a guest page.
1660	*
1661	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1662	* physical address. The PdeSrc argument only the flags are used. No page
1663	* structured will be mapped in this function.
1664	*
1665	* @param pVCpu The cross context virtual CPU structure.
1666	* @param pPteDst Destination page table entry.
1667	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1668	* Can safely assume that only the flags are being used.
1669	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1670	* @param pShwPage Pointer to the shadow page.
1671	* @param iPTDst The index into the shadow table.
1672	*
1673	* @remark Not used for 2/4MB pages!
1674	*/
1675	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1676	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1677	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1678	#else
1679	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1680	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1681	#endif
1682	{
1683	PVM pVM = pVCpu->CTX_SUFF(pVM);
1684	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1685
1686	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1687	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1688	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1689
1690	if (pShwPage->fDirty)
1691	{
1692	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1693	PGSTPT pGstPT;
1694
1695	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1696	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1697	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1698	pGstPT->a[iPTDst].u = PteSrc.u;
1699	}
1700	#else
1701	Assert(!pShwPage->fDirty);
1702	#endif
1703
1704	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1705	if ( PteSrc.n.u1Present
1706	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1707	#endif
1708	{
1709	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1710	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1711	# endif
1712	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1713
1714	/*
1715	* Find the ram range.
1716	*/
1717	PPGMPAGE pPage;
1718	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1719	if (RT_SUCCESS(rc))
1720	{
1721	/* Ignore ballooned pages.
1722	Don't return errors or use a fatal assert here as part of a
1723	shadow sync range might included ballooned pages. */
1724	if (PGM_PAGE_IS_BALLOONED(pPage))
1725	{
1726	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1727	return;
1728	}
1729
1730	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1731	/* Make the page writable if necessary. */
1732	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1733	&& ( PGM_PAGE_IS_ZERO(pPage)
1734	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1735	\|\| ( PteSrc.n.u1Write
1736	# else
1737	\|\| ( 1
1738	# endif
1739	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1740	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1741	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1742	# endif
1743	# ifdef VBOX_WITH_PAGE_SHARING
1744	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1745	# endif
1746	)
1747	)
1748	)
1749	{
1750	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1751	AssertRC(rc);
1752	}
1753	#endif
1754
1755	/*
1756	* Make page table entry.
1757	*/
1758	SHWPTE PteDst;
1759	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1760	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1761	# else
1762	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1763	# endif
1764	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1765	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1766	else
1767	{
1768	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1769	/*
1770	* If the page or page directory entry is not marked accessed,
1771	* we mark the page not present.
1772	*/
1773	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1774	{
1775	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1776	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1777	SHW_PTE_SET(PteDst, 0);
1778	}
1779	/*
1780	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1781	* when the page is modified.
1782	*/
1783	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1784	{
1785	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1786	SHW_PTE_SET(PteDst,
1787	fGstShwPteFlags
1788	\| PGM_PAGE_GET_HCPHYS(pPage)
1789	\| PGM_PTFLAGS_TRACK_DIRTY);
1790	SHW_PTE_SET_RO(PteDst);
1791	}
1792	else
1793	#endif
1794	{
1795	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1796	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1797	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1798	PteDst.n.u1Present = 1;
1799	PteDst.n.u1Write = 1;
1800	PteDst.n.u1Execute = 1;
1801	PteDst.n.u1IgnorePAT = 1;
1802	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1803	/* PteDst.n.u1Size = 0 */
1804	#else
1805	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1806	#endif
1807	}
1808
1809	/*
1810	* Make sure only allocated pages are mapped writable.
1811	*/
1812	if ( SHW_PTE_IS_P_RW(PteDst)
1813	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1814	{
1815	/* Still applies to shared pages. */
1816	Assert(!PGM_PAGE_IS_ZERO(pPage));
1817	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1818	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1819	}
1820	}
1821
1822	/*
1823	* Keep user track up to date.
1824	*/
1825	if (SHW_PTE_IS_P(PteDst))
1826	{
1827	if (!SHW_PTE_IS_P(*pPteDst))
1828	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1829	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1830	{
1831	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1832	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1833	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1834	}
1835	}
1836	else if (SHW_PTE_IS_P(*pPteDst))
1837	{
1838	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1839	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1840	}
1841
1842	/*
1843	* Update statistics and commit the entry.
1844	*/
1845	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1846	if (!PteSrc.n.u1Global)
1847	pShwPage->fSeenNonGlobal = true;
1848	#endif
1849	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1850	return;
1851	}
1852
1853	/** @todo count these three different kinds. */
1854	Log2(("SyncPageWorker: invalid address in Pte\n"));
1855	}
1856	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1857	else if (!PteSrc.n.u1Present)
1858	Log2(("SyncPageWorker: page not present in Pte\n"));
1859	else
1860	Log2(("SyncPageWorker: invalid Pte\n"));
1861	#endif
1862
1863	/*
1864	* The page is not present or the PTE is bad. Replace the shadow PTE by
1865	* an empty entry, making sure to keep the user tracking up to date.
1866	*/
1867	if (SHW_PTE_IS_P(*pPteDst))
1868	{
1869	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1870	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1871	}
1872	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1873	}
1874
1875
1876	/**
1877	* Syncs a guest OS page.
1878	*
1879	* There are no conflicts at this point, neither is there any need for
1880	* page table allocations.
1881	*
1882	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1883	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1884	*
1885	* @returns VBox status code.
1886	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1887	* @param pVCpu The cross context virtual CPU structure.
1888	* @param PdeSrc Page directory entry of the guest.
1889	* @param GCPtrPage Guest context page address.
1890	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1891	* @param uErr Fault error (X86_TRAP_PF_*).
1892	*/
1893	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1894	{
1895	PVM pVM = pVCpu->CTX_SUFF(pVM);
1896	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1897	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1898
1899	PGM_LOCK_ASSERT_OWNER(pVM);
1900
1901	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1902	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1903	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1904	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1905	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1906
1907	/*
1908	* Assert preconditions.
1909	*/
1910	Assert(PdeSrc.n.u1Present);
1911	Assert(cPages);
1912	# if 0 /* rarely useful; leave for debugging. */
1913	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1914	# endif
1915
1916	/*
1917	* Get the shadow PDE, find the shadow page table in the pool.
1918	*/
1919	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1920	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1921	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1922
1923	/* Fetch the pgm pool shadow descriptor. */
1924	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1925	Assert(pShwPde);
1926
1927	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1928	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1929	PPGMPOOLPAGE pShwPde = NULL;
1930	PX86PDPAE pPDDst;
1931
1932	/* Fetch the pgm pool shadow descriptor. */
1933	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1934	AssertRCSuccessReturn(rc2, rc2);
1935	Assert(pShwPde);
1936
1937	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1938	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1939
1940	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1941	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1942	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1943	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1944	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1945
1946	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1947	AssertRCSuccessReturn(rc2, rc2);
1948	Assert(pPDDst && pPdptDst);
1949	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1950	# endif
1951	SHWPDE PdeDst = *pPdeDst;
1952
1953	/*
1954	* - In the guest SMP case we could have blocked while another VCPU reused
1955	* this page table.
1956	* - With W7-64 we may also take this path when the A bit is cleared on
1957	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1958	* relevant TLB entries. If we're write monitoring any page mapped by
1959	* the modified entry, we may end up here with a "stale" TLB entry.
1960	*/
1961	if (!PdeDst.n.u1Present)
1962	{
1963	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1964	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1965	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1966	if (uErr & X86_TRAP_PF_P)
1967	PGM_INVL_PG(pVCpu, GCPtrPage);
1968	return VINF_SUCCESS; /* force the instruction to be executed again. */
1969	}
1970
1971	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1972	Assert(pShwPage);
1973
1974	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1975	/* Fetch the pgm pool shadow descriptor. */
1976	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1977	Assert(pShwPde);
1978	# endif
1979
1980	/*
1981	* Check that the page is present and that the shadow PDE isn't out of sync.
1982	*/
1983	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1984	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1985	RTGCPHYS GCPhys;
1986	if (!fBigPage)
1987	{
1988	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1989	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1990	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1991	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1992	# endif
1993	}
1994	else
1995	{
1996	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1997	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1998	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1999	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2000	# endif
2001	}
2002	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2003	if ( fPdeValid
2004	&& pShwPage->GCPhys == GCPhys
2005	&& PdeSrc.n.u1Present
2006	&& PdeSrc.n.u1User == PdeDst.n.u1User
2007	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2008	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2009	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2010	# endif
2011	)
2012	{
2013	/*
2014	* Check that the PDE is marked accessed already.
2015	* Since we set the accessed bit before getting here on a #PF, this
2016	* check is only meant for dealing with non-#PF'ing paths.
2017	*/
2018	if (PdeSrc.n.u1Accessed)
2019	{
2020	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2021	if (!fBigPage)
2022	{
2023	/*
2024	* 4KB Page - Map the guest page table.
2025	*/
2026	PGSTPT pPTSrc;
2027	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2028	if (RT_SUCCESS(rc))
2029	{
2030	# ifdef PGM_SYNC_N_PAGES
2031	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2032	if ( cPages > 1
2033	&& !(uErr & X86_TRAP_PF_P)
2034	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2035	{
2036	/*
2037	* This code path is currently only taken when the caller is PGMTrap0eHandler
2038	* for non-present pages!
2039	*
2040	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2041	* deal with locality.
2042	*/
2043	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2044	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2045	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2046	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2047	# else
2048	const unsigned offPTSrc = 0;
2049	# endif
2050	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2051	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2052	iPTDst = 0;
2053	else
2054	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2055
2056	for (; iPTDst < iPTDstEnd; iPTDst++)
2057	{
2058	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2059
2060	if ( pPteSrc->n.u1Present
2061	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2062	{
2063	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2064	NOREF(GCPtrCurPage);
2065	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2066	/*
2067	* Assuming kernel code will be marked as supervisor - and not as user level
2068	* and executed using a conforming code selector - And marked as readonly.
2069	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2070	*/
2071	PPGMPAGE pPage;
2072	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2073	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2074	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2075	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2076	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2077	)
2078	# endif /* else: CSAM not active */
2079	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2080	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2081	GCPtrCurPage, pPteSrc->n.u1Present,
2082	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2083	pPteSrc->n.u1User & PdeSrc.n.u1User,
2084	(uint64_t)pPteSrc->u,
2085	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2086	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2087	}
2088	}
2089	}
2090	else
2091	# endif /* PGM_SYNC_N_PAGES */
2092	{
2093	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2094	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2095	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2096	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2097	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2098	GCPtrPage, PteSrc.n.u1Present,
2099	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2100	PteSrc.n.u1User & PdeSrc.n.u1User,
2101	(uint64_t)PteSrc.u,
2102	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2103	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2104	}
2105	}
2106	else /* MMIO or invalid page: emulated in #PF handler. */
2107	{
2108	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2109	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2110	}
2111	}
2112	else
2113	{
2114	/*
2115	* 4/2MB page - lazy syncing shadow 4K pages.
2116	* (There are many causes of getting here, it's no longer only CSAM.)
2117	*/
2118	/* Calculate the GC physical address of this 4KB shadow page. */
2119	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2120	/* Find ram range. */
2121	PPGMPAGE pPage;
2122	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2123	if (RT_SUCCESS(rc))
2124	{
2125	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2126
2127	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2128	/* Try to make the page writable if necessary. */
2129	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2130	&& ( PGM_PAGE_IS_ZERO(pPage)
2131	\|\| ( PdeSrc.n.u1Write
2132	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2133	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2134	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2135	# endif
2136	# ifdef VBOX_WITH_PAGE_SHARING
2137	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2138	# endif
2139	)
2140	)
2141	)
2142	{
2143	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2144	AssertRC(rc);
2145	}
2146	# endif
2147
2148	/*
2149	* Make shadow PTE entry.
2150	*/
2151	SHWPTE PteDst;
2152	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2153	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2154	else
2155	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2156
2157	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2158	if ( SHW_PTE_IS_P(PteDst)
2159	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2160	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2161
2162	/* Make sure only allocated pages are mapped writable. */
2163	if ( SHW_PTE_IS_P_RW(PteDst)
2164	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2165	{
2166	/* Still applies to shared pages. */
2167	Assert(!PGM_PAGE_IS_ZERO(pPage));
2168	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2169	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2170	}
2171
2172	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2173
2174	/*
2175	* If the page is not flagged as dirty and is writable, then make it read-only
2176	* at PD level, so we can set the dirty bit when the page is modified.
2177	*
2178	* ASSUMES that page access handlers are implemented on page table entry level.
2179	* Thus we will first catch the dirty access and set PDE.D and restart. If
2180	* there is an access handler, we'll trap again and let it work on the problem.
2181	*/
2182	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2183	* As for invlpg, it simply frees the whole shadow PT.
2184	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2185	if ( !PdeSrc.b.u1Dirty
2186	&& PdeSrc.b.u1Write)
2187	{
2188	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2189	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2190	PdeDst.n.u1Write = 0;
2191	}
2192	else
2193	{
2194	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2195	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2196	}
2197	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2198	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2199	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2200	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2201	}
2202	else
2203	{
2204	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2205	/** @todo must wipe the shadow page table entry in this
2206	* case. */
2207	}
2208	}
2209	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2210	return VINF_SUCCESS;
2211	}
2212
2213	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2214	}
2215	else if (fPdeValid)
2216	{
2217	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2218	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2219	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2220	}
2221	else
2222	{
2223	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2224	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2225	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2226	}
2227
2228	/*
2229	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2230	* Yea, I'm lazy.
2231	*/
2232	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2233	ASMAtomicWriteSize(pPdeDst, 0);
2234
2235	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2236	PGM_INVL_VCPU_TLBS(pVCpu);
2237	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2238
2239
2240	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2241	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2242	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2243	&& !defined(IN_RC)
2244	NOREF(PdeSrc);
2245
2246	# ifdef PGM_SYNC_N_PAGES
2247	/*
2248	* Get the shadow PDE, find the shadow page table in the pool.
2249	*/
2250	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2251	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2252
2253	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2254	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2255
2256	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2257	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2258	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2259	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2260	X86PDEPAE PdeDst;
2261	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2262
2263	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2264	AssertRCSuccessReturn(rc, rc);
2265	Assert(pPDDst && pPdptDst);
2266	PdeDst = pPDDst->a[iPDDst];
2267	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2268	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2269	PEPTPD pPDDst;
2270	EPTPDE PdeDst;
2271
2272	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2273	if (rc != VINF_SUCCESS)
2274	{
2275	AssertRC(rc);
2276	return rc;
2277	}
2278	Assert(pPDDst);
2279	PdeDst = pPDDst->a[iPDDst];
2280	# endif
2281	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2282	if (!PdeDst.n.u1Present)
2283	{
2284	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2285	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2286	return VINF_SUCCESS; /* force the instruction to be executed again. */
2287	}
2288
2289	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2290	if (PdeDst.n.u1Size)
2291	{
2292	Assert(pVM->pgm.s.fNestedPaging);
2293	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2294	return VINF_SUCCESS;
2295	}
2296
2297	/* Mask away the page offset. */
2298	GCPtrPage &= ~((RTGCPTR)0xfff);
2299
2300	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2301	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2302
2303	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2304	if ( cPages > 1
2305	&& !(uErr & X86_TRAP_PF_P)
2306	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2307	{
2308	/*
2309	* This code path is currently only taken when the caller is PGMTrap0eHandler
2310	* for non-present pages!
2311	*
2312	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2313	* deal with locality.
2314	*/
2315	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2316	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2317	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2318	iPTDst = 0;
2319	else
2320	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2321	for (; iPTDst < iPTDstEnd; iPTDst++)
2322	{
2323	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2324	{
2325	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2326	\| (iPTDst << PAGE_SHIFT));
2327
2328	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2329	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2330	GCPtrCurPage,
2331	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2332	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2333
2334	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2335	break;
2336	}
2337	else
2338	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2339	}
2340	}
2341	else
2342	# endif /* PGM_SYNC_N_PAGES */
2343	{
2344	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2345	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2346	\| (iPTDst << PAGE_SHIFT));
2347
2348	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2349
2350	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2351	GCPtrPage,
2352	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2353	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2354	}
2355	return VINF_SUCCESS;
2356
2357	#else
2358	NOREF(PdeSrc);
2359	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2360	return VERR_PGM_NOT_USED_IN_MODE;
2361	#endif
2362	}
2363
2364
2365	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2366
2367	/**
2368	* CheckPageFault helper for returning a page fault indicating a non-present
2369	* (NP) entry in the page translation structures.
2370	*
2371	* @returns VINF_EM_RAW_GUEST_TRAP.
2372	* @param pVCpu The cross context virtual CPU structure.
2373	* @param uErr The error code of the shadow fault. Corrections to
2374	* TRPM's copy will be made if necessary.
2375	* @param GCPtrPage For logging.
2376	* @param uPageFaultLevel For logging.
2377	*/
2378	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2379	{
2380	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2381	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2382	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2383	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2384	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2385
2386	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2387	return VINF_EM_RAW_GUEST_TRAP;
2388	}
2389
2390
2391	/**
2392	* CheckPageFault helper for returning a page fault indicating a reserved bit
2393	* (RSVD) error in the page translation structures.
2394	*
2395	* @returns VINF_EM_RAW_GUEST_TRAP.
2396	* @param pVCpu The cross context virtual CPU structure.
2397	* @param uErr The error code of the shadow fault. Corrections to
2398	* TRPM's copy will be made if necessary.
2399	* @param GCPtrPage For logging.
2400	* @param uPageFaultLevel For logging.
2401	*/
2402	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2403	{
2404	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2405	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2406	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2407
2408	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2409	return VINF_EM_RAW_GUEST_TRAP;
2410	}
2411
2412
2413	/**
2414	* CheckPageFault helper for returning a page protection fault (P).
2415	*
2416	* @returns VINF_EM_RAW_GUEST_TRAP.
2417	* @param pVCpu The cross context virtual CPU structure.
2418	* @param uErr The error code of the shadow fault. Corrections to
2419	* TRPM's copy will be made if necessary.
2420	* @param GCPtrPage For logging.
2421	* @param uPageFaultLevel For logging.
2422	*/
2423	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2424	{
2425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2426	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2427	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2428	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2429
2430	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2431	return VINF_EM_RAW_GUEST_TRAP;
2432	}
2433
2434
2435	/**
2436	* Handle dirty bit tracking faults.
2437	*
2438	* @returns VBox status code.
2439	* @param pVCpu The cross context virtual CPU structure.
2440	* @param uErr Page fault error code.
2441	* @param pPdeSrc Guest page directory entry.
2442	* @param pPdeDst Shadow page directory entry.
2443	* @param GCPtrPage Guest context page address.
2444	*/
2445	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2446	RTGCPTR GCPtrPage)
2447	{
2448	PVM pVM = pVCpu->CTX_SUFF(pVM);
2449	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2450	NOREF(uErr);
2451
2452	PGM_LOCK_ASSERT_OWNER(pVM);
2453
2454	/*
2455	* Handle big page.
2456	*/
2457	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2458	{
2459	if ( pPdeDst->n.u1Present
2460	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2461	{
2462	SHWPDE PdeDst = *pPdeDst;
2463
2464	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2465	Assert(pPdeSrc->b.u1Write);
2466
2467	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2468	* fault again and take this path to only invalidate the entry (see below).
2469	*/
2470	PdeDst.n.u1Write = 1;
2471	PdeDst.n.u1Accessed = 1;
2472	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2473	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2474	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2475	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2476	}
2477
2478	# ifdef IN_RING0
2479	/* Check for stale TLB entry; only applies to the SMP guest case. */
2480	if ( pVM->cCpus > 1
2481	&& pPdeDst->n.u1Write
2482	&& pPdeDst->n.u1Accessed)
2483	{
2484	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2485	if (pShwPage)
2486	{
2487	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2488	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2489	if (SHW_PTE_IS_P_RW(*pPteDst))
2490	{
2491	/* Stale TLB entry. */
2492	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2493	PGM_INVL_PG(pVCpu, GCPtrPage);
2494	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2495	}
2496	}
2497	}
2498	# endif /* IN_RING0 */
2499	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2500	}
2501
2502	/*
2503	* Map the guest page table.
2504	*/
2505	PGSTPT pPTSrc;
2506	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2507	if (RT_FAILURE(rc))
2508	{
2509	AssertRC(rc);
2510	return rc;
2511	}
2512
2513	if (pPdeDst->n.u1Present)
2514	{
2515	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2516	const GSTPTE PteSrc = *pPteSrc;
2517
2518	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2519	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2520	* Our individual shadow handlers will provide more information and force a fatal exit.
2521	*/
2522	if ( !HMIsEnabled(pVM)
2523	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2524	{
2525	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2526	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2527	}
2528	#endif
2529	/*
2530	* Map shadow page table.
2531	*/
2532	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2533	if (pShwPage)
2534	{
2535	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2536	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2537	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2538	{
2539	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2540	{
2541	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2542	SHWPTE PteDst = *pPteDst;
2543
2544	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2545	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2546
2547	Assert(PteSrc.n.u1Write);
2548
2549	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2550	* entry will not harm; write access will simply fault again and
2551	* take this path to only invalidate the entry.
2552	*/
2553	if (RT_LIKELY(pPage))
2554	{
2555	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2556	{
2557	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2558	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2559	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2560	SHW_PTE_SET_RO(PteDst);
2561	}
2562	else
2563	{
2564	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2565	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2566	{
2567	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2568	AssertRC(rc);
2569	}
2570	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2571	SHW_PTE_SET_RW(PteDst);
2572	else
2573	{
2574	/* Still applies to shared pages. */
2575	Assert(!PGM_PAGE_IS_ZERO(pPage));
2576	SHW_PTE_SET_RO(PteDst);
2577	}
2578	}
2579	}
2580	else
2581	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2582
2583	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2584	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2585	PGM_INVL_PG(pVCpu, GCPtrPage);
2586	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2587	}
2588
2589	# ifdef IN_RING0
2590	/* Check for stale TLB entry; only applies to the SMP guest case. */
2591	if ( pVM->cCpus > 1
2592	&& SHW_PTE_IS_RW(*pPteDst)
2593	&& SHW_PTE_IS_A(*pPteDst))
2594	{
2595	/* Stale TLB entry. */
2596	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2597	PGM_INVL_PG(pVCpu, GCPtrPage);
2598	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2599	}
2600	# endif
2601	}
2602	}
2603	else
2604	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2605	}
2606
2607	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2608	}
2609
2610	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2611
2612
2613	/**
2614	* Sync a shadow page table.
2615	*
2616	* The shadow page table is not present in the shadow PDE.
2617	*
2618	* Handles mapping conflicts.
2619	*
2620	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2621	* conflict), and Trap0eHandler.
2622	*
2623	* A precondition for this method is that the shadow PDE is not present. The
2624	* caller must take the PGM lock before checking this and continue to hold it
2625	* when calling this method.
2626	*
2627	* @returns VBox status code.
2628	* @param pVCpu The cross context virtual CPU structure.
2629	* @param iPDSrc Page directory index.
2630	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2631	* Assume this is a temporary mapping.
2632	* @param GCPtrPage GC Pointer of the page that caused the fault
2633	*/
2634	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2635	{
2636	PVM pVM = pVCpu->CTX_SUFF(pVM);
2637	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2638
2639	#if 0 /* rarely useful; leave for debugging. */
2640	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2641	#endif
2642	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2643
2644	PGM_LOCK_ASSERT_OWNER(pVM);
2645
2646	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2647	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2648	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2649	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2650	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2651
2652	int rc = VINF_SUCCESS;
2653
2654	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2655
2656	/*
2657	* Some input validation first.
2658	*/
2659	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2660
2661	/*
2662	* Get the relevant shadow PDE entry.
2663	*/
2664	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2665	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2666	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2667
2668	/* Fetch the pgm pool shadow descriptor. */
2669	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2670	Assert(pShwPde);
2671
2672	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2673	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2674	PPGMPOOLPAGE pShwPde = NULL;
2675	PX86PDPAE pPDDst;
2676	PSHWPDE pPdeDst;
2677
2678	/* Fetch the pgm pool shadow descriptor. */
2679	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2680	AssertRCSuccessReturn(rc, rc);
2681	Assert(pShwPde);
2682
2683	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2684	pPdeDst = &pPDDst->a[iPDDst];
2685
2686	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2687	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2688	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2689	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2690	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2691	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2692	AssertRCSuccessReturn(rc, rc);
2693	Assert(pPDDst);
2694	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2695	# endif
2696	SHWPDE PdeDst = *pPdeDst;
2697
2698	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2699	/* Fetch the pgm pool shadow descriptor. */
2700	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2701	Assert(pShwPde);
2702	# endif
2703
2704	# ifndef PGM_WITHOUT_MAPPINGS
2705	/*
2706	* Check for conflicts.
2707	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2708	* R3: Simply resolve the conflict.
2709	*/
2710	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2711	{
2712	Assert(pgmMapAreMappingsEnabled(pVM));
2713	# ifndef IN_RING3
2714	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2715	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2716	return VERR_ADDRESS_CONFLICT;
2717
2718	# else /* IN_RING3 */
2719	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2720	Assert(pMapping);
2721	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2722	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2723	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2724	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2725	# else
2726	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2727	# endif
2728	if (RT_FAILURE(rc))
2729	{
2730	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2731	return rc;
2732	}
2733	PdeDst = *pPdeDst;
2734	# endif /* IN_RING3 */
2735	}
2736	# endif /* !PGM_WITHOUT_MAPPINGS */
2737	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2738
2739	/*
2740	* Sync the page directory entry.
2741	*/
2742	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2743	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2744	if ( PdeSrc.n.u1Present
2745	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2746	{
2747	/*
2748	* Allocate & map the page table.
2749	*/
2750	PSHWPT pPTDst;
2751	PPGMPOOLPAGE pShwPage;
2752	RTGCPHYS GCPhys;
2753	if (fPageTable)
2754	{
2755	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2756	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2757	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2758	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2759	# endif
2760	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2761	pShwPde->idx, iPDDst, false /fLockPage/,
2762	&pShwPage);
2763	}
2764	else
2765	{
2766	PGMPOOLACCESS enmAccess;
2767	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2768	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2769	# else
2770	const bool fNoExecute = false;
2771	# endif
2772
2773	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2774	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2775	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2776	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2777	# endif
2778	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2779	if (PdeSrc.n.u1User)
2780	{
2781	if (PdeSrc.n.u1Write)
2782	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2783	else
2784	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2785	}
2786	else
2787	{
2788	if (PdeSrc.n.u1Write)
2789	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2790	else
2791	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2792	}
2793	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2794	pShwPde->idx, iPDDst, false /fLockPage/,
2795	&pShwPage);
2796	}
2797	if (rc == VINF_SUCCESS)
2798	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2799	else if (rc == VINF_PGM_CACHED_PAGE)
2800	{
2801	/*
2802	* The PT was cached, just hook it up.
2803	*/
2804	if (fPageTable)
2805	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2806	else
2807	{
2808	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2809	/* (see explanation and assumptions further down.) */
2810	if ( !PdeSrc.b.u1Dirty
2811	&& PdeSrc.b.u1Write)
2812	{
2813	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2814	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2815	PdeDst.b.u1Write = 0;
2816	}
2817	}
2818	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2819	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2820	return VINF_SUCCESS;
2821	}
2822	else if (rc == VERR_PGM_POOL_FLUSHED)
2823	{
2824	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2825	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2826	return VINF_PGM_SYNC_CR3;
2827	}
2828	else
2829	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2830	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2831	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2832	* irrelevant at this point. */
2833	PdeDst.u &= X86_PDE_AVL_MASK;
2834	PdeDst.u \|= pShwPage->Core.Key;
2835
2836	/*
2837	* Page directory has been accessed (this is a fault situation, remember).
2838	*/
2839	/** @todo
2840	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2841	* fault situation. What's more, the Trap0eHandler has already set the
2842	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2843	* might need setting the accessed flag.
2844	*
2845	* The best idea is to leave this change to the caller and add an
2846	* assertion that it's set already. */
2847	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2848	if (fPageTable)
2849	{
2850	/*
2851	* Page table - 4KB.
2852	*
2853	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2854	*/
2855	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2856	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2857	PGSTPT pPTSrc;
2858	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2859	if (RT_SUCCESS(rc))
2860	{
2861	/*
2862	* Start by syncing the page directory entry so CSAM's TLB trick works.
2863	*/
2864	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2865	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2866	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2867	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2868
2869	/*
2870	* Directory/page user or supervisor privilege: (same goes for read/write)
2871	*
2872	* Directory Page Combined
2873	* U/S U/S U/S
2874	* 0 0 0
2875	* 0 1 0
2876	* 1 0 0
2877	* 1 1 1
2878	*
2879	* Simple AND operation. Table listed for completeness.
2880	*
2881	*/
2882	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2883	# ifdef PGM_SYNC_N_PAGES
2884	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2885	unsigned iPTDst = iPTBase;
2886	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2887	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2888	iPTDst = 0;
2889	else
2890	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2891	# else /* !PGM_SYNC_N_PAGES */
2892	unsigned iPTDst = 0;
2893	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2894	# endif /* !PGM_SYNC_N_PAGES */
2895	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2896	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2898	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2899	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2900	# else
2901	const unsigned offPTSrc = 0;
2902	# endif
2903	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2904	{
2905	const unsigned iPTSrc = iPTDst + offPTSrc;
2906	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2907
2908	if (PteSrc.n.u1Present)
2909	{
2910	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2911	/*
2912	* Assuming kernel code will be marked as supervisor - and not as user level
2913	* and executed using a conforming code selector - And marked as readonly.
2914	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2915	*/
2916	PPGMPAGE pPage;
2917	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2918	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2919	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2920	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2921	)
2922	# endif
2923	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2924	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2925	GCPtrCur,
2926	PteSrc.n.u1Present,
2927	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2928	PteSrc.n.u1User & PdeSrc.n.u1User,
2929	(uint64_t)PteSrc.u,
2930	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2931	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2932	}
2933	/* else: the page table was cleared by the pool */
2934	} /* for PTEs */
2935	}
2936	}
2937	else
2938	{
2939	/*
2940	* Big page - 2/4MB.
2941	*
2942	* We'll walk the ram range list in parallel and optimize lookups.
2943	* We will only sync one shadow page table at a time.
2944	*/
2945	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2946
2947	/**
2948	* @todo It might be more efficient to sync only a part of the 4MB
2949	* page (similar to what we do for 4KB PDs).
2950	*/
2951
2952	/*
2953	* Start by syncing the page directory entry.
2954	*/
2955	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2956	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2957
2958	/*
2959	* If the page is not flagged as dirty and is writable, then make it read-only
2960	* at PD level, so we can set the dirty bit when the page is modified.
2961	*
2962	* ASSUMES that page access handlers are implemented on page table entry level.
2963	* Thus we will first catch the dirty access and set PDE.D and restart. If
2964	* there is an access handler, we'll trap again and let it work on the problem.
2965	*/
2966	/** @todo move the above stuff to a section in the PGM documentation. */
2967	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2968	if ( !PdeSrc.b.u1Dirty
2969	&& PdeSrc.b.u1Write)
2970	{
2971	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2972	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2973	PdeDst.b.u1Write = 0;
2974	}
2975	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2976	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2977
2978	/*
2979	* Fill the shadow page table.
2980	*/
2981	/* Get address and flags from the source PDE. */
2982	SHWPTE PteDstBase;
2983	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2984
2985	/* Loop thru the entries in the shadow PT. */
2986	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2987	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2988	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2989	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2990	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2991	unsigned iPTDst = 0;
2992	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2993	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2994	{
2995	if (pRam && GCPhys >= pRam->GCPhys)
2996	{
2997	# ifndef PGM_WITH_A20
2998	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2999	# endif
3000	do
3001	{
3002	/* Make shadow PTE. */
3003	# ifdef PGM_WITH_A20
3004	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3005	# else
3006	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3007	# endif
3008	SHWPTE PteDst;
3009
3010	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3011	/* Try to make the page writable if necessary. */
3012	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3013	&& ( PGM_PAGE_IS_ZERO(pPage)
3014	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3015	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3016	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3017	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3018	# endif
3019	# ifdef VBOX_WITH_PAGE_SHARING
3020	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3021	# endif
3022	&& !PGM_PAGE_IS_BALLOONED(pPage))
3023	)
3024	)
3025	{
3026	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3027	AssertRCReturn(rc, rc);
3028	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3029	break;
3030	}
3031	# endif
3032
3033	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3034	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3035	else if (PGM_PAGE_IS_BALLOONED(pPage))
3036	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3037	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3038	/*
3039	* Assuming kernel code will be marked as supervisor and not as user level and executed
3040	* using a conforming code selector. Don't check for readonly, as that implies the whole
3041	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3042	*/
3043	else if ( !PdeSrc.n.u1User
3044	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3045	SHW_PTE_SET(PteDst, 0);
3046	# endif
3047	else
3048	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3049
3050	/* Only map writable pages writable. */
3051	if ( SHW_PTE_IS_P_RW(PteDst)
3052	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3053	{
3054	/* Still applies to shared pages. */
3055	Assert(!PGM_PAGE_IS_ZERO(pPage));
3056	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3057	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3058	}
3059
3060	if (SHW_PTE_IS_P(PteDst))
3061	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3062
3063	/* commit it (not atomic, new table) */
3064	pPTDst->a[iPTDst] = PteDst;
3065	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3066	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3067	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3068
3069	/* advance */
3070	GCPhys += PAGE_SIZE;
3071	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3072	# ifndef PGM_WITH_A20
3073	iHCPage++;
3074	# endif
3075	iPTDst++;
3076	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3077	&& GCPhys <= pRam->GCPhysLast);
3078
3079	/* Advance ram range list. */
3080	while (pRam && GCPhys > pRam->GCPhysLast)
3081	pRam = pRam->CTX_SUFF(pNext);
3082	}
3083	else if (pRam)
3084	{
3085	Log(("Invalid pages at %RGp\n", GCPhys));
3086	do
3087	{
3088	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3089	GCPhys += PAGE_SIZE;
3090	iPTDst++;
3091	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3092	&& GCPhys < pRam->GCPhys);
3093	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3094	}
3095	else
3096	{
3097	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3098	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3099	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3100	}
3101	} /* while more PTEs */
3102	} /* 4KB / 4MB */
3103	}
3104	else
3105	AssertRelease(!PdeDst.n.u1Present);
3106
3107	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3108	if (RT_FAILURE(rc))
3109	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3110	return rc;
3111
3112	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3113	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3114	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3115	&& !defined(IN_RC)
3116	NOREF(iPDSrc); NOREF(pPDSrc);
3117
3118	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3119
3120	/*
3121	* Validate input a little bit.
3122	*/
3123	int rc = VINF_SUCCESS;
3124	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3125	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3126	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3127
3128	/* Fetch the pgm pool shadow descriptor. */
3129	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3130	Assert(pShwPde);
3131
3132	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3133	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3134	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3135	PX86PDPAE pPDDst;
3136	PSHWPDE pPdeDst;
3137
3138	/* Fetch the pgm pool shadow descriptor. */
3139	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3140	AssertRCSuccessReturn(rc, rc);
3141	Assert(pShwPde);
3142
3143	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3144	pPdeDst = &pPDDst->a[iPDDst];
3145
3146	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3147	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3148	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3149	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3150	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3151	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3152	AssertRCSuccessReturn(rc, rc);
3153	Assert(pPDDst);
3154	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3155
3156	/* Fetch the pgm pool shadow descriptor. */
3157	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3158	Assert(pShwPde);
3159
3160	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3161	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3162	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3163	PEPTPD pPDDst;
3164	PEPTPDPT pPdptDst;
3165
3166	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3167	if (rc != VINF_SUCCESS)
3168	{
3169	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3170	AssertRC(rc);
3171	return rc;
3172	}
3173	Assert(pPDDst);
3174	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3175
3176	/* Fetch the pgm pool shadow descriptor. */
3177	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3178	Assert(pShwPde);
3179	# endif
3180	SHWPDE PdeDst = *pPdeDst;
3181
3182	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3183	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3184
3185	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3186	if (BTH_IS_NP_ACTIVE(pVM))
3187	{
3188	/* Check if we allocated a big page before for this 2 MB range. */
3189	PPGMPAGE pPage;
3190	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3191	if (RT_SUCCESS(rc))
3192	{
3193	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3194	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3195	{
3196	if (PGM_A20_IS_ENABLED(pVCpu))
3197	{
3198	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3199	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3200	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3201	}
3202	else
3203	{
3204	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3205	pVM->pgm.s.cLargePagesDisabled++;
3206	}
3207	}
3208	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3209	&& PGM_A20_IS_ENABLED(pVCpu))
3210	{
3211	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3212	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3213	if (RT_SUCCESS(rc))
3214	{
3215	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3216	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3217	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3218	}
3219	}
3220	else if ( PGMIsUsingLargePages(pVM)
3221	&& PGM_A20_IS_ENABLED(pVCpu))
3222	{
3223	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3224	if (RT_SUCCESS(rc))
3225	{
3226	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3227	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3228	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3229	}
3230	else
3231	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3232	}
3233
3234	if (HCPhys != NIL_RTHCPHYS)
3235	{
3236	PdeDst.u &= X86_PDE_AVL_MASK;
3237	PdeDst.u \|= HCPhys;
3238	PdeDst.n.u1Present = 1;
3239	PdeDst.n.u1Write = 1;
3240	PdeDst.b.u1Size = 1;
3241	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3242	PdeDst.n.u1Execute = 1;
3243	PdeDst.b.u1IgnorePAT = 1;
3244	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3245	# else
3246	PdeDst.n.u1User = 1;
3247	# endif
3248	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3249
3250	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3251	/* Add a reference to the first page only. */
3252	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3253
3254	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3255	return VINF_SUCCESS;
3256	}
3257	}
3258	}
3259	# endif /* HC_ARCH_BITS == 64 */
3260
3261	/*
3262	* Allocate & map the page table.
3263	*/
3264	PSHWPT pPTDst;
3265	PPGMPOOLPAGE pShwPage;
3266	RTGCPHYS GCPhys;
3267
3268	/* Virtual address = physical address */
3269	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3270	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3271	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3272	&pShwPage);
3273	if ( rc == VINF_SUCCESS
3274	\|\| rc == VINF_PGM_CACHED_PAGE)
3275	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3276	else
3277	{
3278	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3279	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3280	}
3281
3282	if (rc == VINF_SUCCESS)
3283	{
3284	/* New page table; fully set it up. */
3285	Assert(pPTDst);
3286
3287	/* Mask away the page offset. */
3288	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3289
3290	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3291	{
3292	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3293	\| (iPTDst << PAGE_SHIFT));
3294
3295	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3296	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3297	GCPtrCurPage,
3298	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3299	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3300
3301	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3302	break;
3303	}
3304	}
3305	else
3306	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3307
3308	/* Save the new PDE. */
3309	PdeDst.u &= X86_PDE_AVL_MASK;
3310	PdeDst.u \|= pShwPage->Core.Key;
3311	PdeDst.n.u1Present = 1;
3312	PdeDst.n.u1Write = 1;
3313	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3314	PdeDst.n.u1Execute = 1;
3315	# else
3316	PdeDst.n.u1User = 1;
3317	PdeDst.n.u1Accessed = 1;
3318	# endif
3319	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3320
3321	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3322	if (RT_FAILURE(rc))
3323	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3324	return rc;
3325
3326	#else
3327	NOREF(iPDSrc); NOREF(pPDSrc);
3328	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3329	return VERR_PGM_NOT_USED_IN_MODE;
3330	#endif
3331	}
3332
3333
3334
3335	/**
3336	* Prefetch a page/set of pages.
3337	*
3338	* Typically used to sync commonly used pages before entering raw mode
3339	* after a CR3 reload.
3340	*
3341	* @returns VBox status code.
3342	* @param pVCpu The cross context virtual CPU structure.
3343	* @param GCPtrPage Page to invalidate.
3344	*/
3345	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3346	{
3347	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3348	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3349	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3350	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3351	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3352	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3353	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3354
3355	/*
3356	* Check that all Guest levels thru the PDE are present, getting the
3357	* PD and PDE in the processes.
3358	*/
3359	int rc = VINF_SUCCESS;
3360	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3361	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3362	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3363	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3364	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3365	unsigned iPDSrc;
3366	X86PDPE PdpeSrc;
3367	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3368	if (!pPDSrc)
3369	return VINF_SUCCESS; /* not present */
3370	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3371	unsigned iPDSrc;
3372	PX86PML4E pPml4eSrc;
3373	X86PDPE PdpeSrc;
3374	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3375	if (!pPDSrc)
3376	return VINF_SUCCESS; /* not present */
3377	# endif
3378	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3379	# else
3380	PGSTPD pPDSrc = NULL;
3381	const unsigned iPDSrc = 0;
3382	GSTPDE PdeSrc;
3383
3384	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3385	PdeSrc.n.u1Present = 1;
3386	PdeSrc.n.u1Write = 1;
3387	PdeSrc.n.u1Accessed = 1;
3388	PdeSrc.n.u1User = 1;
3389	# endif
3390
3391	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3392	{
3393	PVM pVM = pVCpu->CTX_SUFF(pVM);
3394	pgmLock(pVM);
3395
3396	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3397	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3398	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3399	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3400	PX86PDPAE pPDDst;
3401	X86PDEPAE PdeDst;
3402	# if PGM_GST_TYPE != PGM_TYPE_PAE
3403	X86PDPE PdpeSrc;
3404
3405	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3406	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3407	# endif
3408	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3409	if (rc != VINF_SUCCESS)
3410	{
3411	pgmUnlock(pVM);
3412	AssertRC(rc);
3413	return rc;
3414	}
3415	Assert(pPDDst);
3416	PdeDst = pPDDst->a[iPDDst];
3417
3418	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3419	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3420	PX86PDPAE pPDDst;
3421	X86PDEPAE PdeDst;
3422
3423	# if PGM_GST_TYPE == PGM_TYPE_PROT
3424	/* AMD-V nested paging */
3425	X86PML4E Pml4eSrc;
3426	X86PDPE PdpeSrc;
3427	PX86PML4E pPml4eSrc = &Pml4eSrc;
3428
3429	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3430	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3431	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3432	# endif
3433
3434	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3435	if (rc != VINF_SUCCESS)
3436	{
3437	pgmUnlock(pVM);
3438	AssertRC(rc);
3439	return rc;
3440	}
3441	Assert(pPDDst);
3442	PdeDst = pPDDst->a[iPDDst];
3443	# endif
3444	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3445	{
3446	if (!PdeDst.n.u1Present)
3447	{
3448	/** @todo r=bird: This guy will set the A bit on the PDE,
3449	* probably harmless. */
3450	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3451	}
3452	else
3453	{
3454	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3455	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3456	* makes no sense to prefetch more than one page.
3457	*/
3458	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3459	if (RT_SUCCESS(rc))
3460	rc = VINF_SUCCESS;
3461	}
3462	}
3463	pgmUnlock(pVM);
3464	}
3465	return rc;
3466
3467	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3468	NOREF(pVCpu); NOREF(GCPtrPage);
3469	return VINF_SUCCESS; /* ignore */
3470	#else
3471	AssertCompile(0);
3472	#endif
3473	}
3474
3475
3476
3477
3478	/**
3479	* Syncs a page during a PGMVerifyAccess() call.
3480	*
3481	* @returns VBox status code (informational included).
3482	* @param pVCpu The cross context virtual CPU structure.
3483	* @param GCPtrPage The address of the page to sync.
3484	* @param fPage The effective guest page flags.
3485	* @param uErr The trap error code.
3486	* @remarks This will normally never be called on invalid guest page
3487	* translation entries.
3488	*/
3489	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3490	{
3491	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3492
3493	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3494
3495	Assert(!pVM->pgm.s.fNestedPaging);
3496	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3497	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3498	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3499	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3500	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3501	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3502	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3503
3504	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3505	if (!(fPage & X86_PTE_US))
3506	{
3507	/*
3508	* Mark this page as safe.
3509	*/
3510	/** @todo not correct for pages that contain both code and data!! */
3511	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3512	CSAMMarkPage(pVM, GCPtrPage, true);
3513	}
3514	# endif
3515
3516	/*
3517	* Get guest PD and index.
3518	*/
3519	/** @todo Performance: We've done all this a jiffy ago in the
3520	* PGMGstGetPage call. */
3521	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3522	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3523	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3524	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3525
3526	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3527	unsigned iPDSrc = 0;
3528	X86PDPE PdpeSrc;
3529	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3530	if (RT_UNLIKELY(!pPDSrc))
3531	{
3532	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3533	return VINF_EM_RAW_GUEST_TRAP;
3534	}
3535
3536	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3537	unsigned iPDSrc = 0; /* shut up gcc */
3538	PX86PML4E pPml4eSrc = NULL; /* ditto */
3539	X86PDPE PdpeSrc;
3540	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3541	if (RT_UNLIKELY(!pPDSrc))
3542	{
3543	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3544	return VINF_EM_RAW_GUEST_TRAP;
3545	}
3546	# endif
3547
3548	# else /* !PGM_WITH_PAGING */
3549	PGSTPD pPDSrc = NULL;
3550	const unsigned iPDSrc = 0;
3551	# endif /* !PGM_WITH_PAGING */
3552	int rc = VINF_SUCCESS;
3553
3554	pgmLock(pVM);
3555
3556	/*
3557	* First check if the shadow pd is present.
3558	*/
3559	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3560	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3561
3562	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3563	PX86PDEPAE pPdeDst;
3564	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3565	PX86PDPAE pPDDst;
3566	# if PGM_GST_TYPE != PGM_TYPE_PAE
3567	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3568	X86PDPE PdpeSrc;
3569	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3570	# endif
3571	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3572	if (rc != VINF_SUCCESS)
3573	{
3574	pgmUnlock(pVM);
3575	AssertRC(rc);
3576	return rc;
3577	}
3578	Assert(pPDDst);
3579	pPdeDst = &pPDDst->a[iPDDst];
3580
3581	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3582	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3583	PX86PDPAE pPDDst;
3584	PX86PDEPAE pPdeDst;
3585
3586	# if PGM_GST_TYPE == PGM_TYPE_PROT
3587	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3588	X86PML4E Pml4eSrc;
3589	X86PDPE PdpeSrc;
3590	PX86PML4E pPml4eSrc = &Pml4eSrc;
3591	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3592	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3593	# endif
3594
3595	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3596	if (rc != VINF_SUCCESS)
3597	{
3598	pgmUnlock(pVM);
3599	AssertRC(rc);
3600	return rc;
3601	}
3602	Assert(pPDDst);
3603	pPdeDst = &pPDDst->a[iPDDst];
3604	# endif
3605
3606	if (!pPdeDst->n.u1Present)
3607	{
3608	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3609	if (rc != VINF_SUCCESS)
3610	{
3611	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3612	pgmUnlock(pVM);
3613	AssertRC(rc);
3614	return rc;
3615	}
3616	}
3617
3618	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3619	/* Check for dirty bit fault */
3620	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3621	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3622	Log(("PGMVerifyAccess: success (dirty)\n"));
3623	else
3624	# endif
3625	{
3626	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3627	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3628	# else
3629	GSTPDE PdeSrc;
3630	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3631	PdeSrc.n.u1Present = 1;
3632	PdeSrc.n.u1Write = 1;
3633	PdeSrc.n.u1Accessed = 1;
3634	PdeSrc.n.u1User = 1;
3635	# endif
3636
3637	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3638	if (uErr & X86_TRAP_PF_US)
3639	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3640	else /* supervisor */
3641	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3642
3643	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3644	if (RT_SUCCESS(rc))
3645	{
3646	/* Page was successfully synced */
3647	Log2(("PGMVerifyAccess: success (sync)\n"));
3648	rc = VINF_SUCCESS;
3649	}
3650	else
3651	{
3652	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3653	rc = VINF_EM_RAW_GUEST_TRAP;
3654	}
3655	}
3656	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3657	pgmUnlock(pVM);
3658	return rc;
3659
3660	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3661
3662	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3663	return VERR_PGM_NOT_USED_IN_MODE;
3664	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3665	}
3666
3667
3668	/**
3669	* Syncs the paging hierarchy starting at CR3.
3670	*
3671	* @returns VBox status code, no specials.
3672	* @param pVCpu The cross context virtual CPU structure.
3673	* @param cr0 Guest context CR0 register.
3674	* @param cr3 Guest context CR3 register. Not subjected to the A20
3675	* mask.
3676	* @param cr4 Guest context CR4 register.
3677	* @param fGlobal Including global page directories or not
3678	*/
3679	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3680	{
3681	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3682	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3683
3684	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3685
3686	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3687
3688	pgmLock(pVM);
3689
3690	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3691	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3692	if (pPool->cDirtyPages)
3693	pgmPoolResetDirtyPages(pVM);
3694	# endif
3695
3696	/*
3697	* Update page access handlers.
3698	* The virtual are always flushed, while the physical are only on demand.
3699	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3700	* have to look into that later because it will have a bad influence on the performance.
3701	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3702	* bird: Yes, but that won't work for aliases.
3703	*/
3704	/** @todo this MUST go away. See @bugref{1557}. */
3705	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3706	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3707	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3708	pgmUnlock(pVM);
3709	#endif /* !NESTED && !EPT */
3710
3711	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3712	/*
3713	* Nested / EPT - almost no work.
3714	*/
3715	Assert(!pgmMapAreMappingsEnabled(pVM));
3716	return VINF_SUCCESS;
3717
3718	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3719	/*
3720	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3721	* out the shadow parts when the guest modifies its tables.
3722	*/
3723	Assert(!pgmMapAreMappingsEnabled(pVM));
3724	return VINF_SUCCESS;
3725
3726	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3727
3728	# ifndef PGM_WITHOUT_MAPPINGS
3729	/*
3730	* Check for and resolve conflicts with our guest mappings if they
3731	* are enabled and not fixed.
3732	*/
3733	if (pgmMapAreMappingsFloating(pVM))
3734	{
3735	int rc = pgmMapResolveConflicts(pVM);
3736	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3737	if (rc == VINF_PGM_SYNC_CR3)
3738	{
3739	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3740	return VINF_PGM_SYNC_CR3;
3741	}
3742	}
3743	# else
3744	Assert(!pgmMapAreMappingsEnabled(pVM));
3745	# endif
3746	return VINF_SUCCESS;
3747	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3748	}
3749
3750
3751
3752
3753	#ifdef VBOX_STRICT
3754	# ifdef IN_RC
3755	# undef AssertMsgFailed
3756	# define AssertMsgFailed Log
3757	# endif
3758
3759	/**
3760	* Checks that the shadow page table is in sync with the guest one.
3761	*
3762	* @returns The number of errors.
3763	* @param pVCpu The cross context virtual CPU structure.
3764	* @param cr3 Guest context CR3 register.
3765	* @param cr4 Guest context CR4 register.
3766	* @param GCPtr Where to start. Defaults to 0.
3767	* @param cb How much to check. Defaults to everything.
3768	*/
3769	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3770	{
3771	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3772	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3773	return 0;
3774	#else
3775	unsigned cErrors = 0;
3776	PVM pVM = pVCpu->CTX_SUFF(pVM);
3777	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3778
3779	# if PGM_GST_TYPE == PGM_TYPE_PAE
3780	/** @todo currently broken; crashes below somewhere */
3781	AssertFailed();
3782	# endif
3783
3784	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3785	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3786	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3787
3788	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3789	PPGMCPU pPGM = &pVCpu->pgm.s;
3790	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3791	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3792	# ifndef IN_RING0
3793	RTHCPHYS HCPhys; /* general usage. */
3794	# endif
3795	int rc;
3796
3797	/*
3798	* Check that the Guest CR3 and all its mappings are correct.
3799	*/
3800	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3801	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3802	false);
3803	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3804	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3805	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3806	# else
3807	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3808	# endif
3809	AssertRCReturn(rc, 1);
3810	HCPhys = NIL_RTHCPHYS;
3811	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3812	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3813	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3814	pgmGstGet32bitPDPtr(pVCpu);
3815	RTGCPHYS GCPhys;
3816	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3817	AssertRCReturn(rc, 1);
3818	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3819	# endif
3820	# endif /* !IN_RING0 */
3821
3822	/*
3823	* Get and check the Shadow CR3.
3824	*/
3825	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3826	unsigned cPDEs = X86_PG_ENTRIES;
3827	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3828	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3829	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3830	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3831	# else
3832	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3833	# endif
3834	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3835	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3836	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3837	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3838	# endif
3839	if (cb != ~(RTGCPTR)0)
3840	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3841
3842	/** @todo call the other two PGMAssert() functions. /
3843
3844	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3845	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3846
3847	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3848	{
3849	PPGMPOOLPAGE pShwPdpt = NULL;
3850	PX86PML4E pPml4eSrc;
3851	PX86PML4E pPml4eDst;
3852	RTGCPHYS GCPhysPdptSrc;
3853
3854	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3855	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3856
3857	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3858	if (!pPml4eDst->n.u1Present)
3859	{
3860	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3861	continue;
3862	}
3863
3864	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3865	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3866
3867	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3868	{
3869	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3870	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3871	cErrors++;
3872	continue;
3873	}
3874
3875	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3876	{
3877	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3878	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3879	cErrors++;
3880	continue;
3881	}
3882
3883	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3884	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3885	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3886	{
3887	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3888	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3889	cErrors++;
3890	continue;
3891	}
3892	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3893	{
3894	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3895
3896	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3897	/*
3898	* Check the PDPTEs too.
3899	*/
3900	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3901
3902	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3903	{
3904	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3905	PPGMPOOLPAGE pShwPde = NULL;
3906	PX86PDPE pPdpeDst;
3907	RTGCPHYS GCPhysPdeSrc;
3908	X86PDPE PdpeSrc;
3909	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3910	# if PGM_GST_TYPE == PGM_TYPE_PAE
3911	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3912	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3913	# else
3914	PX86PML4E pPml4eSrcIgn;
3915	PX86PDPT pPdptDst;
3916	PX86PDPAE pPDDst;
3917	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3918
3919	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3920	if (rc != VINF_SUCCESS)
3921	{
3922	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3923	GCPtr += 512 * _2M;
3924	continue; /* next PDPTE */
3925	}
3926	Assert(pPDDst);
3927	# endif
3928	Assert(iPDSrc == 0);
3929
3930	pPdpeDst = &pPdptDst->a[iPdpt];
3931
3932	if (!pPdpeDst->n.u1Present)
3933	{
3934	GCPtr += 512 * _2M;
3935	continue; /* next PDPTE */
3936	}
3937
3938	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3939	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3940
3941	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3942	{
3943	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3944	GCPtr += 512 * _2M;
3945	cErrors++;
3946	continue;
3947	}
3948
3949	if (GCPhysPdeSrc != pShwPde->GCPhys)
3950	{
3951	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3952	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3953	# else
3954	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3955	# endif
3956	GCPtr += 512 * _2M;
3957	cErrors++;
3958	continue;
3959	}
3960
3961	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3962	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3963	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3964	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3965	{
3966	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3967	GCPtr += 512 * _2M;
3968	cErrors++;
3969	continue;
3970	}
3971	# endif
3972
3973	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3974	{
3975	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3976	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3977	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3978	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3979	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3980	# endif
3981	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3982	/*
3983	* Iterate the shadow page directory.
3984	*/
3985	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3986	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3987
3988	for (;
3989	iPDDst < cPDEs;
3990	iPDDst++, GCPtr += cIncrement)
3991	{
3992	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3993	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3994	# else
3995	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3996	# endif
3997	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3998	{
3999	Assert(pgmMapAreMappingsEnabled(pVM));
4000	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4001	{
4002	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4003	cErrors++;
4004	continue;
4005	}
4006	}
4007	else if ( (PdeDst.u & X86_PDE_P)
4008	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4009	)
4010	{
4011	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4012	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4013	if (!pPoolPage)
4014	{
4015	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4016	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4017	cErrors++;
4018	continue;
4019	}
4020	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4021
4022	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4023	{
4024	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4025	GCPtr, (uint64_t)PdeDst.u));
4026	cErrors++;
4027	}
4028
4029	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4030	{
4031	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4032	GCPtr, (uint64_t)PdeDst.u));
4033	cErrors++;
4034	}
4035
4036	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4037	if (!PdeSrc.n.u1Present)
4038	{
4039	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4040	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4041	cErrors++;
4042	continue;
4043	}
4044
4045	if ( !PdeSrc.b.u1Size
4046	\|\| !fBigPagesSupported)
4047	{
4048	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4049	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4050	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4051	# endif
4052	}
4053	else
4054	{
4055	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4056	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4057	{
4058	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4059	GCPtr, (uint64_t)PdeSrc.u));
4060	cErrors++;
4061	continue;
4062	}
4063	# endif
4064	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4065	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4066	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4067	# endif
4068	}
4069
4070	if ( pPoolPage->enmKind
4071	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4072	{
4073	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4074	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4075	cErrors++;
4076	}
4077
4078	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4079	if (!pPhysPage)
4080	{
4081	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4082	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4083	cErrors++;
4084	continue;
4085	}
4086
4087	if (GCPhysGst != pPoolPage->GCPhys)
4088	{
4089	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4090	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4091	cErrors++;
4092	continue;
4093	}
4094
4095	if ( !PdeSrc.b.u1Size
4096	\|\| !fBigPagesSupported)
4097	{
4098	/*
4099	* Page Table.
4100	*/
4101	const GSTPT *pPTSrc;
4102	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4103	&pPTSrc);
4104	if (RT_FAILURE(rc))
4105	{
4106	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4107	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4108	cErrors++;
4109	continue;
4110	}
4111	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4112	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4113	{
4114	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4115	// (This problem will go away when/if we shadow multiple CR3s.)
4116	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4117	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4118	cErrors++;
4119	continue;
4120	}
4121	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4122	{
4123	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4124	GCPtr, (uint64_t)PdeDst.u));
4125	cErrors++;
4126	continue;
4127	}
4128
4129	/* iterate the page table. */
4130	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4131	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4132	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4133	# else
4134	const unsigned offPTSrc = 0;
4135	# endif
4136	for (unsigned iPT = 0, off = 0;
4137	iPT < RT_ELEMENTS(pPTDst->a);
4138	iPT++, off += PAGE_SIZE)
4139	{
4140	const SHWPTE PteDst = pPTDst->a[iPT];
4141
4142	/* skip not-present and dirty tracked entries. */
4143	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4144	continue;
4145	Assert(SHW_PTE_IS_P(PteDst));
4146
4147	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4148	if (!PteSrc.n.u1Present)
4149	{
4150	# ifdef IN_RING3
4151	PGMAssertHandlerAndFlagsInSync(pVM);
4152	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4153	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4154	0, 0, UINT64_MAX, 99, NULL);
4155	# endif
4156	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4157	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4158	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4159	cErrors++;
4160	continue;
4161	}
4162
4163	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4164	# if 1 /** @todo sync accessed bit properly... */
4165	fIgnoreFlags \|= X86_PTE_A;
4166	# endif
4167
4168	/* match the physical addresses */
4169	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4170	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4171
4172	# ifdef IN_RING3
4173	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4174	if (RT_FAILURE(rc))
4175	{
4176	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4177	{
4178	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4179	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4180	cErrors++;
4181	continue;
4182	}
4183	}
4184	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4185	{
4186	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4187	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4188	cErrors++;
4189	continue;
4190	}
4191	# endif
4192
4193	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4194	if (!pPhysPage)
4195	{
4196	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4197	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4198	{
4199	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4200	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4201	cErrors++;
4202	continue;
4203	}
4204	# endif
4205	if (SHW_PTE_IS_RW(PteDst))
4206	{
4207	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4209	cErrors++;
4210	}
4211	fIgnoreFlags \|= X86_PTE_RW;
4212	}
4213	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4214	{
4215	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4217	cErrors++;
4218	continue;
4219	}
4220
4221	/* flags */
4222	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4223	{
4224	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4225	{
4226	if (SHW_PTE_IS_RW(PteDst))
4227	{
4228	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4229	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4230	cErrors++;
4231	continue;
4232	}
4233	fIgnoreFlags \|= X86_PTE_RW;
4234	}
4235	else
4236	{
4237	if ( SHW_PTE_IS_P(PteDst)
4238	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4239	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4240	# endif
4241	)
4242	{
4243	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4244	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4245	cErrors++;
4246	continue;
4247	}
4248	fIgnoreFlags \|= X86_PTE_P;
4249	}
4250	}
4251	else
4252	{
4253	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4254	{
4255	if (SHW_PTE_IS_RW(PteDst))
4256	{
4257	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4259	cErrors++;
4260	continue;
4261	}
4262	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4263	{
4264	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4265	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4266	cErrors++;
4267	continue;
4268	}
4269	if (SHW_PTE_IS_D(PteDst))
4270	{
4271	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4272	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4273	cErrors++;
4274	}
4275	# if 0 /** @todo sync access bit properly... */
4276	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4277	{
4278	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4279	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4280	cErrors++;
4281	}
4282	fIgnoreFlags \|= X86_PTE_RW;
4283	# else
4284	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4285	# endif
4286	}
4287	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4288	{
4289	/* access bit emulation (not implemented). */
4290	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4291	{
4292	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4293	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4294	cErrors++;
4295	continue;
4296	}
4297	if (!SHW_PTE_IS_A(PteDst))
4298	{
4299	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4300	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4301	cErrors++;
4302	}
4303	fIgnoreFlags \|= X86_PTE_P;
4304	}
4305	# ifdef DEBUG_sandervl
4306	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4307	# endif
4308	}
4309
4310	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4311	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4312	)
4313	{
4314	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4315	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4316	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4317	cErrors++;
4318	continue;
4319	}
4320	} /* foreach PTE */
4321	}
4322	else
4323	{
4324	/*
4325	* Big Page.
4326	*/
4327	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4328	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4329	{
4330	if (PdeDst.n.u1Write)
4331	{
4332	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4333	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4334	cErrors++;
4335	continue;
4336	}
4337	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4338	{
4339	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4340	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4341	cErrors++;
4342	continue;
4343	}
4344	# if 0 /** @todo sync access bit properly... */
4345	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4346	{
4347	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4348	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4349	cErrors++;
4350	}
4351	fIgnoreFlags \|= X86_PTE_RW;
4352	# else
4353	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4354	# endif
4355	}
4356	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4357	{
4358	/* access bit emulation (not implemented). */
4359	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4360	{
4361	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4362	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4363	cErrors++;
4364	continue;
4365	}
4366	if (!PdeDst.n.u1Accessed)
4367	{
4368	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4369	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4370	cErrors++;
4371	}
4372	fIgnoreFlags \|= X86_PTE_P;
4373	}
4374
4375	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4376	{
4377	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4378	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4379	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4380	cErrors++;
4381	}
4382
4383	/* iterate the page table. */
4384	for (unsigned iPT = 0, off = 0;
4385	iPT < RT_ELEMENTS(pPTDst->a);
4386	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4387	{
4388	const SHWPTE PteDst = pPTDst->a[iPT];
4389
4390	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4391	{
4392	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4393	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4394	cErrors++;
4395	}
4396
4397	/* skip not-present entries. */
4398	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4399	continue;
4400
4401	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4402
4403	/* match the physical addresses */
4404	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4405
4406	# ifdef IN_RING3
4407	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4408	if (RT_FAILURE(rc))
4409	{
4410	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4411	{
4412	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4413	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4414	cErrors++;
4415	}
4416	}
4417	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4418	{
4419	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4420	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4421	cErrors++;
4422	continue;
4423	}
4424	# endif
4425	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4426	if (!pPhysPage)
4427	{
4428	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4429	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4430	{
4431	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4432	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4433	cErrors++;
4434	continue;
4435	}
4436	# endif
4437	if (SHW_PTE_IS_RW(PteDst))
4438	{
4439	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4440	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4441	cErrors++;
4442	}
4443	fIgnoreFlags \|= X86_PTE_RW;
4444	}
4445	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4446	{
4447	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4448	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4449	cErrors++;
4450	continue;
4451	}
4452
4453	/* flags */
4454	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4455	{
4456	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4457	{
4458	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4459	{
4460	if (SHW_PTE_IS_RW(PteDst))
4461	{
4462	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4463	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4464	cErrors++;
4465	continue;
4466	}
4467	fIgnoreFlags \|= X86_PTE_RW;
4468	}
4469	}
4470	else
4471	{
4472	if ( SHW_PTE_IS_P(PteDst)
4473	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4474	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4475	# endif
4476	)
4477	{
4478	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4479	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4480	cErrors++;
4481	continue;
4482	}
4483	fIgnoreFlags \|= X86_PTE_P;
4484	}
4485	}
4486
4487	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4488	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4489	)
4490	{
4491	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4492	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4493	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4494	cErrors++;
4495	continue;
4496	}
4497	} /* for each PTE */
4498	}
4499	}
4500	/* not present */
4501
4502	} /* for each PDE */
4503
4504	} /* for each PDPTE */
4505
4506	} /* for each PML4E */
4507
4508	# ifdef DEBUG
4509	if (cErrors)
4510	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4511	# endif
4512	# endif /* GST is in {32BIT, PAE, AMD64} */
4513	return cErrors;
4514	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4515	}
4516	#endif /* VBOX_STRICT */
4517
4518
4519	/**
4520	* Sets up the CR3 for shadow paging
4521	*
4522	* @returns Strict VBox status code.
4523	* @retval VINF_SUCCESS.
4524	*
4525	* @param pVCpu The cross context virtual CPU structure.
4526	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4527	* mask already applied.)
4528	*/
4529	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4530	{
4531	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4532
4533	/* Update guest paging info. */
4534	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4535	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4536	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4537
4538	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4539	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4540
4541	/*
4542	* Map the page CR3 points at.
4543	*/
4544	RTHCPTR HCPtrGuestCR3;
4545	RTHCPHYS HCPhysGuestCR3;
4546	pgmLock(pVM);
4547	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4548	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4549	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4550	/** @todo this needs some reworking wrt. locking? */
4551	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4552	HCPtrGuestCR3 = NIL_RTHCPTR;
4553	int rc = VINF_SUCCESS;
4554	# else
4555	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4556	# endif
4557	pgmUnlock(pVM);
4558	if (RT_SUCCESS(rc))
4559	{
4560	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4561	if (RT_SUCCESS(rc))
4562	{
4563	# ifdef IN_RC
4564	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4565	# endif
4566	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4567	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4568	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4569	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4570	# endif
4571	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4572
4573	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4574	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4575	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4576	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4577	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4578	# endif
4579	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4580	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4581
4582	/*
4583	* Map the 4 PDs too.
4584	*/
4585	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4586	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4587	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4588	{
4589	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4590	if (pGuestPDPT->a[i].n.u1Present)
4591	{
4592	RTHCPTR HCPtr;
4593	RTHCPHYS HCPhys;
4594	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4595	pgmLock(pVM);
4596	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4597	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4598	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4599	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4600	HCPtr = NIL_RTHCPTR;
4601	int rc2 = VINF_SUCCESS;
4602	# else
4603	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4604	# endif
4605	pgmUnlock(pVM);
4606	if (RT_SUCCESS(rc2))
4607	{
4608	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4609	AssertRCReturn(rc, rc);
4610
4611	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4612	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4613	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4614	# endif
4615	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4616	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4617	# ifdef IN_RC
4618	PGM_INVL_PG(pVCpu, GCPtr);
4619	# endif
4620	continue;
4621	}
4622	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4623	}
4624
4625	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4626	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4627	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4628	# endif
4629	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4630	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4631	# ifdef IN_RC
4632	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4633	# endif
4634	}
4635
4636	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4637	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4638	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4639	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4640	# endif
4641	# endif
4642	}
4643	else
4644	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4645	}
4646	else
4647	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4648
4649	#else /* prot/real stub */
4650	int rc = VINF_SUCCESS;
4651	#endif
4652
4653	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4654	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4655	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4656	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4657	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4658	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4659
4660	Assert(!pVM->pgm.s.fNestedPaging);
4661	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4662
4663	/*
4664	* Update the shadow root page as well since that's not fixed.
4665	*/
4666	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4667	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4668	PPGMPOOLPAGE pNewShwPageCR3;
4669
4670	pgmLock(pVM);
4671
4672	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4673	if (pPool->cDirtyPages)
4674	pgmPoolResetDirtyPages(pVM);
4675	# endif
4676
4677	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4678	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4679	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4680	&pNewShwPageCR3);
4681	AssertFatalRC(rc);
4682	rc = VINF_SUCCESS;
4683
4684	# ifdef IN_RC
4685	/*
4686	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4687	* state will be inconsistent! Flush important things now while
4688	* we still can and then make sure there are no ring-3 calls.
4689	*/
4690	# ifdef VBOX_WITH_REM
4691	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4692	# endif
4693	VMMRZCallRing3Disable(pVCpu);
4694	# endif
4695
4696	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4697	# ifdef IN_RING0
4698	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4699	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4700	# elif defined(IN_RC)
4701	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4702	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4703	# else
4704	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4705	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4706	# endif
4707
4708	# ifndef PGM_WITHOUT_MAPPINGS
4709	/*
4710	* Apply all hypervisor mappings to the new CR3.
4711	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4712	* make sure we check for conflicts in the new CR3 root.
4713	*/
4714	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4715	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4716	# endif
4717	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4718	AssertRCReturn(rc, rc);
4719	# endif
4720
4721	/* Set the current hypervisor CR3. */
4722	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4723	SELMShadowCR3Changed(pVM, pVCpu);
4724
4725	# ifdef IN_RC
4726	/* NOTE: The state is consistent again. */
4727	VMMRZCallRing3Enable(pVCpu);
4728	# endif
4729
4730	/* Clean up the old CR3 root. */
4731	if ( pOldShwPageCR3
4732	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4733	{
4734	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4735	# ifndef PGM_WITHOUT_MAPPINGS
4736	/* Remove the hypervisor mappings from the shadow page table. */
4737	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4738	# endif
4739	/* Mark the page as unlocked; allow flushing again. */
4740	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4741
4742	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4743	}
4744	pgmUnlock(pVM);
4745	# else
4746	NOREF(GCPhysCR3);
4747	# endif
4748
4749	return rc;
4750	}
4751
4752	/**
4753	* Unmaps the shadow CR3.
4754	*
4755	* @returns VBox status, no specials.
4756	* @param pVCpu The cross context virtual CPU structure.
4757	*/
4758	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4759	{
4760	LogFlow(("UnmapCR3\n"));
4761
4762	int rc = VINF_SUCCESS;
4763	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4764
4765	/*
4766	* Update guest paging info.
4767	*/
4768	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4769	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4770	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4771	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4772	# endif
4773	pVCpu->pgm.s.pGst32BitPdRC = 0;
4774
4775	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4776	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4777	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4778	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4779	# endif
4780	pVCpu->pgm.s.pGstPaePdptRC = 0;
4781	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4782	{
4783	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4784	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4785	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4786	# endif
4787	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4788	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4789	}
4790
4791	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4792	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4793	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4794	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4795	# endif
4796
4797	#else /* prot/real mode stub */
4798	/* nothing to do */
4799	#endif
4800
4801	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4802	/*
4803	* Update shadow paging info.
4804	*/
4805	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4806	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4807	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4808
4809	# if PGM_GST_TYPE != PGM_TYPE_REAL
4810	Assert(!pVM->pgm.s.fNestedPaging);
4811	# endif
4812
4813	pgmLock(pVM);
4814
4815	# ifndef PGM_WITHOUT_MAPPINGS
4816	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4817	/* Remove the hypervisor mappings from the shadow page table. */
4818	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4819	# endif
4820
4821	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4822	{
4823	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4824
4825	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4826	if (pPool->cDirtyPages)
4827	pgmPoolResetDirtyPages(pVM);
4828	# endif
4829
4830	/* Mark the page as unlocked; allow flushing again. */
4831	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4832
4833	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4834	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4835	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4836	pVCpu->pgm.s.pShwPageCR3RC = 0;
4837	}
4838	pgmUnlock(pVM);
4839	# endif
4840	#endif /* !IN_RC*/
4841
4842	return rc;
4843	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 60309

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