PGMAllBth.h@ 26624

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1	/* $Id: PGMAllBth.h 26621 2010-02-17 16:50:10Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
34	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
35	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
37	#ifdef VBOX_STRICT
38	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
39	#endif
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
42	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
43	RT_C_DECLS_END
44
45
46	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
47	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
48	# error "Invalid combination; PAE guest implies PAE shadow"
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
53	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
57	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
58	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
59	#endif
60
61	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
62	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
63	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
64	#endif
65
66
67	#ifndef IN_RING3
68	/**
69	* #PF Handler for raw-mode guest execution.
70	*
71	* @returns VBox status code (appropriate for trap handling and GC return).
72	*
73	* @param pVCpu VMCPU Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	* @param pfLockTaken PGM lock taken here or not (out)
78	*/
79	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
80	{
81	PVM pVM = pVCpu->CTX_SUFF(pVM);
82
83	*pfLockTaken = false;
84
85	# if defined(IN_RC) && defined(VBOX_STRICT)
86	PGMDynCheckLocks(pVM);
87	# endif
88
89	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
90	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
91	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
92
93	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
94	/*
95	* Hide the instruction fetch trap indicator for now.
96	*/
97	/** @todo NXE will change this and we must fix NXE in the switcher too! */
98	if (uErr & X86_TRAP_PF_ID)
99	{
100	uErr &= ~X86_TRAP_PF_ID;
101	TRPMSetErrorCode(pVCpu, uErr);
102	}
103	# endif
104
105	/*
106	* Get PDs.
107	*/
108	int rc;
109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
110	# if PGM_GST_TYPE == PGM_TYPE_32BIT
111	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
112	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
113
114	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
115
116	# if PGM_GST_TYPE == PGM_TYPE_PAE
117	unsigned iPDSrc = 0; /* initialized to shut up gcc */
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
122	unsigned iPDSrc = 0; /* initialized to shut up gcc */
123	PX86PML4E pPml4eSrc;
124	X86PDPE PdpeSrc;
125	PGSTPD pPDSrc;
126
127	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
128	Assert(pPml4eSrc);
129	# endif
130
131	/* Quick check for a valid guest trap. (PAE & AMD64) */
132	if (!pPDSrc)
133	{
134	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
135	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
136	# else
137	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# endif
139	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
140	TRPMSetErrorCode(pVCpu, uErr);
141	return VINF_EM_RAW_GUEST_TRAP;
142	}
143	# endif
144
145	# else /* !PGM_WITH_PAGING */
146	PGSTPD pPDSrc = NULL;
147	const unsigned iPDSrc = 0;
148	# endif /* !PGM_WITH_PAGING */
149
150	/* First check for a genuine guest page fault. */
151	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
153	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDSrc->a[iPDSrc], pvFault);
154	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
155	if (rc == VINF_EM_RAW_GUEST_TRAP)
156	{
157	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
158	= &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
159	return rc;
160	}
161	# endif /* PGM_WITH_PAGING */
162
163	/* Take the big lock now. */
164	*pfLockTaken = true;
165	pgmLock(pVM);
166
167	/* Fetch the guest PDE */
168	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
169	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
170	# else
171	GSTPDE PdeSrc;
172	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
173	PdeSrc.n.u1Present = 1;
174	PdeSrc.n.u1Write = 1;
175	PdeSrc.n.u1Accessed = 1;
176	PdeSrc.n.u1User = 1;
177	# endif
178
179	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
180	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
181	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
182
183	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
184	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
185
186	PX86PDPAE pPDDst;
187	# if PGM_GST_TYPE != PGM_TYPE_PAE
188	X86PDPE PdpeSrc;
189
190	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
191	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
192	# endif
193	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
194	if (rc != VINF_SUCCESS)
195	{
196	AssertRC(rc);
197	return rc;
198	}
199	Assert(pPDDst);
200
201	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
202	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
203	PX86PDPAE pPDDst;
204	# if PGM_GST_TYPE == PGM_TYPE_PROT
205	/* AMD-V nested paging */
206	X86PML4E Pml4eSrc;
207	X86PDPE PdpeSrc;
208	PX86PML4E pPml4eSrc = &Pml4eSrc;
209
210	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
211	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
212	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
213	# endif
214
215	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
216	if (rc != VINF_SUCCESS)
217	{
218	AssertRC(rc);
219	return rc;
220	}
221	Assert(pPDDst);
222
223	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
224	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
225	PEPTPD pPDDst;
226
227	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
228	if (rc != VINF_SUCCESS)
229	{
230	AssertRC(rc);
231	return rc;
232	}
233	Assert(pPDDst);
234	# endif
235
236	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
237	/* Dirty page handling. */
238	if (uErr & X86_TRAP_PF_RW) /* write fault? */
239	{
240	/*
241	* If we successfully correct the write protection fault due to dirty bit
242	* tracking, then return immediately.
243	*/
244	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
245	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
246	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
247	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
248	{
249	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
250	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
251	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
252	return VINF_SUCCESS;
253	}
254	}
255
256	# if 0 /* rarely useful; leave for debugging. */
257	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
258	# endif
259	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
260
261	/*
262	* A common case is the not-present error caused by lazy page table syncing.
263	*
264	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
265	* so we can safely assume that the shadow PT is present when calling SyncPage later.
266	*
267	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
268	* of mapping conflict and defer to SyncCR3 in R3.
269	* (Again, we do NOT support access handlers for non-present guest pages.)
270	*
271	*/
272	Assert(PdeSrc.n.u1Present);
273	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
274	&& !pPDDst->a[iPDDst].n.u1Present
275	)
276	{
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
278	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
279	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
280	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
281	if (RT_SUCCESS(rc))
282	{
283	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
284	return rc;
285	}
286	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
287	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
288	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
289	return VINF_PGM_SYNC_CR3;
290	}
291
292	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
293	/*
294	* Check if this address is within any of our mappings.
295	*
296	* This is very fast and it's gonna save us a bit of effort below and prevent
297	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
298	* (BTW, it's impossible to have physical access handlers in a mapping.)
299	*/
300	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
301	{
302	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
303	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
304	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
305	{
306	if (pvFault < pMapping->GCPtr)
307	break;
308	if (pvFault - pMapping->GCPtr < pMapping->cb)
309	{
310	/*
311	* The first thing we check is if we've got an undetected conflict.
312	*/
313	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
314	{
315	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
316	while (iPT-- > 0)
317	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
318	{
319	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
320	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
321	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
322	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
323	return VINF_PGM_SYNC_CR3;
324	}
325	}
326
327	/*
328	* Check if the fault address is in a virtual page access handler range.
329	*/
330	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
331	if ( pCur
332	&& pvFault - pCur->Core.Key < pCur->cb
333	&& uErr & X86_TRAP_PF_RW)
334	{
335	# ifdef IN_RC
336	STAM_PROFILE_START(&pCur->Stat, h);
337	pgmUnlock(pVM);
338	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
339	pgmLock(pVM);
340	STAM_PROFILE_STOP(&pCur->Stat, h);
341	# else
342	AssertFailed();
343	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
344	# endif
345	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
346	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
347	return rc;
348	}
349
350	/*
351	* Pretend we're not here and let the guest handle the trap.
352	*/
353	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
354	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
355	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
356	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
357	return VINF_EM_RAW_GUEST_TRAP;
358	}
359	}
360	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
361	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
362	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
363
364	/*
365	* Check if this fault address is flagged for special treatment,
366	* which means we'll have to figure out the physical address and
367	* check flags associated with it.
368	*
369	* ASSUME that we can limit any special access handling to pages
370	* in page tables which the guest believes to be present.
371	*/
372	Assert(PdeSrc.n.u1Present);
373	{
374	RTGCPHYS GCPhys = NIL_RTGCPHYS;
375
376	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
377	if ( PdeSrc.b.u1Size
378	# if PGM_GST_TYPE != PGM_TYPE_AMD64
379	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
380	# endif
381	)
382	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
383	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
384	else
385	{
386	PGSTPT pPTSrc;
387	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
388	if (RT_SUCCESS(rc))
389	{
390	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
391	if (pPTSrc->a[iPTESrc].n.u1Present)
392	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
393	}
394	}
395	# else
396	/* No paging so the fault address is the physical address */
397	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
398	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
399
400	/*
401	* If we have a GC address we'll check if it has any flags set.
402	*/
403	if (GCPhys != NIL_RTGCPHYS)
404	{
405	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
406
407	PPGMPAGE pPage;
408	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
409	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
410	{
411	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
412	{
413	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
414	{
415	/*
416	* Physical page access handler.
417	*/
418	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
419	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
420	if (pCur)
421	{
422	# ifdef PGM_SYNC_N_PAGES
423	/*
424	* If the region is write protected and we got a page not present fault, then sync
425	* the pages. If the fault was caused by a read, then restart the instruction.
426	* In case of write access continue to the GC write handler.
427	*
428	* ASSUMES that there is only one handler per page or that they have similar write properties.
429	*/
430	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
431	&& !(uErr & X86_TRAP_PF_P))
432	{
433	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
434	if ( RT_FAILURE(rc)
435	\|\| !(uErr & X86_TRAP_PF_RW)
436	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
437	{
438	AssertRC(rc);
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
440	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
441	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
442	return rc;
443	}
444	}
445	# endif
446
447	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
448	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
449	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
450
451	# if defined(IN_RC) \|\| defined(IN_RING0)
452	if (pCur->CTX_SUFF(pfnHandler))
453	{
454	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
455	# ifdef IN_RING0
456	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
457	# else
458	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
459	# endif
460	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
461	void *pvUser = pCur->CTX_SUFF(pvUser);
462
463	STAM_PROFILE_START(&pCur->Stat, h);
464	if (fLeaveLock)
465	pgmUnlock(pVM); /* @todo: Not entirely safe. */
466
467	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
468	if (fLeaveLock)
469	pgmLock(pVM);
470	# ifdef VBOX_WITH_STATISTICS
471	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
472	if (pCur)
473	STAM_PROFILE_STOP(&pCur->Stat, h);
474	# else
475	pCur = NULL; /* might be invalid by now. */
476	# endif
477
478	}
479	else
480	# endif
481	rc = VINF_EM_RAW_EMULATE_INSTR;
482
483	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
484	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
485	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
486	return rc;
487	}
488	}
489	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
490	else
491	{
492	# ifdef PGM_SYNC_N_PAGES
493	/*
494	* If the region is write protected and we got a page not present fault, then sync
495	* the pages. If the fault was caused by a read, then restart the instruction.
496	* In case of write access continue to the GC write handler.
497	*/
498	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
499	&& !(uErr & X86_TRAP_PF_P))
500	{
501	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
502	if ( RT_FAILURE(rc)
503	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
504	\|\| !(uErr & X86_TRAP_PF_RW))
505	{
506	AssertRC(rc);
507	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
508	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
509	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
510	return rc;
511	}
512	}
513	# endif
514	/*
515	* Ok, it's an virtual page access handler.
516	*
517	* Since it's faster to search by address, we'll do that first
518	* and then retry by GCPhys if that fails.
519	*/
520	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
521	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
522	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
523	*/
524	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
525	if (pCur)
526	{
527	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
528	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
529	\|\| !(uErr & X86_TRAP_PF_P)
530	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
531	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
532
533	if ( pvFault - pCur->Core.Key < pCur->cb
534	&& ( uErr & X86_TRAP_PF_RW
535	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
536	{
537	# ifdef IN_RC
538	STAM_PROFILE_START(&pCur->Stat, h);
539	pgmUnlock(pVM);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
541	pgmLock(pVM);
542	STAM_PROFILE_STOP(&pCur->Stat, h);
543	# else
544	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
545	# endif
546	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
547	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
548	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
549	return rc;
550	}
551	/* Unhandled part of a monitored page */
552	}
553	else
554	{
555	/* Check by physical address. */
556	unsigned iPage;
557	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
558	&pCur, &iPage);
559	Assert(RT_SUCCESS(rc) \|\| !pCur);
560	if ( pCur
561	&& ( uErr & X86_TRAP_PF_RW
562	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
563	{
564	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
565	# ifdef IN_RC
566	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
567	Assert(off < pCur->cb);
568	STAM_PROFILE_START(&pCur->Stat, h);
569	pgmUnlock(pVM);
570	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
571	pgmLock(pVM);
572	STAM_PROFILE_STOP(&pCur->Stat, h);
573	# else
574	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
575	# endif
576	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
577	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
578	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
579	return rc;
580	}
581	}
582	}
583	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
584
585	/*
586	* There is a handled area of the page, but this fault doesn't belong to it.
587	* We must emulate the instruction.
588	*
589	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
590	* we first check if this was a page-not-present fault for a page with only
591	* write access handlers. Restart the instruction if it wasn't a write access.
592	*/
593	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
594
595	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
596	&& !(uErr & X86_TRAP_PF_P))
597	{
598	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
599	if ( RT_FAILURE(rc)
600	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
601	\|\| !(uErr & X86_TRAP_PF_RW))
602	{
603	AssertRC(rc);
604	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
605	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
606	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
607	return rc;
608	}
609	}
610
611	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
612	* It's writing to an unhandled part of the LDT page several million times.
613	*/
614	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
615	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
616	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
617	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
618	return rc;
619	} /* if any kind of handler */
620
621	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
622	if (uErr & X86_TRAP_PF_P)
623	{
624	/*
625	* The page isn't marked, but it might still be monitored by a virtual page access handler.
626	* (ASSUMES no temporary disabling of virtual handlers.)
627	*/
628	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
629	* we should correct both the shadow page table and physical memory flags, and not only check for
630	* accesses within the handler region but for access to pages with virtual handlers. */
631	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
632	if (pCur)
633	{
634	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
635	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
636	\|\| !(uErr & X86_TRAP_PF_P)
637	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
638	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
639
640	if ( pvFault - pCur->Core.Key < pCur->cb
641	&& ( uErr & X86_TRAP_PF_RW
642	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
643	{
644	# ifdef IN_RC
645	STAM_PROFILE_START(&pCur->Stat, h);
646	pgmUnlock(pVM);
647	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
648	pgmLock(pVM);
649	STAM_PROFILE_STOP(&pCur->Stat, h);
650	# else
651	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
652	# endif
653	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
654	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
655	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
656	return rc;
657	}
658	}
659	}
660	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
661	}
662	else
663	{
664	/*
665	* When the guest accesses invalid physical memory (e.g. probing
666	* of RAM or accessing a remapped MMIO range), then we'll fall
667	* back to the recompiler to emulate the instruction.
668	*/
669	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
670	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
671	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
672	return VINF_EM_RAW_EMULATE_INSTR;
673	}
674
675	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
676
677	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
678	/*
679	* We are here only if page is present in Guest page tables and
680	* trap is not handled by our handlers.
681	*
682	* Check it for page out-of-sync situation.
683	*/
684	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
685
686	if (!(uErr & X86_TRAP_PF_P))
687	{
688	/*
689	* Page is not present in our page tables.
690	* Try to sync it!
691	* BTW, fPageShw is invalid in this branch!
692	*/
693	if (uErr & X86_TRAP_PF_US)
694	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
695	else /* supervisor */
696	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
697
698	# if defined(LOG_ENABLED) && !defined(IN_RING0)
699	RTGCPHYS GCPhys2;
700	uint64_t fPageGst2;
701	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
702	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
703	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
704	# endif /* LOG_ENABLED */
705
706	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
707	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
708	{
709	uint64_t fPageGst;
710	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
711	if ( RT_SUCCESS(rc)
712	&& !(fPageGst & X86_PTE_US))
713	{
714	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
715	if ( pvFault == (RTGCPTR)pRegFrame->eip
716	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
717	# ifdef CSAM_DETECT_NEW_CODE_PAGES
718	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
719	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
720	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
721	)
722	{
723	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
724	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
725	if (rc != VINF_SUCCESS)
726	{
727	/*
728	* CSAM needs to perform a job in ring 3.
729	*
730	* Sync the page before going to the host context; otherwise we'll end up in a loop if
731	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
732	*/
733	LogFlow(("CSAM ring 3 job\n"));
734	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
735	AssertRC(rc2);
736
737	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
739	return rc;
740	}
741	}
742	# ifdef CSAM_DETECT_NEW_CODE_PAGES
743	else if ( uErr == X86_TRAP_PF_RW
744	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
745	&& pRegFrame->ecx < 0x10000)
746	{
747	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
748	* to detect loading of new code pages.
749	*/
750
751	/*
752	* Decode the instruction.
753	*/
754	RTGCPTR PC;
755	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
756	if (rc == VINF_SUCCESS)
757	{
758	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
759	uint32_t cbOp;
760	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
761
762	/* For now we'll restrict this to rep movsw/d instructions */
763	if ( rc == VINF_SUCCESS
764	&& pDis->pCurInstr->opcode == OP_MOVSWD
765	&& (pDis->prefix & PREFIX_REP))
766	{
767	CSAMMarkPossibleCodePage(pVM, pvFault);
768	}
769	}
770	}
771	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
772
773	/*
774	* Mark this page as safe.
775	*/
776	/** @todo not correct for pages that contain both code and data!! */
777	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
778	CSAMMarkPage(pVM, pvFault, true);
779	}
780	}
781	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
782	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
783	if (RT_SUCCESS(rc))
784	{
785	/* The page was successfully synced, return to the guest. */
786	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
787	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
788	return VINF_SUCCESS;
789	}
790	}
791	else /* uErr & X86_TRAP_PF_P: */
792	{
793	/*
794	* Write protected pages are make writable when the guest makes the first
795	* write to it. This happens for pages that are shared, write monitored
796	* and not yet allocated.
797	*
798	* Also, a side effect of not flushing global PDEs are out of sync pages due
799	* to physical monitored regions, that are no longer valid.
800	* Assume for now it only applies to the read/write flag.
801	*/
802	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
803	{
804	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
805	{
806	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
807	GCPhys, pPage, pvFault, uErr));
808	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
809	if (rc != VINF_SUCCESS)
810	{
811	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
812	return rc;
813	}
814	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
815	return VINF_EM_NO_MEMORY;
816	}
817
818	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
819	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
820	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
821	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
822	{
823	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
824	uint64_t fPageGst;
825	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
826	if ( RT_SUCCESS(rc)
827	&& !(fPageGst & X86_PTE_RW))
828	{
829	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
830	if (RT_SUCCESS(rc))
831	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
832	else
833	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
834	return rc;
835	}
836	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
837	}
838	# endif
839	/// @todo count the above case; else
840	if (uErr & X86_TRAP_PF_US)
841	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
842	else /* supervisor */
843	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
844
845	/*
846	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
847	* page is not present, which is not true in this case.
848	*/
849	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
850	if (RT_SUCCESS(rc))
851	{
852	/*
853	* Page was successfully synced, return to guest.
854	* First invalidate the page as it might be in the TLB.
855	*/
856	# if PGM_SHW_TYPE == PGM_TYPE_EPT
857	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
858	# else
859	PGM_INVL_PG(pVCpu, pvFault);
860	# endif
861	# ifdef VBOX_STRICT
862	RTGCPHYS GCPhys2;
863	uint64_t fPageGst;
864	if (!HWACCMIsNestedPagingActive(pVM))
865	{
866	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
867	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
868	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
869	}
870	uint64_t fPageShw;
871	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
872	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
873	# endif /* VBOX_STRICT */
874	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
875	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
876	return VINF_SUCCESS;
877	}
878	}
879
880	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
881	# ifdef VBOX_STRICT
882	/*
883	* Check for VMM page flags vs. Guest page flags consistency.
884	* Currently only for debug purposes.
885	*/
886	if (RT_SUCCESS(rc))
887	{
888	/* Get guest page flags. */
889	uint64_t fPageGst;
890	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
891	if (RT_SUCCESS(rc))
892	{
893	uint64_t fPageShw;
894	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
895
896	/*
897	* Compare page flags.
898	* Note: we have AVL, A, D bits desynched.
899	*/
900	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
901	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
902	}
903	else
904	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
905	}
906	else
907	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
908	# endif /* VBOX_STRICT */
909	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
910	}
911	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
912	# endif /* PGM_OUT_OF_SYNC_IN_GC */
913	}
914	else /* GCPhys == NIL_RTGCPHYS */
915	{
916	/*
917	* Page not present in Guest OS or invalid page table address.
918	* This is potential virtual page access handler food.
919	*
920	* For the present we'll say that our access handlers don't
921	* work for this case - we've already discarded the page table
922	* not present case which is identical to this.
923	*
924	* When we perchance find we need this, we will probably have AVL
925	* trees (offset based) to operate on and we can measure their speed
926	* agains mapping a page table and probably rearrange this handling
927	* a bit. (Like, searching virtual ranges before checking the
928	* physical address.)
929	*/
930	}
931	}
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
934	/*
935	* Conclusion, this is a guest trap.
936	*/
937	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
938	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
939	return VINF_EM_RAW_GUEST_TRAP;
940	# else
941	/* present, but not a monitored page; perhaps the guest is probing physical memory */
942	return VINF_EM_RAW_EMULATE_INSTR;
943	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
944
945
946	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
947
948	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
949	return VERR_INTERNAL_ERROR;
950	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
951	}
952	#endif /* !IN_RING3 */
953
954
955	/**
956	* Emulation of the invlpg instruction.
957	*
958	*
959	* @returns VBox status code.
960	*
961	* @param pVCpu The VMCPU handle.
962	* @param GCPtrPage Page to invalidate.
963	*
964	* @remark ASSUMES that the guest is updating before invalidating. This order
965	* isn't required by the CPU, so this is speculative and could cause
966	* trouble.
967	* @remark No TLB shootdown is done on any other VCPU as we assume that
968	* invlpg emulation is the only reason for calling this function.
969	* (The guest has to shoot down TLB entries on other CPUs itself)
970	* Currently true, but keep in mind!
971	*
972	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
973	*/
974	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
975	{
976	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
977	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
978	&& PGM_SHW_TYPE != PGM_TYPE_EPT
979	int rc;
980	PVM pVM = pVCpu->CTX_SUFF(pVM);
981	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
982
983	Assert(PGMIsLockOwner(pVM));
984
985	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
986
987	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
988	if (pPool->cDirtyPages)
989	pgmPoolResetDirtyPages(pVM);
990	# endif
991
992	/*
993	* Get the shadow PD entry and skip out if this PD isn't present.
994	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
995	*/
996	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
997	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
998	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
999
1000	/* Fetch the pgm pool shadow descriptor. */
1001	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1002	Assert(pShwPde);
1003
1004	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1005	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1006	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
1007
1008	/* If the shadow PDPE isn't present, then skip the invalidate. */
1009	if (!pPdptDst->a[iPdpt].n.u1Present)
1010	{
1011	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1012	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1013	return VINF_SUCCESS;
1014	}
1015
1016	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1017	PPGMPOOLPAGE pShwPde = NULL;
1018	PX86PDPAE pPDDst;
1019
1020	/* Fetch the pgm pool shadow descriptor. */
1021	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1022	AssertRCSuccessReturn(rc, rc);
1023	Assert(pShwPde);
1024
1025	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1026	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1027
1028	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1029	/* PML4 */
1030	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1031	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1032	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1033	PX86PDPAE pPDDst;
1034	PX86PDPT pPdptDst;
1035	PX86PML4E pPml4eDst;
1036	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1037	if (rc != VINF_SUCCESS)
1038	{
1039	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1041	return VINF_SUCCESS;
1042	}
1043	Assert(pPDDst);
1044
1045	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1046	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1047
1048	if (!pPdpeDst->n.u1Present)
1049	{
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1051	return VINF_SUCCESS;
1052	}
1053
1054	/* Fetch the pgm pool shadow descriptor. */
1055	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1056	Assert(pShwPde);
1057
1058	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1059
1060	const SHWPDE PdeDst = *pPdeDst;
1061	if (!PdeDst.n.u1Present)
1062	{
1063	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1064	return VINF_SUCCESS;
1065	}
1066
1067	# if defined(IN_RC)
1068	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1069	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1070	# endif
1071
1072	/*
1073	* Get the guest PD entry and calc big page.
1074	*/
1075	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1076	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1077	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1078	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1079	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1080	unsigned iPDSrc = 0;
1081	# if PGM_GST_TYPE == PGM_TYPE_PAE
1082	X86PDPE PdpeSrc;
1083	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1084	# else /* AMD64 */
1085	PX86PML4E pPml4eSrc;
1086	X86PDPE PdpeSrc;
1087	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1088	# endif
1089	GSTPDE PdeSrc;
1090
1091	if (pPDSrc)
1092	PdeSrc = pPDSrc->a[iPDSrc];
1093	else
1094	PdeSrc.u = 0;
1095	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1098	const bool fIsBigPage = PdeSrc.b.u1Size;
1099	# else
1100	const bool fIsBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1101	# endif
1102
1103	# ifdef IN_RING3
1104	/*
1105	* If a CR3 Sync is pending we may ignore the invalidate page operation
1106	* depending on the kind of sync and if it's a global page or not.
1107	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1108	*/
1109	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1110	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1111	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1112	&& fIsBigPage
1113	&& PdeSrc.b.u1Global
1114	)
1115	)
1116	# else
1117	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1118	# endif
1119	{
1120	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1121	return VINF_SUCCESS;
1122	}
1123	# endif /* IN_RING3 */
1124
1125	/*
1126	* Deal with the Guest PDE.
1127	*/
1128	rc = VINF_SUCCESS;
1129	if (PdeSrc.n.u1Present)
1130	{
1131	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1132	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1133	# ifndef PGM_WITHOUT_MAPPING
1134	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1135	{
1136	/*
1137	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1138	*/
1139	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1140	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1141	pgmLock(pVM);
1142	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1143	pgmUnlock(pVM);
1144	}
1145	else
1146	# endif /* !PGM_WITHOUT_MAPPING */
1147	if (!fIsBigPage)
1148	{
1149	/*
1150	* 4KB - page.
1151	*/
1152	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1153	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1154
1155	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1156	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1157	if (pShwPage->cModifications)
1158	pShwPage->cModifications = 1;
1159	# endif
1160
1161	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1162	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1163	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1164	# endif
1165	if (pShwPage->GCPhys == GCPhys)
1166	{
1167	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1168	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1169	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1170	if (pPT->a[iPTEDst].n.u1Present)
1171	{
1172	/* This is very unlikely with caching/monitoring enabled. */
1173	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1174	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1175	}
1176	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1177	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1178	if (RT_SUCCESS(rc))
1179	rc = VINF_SUCCESS;
1180	# endif
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1182	PGM_INVL_PG(pVCpu, GCPtrPage);
1183	}
1184	else
1185	{
1186	/*
1187	* The page table address changed.
1188	*/
1189	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1190	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1191	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1192	ASMAtomicWriteSize(pPdeDst, 0);
1193	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1194	PGM_INVL_VCPU_TLBS(pVCpu);
1195	}
1196	}
1197	else
1198	{
1199	/*
1200	* 2/4MB - page.
1201	*/
1202	/* Before freeing the page, check if anything really changed. */
1203	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1204	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1205	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1206	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1207	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1208	# endif
1209	if ( pShwPage->GCPhys == GCPhys
1210	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1211	{
1212	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1213	/** @todo PAT */
1214	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1215	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1216	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1217	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1218	{
1219	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1220	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1221	# if defined(IN_RC)
1222	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1223	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1224	# endif
1225	return VINF_SUCCESS;
1226	}
1227	}
1228
1229	/*
1230	* Ok, the page table is present and it's been changed in the guest.
1231	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1232	* We could do this for some flushes in GC too, but we need an algorithm for
1233	* deciding which 4MB pages containing code likely to be executed very soon.
1234	*/
1235	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1236	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1237	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1238	ASMAtomicWriteSize(pPdeDst, 0);
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1240	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1241	}
1242	}
1243	else
1244	{
1245	/*
1246	* Page directory is not present, mark shadow PDE not present.
1247	*/
1248	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1249	{
1250	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1251	ASMAtomicWriteSize(pPdeDst, 0);
1252	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1253	PGM_INVL_PG(pVCpu, GCPtrPage);
1254	}
1255	else
1256	{
1257	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1258	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1259	}
1260	}
1261	# if defined(IN_RC)
1262	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1263	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1264	# endif
1265	return rc;
1266
1267	#else /* guest real and protected mode */
1268	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1269	return VINF_SUCCESS;
1270	#endif
1271	}
1272
1273
1274	/**
1275	* Update the tracking of shadowed pages.
1276	*
1277	* @param pVCpu The VMCPU handle.
1278	* @param pShwPage The shadow page.
1279	* @param HCPhys The physical page we is being dereferenced.
1280	*/
1281	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1282	{
1283	PVM pVM = pVCpu->CTX_SUFF(pVM);
1284
1285	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1286	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1287
1288	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1289	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1290	* 2. write protect all shadowed pages. I.e. implement caching.
1291	*/
1292	/*
1293	* Find the guest address.
1294	*/
1295	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1296	pRam;
1297	pRam = pRam->CTX_SUFF(pNext))
1298	{
1299	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1300	while (iPage-- > 0)
1301	{
1302	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1303	{
1304	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1305	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1306	pShwPage->cPresent--;
1307	pPool->cPresent--;
1308	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1309	return;
1310	}
1311	}
1312	}
1313
1314	for (;;)
1315	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1316	}
1317
1318
1319	/**
1320	* Update the tracking of shadowed pages.
1321	*
1322	* @param pVCpu The VMCPU handle.
1323	* @param pShwPage The shadow page.
1324	* @param u16 The top 16-bit of the pPage->HCPhys.
1325	* @param pPage Pointer to the guest page. this will be modified.
1326	* @param iPTDst The index into the shadow table.
1327	*/
1328	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1329	{
1330	PVM pVM = pVCpu->CTX_SUFF(pVM);
1331	/*
1332	* Just deal with the simple first time here.
1333	*/
1334	if (!u16)
1335	{
1336	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1337	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1338	}
1339	else
1340	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1341
1342	/* write back */
1343	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1344	PGM_PAGE_SET_TRACKING(pPage, u16);
1345
1346	/* update statistics. */
1347	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1348	pShwPage->cPresent++;
1349	if (pShwPage->iFirstPresent > iPTDst)
1350	pShwPage->iFirstPresent = iPTDst;
1351	}
1352
1353
1354	/**
1355	* Creates a 4K shadow page for a guest page.
1356	*
1357	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1358	* physical address. The PdeSrc argument only the flags are used. No page structured
1359	* will be mapped in this function.
1360	*
1361	* @param pVCpu The VMCPU handle.
1362	* @param pPteDst Destination page table entry.
1363	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1364	* Can safely assume that only the flags are being used.
1365	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1366	* @param pShwPage Pointer to the shadow page.
1367	* @param iPTDst The index into the shadow table.
1368	*
1369	* @remark Not used for 2/4MB pages!
1370	*/
1371	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1372	{
1373	if (PteSrc.n.u1Present)
1374	{
1375	PVM pVM = pVCpu->CTX_SUFF(pVM);
1376
1377	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1378	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1379	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1380	if (pShwPage->fDirty)
1381	{
1382	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1383	PX86PTPAE pGstPT;
1384
1385	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1386	pGstPT->a[iPTDst].u = PteSrc.u;
1387	}
1388	# endif
1389	/*
1390	* Find the ram range.
1391	*/
1392	PPGMPAGE pPage;
1393	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1394	if (RT_SUCCESS(rc))
1395	{
1396	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1397	/* Try make the page writable if necessary. */
1398	if ( PteSrc.n.u1Write
1399	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1400	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1401	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1402	# endif
1403	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1404	{
1405	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1406	AssertRC(rc);
1407	}
1408	#endif
1409
1410	/** @todo investiage PWT, PCD and PAT. */
1411	/*
1412	* Make page table entry.
1413	*/
1414	SHWPTE PteDst;
1415	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1416	{
1417	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1418	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1419	{
1420	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1421	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1422	PteDst.n.u1Present = 1;
1423	PteDst.n.u1Execute = 1;
1424	PteDst.n.u1IgnorePAT = 1;
1425	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1426	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1427	#else
1428	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1429	\| PGM_PAGE_GET_HCPHYS(pPage);
1430	#endif
1431	}
1432	else
1433	{
1434	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1435	PteDst.u = 0;
1436	}
1437	/** @todo count these two kinds. */
1438	}
1439	else
1440	{
1441	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1442	/*
1443	* If the page or page directory entry is not marked accessed,
1444	* we mark the page not present.
1445	*/
1446	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1447	{
1448	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1449	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1450	PteDst.u = 0;
1451	}
1452	else
1453	/*
1454	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1455	* when the page is modified.
1456	*/
1457	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1458	{
1459	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1460	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1461	\| PGM_PAGE_GET_HCPHYS(pPage)
1462	\| PGM_PTFLAGS_TRACK_DIRTY;
1463	}
1464	else
1465	#endif
1466	{
1467	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1468	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1469	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1470	PteDst.n.u1Present = 1;
1471	PteDst.n.u1Write = 1;
1472	PteDst.n.u1Execute = 1;
1473	PteDst.n.u1IgnorePAT = 1;
1474	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1475	/* PteDst.n.u1Size = 0 */
1476	#else
1477	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1478	\| PGM_PAGE_GET_HCPHYS(pPage);
1479	#endif
1480	}
1481	}
1482
1483	/*
1484	* Make sure only allocated pages are mapped writable.
1485	*/
1486	if ( PteDst.n.u1Write
1487	&& PteDst.n.u1Present
1488	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1489	{
1490	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1491	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1492	}
1493
1494	/*
1495	* Keep user track up to date.
1496	*/
1497	if (PteDst.n.u1Present)
1498	{
1499	if (!pPteDst->n.u1Present)
1500	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1501	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1502	{
1503	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1504	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1505	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1506	}
1507	}
1508	else if (pPteDst->n.u1Present)
1509	{
1510	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1511	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1512	}
1513
1514	/*
1515	* Update statistics and commit the entry.
1516	*/
1517	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1518	if (!PteSrc.n.u1Global)
1519	pShwPage->fSeenNonGlobal = true;
1520	#endif
1521	ASMAtomicWriteSize(pPteDst, PteDst.u);
1522	}
1523	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1524	/** @todo count these. */
1525	}
1526	else
1527	{
1528	/*
1529	* Page not-present.
1530	*/
1531	Log2(("SyncPageWorker: page not present in Pte\n"));
1532	/* Keep user track up to date. */
1533	if (pPteDst->n.u1Present)
1534	{
1535	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1536	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1537	}
1538	ASMAtomicWriteSize(pPteDst, 0);
1539	/** @todo count these. */
1540	}
1541	}
1542
1543
1544	/**
1545	* Syncs a guest OS page.
1546	*
1547	* There are no conflicts at this point, neither is there any need for
1548	* page table allocations.
1549	*
1550	* @returns VBox status code.
1551	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1552	* @param pVCpu The VMCPU handle.
1553	* @param PdeSrc Page directory entry of the guest.
1554	* @param GCPtrPage Guest context page address.
1555	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1556	* @param uErr Fault error (X86_TRAP_PF_*).
1557	*/
1558	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1559	{
1560	PVM pVM = pVCpu->CTX_SUFF(pVM);
1561	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1562	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1563
1564	Assert(PGMIsLockOwner(pVM));
1565
1566	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1567	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1568	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1569	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1570	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1571
1572	/*
1573	* Assert preconditions.
1574	*/
1575	Assert(PdeSrc.n.u1Present);
1576	Assert(cPages);
1577	# if 0 /* rarely useful; leave for debugging. */
1578	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1579	# endif
1580
1581	/*
1582	* Get the shadow PDE, find the shadow page table in the pool.
1583	*/
1584	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1585	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1586	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1587
1588	/* Fetch the pgm pool shadow descriptor. */
1589	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1590	Assert(pShwPde);
1591
1592	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1593	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1594	PPGMPOOLPAGE pShwPde = NULL;
1595	PX86PDPAE pPDDst;
1596
1597	/* Fetch the pgm pool shadow descriptor. */
1598	int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1599	AssertRCSuccessReturn(rc2, rc2);
1600	Assert(pShwPde);
1601
1602	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1603	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1604
1605	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1606	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1607	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1608	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1609	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1610
1611	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1612	AssertRCSuccessReturn(rc2, rc2);
1613	Assert(pPDDst && pPdptDst);
1614	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1615	# endif
1616	SHWPDE PdeDst = *pPdeDst;
1617	if (!PdeDst.n.u1Present)
1618	{
1619	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1620	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1621	return VINF_SUCCESS; /* force the instruction to be executed again. */
1622	}
1623
1624	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1625	Assert(pShwPage);
1626
1627	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1628	/* Fetch the pgm pool shadow descriptor. */
1629	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1630	Assert(pShwPde);
1631	# endif
1632
1633	# if defined(IN_RC)
1634	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1635	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1636	# endif
1637
1638	/*
1639	* Check that the page is present and that the shadow PDE isn't out of sync.
1640	*/
1641	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1642	const bool fBigPage = PdeSrc.b.u1Size;
1643	# else
1644	const bool fBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1645	# endif
1646	RTGCPHYS GCPhys;
1647	if (!fBigPage)
1648	{
1649	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1650	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1651	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1652	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1653	# endif
1654	}
1655	else
1656	{
1657	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1658	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1659	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1660	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1661	# endif
1662	}
1663	if ( pShwPage->GCPhys == GCPhys
1664	&& PdeSrc.n.u1Present
1665	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1666	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1667	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1668	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !CPUMIsGuestNXEnabled(pVCpu))
1669	# endif
1670	)
1671	{
1672	/*
1673	* Check that the PDE is marked accessed already.
1674	* Since we set the accessed bit before getting here on a #PF, this
1675	* check is only meant for dealing with non-#PF'ing paths.
1676	*/
1677	if (PdeSrc.n.u1Accessed)
1678	{
1679	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1680	if (!fBigPage)
1681	{
1682	/*
1683	* 4KB Page - Map the guest page table.
1684	*/
1685	PGSTPT pPTSrc;
1686	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1687	if (RT_SUCCESS(rc))
1688	{
1689	# ifdef PGM_SYNC_N_PAGES
1690	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1691	if ( cPages > 1
1692	&& !(uErr & X86_TRAP_PF_P)
1693	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1694	{
1695	/*
1696	* This code path is currently only taken when the caller is PGMTrap0eHandler
1697	* for non-present pages!
1698	*
1699	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1700	* deal with locality.
1701	*/
1702	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1703	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1704	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1705	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1706	# else
1707	const unsigned offPTSrc = 0;
1708	# endif
1709	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1710	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1711	iPTDst = 0;
1712	else
1713	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1714	for (; iPTDst < iPTDstEnd; iPTDst++)
1715	{
1716	if (!pPTDst->a[iPTDst].n.u1Present)
1717	{
1718	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1719	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1720	NOREF(GCPtrCurPage);
1721	#ifndef IN_RING0
1722	/*
1723	* Assuming kernel code will be marked as supervisor - and not as user level
1724	* and executed using a conforming code selector - And marked as readonly.
1725	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1726	*/
1727	PPGMPAGE pPage;
1728	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1729	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1730	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1731	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1732	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1733	)
1734	#endif /* else: CSAM not active */
1735	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1736	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1737	GCPtrCurPage, PteSrc.n.u1Present,
1738	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1739	PteSrc.n.u1User & PdeSrc.n.u1User,
1740	(uint64_t)PteSrc.u,
1741	(uint64_t)pPTDst->a[iPTDst].u,
1742	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1743	}
1744	}
1745	}
1746	else
1747	# endif /* PGM_SYNC_N_PAGES */
1748	{
1749	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1750	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1751	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1752	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1753	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1754	GCPtrPage, PteSrc.n.u1Present,
1755	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1756	PteSrc.n.u1User & PdeSrc.n.u1User,
1757	(uint64_t)PteSrc.u,
1758	(uint64_t)pPTDst->a[iPTDst].u,
1759	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1760	}
1761	}
1762	else /* MMIO or invalid page: emulated in #PF handler. */
1763	{
1764	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1765	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1766	}
1767	}
1768	else
1769	{
1770	/*
1771	* 4/2MB page - lazy syncing shadow 4K pages.
1772	* (There are many causes of getting here, it's no longer only CSAM.)
1773	*/
1774	/* Calculate the GC physical address of this 4KB shadow page. */
1775	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1776	/* Find ram range. */
1777	PPGMPAGE pPage;
1778	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1779	if (RT_SUCCESS(rc))
1780	{
1781	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1782	/* Try make the page writable if necessary. */
1783	if ( PdeSrc.n.u1Write
1784	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1785	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1786	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1787	# endif
1788	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1789	{
1790	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1791	AssertRC(rc);
1792	}
1793	# endif
1794
1795	/*
1796	* Make shadow PTE entry.
1797	*/
1798	SHWPTE PteDst;
1799	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1800	\| PGM_PAGE_GET_HCPHYS(pPage);
1801	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1802	{
1803	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1804	PteDst.n.u1Write = 0;
1805	else
1806	PteDst.u = 0;
1807	}
1808	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1809	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1810	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1811
1812	/* Make sure only allocated pages are mapped writable. */
1813	if ( PteDst.n.u1Write
1814	&& PteDst.n.u1Present
1815	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1816	{
1817	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1818	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1819	}
1820
1821	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1822
1823	/*
1824	* If the page is not flagged as dirty and is writable, then make it read-only
1825	* at PD level, so we can set the dirty bit when the page is modified.
1826	*
1827	* ASSUMES that page access handlers are implemented on page table entry level.
1828	* Thus we will first catch the dirty access and set PDE.D and restart. If
1829	* there is an access handler, we'll trap again and let it work on the problem.
1830	*/
1831	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1832	* As for invlpg, it simply frees the whole shadow PT.
1833	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1834	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1835	{
1836	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1837	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1838	PdeDst.n.u1Write = 0;
1839	}
1840	else
1841	{
1842	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1843	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1844	}
1845	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1846	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1847	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1848	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1849	}
1850	else
1851	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1852	}
1853	# if defined(IN_RC)
1854	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1855	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1856	# endif
1857	return VINF_SUCCESS;
1858	}
1859	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1860	}
1861	else
1862	{
1863	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1864	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1865	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1866	}
1867
1868	/*
1869	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1870	* Yea, I'm lazy.
1871	*/
1872	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1873	ASMAtomicWriteSize(pPdeDst, 0);
1874
1875	# if defined(IN_RC)
1876	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1877	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1878	# endif
1879	PGM_INVL_VCPU_TLBS(pVCpu);
1880	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1881
1882	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1883	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1884	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1885	&& !defined(IN_RC)
1886
1887	# ifdef PGM_SYNC_N_PAGES
1888	/*
1889	* Get the shadow PDE, find the shadow page table in the pool.
1890	*/
1891	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1892	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1893
1894	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1895	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1896
1897	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1898	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1899	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1900	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1901	X86PDEPAE PdeDst;
1902	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1903
1904	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1905	AssertRCSuccessReturn(rc, rc);
1906	Assert(pPDDst && pPdptDst);
1907	PdeDst = pPDDst->a[iPDDst];
1908	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1909	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1910	PEPTPD pPDDst;
1911	EPTPDE PdeDst;
1912
1913	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1914	if (rc != VINF_SUCCESS)
1915	{
1916	AssertRC(rc);
1917	return rc;
1918	}
1919	Assert(pPDDst);
1920	PdeDst = pPDDst->a[iPDDst];
1921	# endif
1922	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1923	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1924	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1925
1926	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1927	if ( cPages > 1
1928	&& !(uErr & X86_TRAP_PF_P)
1929	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1930	{
1931	/*
1932	* This code path is currently only taken when the caller is PGMTrap0eHandler
1933	* for non-present pages!
1934	*
1935	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1936	* deal with locality.
1937	*/
1938	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1939	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1940	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1941	iPTDst = 0;
1942	else
1943	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1944	for (; iPTDst < iPTDstEnd; iPTDst++)
1945	{
1946	if (!pPTDst->a[iPTDst].n.u1Present)
1947	{
1948	GSTPTE PteSrc;
1949
1950	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1951
1952	/* Fake the page table entry */
1953	PteSrc.u = GCPtrCurPage;
1954	PteSrc.n.u1Present = 1;
1955	PteSrc.n.u1Dirty = 1;
1956	PteSrc.n.u1Accessed = 1;
1957	PteSrc.n.u1Write = 1;
1958	PteSrc.n.u1User = 1;
1959
1960	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1961
1962	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1963	GCPtrCurPage, PteSrc.n.u1Present,
1964	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1965	PteSrc.n.u1User & PdeSrc.n.u1User,
1966	(uint64_t)PteSrc.u,
1967	(uint64_t)pPTDst->a[iPTDst].u,
1968	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1969
1970	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
1971	break;
1972	}
1973	else
1974	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1975	}
1976	}
1977	else
1978	# endif /* PGM_SYNC_N_PAGES */
1979	{
1980	GSTPTE PteSrc;
1981	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1982	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1983
1984	/* Fake the page table entry */
1985	PteSrc.u = GCPtrCurPage;
1986	PteSrc.n.u1Present = 1;
1987	PteSrc.n.u1Dirty = 1;
1988	PteSrc.n.u1Accessed = 1;
1989	PteSrc.n.u1Write = 1;
1990	PteSrc.n.u1User = 1;
1991	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1992
1993	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1994	GCPtrPage, PteSrc.n.u1Present,
1995	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1996	PteSrc.n.u1User & PdeSrc.n.u1User,
1997	(uint64_t)PteSrc.u,
1998	(uint64_t)pPTDst->a[iPTDst].u,
1999	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2000	}
2001	return VINF_SUCCESS;
2002
2003	#else
2004	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2005	return VERR_INTERNAL_ERROR;
2006	#endif
2007	}
2008
2009
2010	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2011	/**
2012	* Investigate page fault and handle write protection page faults caused by
2013	* dirty bit tracking.
2014	*
2015	* @returns VBox status code.
2016	* @param pVCpu The VMCPU handle.
2017	* @param uErr Page fault error code.
2018	* @param pPdeSrc Guest page directory entry.
2019	* @param GCPtrPage Guest context page address.
2020	*/
2021	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2022	{
2023	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2024	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2025	bool fMaybeWriteProtFault = fWriteFault && (fUserLevelFault \|\| CPUMIsGuestR0WriteProtEnabled(pVCpu));
2026	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2027	bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && CPUMIsGuestNXEnabled(pVCpu);
2028	# endif
2029	unsigned uPageFaultLevel;
2030	int rc;
2031	PVM pVM = pVCpu->CTX_SUFF(pVM);
2032
2033	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2034
2035	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2036	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2037
2038	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2039	PX86PML4E pPml4eSrc;
2040	PX86PDPE pPdpeSrc;
2041
2042	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2043	Assert(pPml4eSrc);
2044
2045	/*
2046	* Real page fault? (PML4E level)
2047	*/
2048	if ( (uErr & X86_TRAP_PF_RSVD)
2049	\|\| !pPml4eSrc->n.u1Present
2050	\|\| (fMaybeWriteProtFault && !pPml4eSrc->n.u1Write)
2051	\|\| (fMaybeNXEFault && pPml4eSrc->n.u1NoExecute)
2052	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2053	)
2054	{
2055	uPageFaultLevel = 0;
2056	goto l_UpperLevelPageFault;
2057	}
2058	Assert(pPdpeSrc);
2059
2060	# else /* PAE */
2061	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2062	# endif /* PAE */
2063
2064	/*
2065	* Real page fault? (PDPE level)
2066	*/
2067	if ( (uErr & X86_TRAP_PF_RSVD)
2068	\|\| !pPdpeSrc->n.u1Present
2069	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2070	\|\| (fMaybeWriteProtFault && !pPdpeSrc->lm.u1Write)
2071	\|\| (fMaybeNXEFault && pPdpeSrc->lm.u1NoExecute)
2072	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2073	# endif
2074	)
2075	{
2076	uPageFaultLevel = 1;
2077	goto l_UpperLevelPageFault;
2078	}
2079	# endif
2080
2081	/*
2082	* Real page fault? (PDE level)
2083	*/
2084	if ( (uErr & X86_TRAP_PF_RSVD)
2085	\|\| !pPdeSrc->n.u1Present
2086	\|\| (fMaybeWriteProtFault && !pPdeSrc->n.u1Write)
2087	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2088	\|\| (fMaybeNXEFault && pPdeSrc->n.u1NoExecute)
2089	# endif
2090	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2091	{
2092	uPageFaultLevel = 2;
2093	goto l_UpperLevelPageFault;
2094	}
2095
2096	/*
2097	* First check the easy case where the page directory has been marked read-only to track
2098	* the dirty bit of an emulated BIG page
2099	*/
2100	if ( pPdeSrc->b.u1Size
2101	# if PGM_GST_TYPE != PGM_TYPE_AMD64
2102	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2103	# endif
2104	)
2105	{
2106	/* Mark guest page directory as accessed */
2107	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2108	pPml4eSrc->n.u1Accessed = 1;
2109	pPdpeSrc->lm.u1Accessed = 1;
2110	# endif
2111	pPdeSrc->b.u1Accessed = 1;
2112
2113	/*
2114	* Only write protection page faults are relevant here.
2115	*/
2116	if (fWriteFault)
2117	{
2118	/* Mark guest page directory as dirty (BIG page only). */
2119	pPdeSrc->b.u1Dirty = 1;
2120	}
2121	return VINF_SUCCESS;
2122	}
2123	/* else: 4KB page table */
2124
2125	/*
2126	* Map the guest page table.
2127	*/
2128	PGSTPT pPTSrc;
2129	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2130	if (RT_SUCCESS(rc))
2131	{
2132	/*
2133	* Real page fault?
2134	*/
2135	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2136	const GSTPTE PteSrc = *pPteSrc;
2137	if ( !PteSrc.n.u1Present
2138	\|\| (fMaybeWriteProtFault && !PteSrc.n.u1Write)
2139	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2140	\|\| (fMaybeNXEFault && PteSrc.n.u1NoExecute)
2141	# endif
2142	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2143	)
2144	{
2145	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2146	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2147
2148	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2149	* See the 2nd case above as well.
2150	*/
2151	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2152	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2153
2154	return VINF_EM_RAW_GUEST_TRAP;
2155	}
2156	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2157
2158	/*
2159	* Set the accessed bits in the page directory and the page table.
2160	*/
2161	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2162	pPml4eSrc->n.u1Accessed = 1;
2163	pPdpeSrc->lm.u1Accessed = 1;
2164	# endif
2165	pPdeSrc->n.u1Accessed = 1;
2166	pPteSrc->n.u1Accessed = 1;
2167
2168	/*
2169	* Only write protection page faults are relevant here.
2170	*/
2171	if (fWriteFault)
2172	{
2173	/* Write access, so mark guest entry as dirty. */
2174	# ifdef VBOX_WITH_STATISTICS
2175	if (!pPteSrc->n.u1Dirty)
2176	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2177	else
2178	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2179	# endif
2180
2181	pPteSrc->n.u1Dirty = 1;
2182	}
2183	return VINF_SUCCESS;
2184	}
2185	AssertRC(rc);
2186	return rc;
2187
2188
2189	l_UpperLevelPageFault:
2190	/*
2191	* Pagefault detected while checking the PML4E, PDPE or PDE.
2192	* Single exit handler to get rid of duplicate code paths.
2193	*/
2194	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2195	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2196
2197	if ( 1
2198	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2199	&& pPml4eSrc->n.u1Present
2200	# endif
2201	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2202	&& pPdpeSrc->n.u1Present
2203	# endif
2204	&& pPdeSrc->n.u1Present)
2205	{
2206	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2207	if ( pPdeSrc->b.u1Size
2208	# if PGM_GST_TYPE != PGM_TYPE_AMD64
2209	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2210	# endif
2211	)
2212	{
2213	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2214	}
2215	else
2216	{
2217	/*
2218	* Map the guest page table.
2219	*/
2220	PGSTPT pPTSrc2;
2221	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc2);
2222	if (RT_SUCCESS(rc))
2223	{
2224	PGSTPTE pPteSrc = &pPTSrc2->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2225	if (pPteSrc->n.u1Present)
2226	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2227	}
2228	AssertRC(rc);
2229	}
2230	}
2231	return VINF_EM_RAW_GUEST_TRAP;
2232	}
2233
2234	/**
2235	* Handle dirty bit tracking faults.
2236	*
2237	* @returns VBox status code.
2238	* @param pVCpu The VMCPU handle.
2239	* @param uErr Page fault error code.
2240	* @param pPdeSrc Guest page directory entry.
2241	* @param pPdeDst Shadow page directory entry.
2242	* @param GCPtrPage Guest context page address.
2243	*/
2244	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2245	{
2246	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2247	const bool fBigPagesSupported = true;
2248	# else
2249	const bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2250	# endif
2251	PVM pVM = pVCpu->CTX_SUFF(pVM);
2252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2253
2254	Assert(PGMIsLockOwner(pVM));
2255
2256	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2257	{
2258	if ( pPdeDst->n.u1Present
2259	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2260	{
2261	SHWPDE PdeDst = *pPdeDst;
2262
2263	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2264	Assert(pPdeSrc->b.u1Write);
2265
2266	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2267	* fault again and take this path to only invalidate the entry.
2268	*/
2269	PdeDst.n.u1Write = 1;
2270	PdeDst.n.u1Accessed = 1;
2271	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2272	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2273	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2274	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2275	}
2276	# ifdef IN_RING0
2277	else
2278	/* Check for stale TLB entry; only applies to the SMP guest case. */
2279	if ( pVM->cCpus > 1
2280	&& pPdeDst->n.u1Write
2281	&& pPdeDst->n.u1Accessed)
2282	{
2283	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2284	if (pShwPage)
2285	{
2286	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2287	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2288	if ( pPteDst->n.u1Present
2289	&& pPteDst->n.u1Write)
2290	{
2291	/* Stale TLB entry. */
2292	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2293	PGM_INVL_PG(pVCpu, GCPtrPage);
2294	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2295	}
2296	}
2297	}
2298	# endif /* IN_RING0 */
2299	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2300	}
2301
2302	/*
2303	* Map the guest page table.
2304	*/
2305	PGSTPT pPTSrc;
2306	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2307	if (RT_SUCCESS(rc))
2308	{
2309	if (pPdeDst->n.u1Present)
2310	{
2311	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2312	const GSTPTE PteSrc = *pPteSrc;
2313	#ifndef IN_RING0
2314	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2315	* Our individual shadow handlers will provide more information and force a fatal exit.
2316	*/
2317	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2318	{
2319	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2320	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2321	}
2322	#endif
2323	/*
2324	* Map shadow page table.
2325	*/
2326	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2327	if (pShwPage)
2328	{
2329	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2330	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2331	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2332	{
2333	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2334	{
2335	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2336	SHWPTE PteDst = *pPteDst;
2337
2338	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2340
2341	Assert(pPteSrc->n.u1Write);
2342
2343	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2344	* fault again and take this path to only invalidate the entry.
2345	*/
2346	if (RT_LIKELY(pPage))
2347	{
2348	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2349	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2350	PteDst.n.u1Write = 0;
2351	else
2352	{
2353	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2354	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2355	{
2356	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2357	AssertRC(rc);
2358	}
2359	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2360	PteDst.n.u1Write = 1;
2361	else
2362	PteDst.n.u1Write = 0;
2363	}
2364	}
2365	else
2366	PteDst.n.u1Write = 1;
2367
2368	PteDst.n.u1Dirty = 1;
2369	PteDst.n.u1Accessed = 1;
2370	PteDst.au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2371	ASMAtomicWriteSize(pPteDst, PteDst.u);
2372	PGM_INVL_PG(pVCpu, GCPtrPage);
2373	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2374	}
2375	# ifdef IN_RING0
2376	else
2377	/* Check for stale TLB entry; only applies to the SMP guest case. */
2378	if ( pVM->cCpus > 1
2379	&& pPteDst->n.u1Write == 1
2380	&& pPteDst->n.u1Accessed == 1)
2381	{
2382	/* Stale TLB entry. */
2383	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2384	PGM_INVL_PG(pVCpu, GCPtrPage);
2385	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2386	}
2387	# endif
2388	}
2389	}
2390	else
2391	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2392	}
2393	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2394	}
2395	AssertRC(rc);
2396	return rc;
2397	}
2398	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2399
2400
2401	/**
2402	* Sync a shadow page table.
2403	*
2404	* The shadow page table is not present. This includes the case where
2405	* there is a conflict with a mapping.
2406	*
2407	* @returns VBox status code.
2408	* @param pVCpu The VMCPU handle.
2409	* @param iPD Page directory index.
2410	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2411	* Assume this is a temporary mapping.
2412	* @param GCPtrPage GC Pointer of the page that caused the fault
2413	*/
2414	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2415	{
2416	PVM pVM = pVCpu->CTX_SUFF(pVM);
2417	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2418
2419	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2420	#if 0 /* rarely useful; leave for debugging. */
2421	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2422	#endif
2423	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2424
2425	Assert(PGMIsLocked(pVM));
2426
2427	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2428	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2429	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2430	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2431	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2432
2433	int rc = VINF_SUCCESS;
2434
2435	/*
2436	* Validate input a little bit.
2437	*/
2438	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2439	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2440	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2441	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2442
2443	/* Fetch the pgm pool shadow descriptor. */
2444	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2445	Assert(pShwPde);
2446
2447	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2448	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2449	PPGMPOOLPAGE pShwPde = NULL;
2450	PX86PDPAE pPDDst;
2451	PSHWPDE pPdeDst;
2452
2453	/* Fetch the pgm pool shadow descriptor. */
2454	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2455	AssertRCSuccessReturn(rc, rc);
2456	Assert(pShwPde);
2457
2458	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2459	pPdeDst = &pPDDst->a[iPDDst];
2460
2461	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2462	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2463	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2464	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2465	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2466	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2467	AssertRCSuccessReturn(rc, rc);
2468	Assert(pPDDst);
2469	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2470	# endif
2471	SHWPDE PdeDst = *pPdeDst;
2472
2473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2474	/* Fetch the pgm pool shadow descriptor. */
2475	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2476	Assert(pShwPde);
2477	# endif
2478
2479	# ifndef PGM_WITHOUT_MAPPINGS
2480	/*
2481	* Check for conflicts.
2482	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2483	* HC: Simply resolve the conflict.
2484	*/
2485	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2486	{
2487	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2488	# ifndef IN_RING3
2489	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2490	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2491	return VERR_ADDRESS_CONFLICT;
2492	# else
2493	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2494	Assert(pMapping);
2495	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2496	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2497	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2498	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2499	# else
2500	AssertFailed(); /* can't happen for amd64 */
2501	# endif
2502	if (RT_FAILURE(rc))
2503	{
2504	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2505	return rc;
2506	}
2507	PdeDst = *pPdeDst;
2508	# endif
2509	}
2510	# endif /* !PGM_WITHOUT_MAPPINGS */
2511	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2512
2513	# if defined(IN_RC)
2514	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2515	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2516	# endif
2517
2518	/*
2519	* Sync page directory entry.
2520	*/
2521	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2522	if (PdeSrc.n.u1Present)
2523	{
2524	/*
2525	* Allocate & map the page table.
2526	*/
2527	PSHWPT pPTDst;
2528	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2529	const bool fPageTable = !PdeSrc.b.u1Size;
2530	# else
2531	const bool fPageTable = !PdeSrc.b.u1Size \|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu);
2532	# endif
2533	PPGMPOOLPAGE pShwPage;
2534	RTGCPHYS GCPhys;
2535	if (fPageTable)
2536	{
2537	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2538	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2539	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2540	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2541	# endif
2542	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2543	}
2544	else
2545	{
2546	PGMPOOLACCESS enmAccess;
2547	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2548	const bool fNoExecute = PdeSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu);
2549	# else
2550	const bool fNoExecute = false;
2551	# endif
2552
2553	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2554	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2555	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2556	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2557	# endif
2558	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2559	if (PdeSrc.n.u1User)
2560	{
2561	if (PdeSrc.n.u1Write)
2562	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2563	else
2564	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2565	}
2566	else
2567	{
2568	if (PdeSrc.n.u1Write)
2569	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2570	else
2571	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2572	}
2573	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2574	}
2575	if (rc == VINF_SUCCESS)
2576	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2577	else if (rc == VINF_PGM_CACHED_PAGE)
2578	{
2579	/*
2580	* The PT was cached, just hook it up.
2581	*/
2582	if (fPageTable)
2583	PdeDst.u = pShwPage->Core.Key
2584	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2585	else
2586	{
2587	PdeDst.u = pShwPage->Core.Key
2588	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2589	/* (see explanation and assumptions further down.) */
2590	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2591	{
2592	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2593	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2594	PdeDst.b.u1Write = 0;
2595	}
2596	}
2597	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2598	# if defined(IN_RC)
2599	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2600	# endif
2601	return VINF_SUCCESS;
2602	}
2603	else if (rc == VERR_PGM_POOL_FLUSHED)
2604	{
2605	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2606	# if defined(IN_RC)
2607	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2608	# endif
2609	return VINF_PGM_SYNC_CR3;
2610	}
2611	else
2612	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2613	PdeDst.u &= X86_PDE_AVL_MASK;
2614	PdeDst.u \|= pShwPage->Core.Key;
2615
2616	/*
2617	* Page directory has been accessed (this is a fault situation, remember).
2618	*/
2619	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2620	if (fPageTable)
2621	{
2622	/*
2623	* Page table - 4KB.
2624	*
2625	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2626	*/
2627	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2628	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2629	PGSTPT pPTSrc;
2630	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2631	if (RT_SUCCESS(rc))
2632	{
2633	/*
2634	* Start by syncing the page directory entry so CSAM's TLB trick works.
2635	*/
2636	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2637	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2638	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2639	# if defined(IN_RC)
2640	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2641	# endif
2642
2643	/*
2644	* Directory/page user or supervisor privilege: (same goes for read/write)
2645	*
2646	* Directory Page Combined
2647	* U/S U/S U/S
2648	* 0 0 0
2649	* 0 1 0
2650	* 1 0 0
2651	* 1 1 1
2652	*
2653	* Simple AND operation. Table listed for completeness.
2654	*
2655	*/
2656	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2657	# ifdef PGM_SYNC_N_PAGES
2658	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2659	unsigned iPTDst = iPTBase;
2660	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2661	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2662	iPTDst = 0;
2663	else
2664	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2665	# else /* !PGM_SYNC_N_PAGES */
2666	unsigned iPTDst = 0;
2667	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2668	# endif /* !PGM_SYNC_N_PAGES */
2669	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2670	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2671	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2672	# else
2673	const unsigned offPTSrc = 0;
2674	# endif
2675	for (; iPTDst < iPTDstEnd; iPTDst++)
2676	{
2677	const unsigned iPTSrc = iPTDst + offPTSrc;
2678	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2679
2680	if (PteSrc.n.u1Present) /* we've already cleared it above */
2681	{
2682	# ifndef IN_RING0
2683	/*
2684	* Assuming kernel code will be marked as supervisor - and not as user level
2685	* and executed using a conforming code selector - And marked as readonly.
2686	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2687	*/
2688	PPGMPAGE pPage;
2689	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2690	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2691	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2692	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2693	)
2694	# endif
2695	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2696	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2697	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2698	PteSrc.n.u1Present,
2699	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2700	PteSrc.n.u1User & PdeSrc.n.u1User,
2701	(uint64_t)PteSrc.u,
2702	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2703	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2704	}
2705	} /* for PTEs */
2706	}
2707	}
2708	else
2709	{
2710	/*
2711	* Big page - 2/4MB.
2712	*
2713	* We'll walk the ram range list in parallel and optimize lookups.
2714	* We will only sync on shadow page table at a time.
2715	*/
2716	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2717
2718	/**
2719	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2720	*/
2721
2722	/*
2723	* Start by syncing the page directory entry.
2724	*/
2725	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2726	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2727
2728	/*
2729	* If the page is not flagged as dirty and is writable, then make it read-only
2730	* at PD level, so we can set the dirty bit when the page is modified.
2731	*
2732	* ASSUMES that page access handlers are implemented on page table entry level.
2733	* Thus we will first catch the dirty access and set PDE.D and restart. If
2734	* there is an access handler, we'll trap again and let it work on the problem.
2735	*/
2736	/** @todo move the above stuff to a section in the PGM documentation. */
2737	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2738	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2739	{
2740	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2741	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2742	PdeDst.b.u1Write = 0;
2743	}
2744	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2745	# if defined(IN_RC)
2746	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2747	# endif
2748
2749	/*
2750	* Fill the shadow page table.
2751	*/
2752	/* Get address and flags from the source PDE. */
2753	SHWPTE PteDstBase;
2754	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2755
2756	/* Loop thru the entries in the shadow PT. */
2757	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2758	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2759	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2760	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2761	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2762	unsigned iPTDst = 0;
2763	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2764	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2765	{
2766	/* Advance ram range list. */
2767	while (pRam && GCPhys > pRam->GCPhysLast)
2768	pRam = pRam->CTX_SUFF(pNext);
2769	if (pRam && GCPhys >= pRam->GCPhys)
2770	{
2771	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2772	do
2773	{
2774	/* Make shadow PTE. */
2775	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2776	SHWPTE PteDst;
2777
2778	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2779	/* Try make the page writable if necessary. */
2780	if ( PteDstBase.n.u1Write
2781	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2782	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2783	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2784	# endif
2785	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2786	{
2787	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2788	AssertRCReturn(rc, rc);
2789	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2790	break;
2791	}
2792	# endif
2793
2794	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2795	{
2796	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2797	{
2798	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2799	PteDst.n.u1Write = 0;
2800	}
2801	else
2802	PteDst.u = 0;
2803	}
2804	# ifndef IN_RING0
2805	/*
2806	* Assuming kernel code will be marked as supervisor and not as user level and executed
2807	* using a conforming code selector. Don't check for readonly, as that implies the whole
2808	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2809	*/
2810	else if ( !PdeSrc.n.u1User
2811	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2812	PteDst.u = 0;
2813	# endif
2814	else
2815	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2816
2817	/* Only map writable pages writable. */
2818	if ( PteDst.n.u1Write
2819	&& PteDst.n.u1Present
2820	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2821	{
2822	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2823	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2824	}
2825
2826	if (PteDst.n.u1Present)
2827	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2828
2829	/* commit it */
2830	pPTDst->a[iPTDst] = PteDst;
2831	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2832	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2833	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2834
2835	/* advance */
2836	GCPhys += PAGE_SIZE;
2837	iHCPage++;
2838	iPTDst++;
2839	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2840	&& GCPhys <= pRam->GCPhysLast);
2841	}
2842	else if (pRam)
2843	{
2844	Log(("Invalid pages at %RGp\n", GCPhys));
2845	do
2846	{
2847	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2848	GCPhys += PAGE_SIZE;
2849	iPTDst++;
2850	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2851	&& GCPhys < pRam->GCPhys);
2852	}
2853	else
2854	{
2855	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2856	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2857	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2858	}
2859	} /* while more PTEs */
2860	} /* 4KB / 4MB */
2861	}
2862	else
2863	AssertRelease(!PdeDst.n.u1Present);
2864
2865	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2866	if (RT_FAILURE(rc))
2867	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2868	return rc;
2869
2870	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2871	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2872	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2873	&& !defined(IN_RC)
2874
2875	/*
2876	* Validate input a little bit.
2877	*/
2878	int rc = VINF_SUCCESS;
2879	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2880	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2881	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2882
2883	/* Fetch the pgm pool shadow descriptor. */
2884	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2885	Assert(pShwPde);
2886
2887	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2888	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2889	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2890	PX86PDPAE pPDDst;
2891	PSHWPDE pPdeDst;
2892
2893	/* Fetch the pgm pool shadow descriptor. */
2894	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2895	AssertRCSuccessReturn(rc, rc);
2896	Assert(pShwPde);
2897
2898	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2899	pPdeDst = &pPDDst->a[iPDDst];
2900
2901	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2902	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2903	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2904	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2905	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2906	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2907	AssertRCSuccessReturn(rc, rc);
2908	Assert(pPDDst);
2909	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2910
2911	/* Fetch the pgm pool shadow descriptor. */
2912	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2913	Assert(pShwPde);
2914
2915	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2916	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2917	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2918	PEPTPD pPDDst;
2919	PEPTPDPT pPdptDst;
2920
2921	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2922	if (rc != VINF_SUCCESS)
2923	{
2924	AssertRC(rc);
2925	return rc;
2926	}
2927	Assert(pPDDst);
2928	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2929
2930	/* Fetch the pgm pool shadow descriptor. */
2931	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2932	Assert(pShwPde);
2933	# endif
2934	SHWPDE PdeDst = *pPdeDst;
2935
2936	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2937	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2938
2939	# if (PGM_SHW_TYPE == PGM_TYPE_EPT) && (HC_ARCH_BITS == 64) && defined(RT_OS_WINDOWS) && defined(DEBUG_sandervl)
2940	PPGMPAGE pPage;
2941	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & SHW_PDE_PG_MASK, &pPage);
2942	if ( RT_SUCCESS(rc)
2943	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2944	{
2945	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2946	unsigned uPDEType = PGM_PAGE_GET_PDE_TYPE(pPage);
2947
2948	if (uPDEType == PGM_PAGE_PDE_TYPE_PDE)
2949	{
2950	/* Previously allocated 2 MB range can be reused. */
2951	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2952	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2953	}
2954	else
2955	if ( uPDEType == PGM_PAGE_PDE_TYPE_DONTCARE
2956	&& PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
2957	{
2958	RTGCPHYS GCPhysBase = GCPtrPage & SHW_PDE_PG_MASK;
2959	RTGCPHYS GCPhys = GCPhysBase;
2960	unsigned iPage;
2961
2962	/* Lazy approach: check all pages in the 2 MB range.
2963	* The whole range must be ram and unallocated
2964	*/
2965	for (iPage = 0; iPage < _2M/PAGE_SIZE; iPage++)
2966	{
2967	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
2968	if ( RT_FAILURE(rc)
2969	\|\| PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
2970	\|\| PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2971	{
2972	LogFlow(("Found page with wrong attributes; cancel check. rc=%d\n", rc));
2973	break;
2974	}
2975	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_DONTCARE);
2976	GCPhys += PAGE_SIZE;
2977	}
2978	/* Fetch the start page of the 2 MB range again. */
2979	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysBase, &pPage);
2980	AssertRC(rc); /* can't fail */
2981
2982	if (iPage != _2M/PAGE_SIZE)
2983	{
2984	/* Failed. Mark as requiring a PT so we don't check the whole thing again in the future. */
2985	STAM_COUNTER_INC(&pVM->pgm.s.StatLargePageRefused);
2986	PGM_PAGE_SET_PDE_TYPE(pPage, PGM_PAGE_PDE_TYPE_PT);
2987	}
2988	else
2989	{
2990	rc = pgmPhysAllocLargePage(pVM, GCPhysBase);
2991	if (RT_SUCCESS(rc))
2992	{
2993	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2994	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2995	STAM_COUNTER_INC(&pVM->pgm.s.StatLargePageUsed);
2996	}
2997	else
2998	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
2999	}
3000	}
3001
3002	if (HCPhys != NIL_RTHCPHYS)
3003	{
3004	PdeDst.u &= X86_PDE_AVL_MASK;
3005	PdeDst.u \|= HCPhys;
3006	PdeDst.n.u1Present = 1;
3007	PdeDst.n.u1Write = 1;
3008	PdeDst.n.u1Execute = 1;
3009	PdeDst.b.u1Size = 1;
3010	PdeDst.b.u1IgnorePAT = 1;
3011	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3012	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3013
3014	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3015	return VINF_SUCCESS;
3016	}
3017	}
3018	# endif
3019
3020	GSTPDE PdeSrc;
3021	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3022	PdeSrc.n.u1Present = 1;
3023	PdeSrc.n.u1Write = 1;
3024	PdeSrc.n.u1Accessed = 1;
3025	PdeSrc.n.u1User = 1;
3026
3027	/*
3028	* Allocate & map the page table.
3029	*/
3030	PSHWPT pPTDst;
3031	PPGMPOOLPAGE pShwPage;
3032	RTGCPHYS GCPhys;
3033
3034	/* Virtual address = physical address */
3035	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3036	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3037
3038	if ( rc == VINF_SUCCESS
3039	\|\| rc == VINF_PGM_CACHED_PAGE)
3040	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3041	else
3042	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3043
3044	PdeDst.u &= X86_PDE_AVL_MASK;
3045	PdeDst.u \|= pShwPage->Core.Key;
3046	PdeDst.n.u1Present = 1;
3047	PdeDst.n.u1Write = 1;
3048	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3049	PdeDst.n.u1Execute = 1;
3050	# else
3051	PdeDst.n.u1User = 1;
3052	PdeDst.n.u1Accessed = 1;
3053	# endif
3054	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3055
3056	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3057	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3058	return rc;
3059
3060	#else
3061	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3062	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3063	return VERR_INTERNAL_ERROR;
3064	#endif
3065	}
3066
3067
3068
3069	/**
3070	* Prefetch a page/set of pages.
3071	*
3072	* Typically used to sync commonly used pages before entering raw mode
3073	* after a CR3 reload.
3074	*
3075	* @returns VBox status code.
3076	* @param pVCpu The VMCPU handle.
3077	* @param GCPtrPage Page to invalidate.
3078	*/
3079	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3080	{
3081	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3082	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3083	/*
3084	* Check that all Guest levels thru the PDE are present, getting the
3085	* PD and PDE in the processes.
3086	*/
3087	int rc = VINF_SUCCESS;
3088	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3089	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3090	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3091	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3092	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3093	unsigned iPDSrc;
3094	X86PDPE PdpeSrc;
3095	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3096	if (!pPDSrc)
3097	return VINF_SUCCESS; /* not present */
3098	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3099	unsigned iPDSrc;
3100	PX86PML4E pPml4eSrc;
3101	X86PDPE PdpeSrc;
3102	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3103	if (!pPDSrc)
3104	return VINF_SUCCESS; /* not present */
3105	# endif
3106	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3107	# else
3108	PGSTPD pPDSrc = NULL;
3109	const unsigned iPDSrc = 0;
3110	GSTPDE PdeSrc;
3111
3112	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3113	PdeSrc.n.u1Present = 1;
3114	PdeSrc.n.u1Write = 1;
3115	PdeSrc.n.u1Accessed = 1;
3116	PdeSrc.n.u1User = 1;
3117	# endif
3118
3119	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3120	{
3121	PVM pVM = pVCpu->CTX_SUFF(pVM);
3122	pgmLock(pVM);
3123
3124	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3125	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3126	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3127	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3128	PX86PDPAE pPDDst;
3129	X86PDEPAE PdeDst;
3130	# if PGM_GST_TYPE != PGM_TYPE_PAE
3131	X86PDPE PdpeSrc;
3132
3133	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3134	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3135	# endif
3136	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3137	if (rc != VINF_SUCCESS)
3138	{
3139	pgmUnlock(pVM);
3140	AssertRC(rc);
3141	return rc;
3142	}
3143	Assert(pPDDst);
3144	PdeDst = pPDDst->a[iPDDst];
3145
3146	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3147	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3148	PX86PDPAE pPDDst;
3149	X86PDEPAE PdeDst;
3150
3151	# if PGM_GST_TYPE == PGM_TYPE_PROT
3152	/* AMD-V nested paging */
3153	X86PML4E Pml4eSrc;
3154	X86PDPE PdpeSrc;
3155	PX86PML4E pPml4eSrc = &Pml4eSrc;
3156
3157	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3158	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3159	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3160	# endif
3161
3162	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3163	if (rc != VINF_SUCCESS)
3164	{
3165	pgmUnlock(pVM);
3166	AssertRC(rc);
3167	return rc;
3168	}
3169	Assert(pPDDst);
3170	PdeDst = pPDDst->a[iPDDst];
3171	# endif
3172	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3173	{
3174	if (!PdeDst.n.u1Present)
3175	{
3176	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3177	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3178	}
3179	else
3180	{
3181	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3182	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3183	* makes no sense to prefetch more than one page.
3184	*/
3185	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3186	if (RT_SUCCESS(rc))
3187	rc = VINF_SUCCESS;
3188	}
3189	}
3190	pgmUnlock(pVM);
3191	}
3192	return rc;
3193
3194	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3195	return VINF_SUCCESS; /* ignore */
3196	#endif
3197	}
3198
3199
3200
3201
3202	/**
3203	* Syncs a page during a PGMVerifyAccess() call.
3204	*
3205	* @returns VBox status code (informational included).
3206	* @param pVCpu The VMCPU handle.
3207	* @param GCPtrPage The address of the page to sync.
3208	* @param fPage The effective guest page flags.
3209	* @param uErr The trap error code.
3210	*/
3211	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3212	{
3213	PVM pVM = pVCpu->CTX_SUFF(pVM);
3214
3215	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3216
3217	Assert(!HWACCMIsNestedPagingActive(pVM));
3218	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3219	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3220
3221	# ifndef IN_RING0
3222	if (!(fPage & X86_PTE_US))
3223	{
3224	/*
3225	* Mark this page as safe.
3226	*/
3227	/** @todo not correct for pages that contain both code and data!! */
3228	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3229	CSAMMarkPage(pVM, GCPtrPage, true);
3230	}
3231	# endif
3232
3233	/*
3234	* Get guest PD and index.
3235	*/
3236	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3237	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3238	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3239	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3240	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3241	unsigned iPDSrc = 0;
3242	X86PDPE PdpeSrc;
3243	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3244
3245	if (pPDSrc)
3246	{
3247	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3248	return VINF_EM_RAW_GUEST_TRAP;
3249	}
3250	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3251	unsigned iPDSrc;
3252	PX86PML4E pPml4eSrc;
3253	X86PDPE PdpeSrc;
3254	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3255	if (!pPDSrc)
3256	{
3257	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3258	return VINF_EM_RAW_GUEST_TRAP;
3259	}
3260	# endif
3261	# else
3262	PGSTPD pPDSrc = NULL;
3263	const unsigned iPDSrc = 0;
3264	# endif
3265	int rc = VINF_SUCCESS;
3266
3267	pgmLock(pVM);
3268
3269	/*
3270	* First check if the shadow pd is present.
3271	*/
3272	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3273	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3274	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3275	PX86PDEPAE pPdeDst;
3276	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3277	PX86PDPAE pPDDst;
3278	# if PGM_GST_TYPE != PGM_TYPE_PAE
3279	X86PDPE PdpeSrc;
3280
3281	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3282	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3283	# endif
3284	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3285	if (rc != VINF_SUCCESS)
3286	{
3287	pgmUnlock(pVM);
3288	AssertRC(rc);
3289	return rc;
3290	}
3291	Assert(pPDDst);
3292	pPdeDst = &pPDDst->a[iPDDst];
3293
3294	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3295	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3296	PX86PDPAE pPDDst;
3297	PX86PDEPAE pPdeDst;
3298
3299	# if PGM_GST_TYPE == PGM_TYPE_PROT
3300	/* AMD-V nested paging */
3301	X86PML4E Pml4eSrc;
3302	X86PDPE PdpeSrc;
3303	PX86PML4E pPml4eSrc = &Pml4eSrc;
3304
3305	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3306	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3307	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3308	# endif
3309
3310	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3311	if (rc != VINF_SUCCESS)
3312	{
3313	pgmUnlock(pVM);
3314	AssertRC(rc);
3315	return rc;
3316	}
3317	Assert(pPDDst);
3318	pPdeDst = &pPDDst->a[iPDDst];
3319	# endif
3320
3321	# if defined(IN_RC)
3322	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3323	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3324	# endif
3325
3326	if (!pPdeDst->n.u1Present)
3327	{
3328	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3329	if (rc != VINF_SUCCESS)
3330	{
3331	# if defined(IN_RC)
3332	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3333	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3334	# endif
3335	pgmUnlock(pVM);
3336	AssertRC(rc);
3337	return rc;
3338	}
3339	}
3340
3341	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3342	/* Check for dirty bit fault */
3343	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3344	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3345	Log(("PGMVerifyAccess: success (dirty)\n"));
3346	else
3347	{
3348	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3349	# else
3350	{
3351	GSTPDE PdeSrc;
3352	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3353	PdeSrc.n.u1Present = 1;
3354	PdeSrc.n.u1Write = 1;
3355	PdeSrc.n.u1Accessed = 1;
3356	PdeSrc.n.u1User = 1;
3357
3358	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3359	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3360	if (uErr & X86_TRAP_PF_US)
3361	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3362	else /* supervisor */
3363	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3364
3365	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3366	if (RT_SUCCESS(rc))
3367	{
3368	/* Page was successfully synced */
3369	Log2(("PGMVerifyAccess: success (sync)\n"));
3370	rc = VINF_SUCCESS;
3371	}
3372	else
3373	{
3374	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3375	rc = VINF_EM_RAW_GUEST_TRAP;
3376	}
3377	}
3378	# if defined(IN_RC)
3379	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3380	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3381	# endif
3382	pgmUnlock(pVM);
3383	return rc;
3384
3385	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3386
3387	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3388	return VERR_INTERNAL_ERROR;
3389	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3390	}
3391
3392	#undef MY_STAM_COUNTER_INC
3393	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3394
3395
3396	/**
3397	* Syncs the paging hierarchy starting at CR3.
3398	*
3399	* @returns VBox status code, no specials.
3400	* @param pVCpu The VMCPU handle.
3401	* @param cr0 Guest context CR0 register
3402	* @param cr3 Guest context CR3 register
3403	* @param cr4 Guest context CR4 register
3404	* @param fGlobal Including global page directories or not
3405	*/
3406	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3407	{
3408	PVM pVM = pVCpu->CTX_SUFF(pVM);
3409
3410	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3411	fGlobal = true; /* Change this CR3 reload to be a global one. */
3412
3413	LogFlow(("SyncCR3 %d\n", fGlobal));
3414
3415	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3416
3417	pgmLock(pVM);
3418	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3419	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3420	if (pPool->cDirtyPages)
3421	pgmPoolResetDirtyPages(pVM);
3422	# endif
3423
3424	/*
3425	* Update page access handlers.
3426	* The virtual are always flushed, while the physical are only on demand.
3427	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3428	* have to look into that later because it will have a bad influence on the performance.
3429	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3430	* bird: Yes, but that won't work for aliases.
3431	*/
3432	/** @todo this MUST go away. See #1557. */
3433	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3434	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3435	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3436	pgmUnlock(pVM);
3437	#endif /* !NESTED && !EPT */
3438
3439	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3440	/*
3441	* Nested / EPT - almost no work.
3442	*/
3443	/** @todo check if this is really necessary; the call does it as well... */
3444	HWACCMFlushTLB(pVCpu);
3445	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3446	return VINF_SUCCESS;
3447
3448	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3449	/*
3450	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3451	* out the shadow parts when the guest modifies its tables.
3452	*/
3453	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3454	return VINF_SUCCESS;
3455
3456	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3457
3458	# ifndef PGM_WITHOUT_MAPPINGS
3459	/*
3460	* Check for and resolve conflicts with our guest mappings if they
3461	* are enabled and not fixed.
3462	*/
3463	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3464	{
3465	int rc = pgmMapResolveConflicts(pVM);
3466	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3467	if (rc == VINF_PGM_SYNC_CR3)
3468	{
3469	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3470	return VINF_PGM_SYNC_CR3;
3471	}
3472	}
3473	# else
3474	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3475	# endif
3476	return VINF_SUCCESS;
3477	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3478	}
3479
3480
3481
3482
3483	#ifdef VBOX_STRICT
3484	#ifdef IN_RC
3485	# undef AssertMsgFailed
3486	# define AssertMsgFailed Log
3487	#endif
3488	#ifdef IN_RING3
3489	# include <VBox/dbgf.h>
3490
3491	/**
3492	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3493	*
3494	* @returns VBox status code (VINF_SUCCESS).
3495	* @param cr3 The root of the hierarchy.
3496	* @param crr The cr4, only PAE and PSE is currently used.
3497	* @param fLongMode Set if long mode, false if not long mode.
3498	* @param cMaxDepth Number of levels to dump.
3499	* @param pHlp Pointer to the output functions.
3500	*/
3501	RT_C_DECLS_BEGIN
3502	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3503	RT_C_DECLS_END
3504
3505	#endif
3506
3507	/**
3508	* Checks that the shadow page table is in sync with the guest one.
3509	*
3510	* @returns The number of errors.
3511	* @param pVM The virtual machine.
3512	* @param pVCpu The VMCPU handle.
3513	* @param cr3 Guest context CR3 register
3514	* @param cr4 Guest context CR4 register
3515	* @param GCPtr Where to start. Defaults to 0.
3516	* @param cb How much to check. Defaults to everything.
3517	*/
3518	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3519	{
3520	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3521	return 0;
3522	#else
3523	unsigned cErrors = 0;
3524	PVM pVM = pVCpu->CTX_SUFF(pVM);
3525	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3526
3527	#if PGM_GST_TYPE == PGM_TYPE_PAE
3528	/** @todo currently broken; crashes below somewhere */
3529	AssertFailed();
3530	#endif
3531
3532	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3533	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3534	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3535
3536	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3537	bool fBigPagesSupported = true;
3538	# else
3539	bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3540	# endif
3541	PPGMCPU pPGM = &pVCpu->pgm.s;
3542	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3543	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3544	# ifndef IN_RING0
3545	RTHCPHYS HCPhys; /* general usage. */
3546	# endif
3547	int rc;
3548
3549	/*
3550	* Check that the Guest CR3 and all its mappings are correct.
3551	*/
3552	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3553	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3554	false);
3555	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3556	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3557	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3558	# else
3559	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3560	# endif
3561	AssertRCReturn(rc, 1);
3562	HCPhys = NIL_RTHCPHYS;
3563	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3564	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3565	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3566	pgmGstGet32bitPDPtr(pPGM);
3567	RTGCPHYS GCPhys;
3568	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3569	AssertRCReturn(rc, 1);
3570	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3571	# endif
3572	# endif /* !IN_RING0 */
3573
3574	/*
3575	* Get and check the Shadow CR3.
3576	*/
3577	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3578	unsigned cPDEs = X86_PG_ENTRIES;
3579	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3580	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3581	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3582	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3583	# else
3584	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3585	# endif
3586	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3587	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3588	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3589	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3590	# endif
3591	if (cb != ~(RTGCPTR)0)
3592	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3593
3594	/** @todo call the other two PGMAssert() functions. /
3595
3596	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3597	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3598
3599	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3600	{
3601	PPGMPOOLPAGE pShwPdpt = NULL;
3602	PX86PML4E pPml4eSrc;
3603	PX86PML4E pPml4eDst;
3604	RTGCPHYS GCPhysPdptSrc;
3605
3606	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3607	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3608
3609	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3610	if (!pPml4eDst->n.u1Present)
3611	{
3612	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3613	continue;
3614	}
3615
3616	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3617	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3618
3619	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3620	{
3621	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3622	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3623	cErrors++;
3624	continue;
3625	}
3626
3627	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3628	{
3629	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3630	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3631	cErrors++;
3632	continue;
3633	}
3634
3635	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3636	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3637	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3638	{
3639	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3640	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3641	cErrors++;
3642	continue;
3643	}
3644	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3645	{
3646	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3647
3648	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3649	/*
3650	* Check the PDPTEs too.
3651	*/
3652	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3653
3654	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3655	{
3656	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3657	PPGMPOOLPAGE pShwPde = NULL;
3658	PX86PDPE pPdpeDst;
3659	RTGCPHYS GCPhysPdeSrc;
3660	# if PGM_GST_TYPE == PGM_TYPE_PAE
3661	X86PDPE PdpeSrc;
3662	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3663	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3664	# else
3665	PX86PML4E pPml4eSrcIgn;
3666	X86PDPE PdpeSrc;
3667	PX86PDPT pPdptDst;
3668	PX86PDPAE pPDDst;
3669	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3670
3671	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3672	if (rc != VINF_SUCCESS)
3673	{
3674	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3675	GCPtr += 512 * _2M;
3676	continue; /* next PDPTE */
3677	}
3678	Assert(pPDDst);
3679	# endif
3680	Assert(iPDSrc == 0);
3681
3682	pPdpeDst = &pPdptDst->a[iPdpt];
3683
3684	if (!pPdpeDst->n.u1Present)
3685	{
3686	GCPtr += 512 * _2M;
3687	continue; /* next PDPTE */
3688	}
3689
3690	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3691	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3692
3693	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3694	{
3695	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3696	GCPtr += 512 * _2M;
3697	cErrors++;
3698	continue;
3699	}
3700
3701	if (GCPhysPdeSrc != pShwPde->GCPhys)
3702	{
3703	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3704	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3705	# else
3706	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3707	# endif
3708	GCPtr += 512 * _2M;
3709	cErrors++;
3710	continue;
3711	}
3712
3713	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3714	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3715	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3716	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3717	{
3718	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3719	GCPtr += 512 * _2M;
3720	cErrors++;
3721	continue;
3722	}
3723	# endif
3724
3725	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3726	{
3727	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3728	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3729	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3730	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3731	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3732	# endif
3733	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3734	/*
3735	* Iterate the shadow page directory.
3736	*/
3737	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3738	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3739
3740	for (;
3741	iPDDst < cPDEs;
3742	iPDDst++, GCPtr += cIncrement)
3743	{
3744	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3745	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3746	# else
3747	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3748	# endif
3749	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3750	{
3751	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3752	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3753	{
3754	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3755	cErrors++;
3756	continue;
3757	}
3758	}
3759	else if ( (PdeDst.u & X86_PDE_P)
3760	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3761	)
3762	{
3763	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3764	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3765	if (!pPoolPage)
3766	{
3767	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3768	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3769	cErrors++;
3770	continue;
3771	}
3772	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3773
3774	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3775	{
3776	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3777	GCPtr, (uint64_t)PdeDst.u));
3778	cErrors++;
3779	}
3780
3781	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3782	{
3783	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3784	GCPtr, (uint64_t)PdeDst.u));
3785	cErrors++;
3786	}
3787
3788	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3789	if (!PdeSrc.n.u1Present)
3790	{
3791	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3792	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3793	cErrors++;
3794	continue;
3795	}
3796
3797	if ( !PdeSrc.b.u1Size
3798	\|\| !fBigPagesSupported)
3799	{
3800	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3801	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3802	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3803	# endif
3804	}
3805	else
3806	{
3807	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3808	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3809	{
3810	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3811	GCPtr, (uint64_t)PdeSrc.u));
3812	cErrors++;
3813	continue;
3814	}
3815	# endif
3816	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3817	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3818	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3819	# endif
3820	}
3821
3822	if ( pPoolPage->enmKind
3823	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3824	{
3825	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3826	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3827	cErrors++;
3828	}
3829
3830	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3831	if (!pPhysPage)
3832	{
3833	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3834	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3835	cErrors++;
3836	continue;
3837	}
3838
3839	if (GCPhysGst != pPoolPage->GCPhys)
3840	{
3841	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3842	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3843	cErrors++;
3844	continue;
3845	}
3846
3847	if ( !PdeSrc.b.u1Size
3848	\|\| !fBigPagesSupported)
3849	{
3850	/*
3851	* Page Table.
3852	*/
3853	const GSTPT *pPTSrc;
3854	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3855	if (RT_FAILURE(rc))
3856	{
3857	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3858	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3859	cErrors++;
3860	continue;
3861	}
3862	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3863	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3864	{
3865	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3866	// (This problem will go away when/if we shadow multiple CR3s.)
3867	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3868	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3869	cErrors++;
3870	continue;
3871	}
3872	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3873	{
3874	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3875	GCPtr, (uint64_t)PdeDst.u));
3876	cErrors++;
3877	continue;
3878	}
3879
3880	/* iterate the page table. */
3881	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3882	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3883	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3884	# else
3885	const unsigned offPTSrc = 0;
3886	# endif
3887	for (unsigned iPT = 0, off = 0;
3888	iPT < RT_ELEMENTS(pPTDst->a);
3889	iPT++, off += PAGE_SIZE)
3890	{
3891	const SHWPTE PteDst = pPTDst->a[iPT];
3892
3893	/* skip not-present entries. */
3894	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3895	continue;
3896	Assert(PteDst.n.u1Present);
3897
3898	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3899	if (!PteSrc.n.u1Present)
3900	{
3901	# ifdef IN_RING3
3902	PGMAssertHandlerAndFlagsInSync(pVM);
3903	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3904	# endif
3905	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3906	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3907	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3908	cErrors++;
3909	continue;
3910	}
3911
3912	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3913	# if 1 /** @todo sync accessed bit properly... */
3914	fIgnoreFlags \|= X86_PTE_A;
3915	# endif
3916
3917	/* match the physical addresses */
3918	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3919	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3920
3921	# ifdef IN_RING3
3922	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3923	if (RT_FAILURE(rc))
3924	{
3925	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3926	{
3927	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3928	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3929	cErrors++;
3930	continue;
3931	}
3932	}
3933	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3934	{
3935	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3936	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3937	cErrors++;
3938	continue;
3939	}
3940	# endif
3941
3942	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3943	if (!pPhysPage)
3944	{
3945	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3946	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3947	{
3948	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3949	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3950	cErrors++;
3951	continue;
3952	}
3953	# endif
3954	if (PteDst.n.u1Write)
3955	{
3956	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3957	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3958	cErrors++;
3959	}
3960	fIgnoreFlags \|= X86_PTE_RW;
3961	}
3962	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3963	{
3964	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3965	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3966	cErrors++;
3967	continue;
3968	}
3969
3970	/* flags */
3971	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3972	{
3973	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3974	{
3975	if (PteDst.n.u1Write)
3976	{
3977	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3978	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3979	cErrors++;
3980	continue;
3981	}
3982	fIgnoreFlags \|= X86_PTE_RW;
3983	}
3984	else
3985	{
3986	if (PteDst.n.u1Present)
3987	{
3988	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3989	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3990	cErrors++;
3991	continue;
3992	}
3993	fIgnoreFlags \|= X86_PTE_P;
3994	}
3995	}
3996	else
3997	{
3998	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3999	{
4000	if (PteDst.n.u1Write)
4001	{
4002	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4003	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4004	cErrors++;
4005	continue;
4006	}
4007	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4008	{
4009	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4010	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4011	cErrors++;
4012	continue;
4013	}
4014	if (PteDst.n.u1Dirty)
4015	{
4016	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4018	cErrors++;
4019	}
4020	# if 0 /** @todo sync access bit properly... */
4021	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4022	{
4023	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4024	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4025	cErrors++;
4026	}
4027	fIgnoreFlags \|= X86_PTE_RW;
4028	# else
4029	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4030	# endif
4031	}
4032	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4033	{
4034	/* access bit emulation (not implemented). */
4035	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4036	{
4037	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4038	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4039	cErrors++;
4040	continue;
4041	}
4042	if (!PteDst.n.u1Accessed)
4043	{
4044	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4045	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4046	cErrors++;
4047	}
4048	fIgnoreFlags \|= X86_PTE_P;
4049	}
4050	# ifdef DEBUG_sandervl
4051	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4052	# endif
4053	}
4054
4055	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4056	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4057	)
4058	{
4059	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4061	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4062	cErrors++;
4063	continue;
4064	}
4065	} /* foreach PTE */
4066	}
4067	else
4068	{
4069	/*
4070	* Big Page.
4071	*/
4072	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4073	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4074	{
4075	if (PdeDst.n.u1Write)
4076	{
4077	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4078	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4079	cErrors++;
4080	continue;
4081	}
4082	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4083	{
4084	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4085	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4086	cErrors++;
4087	continue;
4088	}
4089	# if 0 /** @todo sync access bit properly... */
4090	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4091	{
4092	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4093	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4094	cErrors++;
4095	}
4096	fIgnoreFlags \|= X86_PTE_RW;
4097	# else
4098	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4099	# endif
4100	}
4101	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4102	{
4103	/* access bit emulation (not implemented). */
4104	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4105	{
4106	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4107	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4108	cErrors++;
4109	continue;
4110	}
4111	if (!PdeDst.n.u1Accessed)
4112	{
4113	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4114	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4115	cErrors++;
4116	}
4117	fIgnoreFlags \|= X86_PTE_P;
4118	}
4119
4120	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4121	{
4122	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4123	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4124	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4125	cErrors++;
4126	}
4127
4128	/* iterate the page table. */
4129	for (unsigned iPT = 0, off = 0;
4130	iPT < RT_ELEMENTS(pPTDst->a);
4131	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4132	{
4133	const SHWPTE PteDst = pPTDst->a[iPT];
4134
4135	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4136	{
4137	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4138	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4139	cErrors++;
4140	}
4141
4142	/* skip not-present entries. */
4143	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4144	continue;
4145
4146	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4147
4148	/* match the physical addresses */
4149	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4150
4151	# ifdef IN_RING3
4152	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4153	if (RT_FAILURE(rc))
4154	{
4155	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4156	{
4157	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4158	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4159	cErrors++;
4160	}
4161	}
4162	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4163	{
4164	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4165	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4166	cErrors++;
4167	continue;
4168	}
4169	# endif
4170	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4171	if (!pPhysPage)
4172	{
4173	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4174	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4175	{
4176	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4177	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4178	cErrors++;
4179	continue;
4180	}
4181	# endif
4182	if (PteDst.n.u1Write)
4183	{
4184	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4185	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4186	cErrors++;
4187	}
4188	fIgnoreFlags \|= X86_PTE_RW;
4189	}
4190	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4191	{
4192	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4193	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4194	cErrors++;
4195	continue;
4196	}
4197
4198	/* flags */
4199	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4200	{
4201	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4202	{
4203	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4204	{
4205	if (PteDst.n.u1Write)
4206	{
4207	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4209	cErrors++;
4210	continue;
4211	}
4212	fIgnoreFlags \|= X86_PTE_RW;
4213	}
4214	}
4215	else
4216	{
4217	if (PteDst.n.u1Present)
4218	{
4219	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4220	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4221	cErrors++;
4222	continue;
4223	}
4224	fIgnoreFlags \|= X86_PTE_P;
4225	}
4226	}
4227
4228	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4229	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4230	)
4231	{
4232	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4233	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4234	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4235	cErrors++;
4236	continue;
4237	}
4238	} /* for each PTE */
4239	}
4240	}
4241	/* not present */
4242
4243	} /* for each PDE */
4244
4245	} /* for each PDPTE */
4246
4247	} /* for each PML4E */
4248
4249	# ifdef DEBUG
4250	if (cErrors)
4251	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4252	# endif
4253
4254	#endif /* GST == 32BIT, PAE or AMD64 */
4255	return cErrors;
4256
4257	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4258	}
4259	#endif /* VBOX_STRICT */
4260
4261
4262	/**
4263	* Sets up the CR3 for shadow paging
4264	*
4265	* @returns Strict VBox status code.
4266	* @retval VINF_SUCCESS.
4267	*
4268	* @param pVCpu The VMCPU handle.
4269	* @param GCPhysCR3 The physical address in the CR3 register.
4270	*/
4271	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4272	{
4273	PVM pVM = pVCpu->CTX_SUFF(pVM);
4274
4275	/* Update guest paging info. */
4276	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4277	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4278	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4279
4280	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4281
4282	/*
4283	* Map the page CR3 points at.
4284	*/
4285	RTHCPTR HCPtrGuestCR3;
4286	RTHCPHYS HCPhysGuestCR3;
4287	pgmLock(pVM);
4288	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4289	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4290	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4291	/** @todo this needs some reworking wrt. locking. */
4292	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4293	HCPtrGuestCR3 = NIL_RTHCPTR;
4294	int rc = VINF_SUCCESS;
4295	# else
4296	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4297	# endif
4298	pgmUnlock(pVM);
4299	if (RT_SUCCESS(rc))
4300	{
4301	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4302	if (RT_SUCCESS(rc))
4303	{
4304	# ifdef IN_RC
4305	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4306	# endif
4307	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4308	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4309	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4310	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4311	# endif
4312	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4313
4314	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4315	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4316	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4317	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4318	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4319	# endif
4320	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4321	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4322
4323	/*
4324	* Map the 4 PDs too.
4325	*/
4326	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4327	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4328	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4329	{
4330	if (pGuestPDPT->a[i].n.u1Present)
4331	{
4332	RTHCPTR HCPtr;
4333	RTHCPHYS HCPhys;
4334	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4335	pgmLock(pVM);
4336	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4337	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4338	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4339	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4340	HCPtr = NIL_RTHCPTR;
4341	int rc2 = VINF_SUCCESS;
4342	# else
4343	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4344	# endif
4345	pgmUnlock(pVM);
4346	if (RT_SUCCESS(rc2))
4347	{
4348	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4349	AssertRCReturn(rc, rc);
4350
4351	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4352	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4353	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4354	# endif
4355	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4356	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4357	# ifdef IN_RC
4358	PGM_INVL_PG(pVCpu, GCPtr);
4359	# endif
4360	continue;
4361	}
4362	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4363	}
4364
4365	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4366	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4367	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4368	# endif
4369	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4370	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4371	# ifdef IN_RC
4372	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4373	# endif
4374	}
4375
4376	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4377	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4378	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4379	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4380	# endif
4381	# endif
4382	}
4383	else
4384	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4385	}
4386	else
4387	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4388
4389	#else /* prot/real stub */
4390	int rc = VINF_SUCCESS;
4391	#endif
4392
4393	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4394	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4395	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4396	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4397	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4398	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4399
4400	Assert(!HWACCMIsNestedPagingActive(pVM));
4401
4402	/*
4403	* Update the shadow root page as well since that's not fixed.
4404	*/
4405	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4406	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4407	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4408	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4409	PPGMPOOLPAGE pNewShwPageCR3;
4410
4411	pgmLock(pVM);
4412
4413	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4414	if (pPool->cDirtyPages)
4415	pgmPoolResetDirtyPages(pVM);
4416	# endif
4417
4418	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4419	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4420	AssertFatalRC(rc);
4421	rc = VINF_SUCCESS;
4422
4423	# ifdef IN_RC
4424	/*
4425	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4426	* state will be inconsistent! Flush important things now while
4427	* we still can and then make sure there are no ring-3 calls.
4428	*/
4429	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4430	VMMRZCallRing3Disable(pVCpu);
4431	# endif
4432
4433	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4434	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4435	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4436	# ifdef IN_RING0
4437	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4438	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4439	# elif defined(IN_RC)
4440	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4441	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4442	# else
4443	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4444	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4445	# endif
4446
4447	# ifndef PGM_WITHOUT_MAPPINGS
4448	/*
4449	* Apply all hypervisor mappings to the new CR3.
4450	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4451	* make sure we check for conflicts in the new CR3 root.
4452	*/
4453	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4454	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4455	# endif
4456	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4457	AssertRCReturn(rc, rc);
4458	# endif
4459
4460	/* Set the current hypervisor CR3. */
4461	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4462	SELMShadowCR3Changed(pVM, pVCpu);
4463
4464	# ifdef IN_RC
4465	/* NOTE: The state is consistent again. */
4466	VMMRZCallRing3Enable(pVCpu);
4467	# endif
4468
4469	/* Clean up the old CR3 root. */
4470	if ( pOldShwPageCR3
4471	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4472	{
4473	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4474	# ifndef PGM_WITHOUT_MAPPINGS
4475	/* Remove the hypervisor mappings from the shadow page table. */
4476	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4477	# endif
4478	/* Mark the page as unlocked; allow flushing again. */
4479	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4480
4481	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4482	}
4483	pgmUnlock(pVM);
4484	# endif
4485
4486	return rc;
4487	}
4488
4489	/**
4490	* Unmaps the shadow CR3.
4491	*
4492	* @returns VBox status, no specials.
4493	* @param pVCpu The VMCPU handle.
4494	*/
4495	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4496	{
4497	LogFlow(("UnmapCR3\n"));
4498
4499	int rc = VINF_SUCCESS;
4500	PVM pVM = pVCpu->CTX_SUFF(pVM);
4501
4502	/*
4503	* Update guest paging info.
4504	*/
4505	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4506	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4507	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4508	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4509	# endif
4510	pVCpu->pgm.s.pGst32BitPdRC = 0;
4511
4512	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4513	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4514	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4515	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4516	# endif
4517	pVCpu->pgm.s.pGstPaePdptRC = 0;
4518	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4519	{
4520	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4521	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4522	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4523	# endif
4524	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4525	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4526	}
4527
4528	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4529	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4530	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4531	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4532	# endif
4533
4534	#else /* prot/real mode stub */
4535	/* nothing to do */
4536	#endif
4537
4538	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4539	/*
4540	* Update shadow paging info.
4541	*/
4542	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4543	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4544	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4545
4546	# if PGM_GST_TYPE != PGM_TYPE_REAL
4547	Assert(!HWACCMIsNestedPagingActive(pVM));
4548	# endif
4549
4550	pgmLock(pVM);
4551
4552	# ifndef PGM_WITHOUT_MAPPINGS
4553	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4554	/* Remove the hypervisor mappings from the shadow page table. */
4555	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4556	# endif
4557
4558	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4559	{
4560	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4561
4562	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4563
4564	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4565	if (pPool->cDirtyPages)
4566	pgmPoolResetDirtyPages(pVM);
4567	# endif
4568
4569	/* Mark the page as unlocked; allow flushing again. */
4570	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4571
4572	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4573	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4574	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4575	pVCpu->pgm.s.pShwPageCR3RC = 0;
4576	pVCpu->pgm.s.iShwUser = 0;
4577	pVCpu->pgm.s.iShwUserTable = 0;
4578	}
4579	pgmUnlock(pVM);
4580	# endif
4581	#endif /* !IN_RC*/
4582
4583	return rc;
4584	}
4585

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 26624

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