VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 80150

Last change on this file since 80150 was 80118, checked in by vboxsync, 6 years ago

VMM: Kicking out raw-mode and 32-bit hosts - MM, PGM, ++. bugref:9517 bugref:9511
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  • Property svn:keywords set to Id Revision
File size: 135.3 KB
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1/* $Id: PGMAll.cpp 80118 2019-08-04 02:39:54Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/selm.h>
26#include <VBox/vmm/iem.h>
27#include <VBox/vmm/iom.h>
28#include <VBox/sup.h>
29#include <VBox/vmm/mm.h>
30#include <VBox/vmm/stam.h>
31#include <VBox/vmm/trpm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/hm_vmx.h>
38#include "PGMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "PGMInline.h"
41#include <iprt/assert.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*********************************************************************************************************************************
50* Structures and Typedefs *
51*********************************************************************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** Pointer to the VM. */
59 PVM pVM;
60 /** Pointer to the VMCPU. */
61 PVMCPU pVCpu;
62 /** The todo flags. */
63 RTUINT fTodo;
64 /** The CR4 register value. */
65 uint32_t cr4;
66} PGMHVUSTATE, *PPGMHVUSTATE;
67
68
69/*********************************************************************************************************************************
70* Internal Functions *
71*********************************************************************************************************************************/
72DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74#ifndef IN_RC
75static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
77#endif
78
79
80/*
81 * Shadow - 32-bit mode
82 */
83#define PGM_SHW_TYPE PGM_TYPE_32BIT
84#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
85#include "PGMAllShw.h"
86
87/* Guest - real mode */
88#define PGM_GST_TYPE PGM_TYPE_REAL
89#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
90#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
91#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
92#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
93#include "PGMGstDefs.h"
94#include "PGMAllGst.h"
95#include "PGMAllBth.h"
96#undef BTH_PGMPOOLKIND_PT_FOR_PT
97#undef BTH_PGMPOOLKIND_ROOT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - protected mode */
103#define PGM_GST_TYPE PGM_TYPE_PROT
104#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
108#include "PGMGstDefs.h"
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef BTH_PGMPOOLKIND_ROOT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117/* Guest - 32-bit mode */
118#define PGM_GST_TYPE PGM_TYPE_32BIT
119#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
124#include "PGMGstDefs.h"
125#include "PGMAllGst.h"
126#include "PGMAllBth.h"
127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
128#undef BTH_PGMPOOLKIND_PT_FOR_PT
129#undef BTH_PGMPOOLKIND_ROOT
130#undef PGM_BTH_NAME
131#undef PGM_GST_TYPE
132#undef PGM_GST_NAME
133
134#undef PGM_SHW_TYPE
135#undef PGM_SHW_NAME
136
137
138/*
139 * Shadow - PAE mode
140 */
141#define PGM_SHW_TYPE PGM_TYPE_PAE
142#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#include "PGMAllShw.h"
145
146/* Guest - real mode */
147#define PGM_GST_TYPE PGM_TYPE_REAL
148#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
152#include "PGMGstDefs.h"
153#include "PGMAllBth.h"
154#undef BTH_PGMPOOLKIND_PT_FOR_PT
155#undef BTH_PGMPOOLKIND_ROOT
156#undef PGM_BTH_NAME
157#undef PGM_GST_TYPE
158#undef PGM_GST_NAME
159
160/* Guest - protected mode */
161#define PGM_GST_TYPE PGM_TYPE_PROT
162#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
163#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
164#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
165#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
166#include "PGMGstDefs.h"
167#include "PGMAllBth.h"
168#undef BTH_PGMPOOLKIND_PT_FOR_PT
169#undef BTH_PGMPOOLKIND_ROOT
170#undef PGM_BTH_NAME
171#undef PGM_GST_TYPE
172#undef PGM_GST_NAME
173
174/* Guest - 32-bit mode */
175#define PGM_GST_TYPE PGM_TYPE_32BIT
176#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
177#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
178#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
179#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
180#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
181#include "PGMGstDefs.h"
182#include "PGMAllBth.h"
183#undef BTH_PGMPOOLKIND_PT_FOR_BIG
184#undef BTH_PGMPOOLKIND_PT_FOR_PT
185#undef BTH_PGMPOOLKIND_ROOT
186#undef PGM_BTH_NAME
187#undef PGM_GST_TYPE
188#undef PGM_GST_NAME
189
190
191/* Guest - PAE mode */
192#define PGM_GST_TYPE PGM_TYPE_PAE
193#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
196#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
197#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
198#include "PGMGstDefs.h"
199#include "PGMAllGst.h"
200#include "PGMAllBth.h"
201#undef BTH_PGMPOOLKIND_PT_FOR_BIG
202#undef BTH_PGMPOOLKIND_PT_FOR_PT
203#undef BTH_PGMPOOLKIND_ROOT
204#undef PGM_BTH_NAME
205#undef PGM_GST_TYPE
206#undef PGM_GST_NAME
207
208#undef PGM_SHW_TYPE
209#undef PGM_SHW_NAME
210
211
212#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
213/*
214 * Shadow - AMD64 mode
215 */
216# define PGM_SHW_TYPE PGM_TYPE_AMD64
217# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
218# include "PGMAllShw.h"
219
220/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
221/** @todo retire this hack. */
222# define PGM_GST_TYPE PGM_TYPE_PROT
223# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
224# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
225# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
226# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
227# include "PGMGstDefs.h"
228# include "PGMAllBth.h"
229# undef BTH_PGMPOOLKIND_PT_FOR_PT
230# undef BTH_PGMPOOLKIND_ROOT
231# undef PGM_BTH_NAME
232# undef PGM_GST_TYPE
233# undef PGM_GST_NAME
234
235# ifdef VBOX_WITH_64_BITS_GUESTS
236/* Guest - AMD64 mode */
237# define PGM_GST_TYPE PGM_TYPE_AMD64
238# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
239# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
240# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
241# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
242# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
243# include "PGMGstDefs.h"
244# include "PGMAllGst.h"
245# include "PGMAllBth.h"
246# undef BTH_PGMPOOLKIND_PT_FOR_BIG
247# undef BTH_PGMPOOLKIND_PT_FOR_PT
248# undef BTH_PGMPOOLKIND_ROOT
249# undef PGM_BTH_NAME
250# undef PGM_GST_TYPE
251# undef PGM_GST_NAME
252# endif /* VBOX_WITH_64_BITS_GUESTS */
253
254# undef PGM_SHW_TYPE
255# undef PGM_SHW_NAME
256
257
258/*
259 * Shadow - 32-bit nested paging mode.
260 */
261# define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
262# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
263# include "PGMAllShw.h"
264
265/* Guest - real mode */
266# define PGM_GST_TYPE PGM_TYPE_REAL
267# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
268# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
269# include "PGMGstDefs.h"
270# include "PGMAllBth.h"
271# undef PGM_BTH_NAME
272# undef PGM_GST_TYPE
273# undef PGM_GST_NAME
274
275/* Guest - protected mode */
276# define PGM_GST_TYPE PGM_TYPE_PROT
277# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
278# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
279# include "PGMGstDefs.h"
280# include "PGMAllBth.h"
281# undef PGM_BTH_NAME
282# undef PGM_GST_TYPE
283# undef PGM_GST_NAME
284
285/* Guest - 32-bit mode */
286# define PGM_GST_TYPE PGM_TYPE_32BIT
287# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
288# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
289# include "PGMGstDefs.h"
290# include "PGMAllBth.h"
291# undef PGM_BTH_NAME
292# undef PGM_GST_TYPE
293# undef PGM_GST_NAME
294
295/* Guest - PAE mode */
296# define PGM_GST_TYPE PGM_TYPE_PAE
297# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
298# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
299# include "PGMGstDefs.h"
300# include "PGMAllBth.h"
301# undef PGM_BTH_NAME
302# undef PGM_GST_TYPE
303# undef PGM_GST_NAME
304
305# ifdef VBOX_WITH_64_BITS_GUESTS
306/* Guest - AMD64 mode */
307# define PGM_GST_TYPE PGM_TYPE_AMD64
308# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
309# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
310# include "PGMGstDefs.h"
311# include "PGMAllBth.h"
312# undef PGM_BTH_NAME
313# undef PGM_GST_TYPE
314# undef PGM_GST_NAME
315# endif /* VBOX_WITH_64_BITS_GUESTS */
316
317# undef PGM_SHW_TYPE
318# undef PGM_SHW_NAME
319
320
321/*
322 * Shadow - PAE nested paging mode.
323 */
324# define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
325# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
326# include "PGMAllShw.h"
327
328/* Guest - real mode */
329# define PGM_GST_TYPE PGM_TYPE_REAL
330# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
331# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
332# include "PGMGstDefs.h"
333# include "PGMAllBth.h"
334# undef PGM_BTH_NAME
335# undef PGM_GST_TYPE
336# undef PGM_GST_NAME
337
338/* Guest - protected mode */
339# define PGM_GST_TYPE PGM_TYPE_PROT
340# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
341# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
342# include "PGMGstDefs.h"
343# include "PGMAllBth.h"
344# undef PGM_BTH_NAME
345# undef PGM_GST_TYPE
346# undef PGM_GST_NAME
347
348/* Guest - 32-bit mode */
349# define PGM_GST_TYPE PGM_TYPE_32BIT
350# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
351# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
352# include "PGMGstDefs.h"
353# include "PGMAllBth.h"
354# undef PGM_BTH_NAME
355# undef PGM_GST_TYPE
356# undef PGM_GST_NAME
357
358/* Guest - PAE mode */
359# define PGM_GST_TYPE PGM_TYPE_PAE
360# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
361# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
362# include "PGMGstDefs.h"
363# include "PGMAllBth.h"
364# undef PGM_BTH_NAME
365# undef PGM_GST_TYPE
366# undef PGM_GST_NAME
367
368# ifdef VBOX_WITH_64_BITS_GUESTS
369/* Guest - AMD64 mode */
370# define PGM_GST_TYPE PGM_TYPE_AMD64
371# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
372# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
373# include "PGMGstDefs.h"
374# include "PGMAllBth.h"
375# undef PGM_BTH_NAME
376# undef PGM_GST_TYPE
377# undef PGM_GST_NAME
378# endif /* VBOX_WITH_64_BITS_GUESTS */
379
380# undef PGM_SHW_TYPE
381# undef PGM_SHW_NAME
382
383
384/*
385 * Shadow - AMD64 nested paging mode.
386 */
387# define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
388# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
389# include "PGMAllShw.h"
390
391/* Guest - real mode */
392# define PGM_GST_TYPE PGM_TYPE_REAL
393# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
394# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
395# include "PGMGstDefs.h"
396# include "PGMAllBth.h"
397# undef PGM_BTH_NAME
398# undef PGM_GST_TYPE
399# undef PGM_GST_NAME
400
401/* Guest - protected mode */
402# define PGM_GST_TYPE PGM_TYPE_PROT
403# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
404# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
405# include "PGMGstDefs.h"
406# include "PGMAllBth.h"
407# undef PGM_BTH_NAME
408# undef PGM_GST_TYPE
409# undef PGM_GST_NAME
410
411/* Guest - 32-bit mode */
412# define PGM_GST_TYPE PGM_TYPE_32BIT
413# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
414# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
415# include "PGMGstDefs.h"
416# include "PGMAllBth.h"
417# undef PGM_BTH_NAME
418# undef PGM_GST_TYPE
419# undef PGM_GST_NAME
420
421/* Guest - PAE mode */
422# define PGM_GST_TYPE PGM_TYPE_PAE
423# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
424# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
425# include "PGMGstDefs.h"
426# include "PGMAllBth.h"
427# undef PGM_BTH_NAME
428# undef PGM_GST_TYPE
429# undef PGM_GST_NAME
430
431# ifdef VBOX_WITH_64_BITS_GUESTS
432/* Guest - AMD64 mode */
433# define PGM_GST_TYPE PGM_TYPE_AMD64
434# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
435# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
436# include "PGMGstDefs.h"
437# include "PGMAllBth.h"
438# undef PGM_BTH_NAME
439# undef PGM_GST_TYPE
440# undef PGM_GST_NAME
441# endif /* VBOX_WITH_64_BITS_GUESTS */
442
443# undef PGM_SHW_TYPE
444# undef PGM_SHW_NAME
445
446
447/*
448 * Shadow - EPT.
449 */
450# define PGM_SHW_TYPE PGM_TYPE_EPT
451# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
452# include "PGMAllShw.h"
453
454/* Guest - real mode */
455# define PGM_GST_TYPE PGM_TYPE_REAL
456# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
457# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
458# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
459# include "PGMGstDefs.h"
460# include "PGMAllBth.h"
461# undef BTH_PGMPOOLKIND_PT_FOR_PT
462# undef PGM_BTH_NAME
463# undef PGM_GST_TYPE
464# undef PGM_GST_NAME
465
466/* Guest - protected mode */
467# define PGM_GST_TYPE PGM_TYPE_PROT
468# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
469# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
470# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
471# include "PGMGstDefs.h"
472# include "PGMAllBth.h"
473# undef BTH_PGMPOOLKIND_PT_FOR_PT
474# undef PGM_BTH_NAME
475# undef PGM_GST_TYPE
476# undef PGM_GST_NAME
477
478/* Guest - 32-bit mode */
479# define PGM_GST_TYPE PGM_TYPE_32BIT
480# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
481# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
482# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
483# include "PGMGstDefs.h"
484# include "PGMAllBth.h"
485# undef BTH_PGMPOOLKIND_PT_FOR_PT
486# undef PGM_BTH_NAME
487# undef PGM_GST_TYPE
488# undef PGM_GST_NAME
489
490/* Guest - PAE mode */
491# define PGM_GST_TYPE PGM_TYPE_PAE
492# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
493# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
494# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
495# include "PGMGstDefs.h"
496# include "PGMAllBth.h"
497# undef BTH_PGMPOOLKIND_PT_FOR_PT
498# undef PGM_BTH_NAME
499# undef PGM_GST_TYPE
500# undef PGM_GST_NAME
501
502# ifdef VBOX_WITH_64_BITS_GUESTS
503/* Guest - AMD64 mode */
504# define PGM_GST_TYPE PGM_TYPE_AMD64
505# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
506# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
507# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
508# include "PGMGstDefs.h"
509# include "PGMAllBth.h"
510# undef BTH_PGMPOOLKIND_PT_FOR_PT
511# undef PGM_BTH_NAME
512# undef PGM_GST_TYPE
513# undef PGM_GST_NAME
514# endif /* VBOX_WITH_64_BITS_GUESTS */
515
516# undef PGM_SHW_TYPE
517# undef PGM_SHW_NAME
518
519
520/*
521 * Shadow - NEM / None.
522 */
523# define PGM_SHW_TYPE PGM_TYPE_NONE
524# define PGM_SHW_NAME(name) PGM_SHW_NAME_NONE(name)
525# include "PGMAllShw.h"
526
527/* Guest - real mode */
528# define PGM_GST_TYPE PGM_TYPE_REAL
529# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
530# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_REAL(name)
531# include "PGMGstDefs.h"
532# include "PGMAllBth.h"
533# undef PGM_BTH_NAME
534# undef PGM_GST_TYPE
535# undef PGM_GST_NAME
536
537/* Guest - protected mode */
538# define PGM_GST_TYPE PGM_TYPE_PROT
539# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
540# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PROT(name)
541# include "PGMGstDefs.h"
542# include "PGMAllBth.h"
543# undef PGM_BTH_NAME
544# undef PGM_GST_TYPE
545# undef PGM_GST_NAME
546
547/* Guest - 32-bit mode */
548# define PGM_GST_TYPE PGM_TYPE_32BIT
549# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
550# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_32BIT(name)
551# include "PGMGstDefs.h"
552# include "PGMAllBth.h"
553# undef PGM_BTH_NAME
554# undef PGM_GST_TYPE
555# undef PGM_GST_NAME
556
557/* Guest - PAE mode */
558# define PGM_GST_TYPE PGM_TYPE_PAE
559# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
560# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PAE(name)
561# include "PGMGstDefs.h"
562# include "PGMAllBth.h"
563# undef PGM_BTH_NAME
564# undef PGM_GST_TYPE
565# undef PGM_GST_NAME
566
567# ifdef VBOX_WITH_64_BITS_GUESTS
568/* Guest - AMD64 mode */
569# define PGM_GST_TYPE PGM_TYPE_AMD64
570# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
571# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_AMD64(name)
572# include "PGMGstDefs.h"
573# include "PGMAllBth.h"
574# undef PGM_BTH_NAME
575# undef PGM_GST_TYPE
576# undef PGM_GST_NAME
577# endif /* VBOX_WITH_64_BITS_GUESTS */
578
579# undef PGM_SHW_TYPE
580# undef PGM_SHW_NAME
581
582#endif /* !IN_RC */
583
584
585/**
586 * Guest mode data array.
587 */
588PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
589{
590 { UINT32_MAX, NULL, NULL, NULL, NULL, NULL }, /* 0 */
591 {
592 PGM_TYPE_REAL,
593 PGM_GST_NAME_REAL(GetPage),
594 PGM_GST_NAME_REAL(ModifyPage),
595 PGM_GST_NAME_REAL(GetPDE),
596 PGM_GST_NAME_REAL(Enter),
597 PGM_GST_NAME_REAL(Exit),
598#ifdef IN_RING3
599 PGM_GST_NAME_REAL(Relocate),
600#endif
601 },
602 {
603 PGM_TYPE_PROT,
604 PGM_GST_NAME_PROT(GetPage),
605 PGM_GST_NAME_PROT(ModifyPage),
606 PGM_GST_NAME_PROT(GetPDE),
607 PGM_GST_NAME_PROT(Enter),
608 PGM_GST_NAME_PROT(Exit),
609#ifdef IN_RING3
610 PGM_GST_NAME_PROT(Relocate),
611#endif
612 },
613 {
614 PGM_TYPE_32BIT,
615 PGM_GST_NAME_32BIT(GetPage),
616 PGM_GST_NAME_32BIT(ModifyPage),
617 PGM_GST_NAME_32BIT(GetPDE),
618 PGM_GST_NAME_32BIT(Enter),
619 PGM_GST_NAME_32BIT(Exit),
620#ifdef IN_RING3
621 PGM_GST_NAME_32BIT(Relocate),
622#endif
623 },
624 {
625 PGM_TYPE_PAE,
626 PGM_GST_NAME_PAE(GetPage),
627 PGM_GST_NAME_PAE(ModifyPage),
628 PGM_GST_NAME_PAE(GetPDE),
629 PGM_GST_NAME_PAE(Enter),
630 PGM_GST_NAME_PAE(Exit),
631#ifdef IN_RING3
632 PGM_GST_NAME_PAE(Relocate),
633#endif
634 },
635#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
636 {
637 PGM_TYPE_AMD64,
638 PGM_GST_NAME_AMD64(GetPage),
639 PGM_GST_NAME_AMD64(ModifyPage),
640 PGM_GST_NAME_AMD64(GetPDE),
641 PGM_GST_NAME_AMD64(Enter),
642 PGM_GST_NAME_AMD64(Exit),
643# ifdef IN_RING3
644 PGM_GST_NAME_AMD64(Relocate),
645# endif
646 },
647#endif
648};
649
650
651/**
652 * The shadow mode data array.
653 */
654PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
655{
656 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* 0 */
657 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
658 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
659 {
660 PGM_TYPE_32BIT,
661 PGM_SHW_NAME_32BIT(GetPage),
662 PGM_SHW_NAME_32BIT(ModifyPage),
663 PGM_SHW_NAME_32BIT(Enter),
664 PGM_SHW_NAME_32BIT(Exit),
665#ifdef IN_RING3
666 PGM_SHW_NAME_32BIT(Relocate),
667#endif
668 },
669 {
670 PGM_TYPE_PAE,
671 PGM_SHW_NAME_PAE(GetPage),
672 PGM_SHW_NAME_PAE(ModifyPage),
673 PGM_SHW_NAME_PAE(Enter),
674 PGM_SHW_NAME_PAE(Exit),
675#ifdef IN_RING3
676 PGM_SHW_NAME_PAE(Relocate),
677#endif
678 },
679#ifndef IN_RC
680 {
681 PGM_TYPE_AMD64,
682 PGM_SHW_NAME_AMD64(GetPage),
683 PGM_SHW_NAME_AMD64(ModifyPage),
684 PGM_SHW_NAME_AMD64(Enter),
685 PGM_SHW_NAME_AMD64(Exit),
686# ifdef IN_RING3
687 PGM_SHW_NAME_AMD64(Relocate),
688# endif
689 },
690 {
691 PGM_TYPE_NESTED_32BIT,
692 PGM_SHW_NAME_NESTED_32BIT(GetPage),
693 PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
694 PGM_SHW_NAME_NESTED_32BIT(Enter),
695 PGM_SHW_NAME_NESTED_32BIT(Exit),
696# ifdef IN_RING3
697 PGM_SHW_NAME_NESTED_32BIT(Relocate),
698# endif
699 },
700 {
701 PGM_TYPE_NESTED_PAE,
702 PGM_SHW_NAME_NESTED_PAE(GetPage),
703 PGM_SHW_NAME_NESTED_PAE(ModifyPage),
704 PGM_SHW_NAME_NESTED_PAE(Enter),
705 PGM_SHW_NAME_NESTED_PAE(Exit),
706# ifdef IN_RING3
707 PGM_SHW_NAME_NESTED_PAE(Relocate),
708# endif
709 },
710 {
711 PGM_TYPE_NESTED_AMD64,
712 PGM_SHW_NAME_NESTED_AMD64(GetPage),
713 PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
714 PGM_SHW_NAME_NESTED_AMD64(Enter),
715 PGM_SHW_NAME_NESTED_AMD64(Exit),
716# ifdef IN_RING3
717 PGM_SHW_NAME_NESTED_AMD64(Relocate),
718# endif
719 },
720 {
721 PGM_TYPE_EPT,
722 PGM_SHW_NAME_EPT(GetPage),
723 PGM_SHW_NAME_EPT(ModifyPage),
724 PGM_SHW_NAME_EPT(Enter),
725 PGM_SHW_NAME_EPT(Exit),
726# ifdef IN_RING3
727 PGM_SHW_NAME_EPT(Relocate),
728# endif
729 },
730 {
731 PGM_TYPE_NONE,
732 PGM_SHW_NAME_NONE(GetPage),
733 PGM_SHW_NAME_NONE(ModifyPage),
734 PGM_SHW_NAME_NONE(Enter),
735 PGM_SHW_NAME_NONE(Exit),
736# ifdef IN_RING3
737 PGM_SHW_NAME_NONE(Relocate),
738# endif
739 },
740#endif /* IN_RC */
741};
742
743
744/**
745 * The guest+shadow mode data array.
746 */
747PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
748{
749#if !defined(IN_RING3) && !defined(VBOX_STRICT)
750# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
751# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
752 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler) }
753
754#elif !defined(IN_RING3) && defined(VBOX_STRICT)
755# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
756# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
757 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(AssertCR3) }
758
759#elif defined(IN_RING3) && !defined(VBOX_STRICT)
760# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
761# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
762 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), }
763
764#elif defined(IN_RING3) && defined(VBOX_STRICT)
765# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
766# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
767 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(AssertCR3) }
768
769#else
770# error "Misconfig."
771#endif
772
773 /* 32-bit shadow paging mode: */
774 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
775 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
776 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
777 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
778 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
779 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
780 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
781 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
782 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
783 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
784 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NONE - illegal */
785
786 /* PAE shadow paging mode: */
787 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
788 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
789 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
790 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
791 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
792 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
793 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
794 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
795 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
796 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
797 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NONE - illegal */
798
799#ifndef IN_RC
800 /* AMD64 shadow paging mode: */
801 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
802 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
803 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
804 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
805 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
806# ifdef VBOX_WITH_64_BITS_GUESTS
807 PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
808# else
809 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
810# endif
811 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
812 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
813 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
814 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
815 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NONE - illegal */
816
817 /* 32-bit nested paging mode: */
818 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
819 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
820 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
821 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
822 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
823# ifdef VBOX_WITH_64_BITS_GUESTS
824 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
825# else
826 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
827# endif
828 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
829 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
830 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
831 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
832 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NONE - illegal */
833
834 /* PAE nested paging mode: */
835 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
836 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
837 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
838 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
839 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
840# ifdef VBOX_WITH_64_BITS_GUESTS
841 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
842# else
843 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
844# endif
845 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
846 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
847 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
848 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
849 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NONE - illegal */
850
851 /* AMD64 nested paging mode: */
852 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
853 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
854 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
855 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
856 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
857# ifdef VBOX_WITH_64_BITS_GUESTS
858 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
859# else
860 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
861# endif
862 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
863 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
864 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
865 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
866 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NONE - illegal */
867
868 /* EPT nested paging mode: */
869 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
870 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
871 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
872 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
873 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
874# ifdef VBOX_WITH_64_BITS_GUESTS
875 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
876# else
877 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
878# endif
879 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
880 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
881 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
882 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
883 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NONE - illegal */
884
885 /* NONE / NEM: */
886 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
887 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
888 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
889 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
890 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
891# ifdef VBOX_WITH_64_BITS_GUESTS
892 PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
893# else
894 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_AMD64 - illegal */
895# endif
896 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_32BIT - illegal */
897 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_PAE - illegal */
898 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_AMD64 - illegal */
899 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_EPT - illegal */
900 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NONE - illegal */
901
902#endif /* IN_RC */
903
904#undef PGMMODEDATABTH_ENTRY
905#undef PGMMODEDATABTH_NULL_ENTRY
906};
907
908
909#ifndef IN_RING3
910/**
911 * #PF Handler.
912 *
913 * @returns VBox status code (appropriate for trap handling and GC return).
914 * @param pVCpu The cross context virtual CPU structure.
915 * @param uErr The trap error code.
916 * @param pRegFrame Trap register frame.
917 * @param pvFault The fault address.
918 */
919VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
920{
921 PVM pVM = pVCpu->CTX_SUFF(pVM);
922
923 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
924 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
925 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
926
927
928#ifdef VBOX_WITH_STATISTICS
929 /*
930 * Error code stats.
931 */
932 if (uErr & X86_TRAP_PF_US)
933 {
934 if (!(uErr & X86_TRAP_PF_P))
935 {
936 if (uErr & X86_TRAP_PF_RW)
937 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
938 else
939 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
940 }
941 else if (uErr & X86_TRAP_PF_RW)
942 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
943 else if (uErr & X86_TRAP_PF_RSVD)
944 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
945 else if (uErr & X86_TRAP_PF_ID)
946 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
947 else
948 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
949 }
950 else
951 { /* Supervisor */
952 if (!(uErr & X86_TRAP_PF_P))
953 {
954 if (uErr & X86_TRAP_PF_RW)
955 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
956 else
957 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
958 }
959 else if (uErr & X86_TRAP_PF_RW)
960 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
961 else if (uErr & X86_TRAP_PF_ID)
962 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
963 else if (uErr & X86_TRAP_PF_RSVD)
964 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
965 }
966#endif /* VBOX_WITH_STATISTICS */
967
968 /*
969 * Call the worker.
970 */
971 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
972 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
973 AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
974 bool fLockTaken = false;
975 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
976 if (fLockTaken)
977 {
978 PGM_LOCK_ASSERT_OWNER(pVM);
979 pgmUnlock(pVM);
980 }
981 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
982
983 /*
984 * Return code tweaks.
985 */
986 if (rc != VINF_SUCCESS)
987 {
988 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
989 rc = VINF_SUCCESS;
990
991# ifdef IN_RING0
992 /* Note: hack alert for difficult to reproduce problem. */
993 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
994 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
995 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
996 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
997 {
998 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
999 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
1000 rc = VINF_SUCCESS;
1001 }
1002# endif
1003 }
1004
1005 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
1006 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
1007 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
1008 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
1009 return rc;
1010}
1011#endif /* !IN_RING3 */
1012
1013
1014/**
1015 * Prefetch a page
1016 *
1017 * Typically used to sync commonly used pages before entering raw mode
1018 * after a CR3 reload.
1019 *
1020 * @returns VBox status code suitable for scheduling.
1021 * @retval VINF_SUCCESS on success.
1022 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
1023 * @param pVCpu The cross context virtual CPU structure.
1024 * @param GCPtrPage Page to invalidate.
1025 */
1026VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1027{
1028 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
1029
1030 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1031 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1032 AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
1033 int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
1034
1035 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
1036 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1037 return rc;
1038}
1039
1040
1041#ifndef PGM_WITHOUT_MAPPINGS
1042/**
1043 * Gets the mapping corresponding to the specified address (if any).
1044 *
1045 * @returns Pointer to the mapping.
1046 * @returns NULL if not
1047 *
1048 * @param pVM The cross context VM structure.
1049 * @param GCPtr The guest context pointer.
1050 */
1051PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
1052{
1053 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
1054 while (pMapping)
1055 {
1056 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
1057 break;
1058 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
1059 return pMapping;
1060 pMapping = pMapping->CTX_SUFF(pNext);
1061 }
1062 return NULL;
1063}
1064#endif
1065
1066
1067/**
1068 * Verifies a range of pages for read or write access
1069 *
1070 * Only checks the guest's page tables
1071 *
1072 * @returns VBox status code.
1073 * @param pVCpu The cross context virtual CPU structure.
1074 * @param Addr Guest virtual address to check
1075 * @param cbSize Access size
1076 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
1077 * @remarks Current not in use.
1078 */
1079VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
1080{
1081 /*
1082 * Validate input.
1083 */
1084 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
1085 {
1086 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
1087 return VERR_INVALID_PARAMETER;
1088 }
1089
1090 uint64_t fPage;
1091 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
1092 if (RT_FAILURE(rc))
1093 {
1094 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
1095 return VINF_EM_RAW_GUEST_TRAP;
1096 }
1097
1098 /*
1099 * Check if the access would cause a page fault
1100 *
1101 * Note that hypervisor page directories are not present in the guest's tables, so this check
1102 * is sufficient.
1103 */
1104 bool fWrite = !!(fAccess & X86_PTE_RW);
1105 bool fUser = !!(fAccess & X86_PTE_US);
1106 if ( !(fPage & X86_PTE_P)
1107 || (fWrite && !(fPage & X86_PTE_RW))
1108 || (fUser && !(fPage & X86_PTE_US)) )
1109 {
1110 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
1111 return VINF_EM_RAW_GUEST_TRAP;
1112 }
1113 if ( RT_SUCCESS(rc)
1114 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
1115 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
1116 return rc;
1117}
1118
1119
1120/**
1121 * Verifies a range of pages for read or write access
1122 *
1123 * Supports handling of pages marked for dirty bit tracking and CSAM
1124 *
1125 * @returns VBox status code.
1126 * @param pVCpu The cross context virtual CPU structure.
1127 * @param Addr Guest virtual address to check
1128 * @param cbSize Access size
1129 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
1130 */
1131VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
1132{
1133 PVM pVM = pVCpu->CTX_SUFF(pVM);
1134
1135 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
1136
1137 /*
1138 * Get going.
1139 */
1140 uint64_t fPageGst;
1141 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
1142 if (RT_FAILURE(rc))
1143 {
1144 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
1145 return VINF_EM_RAW_GUEST_TRAP;
1146 }
1147
1148 /*
1149 * Check if the access would cause a page fault
1150 *
1151 * Note that hypervisor page directories are not present in the guest's tables, so this check
1152 * is sufficient.
1153 */
1154 const bool fWrite = !!(fAccess & X86_PTE_RW);
1155 const bool fUser = !!(fAccess & X86_PTE_US);
1156 if ( !(fPageGst & X86_PTE_P)
1157 || (fWrite && !(fPageGst & X86_PTE_RW))
1158 || (fUser && !(fPageGst & X86_PTE_US)) )
1159 {
1160 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
1161 return VINF_EM_RAW_GUEST_TRAP;
1162 }
1163
1164 if (!pVM->pgm.s.fNestedPaging)
1165 {
1166 /*
1167 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
1168 */
1169 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
1170 if ( rc == VERR_PAGE_NOT_PRESENT
1171 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
1172 {
1173 /*
1174 * Page is not present in our page tables.
1175 * Try to sync it!
1176 */
1177 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
1178 uint32_t const uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
1179 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1180 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1181 AssertReturn(g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
1182 rc = g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage(pVCpu, Addr, fPageGst, uErr);
1183 if (rc != VINF_SUCCESS)
1184 return rc;
1185 }
1186 else
1187 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
1188 }
1189
1190#if 0 /* def VBOX_STRICT; triggers too often now */
1191 /*
1192 * This check is a bit paranoid, but useful.
1193 */
1194 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
1195 uint64_t fPageShw;
1196 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
1197 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
1198 || (fWrite && !(fPageShw & X86_PTE_RW))
1199 || (fUser && !(fPageShw & X86_PTE_US)) )
1200 {
1201 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
1202 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
1203 return VINF_EM_RAW_GUEST_TRAP;
1204 }
1205#endif
1206
1207 if ( RT_SUCCESS(rc)
1208 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
1209 || Addr + cbSize < Addr))
1210 {
1211 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
1212 for (;;)
1213 {
1214 Addr += PAGE_SIZE;
1215 if (cbSize > PAGE_SIZE)
1216 cbSize -= PAGE_SIZE;
1217 else
1218 cbSize = 1;
1219 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
1220 if (rc != VINF_SUCCESS)
1221 break;
1222 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
1223 break;
1224 }
1225 }
1226 return rc;
1227}
1228
1229
1230/**
1231 * Emulation of the invlpg instruction (HC only actually).
1232 *
1233 * @returns Strict VBox status code, special care required.
1234 * @retval VINF_PGM_SYNC_CR3 - handled.
1235 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1236 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
1237 *
1238 * @param pVCpu The cross context virtual CPU structure.
1239 * @param GCPtrPage Page to invalidate.
1240 *
1241 * @remark ASSUMES the page table entry or page directory is valid. Fairly
1242 * safe, but there could be edge cases!
1243 *
1244 * @todo Flush page or page directory only if necessary!
1245 * @todo VBOXSTRICTRC
1246 */
1247VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1248{
1249 PVM pVM = pVCpu->CTX_SUFF(pVM);
1250 int rc;
1251 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1252
1253#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
1254 /*
1255 * Notify the recompiler so it can record this instruction.
1256 */
1257 REMNotifyInvalidatePage(pVM, GCPtrPage);
1258#endif /* !IN_RING3 */
1259 IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1260
1261
1262#ifdef IN_RC
1263 /*
1264 * Check for conflicts and pending CR3 monitoring updates.
1265 */
1266 if (pgmMapAreMappingsFloating(pVM))
1267 {
1268 if ( pgmGetMapping(pVM, GCPtrPage)
1269 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
1270 {
1271 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
1272 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1273 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
1274 return VINF_PGM_SYNC_CR3;
1275 }
1276
1277 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1278 {
1279 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
1280 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
1281 return VINF_EM_RAW_EMULATE_INSTR;
1282 }
1283 }
1284#endif /* IN_RC */
1285
1286 /*
1287 * Call paging mode specific worker.
1288 */
1289 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1290 pgmLock(pVM);
1291
1292 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1293 AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1294 AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1295 rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1296
1297 pgmUnlock(pVM);
1298 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1299
1300#ifdef IN_RING3
1301 /*
1302 * Check if we have a pending update of the CR3 monitoring.
1303 */
1304 if ( RT_SUCCESS(rc)
1305 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
1306 {
1307 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1308 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
1309 }
1310
1311# ifdef VBOX_WITH_RAW_MODE
1312 /*
1313 * Inform CSAM about the flush
1314 *
1315 * Note: This is to check if monitored pages have been changed; when we implement
1316 * callbacks for virtual handlers, this is no longer required.
1317 */
1318 CSAMR3FlushPage(pVM, GCPtrPage);
1319# endif
1320#endif /* IN_RING3 */
1321
1322 /* Ignore all irrelevant error codes. */
1323 if ( rc == VERR_PAGE_NOT_PRESENT
1324 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1325 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1326 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1327 rc = VINF_SUCCESS;
1328
1329 return rc;
1330}
1331
1332
1333/**
1334 * Executes an instruction using the interpreter.
1335 *
1336 * @returns VBox status code (appropriate for trap handling and GC return).
1337 * @param pVM The cross context VM structure.
1338 * @param pVCpu The cross context virtual CPU structure.
1339 * @param pRegFrame Register frame.
1340 * @param pvFault Fault address.
1341 */
1342VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1343{
1344 NOREF(pVM);
1345 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
1346 if (rc == VERR_EM_INTERPRETER)
1347 rc = VINF_EM_RAW_EMULATE_INSTR;
1348 if (rc != VINF_SUCCESS)
1349 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1350 return rc;
1351}
1352
1353
1354/**
1355 * Gets effective page information (from the VMM page directory).
1356 *
1357 * @returns VBox status code.
1358 * @param pVCpu The cross context virtual CPU structure.
1359 * @param GCPtr Guest Context virtual address of the page.
1360 * @param pfFlags Where to store the flags. These are X86_PTE_*.
1361 * @param pHCPhys Where to store the HC physical address of the page.
1362 * This is page aligned.
1363 * @remark You should use PGMMapGetPage() for pages in a mapping.
1364 */
1365VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1366{
1367 PVM pVM = pVCpu->CTX_SUFF(pVM);
1368 pgmLock(pVM);
1369
1370 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1371 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1372 AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1373 int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1374
1375 pgmUnlock(pVM);
1376 return rc;
1377}
1378
1379
1380/**
1381 * Modify page flags for a range of pages in the shadow context.
1382 *
1383 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1384 *
1385 * @returns VBox status code.
1386 * @param pVCpu The cross context virtual CPU structure.
1387 * @param GCPtr Virtual address of the first page in the range.
1388 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1389 * @param fMask The AND mask - page flags X86_PTE_*.
1390 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1391 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1392 * @remark You must use PGMMapModifyPage() for pages in a mapping.
1393 */
1394DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1395{
1396 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1397 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
1398
1399 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
1400
1401 PVM pVM = pVCpu->CTX_SUFF(pVM);
1402 pgmLock(pVM);
1403
1404 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1405 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1406 AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1407 int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
1408
1409 pgmUnlock(pVM);
1410 return rc;
1411}
1412
1413
1414/**
1415 * Changing the page flags for a single page in the shadow page tables so as to
1416 * make it read-only.
1417 *
1418 * @returns VBox status code.
1419 * @param pVCpu The cross context virtual CPU structure.
1420 * @param GCPtr Virtual address of the first page in the range.
1421 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1422 */
1423VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1424{
1425 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1426}
1427
1428
1429/**
1430 * Changing the page flags for a single page in the shadow page tables so as to
1431 * make it writable.
1432 *
1433 * The call must know with 101% certainty that the guest page tables maps this
1434 * as writable too. This function will deal shared, zero and write monitored
1435 * pages.
1436 *
1437 * @returns VBox status code.
1438 * @param pVCpu The cross context virtual CPU structure.
1439 * @param GCPtr Virtual address of the first page in the range.
1440 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1441 */
1442VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1443{
1444 if (pVCpu->pgm.s.enmShadowMode != PGMMODE_NONE) /* avoid assertions */
1445 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1446 return VINF_SUCCESS;
1447}
1448
1449
1450/**
1451 * Changing the page flags for a single page in the shadow page tables so as to
1452 * make it not present.
1453 *
1454 * @returns VBox status code.
1455 * @param pVCpu The cross context virtual CPU structure.
1456 * @param GCPtr Virtual address of the first page in the range.
1457 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1458 */
1459VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1460{
1461 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1462}
1463
1464
1465/**
1466 * Changing the page flags for a single page in the shadow page tables so as to
1467 * make it supervisor and writable.
1468 *
1469 * This if for dealing with CR0.WP=0 and readonly user pages.
1470 *
1471 * @returns VBox status code.
1472 * @param pVCpu The cross context virtual CPU structure.
1473 * @param GCPtr Virtual address of the first page in the range.
1474 * @param fBigPage Whether or not this is a big page. If it is, we have to
1475 * change the shadow PDE as well. If it isn't, the caller
1476 * has checked that the shadow PDE doesn't need changing.
1477 * We ASSUME 4KB pages backing the big page here!
1478 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1479 */
1480int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1481{
1482 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1483 if (rc == VINF_SUCCESS && fBigPage)
1484 {
1485 /* this is a bit ugly... */
1486 switch (pVCpu->pgm.s.enmShadowMode)
1487 {
1488 case PGMMODE_32_BIT:
1489 {
1490 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1491 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1492 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1493 pPde->n.u1Write = 1;
1494 Log(("-> PDE=%#llx (32)\n", pPde->u));
1495 break;
1496 }
1497 case PGMMODE_PAE:
1498 case PGMMODE_PAE_NX:
1499 {
1500 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1501 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1502 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1503 pPde->n.u1Write = 1;
1504 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1505 break;
1506 }
1507 default:
1508 AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1509 }
1510 }
1511 return rc;
1512}
1513
1514
1515/**
1516 * Gets the shadow page directory for the specified address, PAE.
1517 *
1518 * @returns Pointer to the shadow PD.
1519 * @param pVCpu The cross context virtual CPU structure.
1520 * @param GCPtr The address.
1521 * @param uGstPdpe Guest PDPT entry. Valid.
1522 * @param ppPD Receives address of page directory
1523 */
1524int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1525{
1526 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1527 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1528 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1529 PVM pVM = pVCpu->CTX_SUFF(pVM);
1530 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1531 PPGMPOOLPAGE pShwPage;
1532 int rc;
1533
1534 PGM_LOCK_ASSERT_OWNER(pVM);
1535
1536 /* Allocate page directory if not present. */
1537 if ( !pPdpe->n.u1Present
1538 && !(pPdpe->u & X86_PDPE_PG_MASK))
1539 {
1540 RTGCPTR64 GCPdPt;
1541 PGMPOOLKIND enmKind;
1542
1543 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
1544 {
1545 /* AMD-V nested paging or real/protected mode without paging. */
1546 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1547 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1548 }
1549 else
1550 {
1551 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1552 {
1553 if (!(uGstPdpe & X86_PDPE_P))
1554 {
1555 /* PD not present; guest must reload CR3 to change it.
1556 * No need to monitor anything in this case.
1557 */
1558 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1559
1560 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1561 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1562 uGstPdpe |= X86_PDPE_P;
1563 }
1564 else
1565 {
1566 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1567 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1568 }
1569 }
1570 else
1571 {
1572 GCPdPt = CPUMGetGuestCR3(pVCpu);
1573 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1574 }
1575 }
1576
1577 /* Create a reference back to the PDPT by using the index in its shadow page. */
1578 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1579 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1580 &pShwPage);
1581 AssertRCReturn(rc, rc);
1582
1583 /* The PD was cached or created; hook it up now. */
1584 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
1585
1586# if defined(IN_RC)
1587 /*
1588 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
1589 * PDPT entry; the CPU fetches them only during cr3 load, so any
1590 * non-present PDPT will continue to cause page faults.
1591 */
1592 ASMReloadCR3();
1593# endif
1594 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1595 }
1596 else
1597 {
1598 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1599 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1600 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1601
1602 pgmPoolCacheUsed(pPool, pShwPage);
1603 }
1604 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1605 return VINF_SUCCESS;
1606}
1607
1608
1609/**
1610 * Gets the pointer to the shadow page directory entry for an address, PAE.
1611 *
1612 * @returns Pointer to the PDE.
1613 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1614 * @param GCPtr The address.
1615 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1616 */
1617DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1618{
1619 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1620 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1621 PVM pVM = pVCpu->CTX_SUFF(pVM);
1622
1623 PGM_LOCK_ASSERT_OWNER(pVM);
1624
1625 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1626 if (!pPdpt->a[iPdPt].n.u1Present)
1627 {
1628 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1629 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1630 }
1631 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1632
1633 /* Fetch the pgm pool shadow descriptor. */
1634 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1635 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1636
1637 *ppShwPde = pShwPde;
1638 return VINF_SUCCESS;
1639}
1640
1641#ifndef IN_RC
1642
1643/**
1644 * Syncs the SHADOW page directory pointer for the specified address.
1645 *
1646 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1647 *
1648 * The caller is responsible for making sure the guest has a valid PD before
1649 * calling this function.
1650 *
1651 * @returns VBox status code.
1652 * @param pVCpu The cross context virtual CPU structure.
1653 * @param GCPtr The address.
1654 * @param uGstPml4e Guest PML4 entry (valid).
1655 * @param uGstPdpe Guest PDPT entry (valid).
1656 * @param ppPD Receives address of page directory
1657 */
1658static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1659{
1660 PVM pVM = pVCpu->CTX_SUFF(pVM);
1661 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1662 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1663 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1664 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1665 PPGMPOOLPAGE pShwPage;
1666 int rc;
1667
1668 PGM_LOCK_ASSERT_OWNER(pVM);
1669
1670 /* Allocate page directory pointer table if not present. */
1671 if ( !pPml4e->n.u1Present
1672 && !(pPml4e->u & X86_PML4E_PG_MASK))
1673 {
1674 RTGCPTR64 GCPml4;
1675 PGMPOOLKIND enmKind;
1676
1677 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1678
1679 if (fNestedPagingOrNoGstPaging)
1680 {
1681 /* AMD-V nested paging or real/protected mode without paging */
1682 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1683 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1684 }
1685 else
1686 {
1687 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1688 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1689 }
1690
1691 /* Create a reference back to the PDPT by using the index in its shadow page. */
1692 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1693 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1694 &pShwPage);
1695 AssertRCReturn(rc, rc);
1696 }
1697 else
1698 {
1699 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1700 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1701
1702 pgmPoolCacheUsed(pPool, pShwPage);
1703 }
1704 /* The PDPT was cached or created; hook it up now. */
1705 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1706
1707 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1708 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1709 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1710
1711 /* Allocate page directory if not present. */
1712 if ( !pPdpe->n.u1Present
1713 && !(pPdpe->u & X86_PDPE_PG_MASK))
1714 {
1715 RTGCPTR64 GCPdPt;
1716 PGMPOOLKIND enmKind;
1717
1718 if (fNestedPagingOrNoGstPaging)
1719 {
1720 /* AMD-V nested paging or real/protected mode without paging */
1721 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1722 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1723 }
1724 else
1725 {
1726 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1727 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1728 }
1729
1730 /* Create a reference back to the PDPT by using the index in its shadow page. */
1731 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1732 pShwPage->idx, iPdPt, false /*fLockPage*/,
1733 &pShwPage);
1734 AssertRCReturn(rc, rc);
1735 }
1736 else
1737 {
1738 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1739 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1740
1741 pgmPoolCacheUsed(pPool, pShwPage);
1742 }
1743 /* The PD was cached or created; hook it up now. */
1744 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1745
1746 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/**
1752 * Gets the SHADOW page directory pointer for the specified address (long mode).
1753 *
1754 * @returns VBox status code.
1755 * @param pVCpu The cross context virtual CPU structure.
1756 * @param GCPtr The address.
1757 * @param ppPdpt Receives address of pdpt
1758 * @param ppPD Receives address of page directory
1759 */
1760DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1761{
1762 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1763 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1764
1765 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1766
1767 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1768 if (ppPml4e)
1769 *ppPml4e = (PX86PML4E)pPml4e;
1770
1771 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1772
1773 if (!pPml4e->n.u1Present)
1774 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1775
1776 PVM pVM = pVCpu->CTX_SUFF(pVM);
1777 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1778 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1779 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1780
1781 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1782 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1783 if (!pPdpt->a[iPdPt].n.u1Present)
1784 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1785
1786 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1787 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1788
1789 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1790 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1791 return VINF_SUCCESS;
1792}
1793
1794
1795/**
1796 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1797 * backing pages in case the PDPT or PML4 entry is missing.
1798 *
1799 * @returns VBox status code.
1800 * @param pVCpu The cross context virtual CPU structure.
1801 * @param GCPtr The address.
1802 * @param ppPdpt Receives address of pdpt
1803 * @param ppPD Receives address of page directory
1804 */
1805static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1806{
1807 PVM pVM = pVCpu->CTX_SUFF(pVM);
1808 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1809 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1810 PEPTPML4 pPml4;
1811 PEPTPML4E pPml4e;
1812 PPGMPOOLPAGE pShwPage;
1813 int rc;
1814
1815 Assert(pVM->pgm.s.fNestedPaging);
1816 PGM_LOCK_ASSERT_OWNER(pVM);
1817
1818 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1819 Assert(pPml4);
1820
1821 /* Allocate page directory pointer table if not present. */
1822 pPml4e = &pPml4->a[iPml4];
1823 if ( !pPml4e->n.u1Present
1824 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1825 {
1826 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1827 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1828
1829 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1830 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1831 &pShwPage);
1832 AssertRCReturn(rc, rc);
1833 }
1834 else
1835 {
1836 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1837 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1838
1839 pgmPoolCacheUsed(pPool, pShwPage);
1840 }
1841 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1842 pPml4e->u = pShwPage->Core.Key;
1843 pPml4e->n.u1Present = 1;
1844 pPml4e->n.u1Write = 1;
1845 pPml4e->n.u1Execute = 1;
1846
1847 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1848 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1849 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1850
1851 if (ppPdpt)
1852 *ppPdpt = pPdpt;
1853
1854 /* Allocate page directory if not present. */
1855 if ( !pPdpe->n.u1Present
1856 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1857 {
1858 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1859 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1860 pShwPage->idx, iPdPt, false /*fLockPage*/,
1861 &pShwPage);
1862 AssertRCReturn(rc, rc);
1863 }
1864 else
1865 {
1866 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1867 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1868
1869 pgmPoolCacheUsed(pPool, pShwPage);
1870 }
1871 /* The PD was cached or created; hook it up now and fill with the default value. */
1872 pPdpe->u = pShwPage->Core.Key;
1873 pPdpe->n.u1Present = 1;
1874 pPdpe->n.u1Write = 1;
1875 pPdpe->n.u1Execute = 1;
1876
1877 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1878 return VINF_SUCCESS;
1879}
1880
1881#endif /* IN_RC */
1882
1883#ifdef IN_RING0
1884/**
1885 * Synchronizes a range of nested page table entries.
1886 *
1887 * The caller must own the PGM lock.
1888 *
1889 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1890 * @param GCPhys Where to start.
1891 * @param cPages How many pages which entries should be synced.
1892 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1893 * host paging mode for AMD-V).
1894 */
1895int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1896{
1897 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1898
1899/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1900 int rc;
1901 switch (enmShwPagingMode)
1902 {
1903 case PGMMODE_32_BIT:
1904 {
1905 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1906 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1907 break;
1908 }
1909
1910 case PGMMODE_PAE:
1911 case PGMMODE_PAE_NX:
1912 {
1913 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1914 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1915 break;
1916 }
1917
1918 case PGMMODE_AMD64:
1919 case PGMMODE_AMD64_NX:
1920 {
1921 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1922 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1923 break;
1924 }
1925
1926 case PGMMODE_EPT:
1927 {
1928 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1929 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1930 break;
1931 }
1932
1933 default:
1934 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1935 }
1936 return rc;
1937}
1938#endif /* IN_RING0 */
1939
1940
1941/**
1942 * Gets effective Guest OS page information.
1943 *
1944 * When GCPtr is in a big page, the function will return as if it was a normal
1945 * 4KB page. If the need for distinguishing between big and normal page becomes
1946 * necessary at a later point, a PGMGstGetPage() will be created for that
1947 * purpose.
1948 *
1949 * @returns VBox status code.
1950 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1951 * @param GCPtr Guest Context virtual address of the page.
1952 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1953 * @param pGCPhys Where to store the GC physical address of the page.
1954 * This is page aligned. The fact that the
1955 */
1956VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1957{
1958 VMCPU_ASSERT_EMT(pVCpu);
1959 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1960 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1961 AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1962 return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pfFlags, pGCPhys);
1963}
1964
1965
1966/**
1967 * Performs a guest page table walk.
1968 *
1969 * The guest should be in paged protect mode or long mode when making a call to
1970 * this function.
1971 *
1972 * @returns VBox status code.
1973 * @retval VINF_SUCCESS on success.
1974 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1975 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1976 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1977 *
1978 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1979 * @param GCPtr The guest virtual address to walk by.
1980 * @param pWalk Where to return the walk result. This is valid for some
1981 * error codes as well.
1982 */
1983int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1984{
1985 VMCPU_ASSERT_EMT(pVCpu);
1986 switch (pVCpu->pgm.s.enmGuestMode)
1987 {
1988 case PGMMODE_32_BIT:
1989 pWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1990 return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, &pWalk->u.Legacy);
1991
1992 case PGMMODE_PAE:
1993 case PGMMODE_PAE_NX:
1994 pWalk->enmType = PGMPTWALKGSTTYPE_PAE;
1995 return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, &pWalk->u.Pae);
1996
1997#if !defined(IN_RC)
1998 case PGMMODE_AMD64:
1999 case PGMMODE_AMD64_NX:
2000 pWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
2001 return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, &pWalk->u.Amd64);
2002#endif
2003
2004 case PGMMODE_REAL:
2005 case PGMMODE_PROTECTED:
2006 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2007 return VERR_PGM_NOT_USED_IN_MODE;
2008
2009#if defined(IN_RC)
2010 case PGMMODE_AMD64:
2011 case PGMMODE_AMD64_NX:
2012#endif
2013 case PGMMODE_NESTED_32BIT:
2014 case PGMMODE_NESTED_PAE:
2015 case PGMMODE_NESTED_AMD64:
2016 case PGMMODE_EPT:
2017 default:
2018 AssertFailed();
2019 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2020 return VERR_PGM_NOT_USED_IN_MODE;
2021 }
2022}
2023
2024
2025/**
2026 * Tries to continue the previous walk.
2027 *
2028 * @note Requires the caller to hold the PGM lock from the first
2029 * pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
2030 * we cannot use the pointers.
2031 *
2032 * @returns VBox status code.
2033 * @retval VINF_SUCCESS on success.
2034 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2035 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2036 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2037 *
2038 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2039 * @param GCPtr The guest virtual address to walk by.
2040 * @param pWalk Pointer to the previous walk result and where to return
2041 * the result of this walk. This is valid for some error
2042 * codes as well.
2043 */
2044int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
2045{
2046 /*
2047 * We can only handle successfully walks.
2048 * We also limit ourselves to the next page.
2049 */
2050 if ( pWalk->u.Core.fSucceeded
2051 && GCPtr - pWalk->u.Core.GCPtr == PAGE_SIZE)
2052 {
2053 Assert(pWalk->u.Core.uLevel == 0);
2054 if (pWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
2055 {
2056 /*
2057 * AMD64
2058 */
2059 if (!pWalk->u.Core.fGigantPage && !pWalk->u.Core.fBigPage)
2060 {
2061 /*
2062 * We fall back to full walk if the PDE table changes, if any
2063 * reserved bits are set, or if the effective page access changes.
2064 */
2065 const uint64_t fPteSame = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT
2066 | X86_PTE_PCD | X86_PTE_A | X86_PTE_PAE_NX;
2067 const uint64_t fPdeSame = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT
2068 | X86_PDE_PCD | X86_PDE_A | X86_PDE_PAE_NX | X86_PDE_PS;
2069
2070 if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PD_PAE_SHIFT))
2071 {
2072 if (pWalk->u.Amd64.pPte)
2073 {
2074 X86PTEPAE Pte;
2075 Pte.u = pWalk->u.Amd64.pPte[1].u;
2076 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
2077 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2078 {
2079
2080 pWalk->u.Core.GCPtr = GCPtr;
2081 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2082 pWalk->u.Amd64.Pte.u = Pte.u;
2083 pWalk->u.Amd64.pPte++;
2084 return VINF_SUCCESS;
2085 }
2086 }
2087 }
2088 else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PDPT_SHIFT))
2089 {
2090 Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
2091 if (pWalk->u.Amd64.pPde)
2092 {
2093 X86PDEPAE Pde;
2094 Pde.u = pWalk->u.Amd64.pPde[1].u;
2095 if ( (Pde.u & fPdeSame) == (pWalk->u.Amd64.Pde.u & fPdeSame)
2096 && !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
2097 {
2098 /* Get the new PTE and check out the first entry. */
2099 int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2100 &pWalk->u.Amd64.pPt);
2101 if (RT_SUCCESS(rc))
2102 {
2103 pWalk->u.Amd64.pPte = &pWalk->u.Amd64.pPt->a[0];
2104 X86PTEPAE Pte;
2105 Pte.u = pWalk->u.Amd64.pPte->u;
2106 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
2107 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2108 {
2109 pWalk->u.Core.GCPtr = GCPtr;
2110 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2111 pWalk->u.Amd64.Pte.u = Pte.u;
2112 pWalk->u.Amd64.Pde.u = Pde.u;
2113 pWalk->u.Amd64.pPde++;
2114 return VINF_SUCCESS;
2115 }
2116 }
2117 }
2118 }
2119 }
2120 }
2121 else if (!pWalk->u.Core.fGigantPage)
2122 {
2123 if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_2M_BASE_MASK))
2124 {
2125 pWalk->u.Core.GCPtr = GCPtr;
2126 pWalk->u.Core.GCPhys += PAGE_SIZE;
2127 return VINF_SUCCESS;
2128 }
2129 }
2130 else
2131 {
2132 if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_1G_BASE_MASK))
2133 {
2134 pWalk->u.Core.GCPtr = GCPtr;
2135 pWalk->u.Core.GCPhys += PAGE_SIZE;
2136 return VINF_SUCCESS;
2137 }
2138 }
2139 }
2140 }
2141 /* Case we don't handle. Do full walk. */
2142 return pgmGstPtWalk(pVCpu, GCPtr, pWalk);
2143}
2144
2145
2146/**
2147 * Checks if the page is present.
2148 *
2149 * @returns true if the page is present.
2150 * @returns false if the page is not present.
2151 * @param pVCpu The cross context virtual CPU structure.
2152 * @param GCPtr Address within the page.
2153 */
2154VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
2155{
2156 VMCPU_ASSERT_EMT(pVCpu);
2157 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
2158 return RT_SUCCESS(rc);
2159}
2160
2161
2162/**
2163 * Sets (replaces) the page flags for a range of pages in the guest's tables.
2164 *
2165 * @returns VBox status code.
2166 * @param pVCpu The cross context virtual CPU structure.
2167 * @param GCPtr The address of the first page.
2168 * @param cb The size of the range in bytes.
2169 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
2170 */
2171VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
2172{
2173 VMCPU_ASSERT_EMT(pVCpu);
2174 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
2175}
2176
2177
2178/**
2179 * Modify page flags for a range of pages in the guest's tables
2180 *
2181 * The existing flags are ANDed with the fMask and ORed with the fFlags.
2182 *
2183 * @returns VBox status code.
2184 * @param pVCpu The cross context virtual CPU structure.
2185 * @param GCPtr Virtual address of the first page in the range.
2186 * @param cb Size (in bytes) of the range to apply the modification to.
2187 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2188 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2189 * Be very CAREFUL when ~'ing constants which could be 32-bit!
2190 */
2191VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2192{
2193 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2194 VMCPU_ASSERT_EMT(pVCpu);
2195
2196 /*
2197 * Validate input.
2198 */
2199 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2200 Assert(cb);
2201
2202 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2203
2204 /*
2205 * Adjust input.
2206 */
2207 cb += GCPtr & PAGE_OFFSET_MASK;
2208 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
2209 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
2210
2211 /*
2212 * Call worker.
2213 */
2214 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2215 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2216 AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2217 int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2218
2219 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2220 return rc;
2221}
2222
2223
2224#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2225
2226/**
2227 * Performs the lazy mapping of the 32-bit guest PD.
2228 *
2229 * @returns VBox status code.
2230 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2231 * @param ppPd Where to return the pointer to the mapping. This is
2232 * always set.
2233 */
2234int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
2235{
2236 PVM pVM = pVCpu->CTX_SUFF(pVM);
2237 pgmLock(pVM);
2238
2239 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2240
2241 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
2242 PPGMPAGE pPage;
2243 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2244 if (RT_SUCCESS(rc))
2245 {
2246 RTHCPTR HCPtrGuestCR3;
2247 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2248 if (RT_SUCCESS(rc))
2249 {
2250 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
2251# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2252 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
2253# endif
2254 *ppPd = (PX86PD)HCPtrGuestCR3;
2255
2256 pgmUnlock(pVM);
2257 return VINF_SUCCESS;
2258 }
2259
2260 AssertRC(rc);
2261 }
2262 pgmUnlock(pVM);
2263
2264 *ppPd = NULL;
2265 return rc;
2266}
2267
2268
2269/**
2270 * Performs the lazy mapping of the PAE guest PDPT.
2271 *
2272 * @returns VBox status code.
2273 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2274 * @param ppPdpt Where to return the pointer to the mapping. This is
2275 * always set.
2276 */
2277int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
2278{
2279 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2280 PVM pVM = pVCpu->CTX_SUFF(pVM);
2281 pgmLock(pVM);
2282
2283 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
2284 PPGMPAGE pPage;
2285 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2286 if (RT_SUCCESS(rc))
2287 {
2288 RTHCPTR HCPtrGuestCR3;
2289 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2290 if (RT_SUCCESS(rc))
2291 {
2292 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2293# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2294 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2295# endif
2296 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
2297
2298 pgmUnlock(pVM);
2299 return VINF_SUCCESS;
2300 }
2301
2302 AssertRC(rc);
2303 }
2304
2305 pgmUnlock(pVM);
2306 *ppPdpt = NULL;
2307 return rc;
2308}
2309
2310
2311/**
2312 * Performs the lazy mapping / updating of a PAE guest PD.
2313 *
2314 * @returns Pointer to the mapping.
2315 * @returns VBox status code.
2316 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2317 * @param iPdpt Which PD entry to map (0..3).
2318 * @param ppPd Where to return the pointer to the mapping. This is
2319 * always set.
2320 */
2321int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2322{
2323 PVM pVM = pVCpu->CTX_SUFF(pVM);
2324 pgmLock(pVM);
2325
2326 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2327 Assert(pGuestPDPT);
2328 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
2329 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2330 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2331
2332 PPGMPAGE pPage;
2333 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2334 if (RT_SUCCESS(rc))
2335 {
2336 RTRCPTR RCPtr = NIL_RTRCPTR;
2337 RTHCPTR HCPtr = NIL_RTHCPTR;
2338#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2339 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
2340 AssertRC(rc);
2341#endif
2342 if (RT_SUCCESS(rc))
2343 {
2344 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
2345# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2346 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
2347# endif
2348 if (fChanged)
2349 {
2350 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2351 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
2352 }
2353
2354 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
2355 pgmUnlock(pVM);
2356 return VINF_SUCCESS;
2357 }
2358 }
2359
2360 /* Invalid page or some failure, invalidate the entry. */
2361 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2362 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
2363# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2364 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
2365# endif
2366 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
2367
2368 pgmUnlock(pVM);
2369 return rc;
2370}
2371
2372#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2373#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2374/**
2375 * Performs the lazy mapping of the 32-bit guest PD.
2376 *
2377 * @returns VBox status code.
2378 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2379 * @param ppPml4 Where to return the pointer to the mapping. This will
2380 * always be set.
2381 */
2382int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
2383{
2384 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2385 PVM pVM = pVCpu->CTX_SUFF(pVM);
2386 pgmLock(pVM);
2387
2388 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
2389 PPGMPAGE pPage;
2390 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2391 if (RT_SUCCESS(rc))
2392 {
2393 RTHCPTR HCPtrGuestCR3;
2394 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2395 if (RT_SUCCESS(rc))
2396 {
2397 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
2398# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2399 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
2400# endif
2401 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
2402
2403 pgmUnlock(pVM);
2404 return VINF_SUCCESS;
2405 }
2406 }
2407
2408 pgmUnlock(pVM);
2409 *ppPml4 = NULL;
2410 return rc;
2411}
2412#endif
2413
2414
2415/**
2416 * Gets the PAE PDPEs values cached by the CPU.
2417 *
2418 * @returns VBox status code.
2419 * @param pVCpu The cross context virtual CPU structure.
2420 * @param paPdpes Where to return the four PDPEs. The array
2421 * pointed to must have 4 entries.
2422 */
2423VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
2424{
2425 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2426
2427 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
2428 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
2429 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
2430 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
2431 return VINF_SUCCESS;
2432}
2433
2434
2435/**
2436 * Sets the PAE PDPEs values cached by the CPU.
2437 *
2438 * @remarks This must be called *AFTER* PGMUpdateCR3.
2439 *
2440 * @param pVCpu The cross context virtual CPU structure.
2441 * @param paPdpes The four PDPE values. The array pointed to must
2442 * have exactly 4 entries.
2443 *
2444 * @remarks No-long-jump zone!!!
2445 */
2446VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
2447{
2448 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2449
2450 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
2451 {
2452 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
2453 {
2454 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
2455
2456 /* Force lazy remapping if it changed in any way. */
2457 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2458# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2459 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2460# endif
2461 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
2462 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2463 }
2464 }
2465
2466 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
2467}
2468
2469
2470/**
2471 * Gets the current CR3 register value for the shadow memory context.
2472 * @returns CR3 value.
2473 * @param pVCpu The cross context virtual CPU structure.
2474 */
2475VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2476{
2477 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2478 AssertPtrReturn(pPoolPage, NIL_RTHCPHYS);
2479 return pPoolPage->Core.Key;
2480}
2481
2482
2483/**
2484 * Performs and schedules necessary updates following a CR3 load or reload.
2485 *
2486 * This will normally involve mapping the guest PD or nPDPT
2487 *
2488 * @returns VBox status code.
2489 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2490 * safely be ignored and overridden since the FF will be set too then.
2491 * @param pVCpu The cross context virtual CPU structure.
2492 * @param cr3 The new cr3.
2493 * @param fGlobal Indicates whether this is a global flush or not.
2494 */
2495VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
2496{
2497 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2498 PVM pVM = pVCpu->CTX_SUFF(pVM);
2499
2500 VMCPU_ASSERT_EMT(pVCpu);
2501
2502 /*
2503 * Always flag the necessary updates; necessary for hardware acceleration
2504 */
2505 /** @todo optimize this, it shouldn't always be necessary. */
2506 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2507 if (fGlobal)
2508 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2509 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
2510
2511 /*
2512 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2513 */
2514 int rc = VINF_SUCCESS;
2515 RTGCPHYS GCPhysCR3;
2516 switch (pVCpu->pgm.s.enmGuestMode)
2517 {
2518 case PGMMODE_PAE:
2519 case PGMMODE_PAE_NX:
2520 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2521 break;
2522 case PGMMODE_AMD64:
2523 case PGMMODE_AMD64_NX:
2524 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2525 break;
2526 default:
2527 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2528 break;
2529 }
2530 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2531
2532 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2533 if (GCPhysOldCR3 != GCPhysCR3)
2534 {
2535 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2536 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2537 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2538
2539 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2540 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2541 if (RT_LIKELY(rc == VINF_SUCCESS))
2542 {
2543 if (pgmMapAreMappingsFloating(pVM))
2544 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2545 }
2546 else
2547 {
2548 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2549 Assert(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
2550 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2551 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
2552 if (pgmMapAreMappingsFloating(pVM))
2553 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
2554 }
2555
2556 if (fGlobal)
2557 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2558 else
2559 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
2560 }
2561 else
2562 {
2563# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2564 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2565 if (pPool->cDirtyPages)
2566 {
2567 pgmLock(pVM);
2568 pgmPoolResetDirtyPages(pVM);
2569 pgmUnlock(pVM);
2570 }
2571# endif
2572 /*
2573 * Check if we have a pending update of the CR3 monitoring.
2574 */
2575 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2576 {
2577 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2578 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
2579 }
2580 if (fGlobal)
2581 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2582 else
2583 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
2584 }
2585
2586 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
2587 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2588 return rc;
2589}
2590
2591
2592/**
2593 * Performs and schedules necessary updates following a CR3 load or reload when
2594 * using nested or extended paging.
2595 *
2596 * This API is an alternative to PGMFlushTLB that avoids actually flushing the
2597 * TLB and triggering a SyncCR3.
2598 *
2599 * This will normally involve mapping the guest PD or nPDPT
2600 *
2601 * @returns VBox status code.
2602 * @retval VINF_SUCCESS.
2603 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2604 * paging modes). This can safely be ignored and overridden since the
2605 * FF will be set too then.
2606 * @param pVCpu The cross context virtual CPU structure.
2607 * @param cr3 The new cr3.
2608 */
2609VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
2610{
2611 VMCPU_ASSERT_EMT(pVCpu);
2612 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
2613
2614 /* We assume we're only called in nested paging mode. */
2615 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2616 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2617 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
2618
2619 /*
2620 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2621 */
2622 int rc = VINF_SUCCESS;
2623 RTGCPHYS GCPhysCR3;
2624 switch (pVCpu->pgm.s.enmGuestMode)
2625 {
2626 case PGMMODE_PAE:
2627 case PGMMODE_PAE_NX:
2628 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2629 break;
2630 case PGMMODE_AMD64:
2631 case PGMMODE_AMD64_NX:
2632 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2633 break;
2634 default:
2635 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2636 break;
2637 }
2638 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2639
2640 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2641 {
2642 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2643 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2644 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2645
2646 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2647 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2648
2649 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
2650 }
2651
2652 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2653 return rc;
2654}
2655
2656
2657/**
2658 * Synchronize the paging structures.
2659 *
2660 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2661 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2662 * in several places, most importantly whenever the CR3 is loaded.
2663 *
2664 * @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2665 * @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2666 * the VMM into guest context.
2667 * @param pVCpu The cross context virtual CPU structure.
2668 * @param cr0 Guest context CR0 register
2669 * @param cr3 Guest context CR3 register
2670 * @param cr4 Guest context CR4 register
2671 * @param fGlobal Including global page directories or not
2672 */
2673VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2674{
2675 int rc;
2676
2677 VMCPU_ASSERT_EMT(pVCpu);
2678
2679 /*
2680 * The pool may have pending stuff and even require a return to ring-3 to
2681 * clear the whole thing.
2682 */
2683 rc = pgmPoolSyncCR3(pVCpu);
2684 if (rc != VINF_SUCCESS)
2685 return rc;
2686
2687 /*
2688 * We might be called when we shouldn't.
2689 *
2690 * The mode switching will ensure that the PD is resynced after every mode
2691 * switch. So, if we find ourselves here when in protected or real mode
2692 * we can safely clear the FF and return immediately.
2693 */
2694 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2695 {
2696 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2697 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2698 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2699 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2700 return VINF_SUCCESS;
2701 }
2702
2703 /* If global pages are not supported, then all flushes are global. */
2704 if (!(cr4 & X86_CR4_PGE))
2705 fGlobal = true;
2706 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2707 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2708
2709 /*
2710 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2711 * This should be done before SyncCR3.
2712 */
2713 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2714 {
2715 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2716
2717 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2718 RTGCPHYS GCPhysCR3;
2719 switch (pVCpu->pgm.s.enmGuestMode)
2720 {
2721 case PGMMODE_PAE:
2722 case PGMMODE_PAE_NX:
2723 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2724 break;
2725 case PGMMODE_AMD64:
2726 case PGMMODE_AMD64_NX:
2727 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2728 break;
2729 default:
2730 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2731 break;
2732 }
2733 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2734
2735 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2736 {
2737 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2738 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2739 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2740 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2741 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2742 }
2743
2744 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2745 if ( rc == VINF_PGM_SYNC_CR3
2746 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2747 {
2748 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2749#ifdef IN_RING3
2750 rc = pgmPoolSyncCR3(pVCpu);
2751#else
2752 if (rc == VINF_PGM_SYNC_CR3)
2753 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2754 return VINF_PGM_SYNC_CR3;
2755#endif
2756 }
2757 AssertRCReturn(rc, rc);
2758 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2759 }
2760
2761 /*
2762 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2763 */
2764 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2765
2766 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2767 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2768 AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2769 rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2770
2771 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2772 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2773 if (rc == VINF_SUCCESS)
2774 {
2775 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2776 {
2777 /* Go back to ring 3 if a pgm pool sync is again pending. */
2778 return VINF_PGM_SYNC_CR3;
2779 }
2780
2781 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2782 {
2783 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2784 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2785 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2786 }
2787
2788 /*
2789 * Check if we have a pending update of the CR3 monitoring.
2790 */
2791 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2792 {
2793 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2794 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2795 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2796 }
2797 }
2798
2799 /*
2800 * Now flush the CR3 (guest context).
2801 */
2802 if (rc == VINF_SUCCESS)
2803 PGM_INVL_VCPU_TLBS(pVCpu);
2804 return rc;
2805}
2806
2807
2808/**
2809 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2810 *
2811 * @returns VBox status code, with the following informational code for
2812 * VM scheduling.
2813 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2814 * @retval VINF_PGM_CHANGE_MODE if we're in RC the mode changes. This will
2815 * NOT be returned in ring-3 or ring-0.
2816 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2817 *
2818 * @param pVCpu The cross context virtual CPU structure.
2819 * @param cr0 The new cr0.
2820 * @param cr4 The new cr4.
2821 * @param efer The new extended feature enable register.
2822 */
2823VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2824{
2825 VMCPU_ASSERT_EMT(pVCpu);
2826
2827 /*
2828 * Calc the new guest mode.
2829 *
2830 * Note! We check PG before PE and without requiring PE because of the
2831 * special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
2832 */
2833 PGMMODE enmGuestMode;
2834 if (cr0 & X86_CR0_PG)
2835 {
2836 if (!(cr4 & X86_CR4_PAE))
2837 {
2838 bool const fPse = !!(cr4 & X86_CR4_PSE);
2839 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2840 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2841 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2842 enmGuestMode = PGMMODE_32_BIT;
2843 }
2844 else if (!(efer & MSR_K6_EFER_LME))
2845 {
2846 if (!(efer & MSR_K6_EFER_NXE))
2847 enmGuestMode = PGMMODE_PAE;
2848 else
2849 enmGuestMode = PGMMODE_PAE_NX;
2850 }
2851 else
2852 {
2853 if (!(efer & MSR_K6_EFER_NXE))
2854 enmGuestMode = PGMMODE_AMD64;
2855 else
2856 enmGuestMode = PGMMODE_AMD64_NX;
2857 }
2858 }
2859 else if (!(cr0 & X86_CR0_PE))
2860 enmGuestMode = PGMMODE_REAL;
2861 else
2862 enmGuestMode = PGMMODE_PROTECTED;
2863
2864 /*
2865 * Did it change?
2866 */
2867 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2868 return VINF_SUCCESS;
2869
2870 /* Flush the TLB */
2871 PGM_INVL_VCPU_TLBS(pVCpu);
2872
2873#ifndef IN_RC
2874 return PGMHCChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2875#else
2876 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2877 return VINF_PGM_CHANGE_MODE;
2878#endif
2879}
2880
2881#ifndef IN_RC
2882
2883/**
2884 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2885 *
2886 * @returns PGM_TYPE_*.
2887 * @param pgmMode The mode value to convert.
2888 */
2889DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2890{
2891 switch (pgmMode)
2892 {
2893 case PGMMODE_REAL: return PGM_TYPE_REAL;
2894 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2895 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2896 case PGMMODE_PAE:
2897 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2898 case PGMMODE_AMD64:
2899 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2900 case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
2901 case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
2902 case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
2903 case PGMMODE_EPT: return PGM_TYPE_EPT;
2904 case PGMMODE_NONE: return PGM_TYPE_NONE;
2905 default:
2906 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2907 }
2908}
2909
2910
2911/**
2912 * Calculates the shadow paging mode.
2913 *
2914 * @returns The shadow paging mode.
2915 * @param pVM The cross context VM structure.
2916 * @param enmGuestMode The guest mode.
2917 * @param enmHostMode The host mode.
2918 * @param enmShadowMode The current shadow mode.
2919 */
2920static PGMMODE pgmCalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode)
2921{
2922 switch (enmGuestMode)
2923 {
2924 /*
2925 * When switching to real or protected mode we don't change
2926 * anything since it's likely that we'll switch back pretty soon.
2927 *
2928 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2929 * and is supposed to determine which shadow paging and switcher to
2930 * use during init.
2931 */
2932 case PGMMODE_REAL:
2933 case PGMMODE_PROTECTED:
2934 if ( enmShadowMode != PGMMODE_INVALID
2935 && VM_IS_RAW_MODE_ENABLED(pVM) /* always switch in hm and nem modes! */)
2936 break; /* (no change) */
2937
2938 switch (enmHostMode)
2939 {
2940 case SUPPAGINGMODE_32_BIT:
2941 case SUPPAGINGMODE_32_BIT_GLOBAL:
2942 enmShadowMode = PGMMODE_32_BIT;
2943 break;
2944
2945 case SUPPAGINGMODE_PAE:
2946 case SUPPAGINGMODE_PAE_NX:
2947 case SUPPAGINGMODE_PAE_GLOBAL:
2948 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2949 enmShadowMode = PGMMODE_PAE;
2950 break;
2951
2952 case SUPPAGINGMODE_AMD64:
2953 case SUPPAGINGMODE_AMD64_GLOBAL:
2954 case SUPPAGINGMODE_AMD64_NX:
2955 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2956 enmShadowMode = PGMMODE_PAE;
2957 break;
2958
2959 default:
2960 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
2961 }
2962 break;
2963
2964 case PGMMODE_32_BIT:
2965 switch (enmHostMode)
2966 {
2967 case SUPPAGINGMODE_32_BIT:
2968 case SUPPAGINGMODE_32_BIT_GLOBAL:
2969 enmShadowMode = PGMMODE_32_BIT;
2970 break;
2971
2972 case SUPPAGINGMODE_PAE:
2973 case SUPPAGINGMODE_PAE_NX:
2974 case SUPPAGINGMODE_PAE_GLOBAL:
2975 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2976 enmShadowMode = PGMMODE_PAE;
2977 break;
2978
2979 case SUPPAGINGMODE_AMD64:
2980 case SUPPAGINGMODE_AMD64_GLOBAL:
2981 case SUPPAGINGMODE_AMD64_NX:
2982 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2983 enmShadowMode = PGMMODE_PAE;
2984 break;
2985
2986 default:
2987 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
2988 }
2989 break;
2990
2991 case PGMMODE_PAE:
2992 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2993 switch (enmHostMode)
2994 {
2995 case SUPPAGINGMODE_32_BIT:
2996 case SUPPAGINGMODE_32_BIT_GLOBAL:
2997 enmShadowMode = PGMMODE_PAE;
2998 break;
2999
3000 case SUPPAGINGMODE_PAE:
3001 case SUPPAGINGMODE_PAE_NX:
3002 case SUPPAGINGMODE_PAE_GLOBAL:
3003 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3004 enmShadowMode = PGMMODE_PAE;
3005 break;
3006
3007 case SUPPAGINGMODE_AMD64:
3008 case SUPPAGINGMODE_AMD64_GLOBAL:
3009 case SUPPAGINGMODE_AMD64_NX:
3010 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3011 enmShadowMode = PGMMODE_PAE;
3012 break;
3013
3014 default:
3015 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3016 }
3017 break;
3018
3019 case PGMMODE_AMD64:
3020 case PGMMODE_AMD64_NX:
3021 switch (enmHostMode)
3022 {
3023 case SUPPAGINGMODE_32_BIT:
3024 case SUPPAGINGMODE_32_BIT_GLOBAL:
3025 enmShadowMode = PGMMODE_AMD64;
3026 break;
3027
3028 case SUPPAGINGMODE_PAE:
3029 case SUPPAGINGMODE_PAE_NX:
3030 case SUPPAGINGMODE_PAE_GLOBAL:
3031 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3032 enmShadowMode = PGMMODE_AMD64;
3033 break;
3034
3035 case SUPPAGINGMODE_AMD64:
3036 case SUPPAGINGMODE_AMD64_GLOBAL:
3037 case SUPPAGINGMODE_AMD64_NX:
3038 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3039 enmShadowMode = PGMMODE_AMD64;
3040 break;
3041
3042 default:
3043 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3044 }
3045 break;
3046
3047 default:
3048 AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), PGMMODE_INVALID);
3049 }
3050
3051 /*
3052 * Override the shadow mode when NEM or nested paging is active.
3053 */
3054 if (VM_IS_NEM_ENABLED(pVM))
3055 {
3056 pVM->pgm.s.fNestedPaging = true;
3057 enmShadowMode = PGMMODE_NONE;
3058 }
3059 else
3060 {
3061 bool fNestedPaging = HMIsNestedPagingActive(pVM);
3062 pVM->pgm.s.fNestedPaging = fNestedPaging;
3063 if (fNestedPaging)
3064 {
3065 if (HMIsVmxActive(pVM))
3066 enmShadowMode = PGMMODE_EPT;
3067 else
3068 {
3069 /* The nested SVM paging depends on the host one. */
3070 Assert(HMIsSvmActive(pVM));
3071 if ( enmGuestMode == PGMMODE_AMD64
3072 || enmGuestMode == PGMMODE_AMD64_NX)
3073 enmShadowMode = PGMMODE_NESTED_AMD64;
3074 else
3075 switch (pVM->pgm.s.enmHostMode)
3076 {
3077 case SUPPAGINGMODE_32_BIT:
3078 case SUPPAGINGMODE_32_BIT_GLOBAL:
3079 enmShadowMode = PGMMODE_NESTED_32BIT;
3080 break;
3081
3082 case SUPPAGINGMODE_PAE:
3083 case SUPPAGINGMODE_PAE_GLOBAL:
3084 case SUPPAGINGMODE_PAE_NX:
3085 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3086 enmShadowMode = PGMMODE_NESTED_PAE;
3087 break;
3088
3089#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
3090 case SUPPAGINGMODE_AMD64:
3091 case SUPPAGINGMODE_AMD64_GLOBAL:
3092 case SUPPAGINGMODE_AMD64_NX:
3093 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3094 enmShadowMode = PGMMODE_NESTED_AMD64;
3095 break;
3096#endif
3097 default:
3098 AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3099 }
3100 }
3101 }
3102 }
3103
3104 return enmShadowMode;
3105}
3106
3107
3108/**
3109 * Performs the actual mode change.
3110 * This is called by PGMChangeMode and pgmR3InitPaging().
3111 *
3112 * @returns VBox status code. May suspend or power off the VM on error, but this
3113 * will trigger using FFs and not informational status codes.
3114 *
3115 * @param pVM The cross context VM structure.
3116 * @param pVCpu The cross context virtual CPU structure.
3117 * @param enmGuestMode The new guest mode. This is assumed to be different from
3118 * the current mode.
3119 */
3120VMM_INT_DECL(int) PGMHCChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3121{
3122 Log(("PGMHCChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3123 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3124
3125 /*
3126 * Calc the shadow mode and switcher.
3127 */
3128 PGMMODE enmShadowMode = pgmCalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode);
3129
3130 /*
3131 * Exit old mode(s).
3132 */
3133 /* shadow */
3134 if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3135 {
3136 LogFlow(("PGMHCChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3137 uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3138 if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3139 && g_aPgmShadowModeData[idxOldShw].pfnExit)
3140 {
3141 int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3142 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3143 }
3144 }
3145 else
3146 LogFlow(("PGMHCChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3147
3148 /* guest */
3149 uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3150 if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3151 && g_aPgmGuestModeData[idxOldGst].pfnExit)
3152 {
3153 int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3154 AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3155 }
3156 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3157
3158 /*
3159 * Change the paging mode data indexes.
3160 */
3161 uintptr_t idxNewGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGuestMode);
3162 AssertReturn(idxNewGst < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
3163 AssertReturn(g_aPgmGuestModeData[idxNewGst].uType == idxNewGst, VERR_PGM_MODE_IPE);
3164 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPage, VERR_PGM_MODE_IPE);
3165 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnModifyPage, VERR_PGM_MODE_IPE);
3166 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPDE, VERR_PGM_MODE_IPE);
3167 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnExit, VERR_PGM_MODE_IPE);
3168 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnEnter, VERR_PGM_MODE_IPE);
3169#ifdef IN_RING3
3170 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnRelocate, VERR_PGM_MODE_IPE);
3171#endif
3172
3173 uintptr_t const idxNewShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShadowMode);
3174 AssertReturn(idxNewShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
3175 AssertReturn(g_aPgmShadowModeData[idxNewShw].uType == idxNewShw, VERR_PGM_MODE_IPE);
3176 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnGetPage, VERR_PGM_MODE_IPE);
3177 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnModifyPage, VERR_PGM_MODE_IPE);
3178 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnExit, VERR_PGM_MODE_IPE);
3179 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnEnter, VERR_PGM_MODE_IPE);
3180#ifdef IN_RING3
3181 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnRelocate, VERR_PGM_MODE_IPE);
3182#endif
3183
3184 uintptr_t const idxNewBth = pVCpu->pgm.s.idxBothModeData = (idxNewShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxNewGst;
3185 AssertReturn(g_aPgmBothModeData[idxNewBth].uShwType == idxNewShw, VERR_PGM_MODE_IPE);
3186 AssertReturn(g_aPgmBothModeData[idxNewBth].uGstType == idxNewGst, VERR_PGM_MODE_IPE);
3187 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnInvalidatePage, VERR_PGM_MODE_IPE);
3188 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
3189 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
3190 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
3191 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnMapCR3, VERR_PGM_MODE_IPE);
3192 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
3193 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnEnter, VERR_PGM_MODE_IPE);
3194#ifdef VBOX_STRICT
3195 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnAssertCR3, VERR_PGM_MODE_IPE);
3196#endif
3197
3198 /*
3199 * Enter new shadow mode (if changed).
3200 */
3201 if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3202 {
3203 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3204 int rc = g_aPgmShadowModeData[idxNewShw].pfnEnter(pVCpu, enmGuestMode >= PGMMODE_AMD64);
3205 AssertLogRelMsgRCReturnStmt(rc, ("Entering enmShadowMode=%s failed: %Rrc\n", PGMGetModeName(enmShadowMode), rc),
3206 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID, rc);
3207 }
3208
3209 /*
3210 * Always flag the necessary updates
3211 */
3212 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3213
3214 /*
3215 * Enter the new guest and shadow+guest modes.
3216 */
3217 /* Calc the new CR3 value. */
3218 RTGCPHYS GCPhysCR3;
3219 switch (enmGuestMode)
3220 {
3221 case PGMMODE_REAL:
3222 case PGMMODE_PROTECTED:
3223 GCPhysCR3 = NIL_RTGCPHYS;
3224 break;
3225
3226 case PGMMODE_32_BIT:
3227 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3228 break;
3229
3230 case PGMMODE_PAE_NX:
3231 case PGMMODE_PAE:
3232 if (!pVM->cpum.ro.GuestFeatures.fPae)
3233 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3234 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3235 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3236 break;
3237
3238#ifdef VBOX_WITH_64_BITS_GUESTS
3239 case PGMMODE_AMD64_NX:
3240 case PGMMODE_AMD64:
3241 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3242 break;
3243#endif
3244 default:
3245 AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), VERR_PGM_MODE_IPE);
3246 }
3247
3248 /* Enter the new guest mode. */
3249 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3250 int rc = g_aPgmGuestModeData[idxNewGst].pfnEnter(pVCpu, GCPhysCR3);
3251 int rc2 = g_aPgmBothModeData[idxNewBth].pfnEnter(pVCpu, GCPhysCR3);
3252
3253 /* Set the new guest CR3. */
3254 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3255
3256 /* status codes. */
3257 AssertRC(rc);
3258 AssertRC(rc2);
3259 if (RT_SUCCESS(rc))
3260 {
3261 rc = rc2;
3262 if (RT_SUCCESS(rc)) /* no informational status codes. */
3263 rc = VINF_SUCCESS;
3264 }
3265
3266 /*
3267 * Notify HM.
3268 */
3269 HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3270 return rc;
3271}
3272
3273#endif /* !IN_RC */
3274
3275/**
3276 * Called by CPUM or REM when CR0.WP changes to 1.
3277 *
3278 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3279 * @thread EMT
3280 */
3281VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
3282{
3283 /*
3284 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
3285 *
3286 * Use the counter to judge whether there might be pool pages with active
3287 * hacks in them. If there are, we will be running the risk of messing up
3288 * the guest by allowing it to write to read-only pages. Thus, we have to
3289 * clear the page pool ASAP if there is the slightest chance.
3290 */
3291 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
3292 {
3293 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
3294
3295 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
3296 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
3297 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3298 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3299 }
3300}
3301
3302
3303/**
3304 * Gets the current guest paging mode.
3305 *
3306 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
3307 *
3308 * @returns The current paging mode.
3309 * @param pVCpu The cross context virtual CPU structure.
3310 */
3311VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
3312{
3313 return pVCpu->pgm.s.enmGuestMode;
3314}
3315
3316
3317/**
3318 * Gets the current shadow paging mode.
3319 *
3320 * @returns The current paging mode.
3321 * @param pVCpu The cross context virtual CPU structure.
3322 */
3323VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
3324{
3325 return pVCpu->pgm.s.enmShadowMode;
3326}
3327
3328
3329/**
3330 * Gets the current host paging mode.
3331 *
3332 * @returns The current paging mode.
3333 * @param pVM The cross context VM structure.
3334 */
3335VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
3336{
3337 switch (pVM->pgm.s.enmHostMode)
3338 {
3339 case SUPPAGINGMODE_32_BIT:
3340 case SUPPAGINGMODE_32_BIT_GLOBAL:
3341 return PGMMODE_32_BIT;
3342
3343 case SUPPAGINGMODE_PAE:
3344 case SUPPAGINGMODE_PAE_GLOBAL:
3345 return PGMMODE_PAE;
3346
3347 case SUPPAGINGMODE_PAE_NX:
3348 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3349 return PGMMODE_PAE_NX;
3350
3351 case SUPPAGINGMODE_AMD64:
3352 case SUPPAGINGMODE_AMD64_GLOBAL:
3353 return PGMMODE_AMD64;
3354
3355 case SUPPAGINGMODE_AMD64_NX:
3356 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3357 return PGMMODE_AMD64_NX;
3358
3359 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3360 }
3361
3362 return PGMMODE_INVALID;
3363}
3364
3365
3366/**
3367 * Get mode name.
3368 *
3369 * @returns read-only name string.
3370 * @param enmMode The mode which name is desired.
3371 */
3372VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3373{
3374 switch (enmMode)
3375 {
3376 case PGMMODE_REAL: return "Real";
3377 case PGMMODE_PROTECTED: return "Protected";
3378 case PGMMODE_32_BIT: return "32-bit";
3379 case PGMMODE_PAE: return "PAE";
3380 case PGMMODE_PAE_NX: return "PAE+NX";
3381 case PGMMODE_AMD64: return "AMD64";
3382 case PGMMODE_AMD64_NX: return "AMD64+NX";
3383 case PGMMODE_NESTED_32BIT: return "Nested-32";
3384 case PGMMODE_NESTED_PAE: return "Nested-PAE";
3385 case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3386 case PGMMODE_EPT: return "EPT";
3387 case PGMMODE_NONE: return "None";
3388 default: return "unknown mode value";
3389 }
3390}
3391
3392
3393/**
3394 * Gets the physical address represented in the guest CR3 as PGM sees it.
3395 *
3396 * This is mainly for logging and debugging.
3397 *
3398 * @returns PGM's guest CR3 value.
3399 * @param pVCpu The cross context virtual CPU structure.
3400 */
3401VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3402{
3403 return pVCpu->pgm.s.GCPhysCR3;
3404}
3405
3406
3407
3408/**
3409 * Notification from CPUM that the EFER.NXE bit has changed.
3410 *
3411 * @param pVCpu The cross context virtual CPU structure of the CPU for
3412 * which EFER changed.
3413 * @param fNxe The new NXE state.
3414 */
3415VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3416{
3417/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3418 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3419
3420 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3421 if (fNxe)
3422 {
3423 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3424 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3425 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3426 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3427 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
3428 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3429 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3430 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3431 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3432 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3433 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3434
3435 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
3436 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
3437 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
3438 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
3439 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
3440 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
3441 }
3442 else
3443 {
3444 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3445 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
3446 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
3447 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
3448 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
3449 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
3450 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
3451 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
3452 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
3453 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
3454 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
3455
3456 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3457 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3458 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3459 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3460 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3461 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3462 }
3463}
3464
3465
3466/**
3467 * Check if any pgm pool pages are marked dirty (not monitored)
3468 *
3469 * @returns bool locked/not locked
3470 * @param pVM The cross context VM structure.
3471 */
3472VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3473{
3474 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3475}
3476
3477
3478/**
3479 * Check if this VCPU currently owns the PGM lock.
3480 *
3481 * @returns bool owner/not owner
3482 * @param pVM The cross context VM structure.
3483 */
3484VMMDECL(bool) PGMIsLockOwner(PVM pVM)
3485{
3486 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
3487}
3488
3489
3490/**
3491 * Enable or disable large page usage
3492 *
3493 * @returns VBox status code.
3494 * @param pVM The cross context VM structure.
3495 * @param fUseLargePages Use/not use large pages
3496 */
3497VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
3498{
3499 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3500
3501 pVM->fUseLargePages = fUseLargePages;
3502 return VINF_SUCCESS;
3503}
3504
3505
3506/**
3507 * Acquire the PGM lock.
3508 *
3509 * @returns VBox status code
3510 * @param pVM The cross context VM structure.
3511 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3512 */
3513#if (defined(VBOX_STRICT) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
3514int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL)
3515#else
3516int pgmLock(PVM pVM)
3517#endif
3518{
3519#if defined(VBOX_STRICT) && defined(IN_RING3)
3520 int rc = PDMCritSectEnterDebug(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3521#else
3522 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
3523#endif
3524#if defined(IN_RC) || defined(IN_RING0)
3525 if (rc == VERR_SEM_BUSY)
3526 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
3527#endif
3528 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3529 return rc;
3530}
3531
3532
3533/**
3534 * Release the PGM lock.
3535 *
3536 * @returns VBox status code
3537 * @param pVM The cross context VM structure.
3538 */
3539void pgmUnlock(PVM pVM)
3540{
3541 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3542 pVM->pgm.s.cDeprecatedPageLocks = 0;
3543 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
3544 if (rc == VINF_SEM_NESTED)
3545 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3546}
3547
3548#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3549
3550/**
3551 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
3552 *
3553 * @returns VBox status code.
3554 * @param pVM The cross context VM structure.
3555 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3556 * @param GCPhys The guest physical address of the page to map. The
3557 * offset bits are not ignored.
3558 * @param ppv Where to return the address corresponding to @a GCPhys.
3559 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3560 */
3561int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
3562{
3563 pgmLock(pVM);
3564
3565 /*
3566 * Convert it to a writable page and it on to the dynamic mapper.
3567 */
3568 int rc;
3569 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
3570 if (RT_LIKELY(pPage))
3571 {
3572 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3573 if (RT_SUCCESS(rc))
3574 {
3575 void *pv;
3576 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
3577 if (RT_SUCCESS(rc))
3578 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
3579 }
3580 else
3581 AssertRC(rc);
3582 }
3583 else
3584 {
3585 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
3586 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3587 }
3588
3589 pgmUnlock(pVM);
3590 return rc;
3591}
3592
3593#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3594#if !defined(IN_R0) || defined(LOG_ENABLED)
3595
3596/** Format handler for PGMPAGE.
3597 * @copydoc FNRTSTRFORMATTYPE */
3598static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3599 const char *pszType, void const *pvValue,
3600 int cchWidth, int cchPrecision, unsigned fFlags,
3601 void *pvUser)
3602{
3603 size_t cch;
3604 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3605 if (RT_VALID_PTR(pPage))
3606 {
3607 char szTmp[64+80];
3608
3609 cch = 0;
3610
3611 /* The single char state stuff. */
3612 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3613 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3614
3615#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
3616 if (IS_PART_INCLUDED(5))
3617 {
3618 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
3619 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
3620 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
3621 }
3622
3623 /* The type. */
3624 if (IS_PART_INCLUDED(4))
3625 {
3626 szTmp[cch++] = ':';
3627 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3628 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3629 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3630 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3631 }
3632
3633 /* The numbers. */
3634 if (IS_PART_INCLUDED(3))
3635 {
3636 szTmp[cch++] = ':';
3637 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
3638 }
3639
3640 if (IS_PART_INCLUDED(2))
3641 {
3642 szTmp[cch++] = ':';
3643 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
3644 }
3645
3646 if (IS_PART_INCLUDED(6))
3647 {
3648 szTmp[cch++] = ':';
3649 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3650 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3651 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
3652 }
3653#undef IS_PART_INCLUDED
3654
3655 cch = pfnOutput(pvArgOutput, szTmp, cch);
3656 }
3657 else
3658 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3659 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3660 return cch;
3661}
3662
3663
3664/** Format handler for PGMRAMRANGE.
3665 * @copydoc FNRTSTRFORMATTYPE */
3666static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3667 const char *pszType, void const *pvValue,
3668 int cchWidth, int cchPrecision, unsigned fFlags,
3669 void *pvUser)
3670{
3671 size_t cch;
3672 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
3673 if (VALID_PTR(pRam))
3674 {
3675 char szTmp[80];
3676 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3677 cch = pfnOutput(pvArgOutput, szTmp, cch);
3678 }
3679 else
3680 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3681 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3682 return cch;
3683}
3684
3685/** Format type andlers to be registered/deregistered. */
3686static const struct
3687{
3688 char szType[24];
3689 PFNRTSTRFORMATTYPE pfnHandler;
3690} g_aPgmFormatTypes[] =
3691{
3692 { "pgmpage", pgmFormatTypeHandlerPage },
3693 { "pgmramrange", pgmFormatTypeHandlerRamRange }
3694};
3695
3696#endif /* !IN_R0 || LOG_ENABLED */
3697
3698/**
3699 * Registers the global string format types.
3700 *
3701 * This should be called at module load time or in some other manner that ensure
3702 * that it's called exactly one time.
3703 *
3704 * @returns IPRT status code on RTStrFormatTypeRegister failure.
3705 */
3706VMMDECL(int) PGMRegisterStringFormatTypes(void)
3707{
3708#if !defined(IN_R0) || defined(LOG_ENABLED)
3709 int rc = VINF_SUCCESS;
3710 unsigned i;
3711 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3712 {
3713 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3714# ifdef IN_RING0
3715 if (rc == VERR_ALREADY_EXISTS)
3716 {
3717 /* in case of cleanup failure in ring-0 */
3718 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3719 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3720 }
3721# endif
3722 }
3723 if (RT_FAILURE(rc))
3724 while (i-- > 0)
3725 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3726
3727 return rc;
3728#else
3729 return VINF_SUCCESS;
3730#endif
3731}
3732
3733
3734/**
3735 * Deregisters the global string format types.
3736 *
3737 * This should be called at module unload time or in some other manner that
3738 * ensure that it's called exactly one time.
3739 */
3740VMMDECL(void) PGMDeregisterStringFormatTypes(void)
3741{
3742#if !defined(IN_R0) || defined(LOG_ENABLED)
3743 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3744 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3745#endif
3746}
3747
3748#ifdef VBOX_STRICT
3749
3750# ifndef PGM_WITHOUT_MAPPINGS
3751/**
3752 * Asserts that there are no mapping conflicts.
3753 *
3754 * @returns Number of conflicts.
3755 * @param pVM The cross context VM structure.
3756 */
3757VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
3758{
3759 unsigned cErrors = 0;
3760
3761 /* Only applies to raw mode -> 1 VPCU */
3762 Assert(pVM->cCpus == 1);
3763 PVMCPU pVCpu = &pVM->aCpus[0];
3764
3765 /*
3766 * Check for mapping conflicts.
3767 */
3768 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3769 pMapping;
3770 pMapping = pMapping->CTX_SUFF(pNext))
3771 {
3772 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
3773 for (RTGCPTR GCPtr = pMapping->GCPtr; GCPtr <= pMapping->GCPtrLast; GCPtr += PAGE_SIZE)
3774 {
3775 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
3776 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
3777 {
3778 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
3779 cErrors++;
3780 break;
3781 }
3782 }
3783 }
3784
3785 return cErrors;
3786}
3787# endif
3788
3789
3790/**
3791 * Asserts that everything related to the guest CR3 is correctly shadowed.
3792 *
3793 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
3794 * and assert the correctness of the guest CR3 mapping before asserting that the
3795 * shadow page tables is in sync with the guest page tables.
3796 *
3797 * @returns Number of conflicts.
3798 * @param pVM The cross context VM structure.
3799 * @param pVCpu The cross context virtual CPU structure.
3800 * @param cr3 The current guest CR3 register value.
3801 * @param cr4 The current guest CR4 register value.
3802 */
3803VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
3804{
3805 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3806
3807 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
3808 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
3809 AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
3810
3811 pgmLock(pVM);
3812 unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
3813 pgmUnlock(pVM);
3814
3815 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3816 return cErrors;
3817}
3818
3819#endif /* VBOX_STRICT */
3820
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