VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 73299

Last change on this file since 73299 was 73280, checked in by vboxsync, 6 years ago

HM,PGM: Clarify VINF_PGM_CHANGE_MODE return and update assertions. bugref:9044.
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File size: 136.6 KB
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1/* $Id: PGMAll.cpp 73280 2018-07-20 19:50:17Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/selm.h>
26#include <VBox/vmm/iem.h>
27#include <VBox/vmm/iom.h>
28#include <VBox/sup.h>
29#include <VBox/vmm/mm.h>
30#include <VBox/vmm/stam.h>
31#include <VBox/vmm/csam.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/trpm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/em.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vmm/vm.h>
42#include "PGMInline.h"
43#include <iprt/assert.h>
44#include <iprt/asm-amd64-x86.h>
45#include <iprt/string.h>
46#include <VBox/log.h>
47#include <VBox/param.h>
48#include <VBox/err.h>
49
50
51/*********************************************************************************************************************************
52* Structures and Typedefs *
53*********************************************************************************************************************************/
54/**
55 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
56 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
57 */
58typedef struct PGMHVUSTATE
59{
60 /** Pointer to the VM. */
61 PVM pVM;
62 /** Pointer to the VMCPU. */
63 PVMCPU pVCpu;
64 /** The todo flags. */
65 RTUINT fTodo;
66 /** The CR4 register value. */
67 uint32_t cr4;
68} PGMHVUSTATE, *PPGMHVUSTATE;
69
70
71/*********************************************************************************************************************************
72* Internal Functions *
73*********************************************************************************************************************************/
74DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
75DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
76#ifndef IN_RC
77static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
78static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
79#endif
80
81
82/*
83 * Shadow - 32-bit mode
84 */
85#define PGM_SHW_TYPE PGM_TYPE_32BIT
86#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
87#include "PGMAllShw.h"
88
89/* Guest - real mode */
90#define PGM_GST_TYPE PGM_TYPE_REAL
91#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
92#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
93#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
94#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
95#include "PGMGstDefs.h"
96#include "PGMAllGst.h"
97#include "PGMAllBth.h"
98#undef BTH_PGMPOOLKIND_PT_FOR_PT
99#undef BTH_PGMPOOLKIND_ROOT
100#undef PGM_BTH_NAME
101#undef PGM_GST_TYPE
102#undef PGM_GST_NAME
103
104/* Guest - protected mode */
105#define PGM_GST_TYPE PGM_TYPE_PROT
106#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
107#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
108#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
109#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
110#include "PGMGstDefs.h"
111#include "PGMAllGst.h"
112#include "PGMAllBth.h"
113#undef BTH_PGMPOOLKIND_PT_FOR_PT
114#undef BTH_PGMPOOLKIND_ROOT
115#undef PGM_BTH_NAME
116#undef PGM_GST_TYPE
117#undef PGM_GST_NAME
118
119/* Guest - 32-bit mode */
120#define PGM_GST_TYPE PGM_TYPE_32BIT
121#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
122#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
123#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
124#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
125#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
126#include "PGMGstDefs.h"
127#include "PGMAllGst.h"
128#include "PGMAllBth.h"
129#undef BTH_PGMPOOLKIND_PT_FOR_BIG
130#undef BTH_PGMPOOLKIND_PT_FOR_PT
131#undef BTH_PGMPOOLKIND_ROOT
132#undef PGM_BTH_NAME
133#undef PGM_GST_TYPE
134#undef PGM_GST_NAME
135
136#undef PGM_SHW_TYPE
137#undef PGM_SHW_NAME
138
139
140/*
141 * Shadow - PAE mode
142 */
143#define PGM_SHW_TYPE PGM_TYPE_PAE
144#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
145#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146#include "PGMAllShw.h"
147
148/* Guest - real mode */
149#define PGM_GST_TYPE PGM_TYPE_REAL
150#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
151#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
152#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
153#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
154#include "PGMGstDefs.h"
155#include "PGMAllBth.h"
156#undef BTH_PGMPOOLKIND_PT_FOR_PT
157#undef BTH_PGMPOOLKIND_ROOT
158#undef PGM_BTH_NAME
159#undef PGM_GST_TYPE
160#undef PGM_GST_NAME
161
162/* Guest - protected mode */
163#define PGM_GST_TYPE PGM_TYPE_PROT
164#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
165#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
166#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
167#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
168#include "PGMGstDefs.h"
169#include "PGMAllBth.h"
170#undef BTH_PGMPOOLKIND_PT_FOR_PT
171#undef BTH_PGMPOOLKIND_ROOT
172#undef PGM_BTH_NAME
173#undef PGM_GST_TYPE
174#undef PGM_GST_NAME
175
176/* Guest - 32-bit mode */
177#define PGM_GST_TYPE PGM_TYPE_32BIT
178#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
179#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
180#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
181#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
182#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
183#include "PGMGstDefs.h"
184#include "PGMAllBth.h"
185#undef BTH_PGMPOOLKIND_PT_FOR_BIG
186#undef BTH_PGMPOOLKIND_PT_FOR_PT
187#undef BTH_PGMPOOLKIND_ROOT
188#undef PGM_BTH_NAME
189#undef PGM_GST_TYPE
190#undef PGM_GST_NAME
191
192
193/* Guest - PAE mode */
194#define PGM_GST_TYPE PGM_TYPE_PAE
195#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
196#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
197#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
198#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
199#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
200#include "PGMGstDefs.h"
201#include "PGMAllGst.h"
202#include "PGMAllBth.h"
203#undef BTH_PGMPOOLKIND_PT_FOR_BIG
204#undef BTH_PGMPOOLKIND_PT_FOR_PT
205#undef BTH_PGMPOOLKIND_ROOT
206#undef PGM_BTH_NAME
207#undef PGM_GST_TYPE
208#undef PGM_GST_NAME
209
210#undef PGM_SHW_TYPE
211#undef PGM_SHW_NAME
212
213
214#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
215/*
216 * Shadow - AMD64 mode
217 */
218# define PGM_SHW_TYPE PGM_TYPE_AMD64
219# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
220# include "PGMAllShw.h"
221
222/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
223/** @todo retire this hack. */
224# define PGM_GST_TYPE PGM_TYPE_PROT
225# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
226# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
227# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
228# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
229# include "PGMGstDefs.h"
230# include "PGMAllBth.h"
231# undef BTH_PGMPOOLKIND_PT_FOR_PT
232# undef BTH_PGMPOOLKIND_ROOT
233# undef PGM_BTH_NAME
234# undef PGM_GST_TYPE
235# undef PGM_GST_NAME
236
237# ifdef VBOX_WITH_64_BITS_GUESTS
238/* Guest - AMD64 mode */
239# define PGM_GST_TYPE PGM_TYPE_AMD64
240# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
241# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
242# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
243# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
244# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
245# include "PGMGstDefs.h"
246# include "PGMAllGst.h"
247# include "PGMAllBth.h"
248# undef BTH_PGMPOOLKIND_PT_FOR_BIG
249# undef BTH_PGMPOOLKIND_PT_FOR_PT
250# undef BTH_PGMPOOLKIND_ROOT
251# undef PGM_BTH_NAME
252# undef PGM_GST_TYPE
253# undef PGM_GST_NAME
254# endif /* VBOX_WITH_64_BITS_GUESTS */
255
256# undef PGM_SHW_TYPE
257# undef PGM_SHW_NAME
258
259
260/*
261 * Shadow - 32-bit nested paging mode.
262 */
263# define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
264# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
265# include "PGMAllShw.h"
266
267/* Guest - real mode */
268# define PGM_GST_TYPE PGM_TYPE_REAL
269# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
270# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
271# include "PGMGstDefs.h"
272# include "PGMAllBth.h"
273# undef PGM_BTH_NAME
274# undef PGM_GST_TYPE
275# undef PGM_GST_NAME
276
277/* Guest - protected mode */
278# define PGM_GST_TYPE PGM_TYPE_PROT
279# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
280# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
281# include "PGMGstDefs.h"
282# include "PGMAllBth.h"
283# undef PGM_BTH_NAME
284# undef PGM_GST_TYPE
285# undef PGM_GST_NAME
286
287/* Guest - 32-bit mode */
288# define PGM_GST_TYPE PGM_TYPE_32BIT
289# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
291# include "PGMGstDefs.h"
292# include "PGMAllBth.h"
293# undef PGM_BTH_NAME
294# undef PGM_GST_TYPE
295# undef PGM_GST_NAME
296
297/* Guest - PAE mode */
298# define PGM_GST_TYPE PGM_TYPE_PAE
299# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
300# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
301# include "PGMGstDefs.h"
302# include "PGMAllBth.h"
303# undef PGM_BTH_NAME
304# undef PGM_GST_TYPE
305# undef PGM_GST_NAME
306
307# ifdef VBOX_WITH_64_BITS_GUESTS
308/* Guest - AMD64 mode */
309# define PGM_GST_TYPE PGM_TYPE_AMD64
310# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
311# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
312# include "PGMGstDefs.h"
313# include "PGMAllBth.h"
314# undef PGM_BTH_NAME
315# undef PGM_GST_TYPE
316# undef PGM_GST_NAME
317# endif /* VBOX_WITH_64_BITS_GUESTS */
318
319# undef PGM_SHW_TYPE
320# undef PGM_SHW_NAME
321
322
323/*
324 * Shadow - PAE nested paging mode.
325 */
326# define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
327# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
328# include "PGMAllShw.h"
329
330/* Guest - real mode */
331# define PGM_GST_TYPE PGM_TYPE_REAL
332# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
333# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
334# include "PGMGstDefs.h"
335# include "PGMAllBth.h"
336# undef PGM_BTH_NAME
337# undef PGM_GST_TYPE
338# undef PGM_GST_NAME
339
340/* Guest - protected mode */
341# define PGM_GST_TYPE PGM_TYPE_PROT
342# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
343# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef PGM_BTH_NAME
347# undef PGM_GST_TYPE
348# undef PGM_GST_NAME
349
350/* Guest - 32-bit mode */
351# define PGM_GST_TYPE PGM_TYPE_32BIT
352# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
353# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
354# include "PGMGstDefs.h"
355# include "PGMAllBth.h"
356# undef PGM_BTH_NAME
357# undef PGM_GST_TYPE
358# undef PGM_GST_NAME
359
360/* Guest - PAE mode */
361# define PGM_GST_TYPE PGM_TYPE_PAE
362# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
363# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
364# include "PGMGstDefs.h"
365# include "PGMAllBth.h"
366# undef PGM_BTH_NAME
367# undef PGM_GST_TYPE
368# undef PGM_GST_NAME
369
370# ifdef VBOX_WITH_64_BITS_GUESTS
371/* Guest - AMD64 mode */
372# define PGM_GST_TYPE PGM_TYPE_AMD64
373# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
374# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
375# include "PGMGstDefs.h"
376# include "PGMAllBth.h"
377# undef PGM_BTH_NAME
378# undef PGM_GST_TYPE
379# undef PGM_GST_NAME
380# endif /* VBOX_WITH_64_BITS_GUESTS */
381
382# undef PGM_SHW_TYPE
383# undef PGM_SHW_NAME
384
385
386/*
387 * Shadow - AMD64 nested paging mode.
388 */
389# define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
390# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
391# include "PGMAllShw.h"
392
393/* Guest - real mode */
394# define PGM_GST_TYPE PGM_TYPE_REAL
395# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
396# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
397# include "PGMGstDefs.h"
398# include "PGMAllBth.h"
399# undef PGM_BTH_NAME
400# undef PGM_GST_TYPE
401# undef PGM_GST_NAME
402
403/* Guest - protected mode */
404# define PGM_GST_TYPE PGM_TYPE_PROT
405# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
406# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
407# include "PGMGstDefs.h"
408# include "PGMAllBth.h"
409# undef PGM_BTH_NAME
410# undef PGM_GST_TYPE
411# undef PGM_GST_NAME
412
413/* Guest - 32-bit mode */
414# define PGM_GST_TYPE PGM_TYPE_32BIT
415# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
416# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
417# include "PGMGstDefs.h"
418# include "PGMAllBth.h"
419# undef PGM_BTH_NAME
420# undef PGM_GST_TYPE
421# undef PGM_GST_NAME
422
423/* Guest - PAE mode */
424# define PGM_GST_TYPE PGM_TYPE_PAE
425# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
426# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
427# include "PGMGstDefs.h"
428# include "PGMAllBth.h"
429# undef PGM_BTH_NAME
430# undef PGM_GST_TYPE
431# undef PGM_GST_NAME
432
433# ifdef VBOX_WITH_64_BITS_GUESTS
434/* Guest - AMD64 mode */
435# define PGM_GST_TYPE PGM_TYPE_AMD64
436# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
437# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
438# include "PGMGstDefs.h"
439# include "PGMAllBth.h"
440# undef PGM_BTH_NAME
441# undef PGM_GST_TYPE
442# undef PGM_GST_NAME
443# endif /* VBOX_WITH_64_BITS_GUESTS */
444
445# undef PGM_SHW_TYPE
446# undef PGM_SHW_NAME
447
448
449/*
450 * Shadow - EPT.
451 */
452# define PGM_SHW_TYPE PGM_TYPE_EPT
453# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
454# include "PGMAllShw.h"
455
456/* Guest - real mode */
457# define PGM_GST_TYPE PGM_TYPE_REAL
458# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
459# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
460# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
461# include "PGMGstDefs.h"
462# include "PGMAllBth.h"
463# undef BTH_PGMPOOLKIND_PT_FOR_PT
464# undef PGM_BTH_NAME
465# undef PGM_GST_TYPE
466# undef PGM_GST_NAME
467
468/* Guest - protected mode */
469# define PGM_GST_TYPE PGM_TYPE_PROT
470# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
471# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
472# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
473# include "PGMGstDefs.h"
474# include "PGMAllBth.h"
475# undef BTH_PGMPOOLKIND_PT_FOR_PT
476# undef PGM_BTH_NAME
477# undef PGM_GST_TYPE
478# undef PGM_GST_NAME
479
480/* Guest - 32-bit mode */
481# define PGM_GST_TYPE PGM_TYPE_32BIT
482# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
483# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
484# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
485# include "PGMGstDefs.h"
486# include "PGMAllBth.h"
487# undef BTH_PGMPOOLKIND_PT_FOR_PT
488# undef PGM_BTH_NAME
489# undef PGM_GST_TYPE
490# undef PGM_GST_NAME
491
492/* Guest - PAE mode */
493# define PGM_GST_TYPE PGM_TYPE_PAE
494# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
495# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
496# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
497# include "PGMGstDefs.h"
498# include "PGMAllBth.h"
499# undef BTH_PGMPOOLKIND_PT_FOR_PT
500# undef PGM_BTH_NAME
501# undef PGM_GST_TYPE
502# undef PGM_GST_NAME
503
504# ifdef VBOX_WITH_64_BITS_GUESTS
505/* Guest - AMD64 mode */
506# define PGM_GST_TYPE PGM_TYPE_AMD64
507# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
508# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
509# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
510# include "PGMGstDefs.h"
511# include "PGMAllBth.h"
512# undef BTH_PGMPOOLKIND_PT_FOR_PT
513# undef PGM_BTH_NAME
514# undef PGM_GST_TYPE
515# undef PGM_GST_NAME
516# endif /* VBOX_WITH_64_BITS_GUESTS */
517
518# undef PGM_SHW_TYPE
519# undef PGM_SHW_NAME
520
521#endif /* !IN_RC */
522
523
524/**
525 * Guest mode data array.
526 */
527PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
528{
529 { UINT32_MAX, NULL, NULL, NULL, NULL, NULL }, /* 0 */
530 {
531 PGM_TYPE_REAL,
532 PGM_GST_NAME_REAL(GetPage),
533 PGM_GST_NAME_REAL(ModifyPage),
534 PGM_GST_NAME_REAL(GetPDE),
535 PGM_GST_NAME_REAL(Enter),
536 PGM_GST_NAME_REAL(Exit),
537#ifdef IN_RING3
538 PGM_GST_NAME_REAL(Relocate),
539#endif
540 },
541 {
542 PGM_TYPE_PROT,
543 PGM_GST_NAME_PROT(GetPage),
544 PGM_GST_NAME_PROT(ModifyPage),
545 PGM_GST_NAME_PROT(GetPDE),
546 PGM_GST_NAME_PROT(Enter),
547 PGM_GST_NAME_PROT(Exit),
548#ifdef IN_RING3
549 PGM_GST_NAME_PROT(Relocate),
550#endif
551 },
552 {
553 PGM_TYPE_32BIT,
554 PGM_GST_NAME_32BIT(GetPage),
555 PGM_GST_NAME_32BIT(ModifyPage),
556 PGM_GST_NAME_32BIT(GetPDE),
557 PGM_GST_NAME_32BIT(Enter),
558 PGM_GST_NAME_32BIT(Exit),
559#ifdef IN_RING3
560 PGM_GST_NAME_32BIT(Relocate),
561#endif
562 },
563 {
564 PGM_TYPE_PAE,
565 PGM_GST_NAME_PAE(GetPage),
566 PGM_GST_NAME_PAE(ModifyPage),
567 PGM_GST_NAME_PAE(GetPDE),
568 PGM_GST_NAME_PAE(Enter),
569 PGM_GST_NAME_PAE(Exit),
570#ifdef IN_RING3
571 PGM_GST_NAME_PAE(Relocate),
572#endif
573 },
574#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
575 {
576 PGM_TYPE_AMD64,
577 PGM_GST_NAME_AMD64(GetPage),
578 PGM_GST_NAME_AMD64(ModifyPage),
579 PGM_GST_NAME_AMD64(GetPDE),
580 PGM_GST_NAME_AMD64(Enter),
581 PGM_GST_NAME_AMD64(Exit),
582# ifdef IN_RING3
583 PGM_GST_NAME_AMD64(Relocate),
584# endif
585 },
586#endif
587};
588
589
590/**
591 * The shadow mode data array.
592 */
593PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
594{
595 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* 0 */
596 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
597 { UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
598 {
599 PGM_TYPE_32BIT,
600 PGM_SHW_NAME_32BIT(GetPage),
601 PGM_SHW_NAME_32BIT(ModifyPage),
602 PGM_SHW_NAME_32BIT(Enter),
603 PGM_SHW_NAME_32BIT(Exit),
604#ifdef IN_RING3
605 PGM_SHW_NAME_32BIT(Relocate),
606#endif
607 },
608 {
609 PGM_TYPE_PAE,
610 PGM_SHW_NAME_PAE(GetPage),
611 PGM_SHW_NAME_PAE(ModifyPage),
612 PGM_SHW_NAME_PAE(Enter),
613 PGM_SHW_NAME_PAE(Exit),
614#ifdef IN_RING3
615 PGM_SHW_NAME_PAE(Relocate),
616#endif
617 },
618#ifndef IN_RC
619 {
620 PGM_TYPE_AMD64,
621 PGM_SHW_NAME_AMD64(GetPage),
622 PGM_SHW_NAME_AMD64(ModifyPage),
623 PGM_SHW_NAME_AMD64(Enter),
624 PGM_SHW_NAME_AMD64(Exit),
625# ifdef IN_RING3
626 PGM_SHW_NAME_AMD64(Relocate),
627# endif
628 },
629 {
630 PGM_TYPE_NESTED_32BIT,
631 PGM_SHW_NAME_NESTED_32BIT(GetPage),
632 PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
633 PGM_SHW_NAME_NESTED_32BIT(Enter),
634 PGM_SHW_NAME_NESTED_32BIT(Exit),
635# ifdef IN_RING3
636 PGM_SHW_NAME_NESTED_32BIT(Relocate),
637# endif
638 },
639 {
640 PGM_TYPE_NESTED_PAE,
641 PGM_SHW_NAME_NESTED_PAE(GetPage),
642 PGM_SHW_NAME_NESTED_PAE(ModifyPage),
643 PGM_SHW_NAME_NESTED_PAE(Enter),
644 PGM_SHW_NAME_NESTED_PAE(Exit),
645# ifdef IN_RING3
646 PGM_SHW_NAME_NESTED_PAE(Relocate),
647# endif
648 },
649 {
650 PGM_TYPE_NESTED_AMD64,
651 PGM_SHW_NAME_NESTED_AMD64(GetPage),
652 PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
653 PGM_SHW_NAME_NESTED_AMD64(Enter),
654 PGM_SHW_NAME_NESTED_AMD64(Exit),
655# ifdef IN_RING3
656 PGM_SHW_NAME_NESTED_AMD64(Relocate),
657# endif
658 },
659 {
660 PGM_TYPE_EPT,
661 PGM_SHW_NAME_EPT(GetPage),
662 PGM_SHW_NAME_EPT(ModifyPage),
663 PGM_SHW_NAME_EPT(Enter),
664 PGM_SHW_NAME_EPT(Exit),
665# ifdef IN_RING3
666 PGM_SHW_NAME_EPT(Relocate),
667# endif
668 },
669#endif /* IN_RC */
670};
671
672
673/**
674 * The guest+shadow mode data array.
675 */
676PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
677{
678#if !defined(IN_RING3) && !defined(VBOX_STRICT)
679# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
680# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
681 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler) }
682
683#elif !defined(IN_RING3) && defined(VBOX_STRICT)
684# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
685# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
686 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(AssertCR3) }
687
688#elif defined(IN_RING3) && !defined(VBOX_STRICT)
689# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
690# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
691 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), }
692
693#elif defined(IN_RING3) && defined(VBOX_STRICT)
694# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
695# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
696 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(AssertCR3) }
697
698#else
699# error "Misconfig."
700#endif
701
702 /* 32-bit shadow paging mode: */
703 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
704 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
705 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
706 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
707 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
708 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
709 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
710 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
711 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
712 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
713
714 /* PAE shadow paging mode: */
715 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
716 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
717 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
718 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
719 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
720 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
721 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
722 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
723 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
724 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
725
726#ifndef IN_RC
727 /* AMD64 shadow paging mode: */
728 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
729 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
730 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
731 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
732 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
733# ifdef VBOX_WITH_64_BITS_GUESTS
734 PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
735# else
736 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
737# endif
738 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
739 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
740 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
741 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
742
743 /* 32-bit nested paging mode: */
744 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
745 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
746 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
747 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
748 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
749# ifdef VBOX_WITH_64_BITS_GUESTS
750 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
751# else
752 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
753# endif
754 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
755 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
756 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
757 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
758
759 /* PAE nested paging mode: */
760 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
761 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
762 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
763 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
764 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
765# ifdef VBOX_WITH_64_BITS_GUESTS
766 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
767# else
768 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
769# endif
770 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
771 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
772 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
773 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
774
775 /* AMD64 nested paging mode: */
776 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
777 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
778 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
779 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
780 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
781# ifdef VBOX_WITH_64_BITS_GUESTS
782 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
783# else
784 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
785# endif
786 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
787 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
788 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
789 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
790
791 /* EPT nested paging mode: */
792 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
793 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
794 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
795 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
796 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
797# ifdef VBOX_WITH_64_BITS_GUESTS
798 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
799# else
800 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
801# endif
802 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
803 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
804 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
805 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
806
807#endif /* IN_RC */
808
809#undef PGMMODEDATABTH_ENTRY
810#undef PGMMODEDATABTH_NULL_ENTRY
811};
812
813
814#ifndef IN_RING3
815/**
816 * #PF Handler.
817 *
818 * @returns VBox status code (appropriate for trap handling and GC return).
819 * @param pVCpu The cross context virtual CPU structure.
820 * @param uErr The trap error code.
821 * @param pRegFrame Trap register frame.
822 * @param pvFault The fault address.
823 */
824VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
825{
826 PVM pVM = pVCpu->CTX_SUFF(pVM);
827
828 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
829 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
830 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
831
832
833#ifdef VBOX_WITH_STATISTICS
834 /*
835 * Error code stats.
836 */
837 if (uErr & X86_TRAP_PF_US)
838 {
839 if (!(uErr & X86_TRAP_PF_P))
840 {
841 if (uErr & X86_TRAP_PF_RW)
842 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
843 else
844 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
845 }
846 else if (uErr & X86_TRAP_PF_RW)
847 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
848 else if (uErr & X86_TRAP_PF_RSVD)
849 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
850 else if (uErr & X86_TRAP_PF_ID)
851 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
852 else
853 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
854 }
855 else
856 { /* Supervisor */
857 if (!(uErr & X86_TRAP_PF_P))
858 {
859 if (uErr & X86_TRAP_PF_RW)
860 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
861 else
862 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
863 }
864 else if (uErr & X86_TRAP_PF_RW)
865 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
866 else if (uErr & X86_TRAP_PF_ID)
867 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
868 else if (uErr & X86_TRAP_PF_RSVD)
869 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
870 }
871#endif /* VBOX_WITH_STATISTICS */
872
873 /*
874 * Call the worker.
875 */
876 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
877 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
878 AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
879 bool fLockTaken = false;
880 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
881 if (fLockTaken)
882 {
883 PGM_LOCK_ASSERT_OWNER(pVM);
884 pgmUnlock(pVM);
885 }
886 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
887
888 /*
889 * Return code tweaks.
890 */
891 if (rc != VINF_SUCCESS)
892 {
893 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
894 rc = VINF_SUCCESS;
895
896# ifdef IN_RING0
897 /* Note: hack alert for difficult to reproduce problem. */
898 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
899 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
900 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
901 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
902 {
903 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
904 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
905 rc = VINF_SUCCESS;
906 }
907# endif
908 }
909
910 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
911 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
912 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
913 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
914 return rc;
915}
916#endif /* !IN_RING3 */
917
918
919/**
920 * Prefetch a page
921 *
922 * Typically used to sync commonly used pages before entering raw mode
923 * after a CR3 reload.
924 *
925 * @returns VBox status code suitable for scheduling.
926 * @retval VINF_SUCCESS on success.
927 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
928 * @param pVCpu The cross context virtual CPU structure.
929 * @param GCPtrPage Page to invalidate.
930 */
931VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
932{
933 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
934
935 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
936 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
937 AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
938 int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
939
940 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
941 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
942 return rc;
943}
944
945
946/**
947 * Gets the mapping corresponding to the specified address (if any).
948 *
949 * @returns Pointer to the mapping.
950 * @returns NULL if not
951 *
952 * @param pVM The cross context VM structure.
953 * @param GCPtr The guest context pointer.
954 */
955PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
956{
957 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
958 while (pMapping)
959 {
960 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
961 break;
962 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
963 return pMapping;
964 pMapping = pMapping->CTX_SUFF(pNext);
965 }
966 return NULL;
967}
968
969
970/**
971 * Verifies a range of pages for read or write access
972 *
973 * Only checks the guest's page tables
974 *
975 * @returns VBox status code.
976 * @param pVCpu The cross context virtual CPU structure.
977 * @param Addr Guest virtual address to check
978 * @param cbSize Access size
979 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
980 * @remarks Current not in use.
981 */
982VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
983{
984 /*
985 * Validate input.
986 */
987 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
988 {
989 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
990 return VERR_INVALID_PARAMETER;
991 }
992
993 uint64_t fPage;
994 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
995 if (RT_FAILURE(rc))
996 {
997 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
998 return VINF_EM_RAW_GUEST_TRAP;
999 }
1000
1001 /*
1002 * Check if the access would cause a page fault
1003 *
1004 * Note that hypervisor page directories are not present in the guest's tables, so this check
1005 * is sufficient.
1006 */
1007 bool fWrite = !!(fAccess & X86_PTE_RW);
1008 bool fUser = !!(fAccess & X86_PTE_US);
1009 if ( !(fPage & X86_PTE_P)
1010 || (fWrite && !(fPage & X86_PTE_RW))
1011 || (fUser && !(fPage & X86_PTE_US)) )
1012 {
1013 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
1014 return VINF_EM_RAW_GUEST_TRAP;
1015 }
1016 if ( RT_SUCCESS(rc)
1017 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
1018 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
1019 return rc;
1020}
1021
1022
1023/**
1024 * Verifies a range of pages for read or write access
1025 *
1026 * Supports handling of pages marked for dirty bit tracking and CSAM
1027 *
1028 * @returns VBox status code.
1029 * @param pVCpu The cross context virtual CPU structure.
1030 * @param Addr Guest virtual address to check
1031 * @param cbSize Access size
1032 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
1033 */
1034VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
1035{
1036 PVM pVM = pVCpu->CTX_SUFF(pVM);
1037
1038 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
1039
1040 /*
1041 * Get going.
1042 */
1043 uint64_t fPageGst;
1044 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
1045 if (RT_FAILURE(rc))
1046 {
1047 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
1048 return VINF_EM_RAW_GUEST_TRAP;
1049 }
1050
1051 /*
1052 * Check if the access would cause a page fault
1053 *
1054 * Note that hypervisor page directories are not present in the guest's tables, so this check
1055 * is sufficient.
1056 */
1057 const bool fWrite = !!(fAccess & X86_PTE_RW);
1058 const bool fUser = !!(fAccess & X86_PTE_US);
1059 if ( !(fPageGst & X86_PTE_P)
1060 || (fWrite && !(fPageGst & X86_PTE_RW))
1061 || (fUser && !(fPageGst & X86_PTE_US)) )
1062 {
1063 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
1064 return VINF_EM_RAW_GUEST_TRAP;
1065 }
1066
1067 if (!pVM->pgm.s.fNestedPaging)
1068 {
1069 /*
1070 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
1071 */
1072 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
1073 if ( rc == VERR_PAGE_NOT_PRESENT
1074 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
1075 {
1076 /*
1077 * Page is not present in our page tables.
1078 * Try to sync it!
1079 */
1080 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
1081 uint32_t const uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
1082 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1083 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1084 AssertReturn(g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
1085 rc = g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage(pVCpu, Addr, fPageGst, uErr);
1086 if (rc != VINF_SUCCESS)
1087 return rc;
1088 }
1089 else
1090 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
1091 }
1092
1093#if 0 /* def VBOX_STRICT; triggers too often now */
1094 /*
1095 * This check is a bit paranoid, but useful.
1096 */
1097 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
1098 uint64_t fPageShw;
1099 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
1100 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
1101 || (fWrite && !(fPageShw & X86_PTE_RW))
1102 || (fUser && !(fPageShw & X86_PTE_US)) )
1103 {
1104 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
1105 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
1106 return VINF_EM_RAW_GUEST_TRAP;
1107 }
1108#endif
1109
1110 if ( RT_SUCCESS(rc)
1111 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
1112 || Addr + cbSize < Addr))
1113 {
1114 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
1115 for (;;)
1116 {
1117 Addr += PAGE_SIZE;
1118 if (cbSize > PAGE_SIZE)
1119 cbSize -= PAGE_SIZE;
1120 else
1121 cbSize = 1;
1122 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
1123 if (rc != VINF_SUCCESS)
1124 break;
1125 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
1126 break;
1127 }
1128 }
1129 return rc;
1130}
1131
1132
1133/**
1134 * Emulation of the invlpg instruction (HC only actually).
1135 *
1136 * @returns Strict VBox status code, special care required.
1137 * @retval VINF_PGM_SYNC_CR3 - handled.
1138 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1139 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
1140 *
1141 * @param pVCpu The cross context virtual CPU structure.
1142 * @param GCPtrPage Page to invalidate.
1143 *
1144 * @remark ASSUMES the page table entry or page directory is valid. Fairly
1145 * safe, but there could be edge cases!
1146 *
1147 * @todo Flush page or page directory only if necessary!
1148 * @todo VBOXSTRICTRC
1149 */
1150VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1151{
1152 PVM pVM = pVCpu->CTX_SUFF(pVM);
1153 int rc;
1154 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1155
1156#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
1157 /*
1158 * Notify the recompiler so it can record this instruction.
1159 */
1160 REMNotifyInvalidatePage(pVM, GCPtrPage);
1161#endif /* !IN_RING3 */
1162 IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1163
1164
1165#ifdef IN_RC
1166 /*
1167 * Check for conflicts and pending CR3 monitoring updates.
1168 */
1169 if (pgmMapAreMappingsFloating(pVM))
1170 {
1171 if ( pgmGetMapping(pVM, GCPtrPage)
1172 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
1173 {
1174 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
1175 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1176 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
1177 return VINF_PGM_SYNC_CR3;
1178 }
1179
1180 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1181 {
1182 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
1183 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
1184 return VINF_EM_RAW_EMULATE_INSTR;
1185 }
1186 }
1187#endif /* IN_RC */
1188
1189 /*
1190 * Call paging mode specific worker.
1191 */
1192 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1193 pgmLock(pVM);
1194
1195 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1196 AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1197 AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1198 rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1199
1200 pgmUnlock(pVM);
1201 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1202
1203#ifdef IN_RING3
1204 /*
1205 * Check if we have a pending update of the CR3 monitoring.
1206 */
1207 if ( RT_SUCCESS(rc)
1208 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
1209 {
1210 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1211 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
1212 }
1213
1214# ifdef VBOX_WITH_RAW_MODE
1215 /*
1216 * Inform CSAM about the flush
1217 *
1218 * Note: This is to check if monitored pages have been changed; when we implement
1219 * callbacks for virtual handlers, this is no longer required.
1220 */
1221 CSAMR3FlushPage(pVM, GCPtrPage);
1222# endif
1223#endif /* IN_RING3 */
1224
1225 /* Ignore all irrelevant error codes. */
1226 if ( rc == VERR_PAGE_NOT_PRESENT
1227 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1228 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1229 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1230 rc = VINF_SUCCESS;
1231
1232 return rc;
1233}
1234
1235
1236/**
1237 * Executes an instruction using the interpreter.
1238 *
1239 * @returns VBox status code (appropriate for trap handling and GC return).
1240 * @param pVM The cross context VM structure.
1241 * @param pVCpu The cross context virtual CPU structure.
1242 * @param pRegFrame Register frame.
1243 * @param pvFault Fault address.
1244 */
1245VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1246{
1247 NOREF(pVM);
1248 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
1249 if (rc == VERR_EM_INTERPRETER)
1250 rc = VINF_EM_RAW_EMULATE_INSTR;
1251 if (rc != VINF_SUCCESS)
1252 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1253 return rc;
1254}
1255
1256
1257/**
1258 * Gets effective page information (from the VMM page directory).
1259 *
1260 * @returns VBox status code.
1261 * @param pVCpu The cross context virtual CPU structure.
1262 * @param GCPtr Guest Context virtual address of the page.
1263 * @param pfFlags Where to store the flags. These are X86_PTE_*.
1264 * @param pHCPhys Where to store the HC physical address of the page.
1265 * This is page aligned.
1266 * @remark You should use PGMMapGetPage() for pages in a mapping.
1267 */
1268VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1269{
1270 PVM pVM = pVCpu->CTX_SUFF(pVM);
1271 pgmLock(pVM);
1272
1273 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1274 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1275 AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1276 int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1277
1278 pgmUnlock(pVM);
1279 return rc;
1280}
1281
1282
1283/**
1284 * Modify page flags for a range of pages in the shadow context.
1285 *
1286 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1287 *
1288 * @returns VBox status code.
1289 * @param pVCpu The cross context virtual CPU structure.
1290 * @param GCPtr Virtual address of the first page in the range.
1291 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1292 * @param fMask The AND mask - page flags X86_PTE_*.
1293 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1294 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1295 * @remark You must use PGMMapModifyPage() for pages in a mapping.
1296 */
1297DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1298{
1299 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1300 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
1301
1302 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
1303
1304 PVM pVM = pVCpu->CTX_SUFF(pVM);
1305 pgmLock(pVM);
1306
1307 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1308 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1309 AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1310 int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
1311
1312 pgmUnlock(pVM);
1313 return rc;
1314}
1315
1316
1317/**
1318 * Changing the page flags for a single page in the shadow page tables so as to
1319 * make it read-only.
1320 *
1321 * @returns VBox status code.
1322 * @param pVCpu The cross context virtual CPU structure.
1323 * @param GCPtr Virtual address of the first page in the range.
1324 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1325 */
1326VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1327{
1328 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1329}
1330
1331
1332/**
1333 * Changing the page flags for a single page in the shadow page tables so as to
1334 * make it writable.
1335 *
1336 * The call must know with 101% certainty that the guest page tables maps this
1337 * as writable too. This function will deal shared, zero and write monitored
1338 * pages.
1339 *
1340 * @returns VBox status code.
1341 * @param pVCpu The cross context virtual CPU structure.
1342 * @param GCPtr Virtual address of the first page in the range.
1343 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1344 */
1345VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1346{
1347 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1348}
1349
1350
1351/**
1352 * Changing the page flags for a single page in the shadow page tables so as to
1353 * make it not present.
1354 *
1355 * @returns VBox status code.
1356 * @param pVCpu The cross context virtual CPU structure.
1357 * @param GCPtr Virtual address of the first page in the range.
1358 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1359 */
1360VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1361{
1362 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1363}
1364
1365
1366/**
1367 * Changing the page flags for a single page in the shadow page tables so as to
1368 * make it supervisor and writable.
1369 *
1370 * This if for dealing with CR0.WP=0 and readonly user pages.
1371 *
1372 * @returns VBox status code.
1373 * @param pVCpu The cross context virtual CPU structure.
1374 * @param GCPtr Virtual address of the first page in the range.
1375 * @param fBigPage Whether or not this is a big page. If it is, we have to
1376 * change the shadow PDE as well. If it isn't, the caller
1377 * has checked that the shadow PDE doesn't need changing.
1378 * We ASSUME 4KB pages backing the big page here!
1379 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1380 */
1381int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1382{
1383 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1384 if (rc == VINF_SUCCESS && fBigPage)
1385 {
1386 /* this is a bit ugly... */
1387 switch (pVCpu->pgm.s.enmShadowMode)
1388 {
1389 case PGMMODE_32_BIT:
1390 {
1391 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1392 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1393 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1394 pPde->n.u1Write = 1;
1395 Log(("-> PDE=%#llx (32)\n", pPde->u));
1396 break;
1397 }
1398 case PGMMODE_PAE:
1399 case PGMMODE_PAE_NX:
1400 {
1401 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1402 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1403 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1404 pPde->n.u1Write = 1;
1405 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1406 break;
1407 }
1408 default:
1409 AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1410 }
1411 }
1412 return rc;
1413}
1414
1415
1416/**
1417 * Gets the shadow page directory for the specified address, PAE.
1418 *
1419 * @returns Pointer to the shadow PD.
1420 * @param pVCpu The cross context virtual CPU structure.
1421 * @param GCPtr The address.
1422 * @param uGstPdpe Guest PDPT entry. Valid.
1423 * @param ppPD Receives address of page directory
1424 */
1425int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1426{
1427 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1428 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1429 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1430 PVM pVM = pVCpu->CTX_SUFF(pVM);
1431 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1432 PPGMPOOLPAGE pShwPage;
1433 int rc;
1434
1435 PGM_LOCK_ASSERT_OWNER(pVM);
1436
1437 /* Allocate page directory if not present. */
1438 if ( !pPdpe->n.u1Present
1439 && !(pPdpe->u & X86_PDPE_PG_MASK))
1440 {
1441 RTGCPTR64 GCPdPt;
1442 PGMPOOLKIND enmKind;
1443
1444 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
1445 {
1446 /* AMD-V nested paging or real/protected mode without paging. */
1447 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1448 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1449 }
1450 else
1451 {
1452 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1453 {
1454 if (!(uGstPdpe & X86_PDPE_P))
1455 {
1456 /* PD not present; guest must reload CR3 to change it.
1457 * No need to monitor anything in this case.
1458 */
1459 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1460
1461 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1462 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1463 uGstPdpe |= X86_PDPE_P;
1464 }
1465 else
1466 {
1467 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1468 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1469 }
1470 }
1471 else
1472 {
1473 GCPdPt = CPUMGetGuestCR3(pVCpu);
1474 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1475 }
1476 }
1477
1478 /* Create a reference back to the PDPT by using the index in its shadow page. */
1479 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1480 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1481 &pShwPage);
1482 AssertRCReturn(rc, rc);
1483
1484 /* The PD was cached or created; hook it up now. */
1485 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
1486
1487# if defined(IN_RC)
1488 /*
1489 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
1490 * PDPT entry; the CPU fetches them only during cr3 load, so any
1491 * non-present PDPT will continue to cause page faults.
1492 */
1493 ASMReloadCR3();
1494# endif
1495 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1496 }
1497 else
1498 {
1499 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1500 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1501 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1502
1503 pgmPoolCacheUsed(pPool, pShwPage);
1504 }
1505 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1506 return VINF_SUCCESS;
1507}
1508
1509
1510/**
1511 * Gets the pointer to the shadow page directory entry for an address, PAE.
1512 *
1513 * @returns Pointer to the PDE.
1514 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1515 * @param GCPtr The address.
1516 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1517 */
1518DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1519{
1520 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1521 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1522 PVM pVM = pVCpu->CTX_SUFF(pVM);
1523
1524 PGM_LOCK_ASSERT_OWNER(pVM);
1525
1526 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1527 if (!pPdpt->a[iPdPt].n.u1Present)
1528 {
1529 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1530 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1531 }
1532 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1533
1534 /* Fetch the pgm pool shadow descriptor. */
1535 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1536 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1537
1538 *ppShwPde = pShwPde;
1539 return VINF_SUCCESS;
1540}
1541
1542#ifndef IN_RC
1543
1544/**
1545 * Syncs the SHADOW page directory pointer for the specified address.
1546 *
1547 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1548 *
1549 * The caller is responsible for making sure the guest has a valid PD before
1550 * calling this function.
1551 *
1552 * @returns VBox status code.
1553 * @param pVCpu The cross context virtual CPU structure.
1554 * @param GCPtr The address.
1555 * @param uGstPml4e Guest PML4 entry (valid).
1556 * @param uGstPdpe Guest PDPT entry (valid).
1557 * @param ppPD Receives address of page directory
1558 */
1559static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1560{
1561 PVM pVM = pVCpu->CTX_SUFF(pVM);
1562 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1563 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1564 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1565 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1566 PPGMPOOLPAGE pShwPage;
1567 int rc;
1568
1569 PGM_LOCK_ASSERT_OWNER(pVM);
1570
1571 /* Allocate page directory pointer table if not present. */
1572 if ( !pPml4e->n.u1Present
1573 && !(pPml4e->u & X86_PML4E_PG_MASK))
1574 {
1575 RTGCPTR64 GCPml4;
1576 PGMPOOLKIND enmKind;
1577
1578 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1579
1580 if (fNestedPagingOrNoGstPaging)
1581 {
1582 /* AMD-V nested paging or real/protected mode without paging */
1583 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1584 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1585 }
1586 else
1587 {
1588 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1589 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1590 }
1591
1592 /* Create a reference back to the PDPT by using the index in its shadow page. */
1593 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1594 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1595 &pShwPage);
1596 AssertRCReturn(rc, rc);
1597 }
1598 else
1599 {
1600 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1601 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1602
1603 pgmPoolCacheUsed(pPool, pShwPage);
1604 }
1605 /* The PDPT was cached or created; hook it up now. */
1606 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1607
1608 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1609 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1610 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1611
1612 /* Allocate page directory if not present. */
1613 if ( !pPdpe->n.u1Present
1614 && !(pPdpe->u & X86_PDPE_PG_MASK))
1615 {
1616 RTGCPTR64 GCPdPt;
1617 PGMPOOLKIND enmKind;
1618
1619 if (fNestedPagingOrNoGstPaging)
1620 {
1621 /* AMD-V nested paging or real/protected mode without paging */
1622 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1623 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1624 }
1625 else
1626 {
1627 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1628 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1629 }
1630
1631 /* Create a reference back to the PDPT by using the index in its shadow page. */
1632 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1633 pShwPage->idx, iPdPt, false /*fLockPage*/,
1634 &pShwPage);
1635 AssertRCReturn(rc, rc);
1636 }
1637 else
1638 {
1639 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1640 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1641
1642 pgmPoolCacheUsed(pPool, pShwPage);
1643 }
1644 /* The PD was cached or created; hook it up now. */
1645 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1646
1647 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1648 return VINF_SUCCESS;
1649}
1650
1651
1652/**
1653 * Gets the SHADOW page directory pointer for the specified address (long mode).
1654 *
1655 * @returns VBox status code.
1656 * @param pVCpu The cross context virtual CPU structure.
1657 * @param GCPtr The address.
1658 * @param ppPdpt Receives address of pdpt
1659 * @param ppPD Receives address of page directory
1660 */
1661DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1662{
1663 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1664 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1665
1666 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1667
1668 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1669 if (ppPml4e)
1670 *ppPml4e = (PX86PML4E)pPml4e;
1671
1672 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1673
1674 if (!pPml4e->n.u1Present)
1675 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1676
1677 PVM pVM = pVCpu->CTX_SUFF(pVM);
1678 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1679 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1680 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1681
1682 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1683 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1684 if (!pPdpt->a[iPdPt].n.u1Present)
1685 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1686
1687 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1688 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1689
1690 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1691 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1692 return VINF_SUCCESS;
1693}
1694
1695
1696/**
1697 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1698 * backing pages in case the PDPT or PML4 entry is missing.
1699 *
1700 * @returns VBox status code.
1701 * @param pVCpu The cross context virtual CPU structure.
1702 * @param GCPtr The address.
1703 * @param ppPdpt Receives address of pdpt
1704 * @param ppPD Receives address of page directory
1705 */
1706static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1707{
1708 PVM pVM = pVCpu->CTX_SUFF(pVM);
1709 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1710 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1711 PEPTPML4 pPml4;
1712 PEPTPML4E pPml4e;
1713 PPGMPOOLPAGE pShwPage;
1714 int rc;
1715
1716 Assert(pVM->pgm.s.fNestedPaging);
1717 PGM_LOCK_ASSERT_OWNER(pVM);
1718
1719 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1720 Assert(pPml4);
1721
1722 /* Allocate page directory pointer table if not present. */
1723 pPml4e = &pPml4->a[iPml4];
1724 if ( !pPml4e->n.u1Present
1725 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1726 {
1727 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1728 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1729
1730 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1731 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1732 &pShwPage);
1733 AssertRCReturn(rc, rc);
1734 }
1735 else
1736 {
1737 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1738 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1739
1740 pgmPoolCacheUsed(pPool, pShwPage);
1741 }
1742 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1743 pPml4e->u = pShwPage->Core.Key;
1744 pPml4e->n.u1Present = 1;
1745 pPml4e->n.u1Write = 1;
1746 pPml4e->n.u1Execute = 1;
1747
1748 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1749 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1750 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1751
1752 if (ppPdpt)
1753 *ppPdpt = pPdpt;
1754
1755 /* Allocate page directory if not present. */
1756 if ( !pPdpe->n.u1Present
1757 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1758 {
1759 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1760 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1761 pShwPage->idx, iPdPt, false /*fLockPage*/,
1762 &pShwPage);
1763 AssertRCReturn(rc, rc);
1764 }
1765 else
1766 {
1767 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1768 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1769
1770 pgmPoolCacheUsed(pPool, pShwPage);
1771 }
1772 /* The PD was cached or created; hook it up now and fill with the default value. */
1773 pPdpe->u = pShwPage->Core.Key;
1774 pPdpe->n.u1Present = 1;
1775 pPdpe->n.u1Write = 1;
1776 pPdpe->n.u1Execute = 1;
1777
1778 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1779 return VINF_SUCCESS;
1780}
1781
1782#endif /* IN_RC */
1783
1784#ifdef IN_RING0
1785/**
1786 * Synchronizes a range of nested page table entries.
1787 *
1788 * The caller must own the PGM lock.
1789 *
1790 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1791 * @param GCPhys Where to start.
1792 * @param cPages How many pages which entries should be synced.
1793 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1794 * host paging mode for AMD-V).
1795 */
1796int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1797{
1798 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1799
1800/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1801 int rc;
1802 switch (enmShwPagingMode)
1803 {
1804 case PGMMODE_32_BIT:
1805 {
1806 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1807 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1808 break;
1809 }
1810
1811 case PGMMODE_PAE:
1812 case PGMMODE_PAE_NX:
1813 {
1814 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1815 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1816 break;
1817 }
1818
1819 case PGMMODE_AMD64:
1820 case PGMMODE_AMD64_NX:
1821 {
1822 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1823 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1824 break;
1825 }
1826
1827 case PGMMODE_EPT:
1828 {
1829 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1830 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1831 break;
1832 }
1833
1834 default:
1835 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1836 }
1837 return rc;
1838}
1839#endif /* IN_RING0 */
1840
1841
1842/**
1843 * Gets effective Guest OS page information.
1844 *
1845 * When GCPtr is in a big page, the function will return as if it was a normal
1846 * 4KB page. If the need for distinguishing between big and normal page becomes
1847 * necessary at a later point, a PGMGstGetPage() will be created for that
1848 * purpose.
1849 *
1850 * @returns VBox status code.
1851 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1852 * @param GCPtr Guest Context virtual address of the page.
1853 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1854 * @param pGCPhys Where to store the GC physical address of the page.
1855 * This is page aligned. The fact that the
1856 */
1857VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1858{
1859 VMCPU_ASSERT_EMT(pVCpu);
1860 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1861 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1862 AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1863 return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pfFlags, pGCPhys);
1864}
1865
1866
1867/**
1868 * Performs a guest page table walk.
1869 *
1870 * The guest should be in paged protect mode or long mode when making a call to
1871 * this function.
1872 *
1873 * @returns VBox status code.
1874 * @retval VINF_SUCCESS on success.
1875 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1876 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1877 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1878 *
1879 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1880 * @param GCPtr The guest virtual address to walk by.
1881 * @param pWalk Where to return the walk result. This is valid for some
1882 * error codes as well.
1883 */
1884int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1885{
1886 VMCPU_ASSERT_EMT(pVCpu);
1887 switch (pVCpu->pgm.s.enmGuestMode)
1888 {
1889 case PGMMODE_32_BIT:
1890 pWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1891 return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, &pWalk->u.Legacy);
1892
1893 case PGMMODE_PAE:
1894 case PGMMODE_PAE_NX:
1895 pWalk->enmType = PGMPTWALKGSTTYPE_PAE;
1896 return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, &pWalk->u.Pae);
1897
1898#if !defined(IN_RC)
1899 case PGMMODE_AMD64:
1900 case PGMMODE_AMD64_NX:
1901 pWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
1902 return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, &pWalk->u.Amd64);
1903#endif
1904
1905 case PGMMODE_REAL:
1906 case PGMMODE_PROTECTED:
1907 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
1908 return VERR_PGM_NOT_USED_IN_MODE;
1909
1910#if defined(IN_RC)
1911 case PGMMODE_AMD64:
1912 case PGMMODE_AMD64_NX:
1913#endif
1914 case PGMMODE_NESTED_32BIT:
1915 case PGMMODE_NESTED_PAE:
1916 case PGMMODE_NESTED_AMD64:
1917 case PGMMODE_EPT:
1918 default:
1919 AssertFailed();
1920 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
1921 return VERR_PGM_NOT_USED_IN_MODE;
1922 }
1923}
1924
1925
1926/**
1927 * Tries to continue the previous walk.
1928 *
1929 * @note Requires the caller to hold the PGM lock from the first
1930 * pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
1931 * we cannot use the pointers.
1932 *
1933 * @returns VBox status code.
1934 * @retval VINF_SUCCESS on success.
1935 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1936 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1937 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1938 *
1939 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1940 * @param GCPtr The guest virtual address to walk by.
1941 * @param pWalk Pointer to the previous walk result and where to return
1942 * the result of this walk. This is valid for some error
1943 * codes as well.
1944 */
1945int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1946{
1947 /*
1948 * We can only handle successfully walks.
1949 * We also limit ourselves to the next page.
1950 */
1951 if ( pWalk->u.Core.fSucceeded
1952 && GCPtr - pWalk->u.Core.GCPtr == PAGE_SIZE)
1953 {
1954 Assert(pWalk->u.Core.uLevel == 0);
1955 if (pWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
1956 {
1957 /*
1958 * AMD64
1959 */
1960 if (!pWalk->u.Core.fGigantPage && !pWalk->u.Core.fBigPage)
1961 {
1962 /*
1963 * We fall back to full walk if the PDE table changes, if any
1964 * reserved bits are set, or if the effective page access changes.
1965 */
1966 const uint64_t fPteSame = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT
1967 | X86_PTE_PCD | X86_PTE_A | X86_PTE_PAE_NX;
1968 const uint64_t fPdeSame = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT
1969 | X86_PDE_PCD | X86_PDE_A | X86_PDE_PAE_NX | X86_PDE_PS;
1970
1971 if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PD_PAE_SHIFT))
1972 {
1973 if (pWalk->u.Amd64.pPte)
1974 {
1975 X86PTEPAE Pte;
1976 Pte.u = pWalk->u.Amd64.pPte[1].u;
1977 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
1978 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
1979 {
1980
1981 pWalk->u.Core.GCPtr = GCPtr;
1982 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
1983 pWalk->u.Amd64.Pte.u = Pte.u;
1984 pWalk->u.Amd64.pPte++;
1985 return VINF_SUCCESS;
1986 }
1987 }
1988 }
1989 else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PDPT_SHIFT))
1990 {
1991 Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
1992 if (pWalk->u.Amd64.pPde)
1993 {
1994 X86PDEPAE Pde;
1995 Pde.u = pWalk->u.Amd64.pPde[1].u;
1996 if ( (Pde.u & fPdeSame) == (pWalk->u.Amd64.Pde.u & fPdeSame)
1997 && !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
1998 {
1999 /* Get the new PTE and check out the first entry. */
2000 int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2001 &pWalk->u.Amd64.pPt);
2002 if (RT_SUCCESS(rc))
2003 {
2004 pWalk->u.Amd64.pPte = &pWalk->u.Amd64.pPt->a[0];
2005 X86PTEPAE Pte;
2006 Pte.u = pWalk->u.Amd64.pPte->u;
2007 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
2008 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2009 {
2010 pWalk->u.Core.GCPtr = GCPtr;
2011 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2012 pWalk->u.Amd64.Pte.u = Pte.u;
2013 pWalk->u.Amd64.Pde.u = Pde.u;
2014 pWalk->u.Amd64.pPde++;
2015 return VINF_SUCCESS;
2016 }
2017 }
2018 }
2019 }
2020 }
2021 }
2022 else if (!pWalk->u.Core.fGigantPage)
2023 {
2024 if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_2M_BASE_MASK))
2025 {
2026 pWalk->u.Core.GCPtr = GCPtr;
2027 pWalk->u.Core.GCPhys += PAGE_SIZE;
2028 return VINF_SUCCESS;
2029 }
2030 }
2031 else
2032 {
2033 if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_1G_BASE_MASK))
2034 {
2035 pWalk->u.Core.GCPtr = GCPtr;
2036 pWalk->u.Core.GCPhys += PAGE_SIZE;
2037 return VINF_SUCCESS;
2038 }
2039 }
2040 }
2041 }
2042 /* Case we don't handle. Do full walk. */
2043 return pgmGstPtWalk(pVCpu, GCPtr, pWalk);
2044}
2045
2046
2047/**
2048 * Checks if the page is present.
2049 *
2050 * @returns true if the page is present.
2051 * @returns false if the page is not present.
2052 * @param pVCpu The cross context virtual CPU structure.
2053 * @param GCPtr Address within the page.
2054 */
2055VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
2056{
2057 VMCPU_ASSERT_EMT(pVCpu);
2058 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
2059 return RT_SUCCESS(rc);
2060}
2061
2062
2063/**
2064 * Sets (replaces) the page flags for a range of pages in the guest's tables.
2065 *
2066 * @returns VBox status code.
2067 * @param pVCpu The cross context virtual CPU structure.
2068 * @param GCPtr The address of the first page.
2069 * @param cb The size of the range in bytes.
2070 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
2071 */
2072VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
2073{
2074 VMCPU_ASSERT_EMT(pVCpu);
2075 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
2076}
2077
2078
2079/**
2080 * Modify page flags for a range of pages in the guest's tables
2081 *
2082 * The existing flags are ANDed with the fMask and ORed with the fFlags.
2083 *
2084 * @returns VBox status code.
2085 * @param pVCpu The cross context virtual CPU structure.
2086 * @param GCPtr Virtual address of the first page in the range.
2087 * @param cb Size (in bytes) of the range to apply the modification to.
2088 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2089 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2090 * Be very CAREFUL when ~'ing constants which could be 32-bit!
2091 */
2092VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2093{
2094 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2095 VMCPU_ASSERT_EMT(pVCpu);
2096
2097 /*
2098 * Validate input.
2099 */
2100 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2101 Assert(cb);
2102
2103 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2104
2105 /*
2106 * Adjust input.
2107 */
2108 cb += GCPtr & PAGE_OFFSET_MASK;
2109 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
2110 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
2111
2112 /*
2113 * Call worker.
2114 */
2115 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2116 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2117 AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2118 int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2119
2120 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2121 return rc;
2122}
2123
2124
2125#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2126
2127/**
2128 * Performs the lazy mapping of the 32-bit guest PD.
2129 *
2130 * @returns VBox status code.
2131 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2132 * @param ppPd Where to return the pointer to the mapping. This is
2133 * always set.
2134 */
2135int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
2136{
2137 PVM pVM = pVCpu->CTX_SUFF(pVM);
2138 pgmLock(pVM);
2139
2140 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2141
2142 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
2143 PPGMPAGE pPage;
2144 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2145 if (RT_SUCCESS(rc))
2146 {
2147 RTHCPTR HCPtrGuestCR3;
2148 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2149 if (RT_SUCCESS(rc))
2150 {
2151 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
2152# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2153 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
2154# endif
2155 *ppPd = (PX86PD)HCPtrGuestCR3;
2156
2157 pgmUnlock(pVM);
2158 return VINF_SUCCESS;
2159 }
2160
2161 AssertRC(rc);
2162 }
2163 pgmUnlock(pVM);
2164
2165 *ppPd = NULL;
2166 return rc;
2167}
2168
2169
2170/**
2171 * Performs the lazy mapping of the PAE guest PDPT.
2172 *
2173 * @returns VBox status code.
2174 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2175 * @param ppPdpt Where to return the pointer to the mapping. This is
2176 * always set.
2177 */
2178int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
2179{
2180 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2181 PVM pVM = pVCpu->CTX_SUFF(pVM);
2182 pgmLock(pVM);
2183
2184 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
2185 PPGMPAGE pPage;
2186 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2187 if (RT_SUCCESS(rc))
2188 {
2189 RTHCPTR HCPtrGuestCR3;
2190 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2191 if (RT_SUCCESS(rc))
2192 {
2193 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2194# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2195 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2196# endif
2197 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
2198
2199 pgmUnlock(pVM);
2200 return VINF_SUCCESS;
2201 }
2202
2203 AssertRC(rc);
2204 }
2205
2206 pgmUnlock(pVM);
2207 *ppPdpt = NULL;
2208 return rc;
2209}
2210
2211
2212/**
2213 * Performs the lazy mapping / updating of a PAE guest PD.
2214 *
2215 * @returns Pointer to the mapping.
2216 * @returns VBox status code.
2217 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2218 * @param iPdpt Which PD entry to map (0..3).
2219 * @param ppPd Where to return the pointer to the mapping. This is
2220 * always set.
2221 */
2222int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2223{
2224 PVM pVM = pVCpu->CTX_SUFF(pVM);
2225 pgmLock(pVM);
2226
2227 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2228 Assert(pGuestPDPT);
2229 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
2230 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2231 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2232
2233 PPGMPAGE pPage;
2234 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2235 if (RT_SUCCESS(rc))
2236 {
2237 RTRCPTR RCPtr = NIL_RTRCPTR;
2238 RTHCPTR HCPtr = NIL_RTHCPTR;
2239#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2240 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
2241 AssertRC(rc);
2242#endif
2243 if (RT_SUCCESS(rc) && fChanged)
2244 {
2245 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
2246 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
2247 }
2248 if (RT_SUCCESS(rc))
2249 {
2250 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
2251# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2252 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
2253# endif
2254 if (fChanged)
2255 {
2256 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2257 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
2258 }
2259
2260 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
2261 pgmUnlock(pVM);
2262 return VINF_SUCCESS;
2263 }
2264 }
2265
2266 /* Invalid page or some failure, invalidate the entry. */
2267 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2268 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
2269# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2270 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
2271# endif
2272 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
2273
2274 pgmUnlock(pVM);
2275 return rc;
2276}
2277
2278#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2279#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2280/**
2281 * Performs the lazy mapping of the 32-bit guest PD.
2282 *
2283 * @returns VBox status code.
2284 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2285 * @param ppPml4 Where to return the pointer to the mapping. This will
2286 * always be set.
2287 */
2288int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
2289{
2290 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2291 PVM pVM = pVCpu->CTX_SUFF(pVM);
2292 pgmLock(pVM);
2293
2294 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
2295 PPGMPAGE pPage;
2296 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2297 if (RT_SUCCESS(rc))
2298 {
2299 RTHCPTR HCPtrGuestCR3;
2300 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2301 if (RT_SUCCESS(rc))
2302 {
2303 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
2304# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2305 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
2306# endif
2307 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
2308
2309 pgmUnlock(pVM);
2310 return VINF_SUCCESS;
2311 }
2312 }
2313
2314 pgmUnlock(pVM);
2315 *ppPml4 = NULL;
2316 return rc;
2317}
2318#endif
2319
2320
2321/**
2322 * Gets the PAE PDPEs values cached by the CPU.
2323 *
2324 * @returns VBox status code.
2325 * @param pVCpu The cross context virtual CPU structure.
2326 * @param paPdpes Where to return the four PDPEs. The array
2327 * pointed to must have 4 entries.
2328 */
2329VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
2330{
2331 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2332
2333 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
2334 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
2335 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
2336 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
2337 return VINF_SUCCESS;
2338}
2339
2340
2341/**
2342 * Sets the PAE PDPEs values cached by the CPU.
2343 *
2344 * @remarks This must be called *AFTER* PGMUpdateCR3.
2345 *
2346 * @param pVCpu The cross context virtual CPU structure.
2347 * @param paPdpes The four PDPE values. The array pointed to must
2348 * have exactly 4 entries.
2349 *
2350 * @remarks No-long-jump zone!!!
2351 */
2352VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
2353{
2354 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2355
2356 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
2357 {
2358 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
2359 {
2360 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
2361
2362 /* Force lazy remapping if it changed in any way. */
2363 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2364# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2365 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2366# endif
2367 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
2368 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2369 }
2370 }
2371
2372 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
2373}
2374
2375
2376/**
2377 * Gets the current CR3 register value for the shadow memory context.
2378 * @returns CR3 value.
2379 * @param pVCpu The cross context virtual CPU structure.
2380 */
2381VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2382{
2383 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2384 AssertPtrReturn(pPoolPage, 0);
2385 return pPoolPage->Core.Key;
2386}
2387
2388
2389/**
2390 * Gets the current CR3 register value for the nested memory context.
2391 * @returns CR3 value.
2392 * @param pVCpu The cross context virtual CPU structure.
2393 * @param enmShadowMode The shadow paging mode.
2394 */
2395VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
2396{
2397 NOREF(enmShadowMode);
2398 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
2399 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
2400}
2401
2402
2403/**
2404 * Gets the current CR3 register value for the HC intermediate memory context.
2405 * @returns CR3 value.
2406 * @param pVM The cross context VM structure.
2407 */
2408VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
2409{
2410 switch (pVM->pgm.s.enmHostMode)
2411 {
2412 case SUPPAGINGMODE_32_BIT:
2413 case SUPPAGINGMODE_32_BIT_GLOBAL:
2414 return pVM->pgm.s.HCPhysInterPD;
2415
2416 case SUPPAGINGMODE_PAE:
2417 case SUPPAGINGMODE_PAE_GLOBAL:
2418 case SUPPAGINGMODE_PAE_NX:
2419 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2420 return pVM->pgm.s.HCPhysInterPaePDPT;
2421
2422 case SUPPAGINGMODE_AMD64:
2423 case SUPPAGINGMODE_AMD64_GLOBAL:
2424 case SUPPAGINGMODE_AMD64_NX:
2425 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2426 return pVM->pgm.s.HCPhysInterPaePDPT;
2427
2428 default:
2429 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
2430 return NIL_RTHCPHYS;
2431 }
2432}
2433
2434
2435/**
2436 * Gets the current CR3 register value for the RC intermediate memory context.
2437 * @returns CR3 value.
2438 * @param pVM The cross context VM structure.
2439 * @param pVCpu The cross context virtual CPU structure.
2440 */
2441VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
2442{
2443 switch (pVCpu->pgm.s.enmShadowMode)
2444 {
2445 case PGMMODE_32_BIT:
2446 return pVM->pgm.s.HCPhysInterPD;
2447
2448 case PGMMODE_PAE:
2449 case PGMMODE_PAE_NX:
2450 return pVM->pgm.s.HCPhysInterPaePDPT;
2451
2452 case PGMMODE_AMD64:
2453 case PGMMODE_AMD64_NX:
2454 return pVM->pgm.s.HCPhysInterPaePML4;
2455
2456 case PGMMODE_NESTED_32BIT:
2457 case PGMMODE_NESTED_PAE:
2458 case PGMMODE_NESTED_AMD64:
2459 case PGMMODE_EPT:
2460 return 0; /* not relevant */
2461
2462 default:
2463 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
2464 return NIL_RTHCPHYS;
2465 }
2466}
2467
2468
2469/**
2470 * Gets the CR3 register value for the 32-Bit intermediate memory context.
2471 * @returns CR3 value.
2472 * @param pVM The cross context VM structure.
2473 */
2474VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
2475{
2476 return pVM->pgm.s.HCPhysInterPD;
2477}
2478
2479
2480/**
2481 * Gets the CR3 register value for the PAE intermediate memory context.
2482 * @returns CR3 value.
2483 * @param pVM The cross context VM structure.
2484 */
2485VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
2486{
2487 return pVM->pgm.s.HCPhysInterPaePDPT;
2488}
2489
2490
2491/**
2492 * Gets the CR3 register value for the AMD64 intermediate memory context.
2493 * @returns CR3 value.
2494 * @param pVM The cross context VM structure.
2495 */
2496VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
2497{
2498 return pVM->pgm.s.HCPhysInterPaePML4;
2499}
2500
2501
2502/**
2503 * Performs and schedules necessary updates following a CR3 load or reload.
2504 *
2505 * This will normally involve mapping the guest PD or nPDPT
2506 *
2507 * @returns VBox status code.
2508 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2509 * safely be ignored and overridden since the FF will be set too then.
2510 * @param pVCpu The cross context virtual CPU structure.
2511 * @param cr3 The new cr3.
2512 * @param fGlobal Indicates whether this is a global flush or not.
2513 */
2514VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
2515{
2516 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2517 PVM pVM = pVCpu->CTX_SUFF(pVM);
2518
2519 VMCPU_ASSERT_EMT(pVCpu);
2520
2521 /*
2522 * Always flag the necessary updates; necessary for hardware acceleration
2523 */
2524 /** @todo optimize this, it shouldn't always be necessary. */
2525 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2526 if (fGlobal)
2527 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2528 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
2529
2530 /*
2531 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2532 */
2533 int rc = VINF_SUCCESS;
2534 RTGCPHYS GCPhysCR3;
2535 switch (pVCpu->pgm.s.enmGuestMode)
2536 {
2537 case PGMMODE_PAE:
2538 case PGMMODE_PAE_NX:
2539 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2540 break;
2541 case PGMMODE_AMD64:
2542 case PGMMODE_AMD64_NX:
2543 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2544 break;
2545 default:
2546 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2547 break;
2548 }
2549 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2550
2551 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2552 if (GCPhysOldCR3 != GCPhysCR3)
2553 {
2554 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2555 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2556 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2557
2558 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2559 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2560 if (RT_LIKELY(rc == VINF_SUCCESS))
2561 {
2562 if (pgmMapAreMappingsFloating(pVM))
2563 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2564 }
2565 else
2566 {
2567 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2568 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
2569 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2570 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
2571 if (pgmMapAreMappingsFloating(pVM))
2572 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
2573 }
2574
2575 if (fGlobal)
2576 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2577 else
2578 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
2579 }
2580 else
2581 {
2582# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2583 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2584 if (pPool->cDirtyPages)
2585 {
2586 pgmLock(pVM);
2587 pgmPoolResetDirtyPages(pVM);
2588 pgmUnlock(pVM);
2589 }
2590# endif
2591 /*
2592 * Check if we have a pending update of the CR3 monitoring.
2593 */
2594 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2595 {
2596 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2597 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
2598 }
2599 if (fGlobal)
2600 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2601 else
2602 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
2603 }
2604
2605 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
2606 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2607 return rc;
2608}
2609
2610
2611/**
2612 * Performs and schedules necessary updates following a CR3 load or reload when
2613 * using nested or extended paging.
2614 *
2615 * This API is an alternative to PGMFlushTLB that avoids actually flushing the
2616 * TLB and triggering a SyncCR3.
2617 *
2618 * This will normally involve mapping the guest PD or nPDPT
2619 *
2620 * @returns VBox status code.
2621 * @retval VINF_SUCCESS.
2622 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2623 * paging modes). This can safely be ignored and overridden since the
2624 * FF will be set too then.
2625 * @param pVCpu The cross context virtual CPU structure.
2626 * @param cr3 The new cr3.
2627 */
2628VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
2629{
2630 VMCPU_ASSERT_EMT(pVCpu);
2631 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
2632
2633 /* We assume we're only called in nested paging mode. */
2634 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2635 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2636 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
2637
2638 /*
2639 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2640 */
2641 int rc = VINF_SUCCESS;
2642 RTGCPHYS GCPhysCR3;
2643 switch (pVCpu->pgm.s.enmGuestMode)
2644 {
2645 case PGMMODE_PAE:
2646 case PGMMODE_PAE_NX:
2647 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2648 break;
2649 case PGMMODE_AMD64:
2650 case PGMMODE_AMD64_NX:
2651 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2652 break;
2653 default:
2654 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2655 break;
2656 }
2657 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2658
2659 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2660 {
2661 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2662 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2663 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2664
2665 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2666 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2667
2668 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
2669 }
2670
2671 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2672 return rc;
2673}
2674
2675
2676/**
2677 * Synchronize the paging structures.
2678 *
2679 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2680 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2681 * in several places, most importantly whenever the CR3 is loaded.
2682 *
2683 * @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2684 * @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2685 * the VMM into guest context.
2686 * @param pVCpu The cross context virtual CPU structure.
2687 * @param cr0 Guest context CR0 register
2688 * @param cr3 Guest context CR3 register
2689 * @param cr4 Guest context CR4 register
2690 * @param fGlobal Including global page directories or not
2691 */
2692VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2693{
2694 int rc;
2695
2696 VMCPU_ASSERT_EMT(pVCpu);
2697
2698 /*
2699 * The pool may have pending stuff and even require a return to ring-3 to
2700 * clear the whole thing.
2701 */
2702 rc = pgmPoolSyncCR3(pVCpu);
2703 if (rc != VINF_SUCCESS)
2704 return rc;
2705
2706 /*
2707 * We might be called when we shouldn't.
2708 *
2709 * The mode switching will ensure that the PD is resynced after every mode
2710 * switch. So, if we find ourselves here when in protected or real mode
2711 * we can safely clear the FF and return immediately.
2712 */
2713 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2714 {
2715 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2716 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2717 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2718 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2719 return VINF_SUCCESS;
2720 }
2721
2722 /* If global pages are not supported, then all flushes are global. */
2723 if (!(cr4 & X86_CR4_PGE))
2724 fGlobal = true;
2725 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2726 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2727
2728 /*
2729 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2730 * This should be done before SyncCR3.
2731 */
2732 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2733 {
2734 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2735
2736 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2737 RTGCPHYS GCPhysCR3;
2738 switch (pVCpu->pgm.s.enmGuestMode)
2739 {
2740 case PGMMODE_PAE:
2741 case PGMMODE_PAE_NX:
2742 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2743 break;
2744 case PGMMODE_AMD64:
2745 case PGMMODE_AMD64_NX:
2746 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2747 break;
2748 default:
2749 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2750 break;
2751 }
2752 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2753
2754 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2755 {
2756 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2757 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2758 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2759 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2760 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2761 }
2762
2763 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2764 if ( rc == VINF_PGM_SYNC_CR3
2765 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2766 {
2767 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2768#ifdef IN_RING3
2769 rc = pgmPoolSyncCR3(pVCpu);
2770#else
2771 if (rc == VINF_PGM_SYNC_CR3)
2772 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2773 return VINF_PGM_SYNC_CR3;
2774#endif
2775 }
2776 AssertRCReturn(rc, rc);
2777 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2778 }
2779
2780 /*
2781 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2782 */
2783 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2784
2785 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2786 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2787 AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2788 rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2789
2790 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2791 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2792 if (rc == VINF_SUCCESS)
2793 {
2794 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2795 {
2796 /* Go back to ring 3 if a pgm pool sync is again pending. */
2797 return VINF_PGM_SYNC_CR3;
2798 }
2799
2800 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2801 {
2802 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2803 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2804 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2805 }
2806
2807 /*
2808 * Check if we have a pending update of the CR3 monitoring.
2809 */
2810 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2811 {
2812 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2813 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2814 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2815 }
2816 }
2817
2818 /*
2819 * Now flush the CR3 (guest context).
2820 */
2821 if (rc == VINF_SUCCESS)
2822 PGM_INVL_VCPU_TLBS(pVCpu);
2823 return rc;
2824}
2825
2826
2827/**
2828 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2829 *
2830 * @returns VBox status code, with the following informational code for
2831 * VM scheduling.
2832 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2833 * @retval VINF_PGM_CHANGE_MODE if we're in RC the mode changes. This will
2834 * NOT be returned in ring-3 or ring-0.
2835 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2836 *
2837 * @param pVCpu The cross context virtual CPU structure.
2838 * @param cr0 The new cr0.
2839 * @param cr4 The new cr4.
2840 * @param efer The new extended feature enable register.
2841 */
2842VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2843{
2844 VMCPU_ASSERT_EMT(pVCpu);
2845
2846 /*
2847 * Calc the new guest mode.
2848 *
2849 * Note! We check PG before PE and without requiring PE because of the
2850 * special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
2851 */
2852 PGMMODE enmGuestMode;
2853 if (cr0 & X86_CR0_PG)
2854 {
2855 if (!(cr4 & X86_CR4_PAE))
2856 {
2857 bool const fPse = !!(cr4 & X86_CR4_PSE);
2858 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2859 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2860 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2861 enmGuestMode = PGMMODE_32_BIT;
2862 }
2863 else if (!(efer & MSR_K6_EFER_LME))
2864 {
2865 if (!(efer & MSR_K6_EFER_NXE))
2866 enmGuestMode = PGMMODE_PAE;
2867 else
2868 enmGuestMode = PGMMODE_PAE_NX;
2869 }
2870 else
2871 {
2872 if (!(efer & MSR_K6_EFER_NXE))
2873 enmGuestMode = PGMMODE_AMD64;
2874 else
2875 enmGuestMode = PGMMODE_AMD64_NX;
2876 }
2877 }
2878 else if (!(cr0 & X86_CR0_PE))
2879 enmGuestMode = PGMMODE_REAL;
2880 else
2881 enmGuestMode = PGMMODE_PROTECTED;
2882
2883 /*
2884 * Did it change?
2885 */
2886 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2887 return VINF_SUCCESS;
2888
2889 /* Flush the TLB */
2890 PGM_INVL_VCPU_TLBS(pVCpu);
2891
2892#ifndef IN_RC
2893 return PGMHCChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2894#else
2895 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2896 return VINF_PGM_CHANGE_MODE;
2897#endif
2898}
2899
2900#ifndef IN_RC
2901
2902/**
2903 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2904 *
2905 * @returns PGM_TYPE_*.
2906 * @param pgmMode The mode value to convert.
2907 */
2908DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2909{
2910 switch (pgmMode)
2911 {
2912 case PGMMODE_REAL: return PGM_TYPE_REAL;
2913 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2914 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2915 case PGMMODE_PAE:
2916 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2917 case PGMMODE_AMD64:
2918 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2919 case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
2920 case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
2921 case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
2922 case PGMMODE_EPT: return PGM_TYPE_EPT;
2923 default:
2924 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2925 }
2926}
2927
2928
2929/**
2930 * Calculates the shadow paging mode.
2931 *
2932 * @returns The shadow paging mode.
2933 * @param pVM The cross context VM structure.
2934 * @param enmGuestMode The guest mode.
2935 * @param enmHostMode The host mode.
2936 * @param enmShadowMode The current shadow mode.
2937 * @param penmSwitcher Where to store the switcher to use.
2938 * VMMSWITCHER_INVALID means no change.
2939 */
2940static PGMMODE pgmCalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode,
2941 VMMSWITCHER *penmSwitcher)
2942{
2943 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2944 switch (enmGuestMode)
2945 {
2946 /*
2947 * When switching to real or protected mode we don't change
2948 * anything since it's likely that we'll switch back pretty soon.
2949 *
2950 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2951 * and is supposed to determine which shadow paging and switcher to
2952 * use during init.
2953 */
2954 case PGMMODE_REAL:
2955 case PGMMODE_PROTECTED:
2956 if ( enmShadowMode != PGMMODE_INVALID
2957 && VM_IS_RAW_MODE_ENABLED(pVM) /* always switch in hm and nem modes! */)
2958 break; /* (no change) */
2959
2960 switch (enmHostMode)
2961 {
2962 case SUPPAGINGMODE_32_BIT:
2963 case SUPPAGINGMODE_32_BIT_GLOBAL:
2964 enmShadowMode = PGMMODE_32_BIT;
2965 enmSwitcher = VMMSWITCHER_32_TO_32;
2966 break;
2967
2968 case SUPPAGINGMODE_PAE:
2969 case SUPPAGINGMODE_PAE_NX:
2970 case SUPPAGINGMODE_PAE_GLOBAL:
2971 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2972 enmShadowMode = PGMMODE_PAE;
2973 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2974 break;
2975
2976 case SUPPAGINGMODE_AMD64:
2977 case SUPPAGINGMODE_AMD64_GLOBAL:
2978 case SUPPAGINGMODE_AMD64_NX:
2979 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2980 enmShadowMode = PGMMODE_PAE;
2981 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2982 break;
2983
2984 default:
2985 AssertLogRelMsgFailedReturnStmt(("enmHostMode=%d\n", enmHostMode),
2986 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
2987 }
2988 break;
2989
2990 case PGMMODE_32_BIT:
2991 switch (enmHostMode)
2992 {
2993 case SUPPAGINGMODE_32_BIT:
2994 case SUPPAGINGMODE_32_BIT_GLOBAL:
2995 enmShadowMode = PGMMODE_32_BIT;
2996 enmSwitcher = VMMSWITCHER_32_TO_32;
2997 break;
2998
2999 case SUPPAGINGMODE_PAE:
3000 case SUPPAGINGMODE_PAE_NX:
3001 case SUPPAGINGMODE_PAE_GLOBAL:
3002 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3003 enmShadowMode = PGMMODE_PAE;
3004 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3005 break;
3006
3007 case SUPPAGINGMODE_AMD64:
3008 case SUPPAGINGMODE_AMD64_GLOBAL:
3009 case SUPPAGINGMODE_AMD64_NX:
3010 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3011 enmShadowMode = PGMMODE_PAE;
3012 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3013 break;
3014
3015 default:
3016 AssertLogRelMsgFailedReturnStmt(("enmHostMode=%d\n", enmHostMode),
3017 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
3018 }
3019 break;
3020
3021 case PGMMODE_PAE:
3022 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3023 switch (enmHostMode)
3024 {
3025 case SUPPAGINGMODE_32_BIT:
3026 case SUPPAGINGMODE_32_BIT_GLOBAL:
3027 enmShadowMode = PGMMODE_PAE;
3028 enmSwitcher = VMMSWITCHER_32_TO_PAE;
3029 break;
3030
3031 case SUPPAGINGMODE_PAE:
3032 case SUPPAGINGMODE_PAE_NX:
3033 case SUPPAGINGMODE_PAE_GLOBAL:
3034 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3035 enmShadowMode = PGMMODE_PAE;
3036 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3037 break;
3038
3039 case SUPPAGINGMODE_AMD64:
3040 case SUPPAGINGMODE_AMD64_GLOBAL:
3041 case SUPPAGINGMODE_AMD64_NX:
3042 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3043 enmShadowMode = PGMMODE_PAE;
3044 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3045 break;
3046
3047 default:
3048 AssertLogRelMsgFailedReturnStmt(("enmHostMode=%d\n", enmHostMode),
3049 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
3050 }
3051 break;
3052
3053 case PGMMODE_AMD64:
3054 case PGMMODE_AMD64_NX:
3055 switch (enmHostMode)
3056 {
3057 case SUPPAGINGMODE_32_BIT:
3058 case SUPPAGINGMODE_32_BIT_GLOBAL:
3059 enmShadowMode = PGMMODE_AMD64;
3060 enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3061 break;
3062
3063 case SUPPAGINGMODE_PAE:
3064 case SUPPAGINGMODE_PAE_NX:
3065 case SUPPAGINGMODE_PAE_GLOBAL:
3066 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3067 enmShadowMode = PGMMODE_AMD64;
3068 enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3069 break;
3070
3071 case SUPPAGINGMODE_AMD64:
3072 case SUPPAGINGMODE_AMD64_GLOBAL:
3073 case SUPPAGINGMODE_AMD64_NX:
3074 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3075 enmShadowMode = PGMMODE_AMD64;
3076 enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3077 break;
3078
3079 default:
3080 AssertLogRelMsgFailedReturnStmt(("enmHostMode=%d\n", enmHostMode),
3081 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
3082 }
3083 break;
3084
3085 default:
3086 AssertLogRelMsgFailedReturnStmt(("enmGuestMode=%d\n", enmGuestMode),
3087 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
3088 }
3089
3090 /*
3091 * Override the shadow mode when NEM or nested paging is active.
3092 */
3093 if (VM_IS_NEM_ENABLED(pVM))
3094 {
3095 pVM->pgm.s.fNestedPaging = true;
3096 enmShadowMode = PGMMODE_EPT; /* whatever harmless... */
3097 }
3098 else
3099 {
3100 bool fNestedPaging = HMIsNestedPagingActive(pVM);
3101 pVM->pgm.s.fNestedPaging = fNestedPaging;
3102 if (fNestedPaging)
3103 {
3104 if (HMIsVmxActive(pVM))
3105 enmShadowMode = PGMMODE_EPT;
3106 else
3107 {
3108 /* The nested SVM paging depends on the host one. */
3109 Assert(HMIsSvmActive(pVM));
3110 if ( enmGuestMode == PGMMODE_AMD64
3111 || enmGuestMode == PGMMODE_AMD64_NX)
3112 enmShadowMode = PGMMODE_NESTED_AMD64;
3113 else
3114 switch (pVM->pgm.s.enmHostMode)
3115 {
3116 case SUPPAGINGMODE_32_BIT:
3117 case SUPPAGINGMODE_32_BIT_GLOBAL:
3118 enmShadowMode = PGMMODE_NESTED_32BIT;
3119 break;
3120
3121 case SUPPAGINGMODE_PAE:
3122 case SUPPAGINGMODE_PAE_GLOBAL:
3123 case SUPPAGINGMODE_PAE_NX:
3124 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3125 enmShadowMode = PGMMODE_NESTED_PAE;
3126 break;
3127
3128#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
3129 case SUPPAGINGMODE_AMD64:
3130 case SUPPAGINGMODE_AMD64_GLOBAL:
3131 case SUPPAGINGMODE_AMD64_NX:
3132 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3133 enmShadowMode = PGMMODE_NESTED_AMD64;
3134 break;
3135#endif
3136 default:
3137 AssertLogRelMsgFailedReturnStmt(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode),
3138 *penmSwitcher = VMMSWITCHER_INVALID, PGMMODE_INVALID);
3139 }
3140 }
3141 }
3142 }
3143
3144 *penmSwitcher = enmSwitcher;
3145 return enmShadowMode;
3146}
3147
3148
3149/**
3150 * Performs the actual mode change.
3151 * This is called by PGMChangeMode and pgmR3InitPaging().
3152 *
3153 * @returns VBox status code. May suspend or power off the VM on error, but this
3154 * will trigger using FFs and not informational status codes.
3155 *
3156 * @param pVM The cross context VM structure.
3157 * @param pVCpu The cross context virtual CPU structure.
3158 * @param enmGuestMode The new guest mode. This is assumed to be different from
3159 * the current mode.
3160 */
3161VMM_INT_DECL(int) PGMHCChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3162{
3163 Log(("PGMHCChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3164 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3165
3166 /*
3167 * Calc the shadow mode and switcher.
3168 */
3169 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3170 PGMMODE enmShadowMode = PGMMODE_INVALID;
3171 enmShadowMode = pgmCalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3172
3173#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3174 if ( enmSwitcher != VMMSWITCHER_INVALID
3175 && VM_IS_RAW_MODE_ENABLED(pVM))
3176 {
3177 /*
3178 * Select new switcher.
3179 */
3180 int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3181 AssertLogRelMsgRCReturn(rc,("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc), rc);
3182 }
3183#endif
3184
3185 /*
3186 * Exit old mode(s).
3187 */
3188 /* shadow */
3189 if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3190 {
3191 LogFlow(("PGMHCChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3192 uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3193 if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3194 && g_aPgmShadowModeData[idxOldShw].pfnExit)
3195 {
3196 int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3197 AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3198 }
3199 }
3200 else
3201 LogFlow(("PGMHCChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3202
3203 /* guest */
3204 uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3205 if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3206 && g_aPgmGuestModeData[idxOldGst].pfnExit)
3207 {
3208 int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3209 AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3210 }
3211 pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3212
3213 /*
3214 * Change the paging mode data indexes.
3215 */
3216 uintptr_t idxNewGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGuestMode);
3217 AssertReturn(idxNewGst < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
3218 AssertReturn(g_aPgmGuestModeData[idxNewGst].uType == idxNewGst, VERR_PGM_MODE_IPE);
3219 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPage, VERR_PGM_MODE_IPE);
3220 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnModifyPage, VERR_PGM_MODE_IPE);
3221 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPDE, VERR_PGM_MODE_IPE);
3222 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnExit, VERR_PGM_MODE_IPE);
3223 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnEnter, VERR_PGM_MODE_IPE);
3224#ifdef IN_RING3
3225 AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnRelocate, VERR_PGM_MODE_IPE);
3226#endif
3227
3228 uintptr_t const idxNewShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShadowMode);
3229 AssertReturn(idxNewShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
3230 AssertReturn(g_aPgmShadowModeData[idxNewShw].uType == idxNewShw, VERR_PGM_MODE_IPE);
3231 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnGetPage, VERR_PGM_MODE_IPE);
3232 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnModifyPage, VERR_PGM_MODE_IPE);
3233 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnExit, VERR_PGM_MODE_IPE);
3234 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnEnter, VERR_PGM_MODE_IPE);
3235#ifdef IN_RING3
3236 AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnRelocate, VERR_PGM_MODE_IPE);
3237#endif
3238
3239 uintptr_t const idxNewBth = pVCpu->pgm.s.idxBothModeData = (idxNewShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxNewGst;
3240 AssertReturn(g_aPgmBothModeData[idxNewBth].uShwType == idxNewShw, VERR_PGM_MODE_IPE);
3241 AssertReturn(g_aPgmBothModeData[idxNewBth].uGstType == idxNewGst, VERR_PGM_MODE_IPE);
3242 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnInvalidatePage, VERR_PGM_MODE_IPE);
3243 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
3244 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
3245 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
3246 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnMapCR3, VERR_PGM_MODE_IPE);
3247 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
3248 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnEnter, VERR_PGM_MODE_IPE);
3249#ifdef VBOX_STRICT
3250 AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnAssertCR3, VERR_PGM_MODE_IPE);
3251#endif
3252
3253 /*
3254 * Enter new shadow mode (if changed).
3255 */
3256 if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3257 {
3258 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3259 int rc = g_aPgmShadowModeData[idxNewShw].pfnEnter(pVCpu, enmGuestMode >= PGMMODE_AMD64);
3260 AssertLogRelMsgRCReturnStmt(rc, ("Entering enmShadowMode=%s failed: %Rrc\n", PGMGetModeName(enmShadowMode), rc),
3261 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID, rc);
3262 }
3263
3264 /*
3265 * Always flag the necessary updates
3266 */
3267 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3268
3269 /*
3270 * Enter the new guest and shadow+guest modes.
3271 */
3272 /* Calc the new CR3 value. */
3273 RTGCPHYS GCPhysCR3;
3274 switch (enmGuestMode)
3275 {
3276 case PGMMODE_REAL:
3277 case PGMMODE_PROTECTED:
3278 GCPhysCR3 = NIL_RTGCPHYS;
3279 break;
3280
3281 case PGMMODE_32_BIT:
3282 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3283 break;
3284
3285 case PGMMODE_PAE_NX:
3286 case PGMMODE_PAE:
3287 if (!pVM->cpum.ro.GuestFeatures.fPae)
3288 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3289 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3290 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3291 break;
3292
3293#ifdef VBOX_WITH_64_BITS_GUESTS
3294 case PGMMODE_AMD64_NX:
3295 case PGMMODE_AMD64:
3296 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3297 break;
3298#endif
3299 default:
3300 AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), VERR_PGM_MODE_IPE);
3301 }
3302
3303 /* Enter the new guest mode. */
3304 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3305 int rc = g_aPgmGuestModeData[idxNewGst].pfnEnter(pVCpu, GCPhysCR3);
3306 int rc2 = g_aPgmBothModeData[idxNewBth].pfnEnter(pVCpu, GCPhysCR3);
3307
3308 /* Set the new guest CR3. */
3309 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3310
3311 /* status codes. */
3312 AssertRC(rc);
3313 AssertRC(rc2);
3314 if (RT_SUCCESS(rc))
3315 {
3316 rc = rc2;
3317 if (RT_SUCCESS(rc)) /* no informational status codes. */
3318 rc = VINF_SUCCESS;
3319 }
3320
3321 /*
3322 * Notify HM.
3323 */
3324 HMHCPagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3325 return rc;
3326}
3327
3328#endif /* !IN_RC */
3329
3330/**
3331 * Called by CPUM or REM when CR0.WP changes to 1.
3332 *
3333 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3334 * @thread EMT
3335 */
3336VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
3337{
3338 /*
3339 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
3340 *
3341 * Use the counter to judge whether there might be pool pages with active
3342 * hacks in them. If there are, we will be running the risk of messing up
3343 * the guest by allowing it to write to read-only pages. Thus, we have to
3344 * clear the page pool ASAP if there is the slightest chance.
3345 */
3346 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
3347 {
3348 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
3349
3350 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
3351 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
3352 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3353 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3354 }
3355}
3356
3357
3358/**
3359 * Gets the current guest paging mode.
3360 *
3361 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
3362 *
3363 * @returns The current paging mode.
3364 * @param pVCpu The cross context virtual CPU structure.
3365 */
3366VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
3367{
3368 return pVCpu->pgm.s.enmGuestMode;
3369}
3370
3371
3372/**
3373 * Gets the current shadow paging mode.
3374 *
3375 * @returns The current paging mode.
3376 * @param pVCpu The cross context virtual CPU structure.
3377 */
3378VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
3379{
3380 return pVCpu->pgm.s.enmShadowMode;
3381}
3382
3383
3384/**
3385 * Gets the current host paging mode.
3386 *
3387 * @returns The current paging mode.
3388 * @param pVM The cross context VM structure.
3389 */
3390VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
3391{
3392 switch (pVM->pgm.s.enmHostMode)
3393 {
3394 case SUPPAGINGMODE_32_BIT:
3395 case SUPPAGINGMODE_32_BIT_GLOBAL:
3396 return PGMMODE_32_BIT;
3397
3398 case SUPPAGINGMODE_PAE:
3399 case SUPPAGINGMODE_PAE_GLOBAL:
3400 return PGMMODE_PAE;
3401
3402 case SUPPAGINGMODE_PAE_NX:
3403 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3404 return PGMMODE_PAE_NX;
3405
3406 case SUPPAGINGMODE_AMD64:
3407 case SUPPAGINGMODE_AMD64_GLOBAL:
3408 return PGMMODE_AMD64;
3409
3410 case SUPPAGINGMODE_AMD64_NX:
3411 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3412 return PGMMODE_AMD64_NX;
3413
3414 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3415 }
3416
3417 return PGMMODE_INVALID;
3418}
3419
3420
3421/**
3422 * Get mode name.
3423 *
3424 * @returns read-only name string.
3425 * @param enmMode The mode which name is desired.
3426 */
3427VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3428{
3429 switch (enmMode)
3430 {
3431 case PGMMODE_REAL: return "Real";
3432 case PGMMODE_PROTECTED: return "Protected";
3433 case PGMMODE_32_BIT: return "32-bit";
3434 case PGMMODE_PAE: return "PAE";
3435 case PGMMODE_PAE_NX: return "PAE+NX";
3436 case PGMMODE_AMD64: return "AMD64";
3437 case PGMMODE_AMD64_NX: return "AMD64+NX";
3438 case PGMMODE_NESTED_32BIT: return "Nested-32";
3439 case PGMMODE_NESTED_PAE: return "Nested-PAE";
3440 case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3441 case PGMMODE_EPT: return "EPT";
3442 default: return "unknown mode value";
3443 }
3444}
3445
3446
3447/**
3448 * Gets the physical address represented in the guest CR3 as PGM sees it.
3449 *
3450 * This is mainly for logging and debugging.
3451 *
3452 * @returns PGM's guest CR3 value.
3453 * @param pVCpu The cross context virtual CPU structure.
3454 */
3455VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3456{
3457 return pVCpu->pgm.s.GCPhysCR3;
3458}
3459
3460
3461
3462/**
3463 * Notification from CPUM that the EFER.NXE bit has changed.
3464 *
3465 * @param pVCpu The cross context virtual CPU structure of the CPU for
3466 * which EFER changed.
3467 * @param fNxe The new NXE state.
3468 */
3469VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3470{
3471/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3472 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3473
3474 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3475 if (fNxe)
3476 {
3477 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3478 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3479 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3480 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3481 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
3482 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3483 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3484 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3485 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3486 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3487 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3488
3489 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
3490 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
3491 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
3492 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
3493 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
3494 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
3495 }
3496 else
3497 {
3498 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3499 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
3500 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
3501 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
3502 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
3503 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
3504 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
3505 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
3506 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
3507 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
3508 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
3509
3510 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3511 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3512 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3513 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3514 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3515 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3516 }
3517}
3518
3519
3520/**
3521 * Check if any pgm pool pages are marked dirty (not monitored)
3522 *
3523 * @returns bool locked/not locked
3524 * @param pVM The cross context VM structure.
3525 */
3526VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3527{
3528 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3529}
3530
3531
3532/**
3533 * Check if this VCPU currently owns the PGM lock.
3534 *
3535 * @returns bool owner/not owner
3536 * @param pVM The cross context VM structure.
3537 */
3538VMMDECL(bool) PGMIsLockOwner(PVM pVM)
3539{
3540 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
3541}
3542
3543
3544/**
3545 * Enable or disable large page usage
3546 *
3547 * @returns VBox status code.
3548 * @param pVM The cross context VM structure.
3549 * @param fUseLargePages Use/not use large pages
3550 */
3551VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
3552{
3553 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3554
3555 pVM->fUseLargePages = fUseLargePages;
3556 return VINF_SUCCESS;
3557}
3558
3559
3560/**
3561 * Acquire the PGM lock.
3562 *
3563 * @returns VBox status code
3564 * @param pVM The cross context VM structure.
3565 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3566 */
3567#if (defined(VBOX_STRICT) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
3568int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL)
3569#else
3570int pgmLock(PVM pVM)
3571#endif
3572{
3573#if defined(VBOX_STRICT) && defined(IN_RING3)
3574 int rc = PDMCritSectEnterDebug(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3575#else
3576 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
3577#endif
3578#if defined(IN_RC) || defined(IN_RING0)
3579 if (rc == VERR_SEM_BUSY)
3580 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
3581#endif
3582 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3583 return rc;
3584}
3585
3586
3587/**
3588 * Release the PGM lock.
3589 *
3590 * @returns VBox status code
3591 * @param pVM The cross context VM structure.
3592 */
3593void pgmUnlock(PVM pVM)
3594{
3595 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3596 pVM->pgm.s.cDeprecatedPageLocks = 0;
3597 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
3598 if (rc == VINF_SEM_NESTED)
3599 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3600}
3601
3602#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3603
3604/**
3605 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
3606 *
3607 * @returns VBox status code.
3608 * @param pVM The cross context VM structure.
3609 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3610 * @param GCPhys The guest physical address of the page to map. The
3611 * offset bits are not ignored.
3612 * @param ppv Where to return the address corresponding to @a GCPhys.
3613 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3614 */
3615int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
3616{
3617 pgmLock(pVM);
3618
3619 /*
3620 * Convert it to a writable page and it on to the dynamic mapper.
3621 */
3622 int rc;
3623 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
3624 if (RT_LIKELY(pPage))
3625 {
3626 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3627 if (RT_SUCCESS(rc))
3628 {
3629 void *pv;
3630 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
3631 if (RT_SUCCESS(rc))
3632 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
3633 }
3634 else
3635 AssertRC(rc);
3636 }
3637 else
3638 {
3639 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
3640 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3641 }
3642
3643 pgmUnlock(pVM);
3644 return rc;
3645}
3646
3647#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3648#if !defined(IN_R0) || defined(LOG_ENABLED)
3649
3650/** Format handler for PGMPAGE.
3651 * @copydoc FNRTSTRFORMATTYPE */
3652static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3653 const char *pszType, void const *pvValue,
3654 int cchWidth, int cchPrecision, unsigned fFlags,
3655 void *pvUser)
3656{
3657 size_t cch;
3658 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3659 if (RT_VALID_PTR(pPage))
3660 {
3661 char szTmp[64+80];
3662
3663 cch = 0;
3664
3665 /* The single char state stuff. */
3666 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3667 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3668
3669#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
3670 if (IS_PART_INCLUDED(5))
3671 {
3672 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
3673 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
3674 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
3675 }
3676
3677 /* The type. */
3678 if (IS_PART_INCLUDED(4))
3679 {
3680 szTmp[cch++] = ':';
3681 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3682 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3683 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3684 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3685 }
3686
3687 /* The numbers. */
3688 if (IS_PART_INCLUDED(3))
3689 {
3690 szTmp[cch++] = ':';
3691 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
3692 }
3693
3694 if (IS_PART_INCLUDED(2))
3695 {
3696 szTmp[cch++] = ':';
3697 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
3698 }
3699
3700 if (IS_PART_INCLUDED(6))
3701 {
3702 szTmp[cch++] = ':';
3703 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3704 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3705 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
3706 }
3707#undef IS_PART_INCLUDED
3708
3709 cch = pfnOutput(pvArgOutput, szTmp, cch);
3710 }
3711 else
3712 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3713 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3714 return cch;
3715}
3716
3717
3718/** Format handler for PGMRAMRANGE.
3719 * @copydoc FNRTSTRFORMATTYPE */
3720static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3721 const char *pszType, void const *pvValue,
3722 int cchWidth, int cchPrecision, unsigned fFlags,
3723 void *pvUser)
3724{
3725 size_t cch;
3726 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
3727 if (VALID_PTR(pRam))
3728 {
3729 char szTmp[80];
3730 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3731 cch = pfnOutput(pvArgOutput, szTmp, cch);
3732 }
3733 else
3734 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3735 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3736 return cch;
3737}
3738
3739/** Format type andlers to be registered/deregistered. */
3740static const struct
3741{
3742 char szType[24];
3743 PFNRTSTRFORMATTYPE pfnHandler;
3744} g_aPgmFormatTypes[] =
3745{
3746 { "pgmpage", pgmFormatTypeHandlerPage },
3747 { "pgmramrange", pgmFormatTypeHandlerRamRange }
3748};
3749
3750#endif /* !IN_R0 || LOG_ENABLED */
3751
3752/**
3753 * Registers the global string format types.
3754 *
3755 * This should be called at module load time or in some other manner that ensure
3756 * that it's called exactly one time.
3757 *
3758 * @returns IPRT status code on RTStrFormatTypeRegister failure.
3759 */
3760VMMDECL(int) PGMRegisterStringFormatTypes(void)
3761{
3762#if !defined(IN_R0) || defined(LOG_ENABLED)
3763 int rc = VINF_SUCCESS;
3764 unsigned i;
3765 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3766 {
3767 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3768# ifdef IN_RING0
3769 if (rc == VERR_ALREADY_EXISTS)
3770 {
3771 /* in case of cleanup failure in ring-0 */
3772 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3773 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3774 }
3775# endif
3776 }
3777 if (RT_FAILURE(rc))
3778 while (i-- > 0)
3779 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3780
3781 return rc;
3782#else
3783 return VINF_SUCCESS;
3784#endif
3785}
3786
3787
3788/**
3789 * Deregisters the global string format types.
3790 *
3791 * This should be called at module unload time or in some other manner that
3792 * ensure that it's called exactly one time.
3793 */
3794VMMDECL(void) PGMDeregisterStringFormatTypes(void)
3795{
3796#if !defined(IN_R0) || defined(LOG_ENABLED)
3797 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3798 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3799#endif
3800}
3801
3802#ifdef VBOX_STRICT
3803
3804/**
3805 * Asserts that there are no mapping conflicts.
3806 *
3807 * @returns Number of conflicts.
3808 * @param pVM The cross context VM structure.
3809 */
3810VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
3811{
3812 unsigned cErrors = 0;
3813
3814 /* Only applies to raw mode -> 1 VPCU */
3815 Assert(pVM->cCpus == 1);
3816 PVMCPU pVCpu = &pVM->aCpus[0];
3817
3818 /*
3819 * Check for mapping conflicts.
3820 */
3821 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3822 pMapping;
3823 pMapping = pMapping->CTX_SUFF(pNext))
3824 {
3825 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
3826 for (RTGCPTR GCPtr = pMapping->GCPtr;
3827 GCPtr <= pMapping->GCPtrLast;
3828 GCPtr += PAGE_SIZE)
3829 {
3830 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
3831 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
3832 {
3833 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
3834 cErrors++;
3835 break;
3836 }
3837 }
3838 }
3839
3840 return cErrors;
3841}
3842
3843
3844/**
3845 * Asserts that everything related to the guest CR3 is correctly shadowed.
3846 *
3847 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
3848 * and assert the correctness of the guest CR3 mapping before asserting that the
3849 * shadow page tables is in sync with the guest page tables.
3850 *
3851 * @returns Number of conflicts.
3852 * @param pVM The cross context VM structure.
3853 * @param pVCpu The cross context virtual CPU structure.
3854 * @param cr3 The current guest CR3 register value.
3855 * @param cr4 The current guest CR4 register value.
3856 */
3857VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
3858{
3859 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3860
3861 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
3862 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
3863 AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
3864
3865 pgmLock(pVM);
3866 unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
3867 pgmUnlock(pVM);
3868
3869 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3870 return cErrors;
3871}
3872
3873#endif /* VBOX_STRICT */
3874
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