VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 73253

Last change on this file since 73253 was 73253, checked in by vboxsync, 7 years ago

PGM,HM: Added todos about cleaning up the nested packing hacks. (bugref:9044)
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  • Property svn:keywords set to Id Revision
File size: 120.4 KB
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1/* $Id: PGMAll.cpp 73253 2018-07-19 20:01:45Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/selm.h>
26#include <VBox/vmm/iem.h>
27#include <VBox/vmm/iom.h>
28#include <VBox/sup.h>
29#include <VBox/vmm/mm.h>
30#include <VBox/vmm/stam.h>
31#include <VBox/vmm/csam.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/trpm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/em.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include "PGMInternal.h"
41#include <VBox/vmm/vm.h>
42#include "PGMInline.h"
43#include <iprt/assert.h>
44#include <iprt/asm-amd64-x86.h>
45#include <iprt/string.h>
46#include <VBox/log.h>
47#include <VBox/param.h>
48#include <VBox/err.h>
49
50
51/*********************************************************************************************************************************
52* Structures and Typedefs *
53*********************************************************************************************************************************/
54/**
55 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
56 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
57 */
58typedef struct PGMHVUSTATE
59{
60 /** Pointer to the VM. */
61 PVM pVM;
62 /** Pointer to the VMCPU. */
63 PVMCPU pVCpu;
64 /** The todo flags. */
65 RTUINT fTodo;
66 /** The CR4 register value. */
67 uint32_t cr4;
68} PGMHVUSTATE, *PPGMHVUSTATE;
69
70
71/*********************************************************************************************************************************
72* Internal Functions *
73*********************************************************************************************************************************/
74DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
75DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
76#ifndef IN_RC
77static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
78static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
79#endif
80
81
82/*
83 * Shadow - 32-bit mode
84 */
85#define PGM_SHW_TYPE PGM_TYPE_32BIT
86#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
87#include "PGMAllShw.h"
88
89/* Guest - real mode */
90#define PGM_GST_TYPE PGM_TYPE_REAL
91#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
92#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
93#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
94#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
95#include "PGMGstDefs.h"
96#include "PGMAllGst.h"
97#include "PGMAllBth.h"
98#undef BTH_PGMPOOLKIND_PT_FOR_PT
99#undef BTH_PGMPOOLKIND_ROOT
100#undef PGM_BTH_NAME
101#undef PGM_GST_TYPE
102#undef PGM_GST_NAME
103
104/* Guest - protected mode */
105#define PGM_GST_TYPE PGM_TYPE_PROT
106#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
107#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
108#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
109#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
110#include "PGMGstDefs.h"
111#include "PGMAllGst.h"
112#include "PGMAllBth.h"
113#undef BTH_PGMPOOLKIND_PT_FOR_PT
114#undef BTH_PGMPOOLKIND_ROOT
115#undef PGM_BTH_NAME
116#undef PGM_GST_TYPE
117#undef PGM_GST_NAME
118
119/* Guest - 32-bit mode */
120#define PGM_GST_TYPE PGM_TYPE_32BIT
121#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
122#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
123#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
124#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
125#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
126#include "PGMGstDefs.h"
127#include "PGMAllGst.h"
128#include "PGMAllBth.h"
129#undef BTH_PGMPOOLKIND_PT_FOR_BIG
130#undef BTH_PGMPOOLKIND_PT_FOR_PT
131#undef BTH_PGMPOOLKIND_ROOT
132#undef PGM_BTH_NAME
133#undef PGM_GST_TYPE
134#undef PGM_GST_NAME
135
136#undef PGM_SHW_TYPE
137#undef PGM_SHW_NAME
138
139
140/*
141 * Shadow - PAE mode
142 */
143#define PGM_SHW_TYPE PGM_TYPE_PAE
144#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
145#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146#include "PGMAllShw.h"
147
148/* Guest - real mode */
149#define PGM_GST_TYPE PGM_TYPE_REAL
150#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
151#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
152#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
153#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
154#include "PGMGstDefs.h"
155#include "PGMAllBth.h"
156#undef BTH_PGMPOOLKIND_PT_FOR_PT
157#undef BTH_PGMPOOLKIND_ROOT
158#undef PGM_BTH_NAME
159#undef PGM_GST_TYPE
160#undef PGM_GST_NAME
161
162/* Guest - protected mode */
163#define PGM_GST_TYPE PGM_TYPE_PROT
164#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
165#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
166#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
167#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
168#include "PGMGstDefs.h"
169#include "PGMAllBth.h"
170#undef BTH_PGMPOOLKIND_PT_FOR_PT
171#undef BTH_PGMPOOLKIND_ROOT
172#undef PGM_BTH_NAME
173#undef PGM_GST_TYPE
174#undef PGM_GST_NAME
175
176/* Guest - 32-bit mode */
177#define PGM_GST_TYPE PGM_TYPE_32BIT
178#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
179#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
180#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
181#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
182#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
183#include "PGMGstDefs.h"
184#include "PGMAllBth.h"
185#undef BTH_PGMPOOLKIND_PT_FOR_BIG
186#undef BTH_PGMPOOLKIND_PT_FOR_PT
187#undef BTH_PGMPOOLKIND_ROOT
188#undef PGM_BTH_NAME
189#undef PGM_GST_TYPE
190#undef PGM_GST_NAME
191
192
193/* Guest - PAE mode */
194#define PGM_GST_TYPE PGM_TYPE_PAE
195#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
196#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
197#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
198#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
199#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
200#include "PGMGstDefs.h"
201#include "PGMAllGst.h"
202#include "PGMAllBth.h"
203#undef BTH_PGMPOOLKIND_PT_FOR_BIG
204#undef BTH_PGMPOOLKIND_PT_FOR_PT
205#undef BTH_PGMPOOLKIND_ROOT
206#undef PGM_BTH_NAME
207#undef PGM_GST_TYPE
208#undef PGM_GST_NAME
209
210#undef PGM_SHW_TYPE
211#undef PGM_SHW_NAME
212
213
214#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
215/*
216 * Shadow - AMD64 mode
217 */
218# define PGM_SHW_TYPE PGM_TYPE_AMD64
219# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
220# include "PGMAllShw.h"
221
222/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
223/** @todo retire this hack. */
224# define PGM_GST_TYPE PGM_TYPE_PROT
225# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
226# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
227# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
228# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
229# include "PGMGstDefs.h"
230# include "PGMAllBth.h"
231# undef BTH_PGMPOOLKIND_PT_FOR_PT
232# undef BTH_PGMPOOLKIND_ROOT
233# undef PGM_BTH_NAME
234# undef PGM_GST_TYPE
235# undef PGM_GST_NAME
236
237# ifdef VBOX_WITH_64_BITS_GUESTS
238/* Guest - AMD64 mode */
239# define PGM_GST_TYPE PGM_TYPE_AMD64
240# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
241# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
242# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
243# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
244# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
245# include "PGMGstDefs.h"
246# include "PGMAllGst.h"
247# include "PGMAllBth.h"
248# undef BTH_PGMPOOLKIND_PT_FOR_BIG
249# undef BTH_PGMPOOLKIND_PT_FOR_PT
250# undef BTH_PGMPOOLKIND_ROOT
251# undef PGM_BTH_NAME
252# undef PGM_GST_TYPE
253# undef PGM_GST_NAME
254# endif /* VBOX_WITH_64_BITS_GUESTS */
255
256# undef PGM_SHW_TYPE
257# undef PGM_SHW_NAME
258
259
260/*
261 * Shadow - 32-bit nested paging mode.
262 */
263# define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
264# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
265# include "PGMAllShw.h"
266
267/* Guest - real mode */
268# define PGM_GST_TYPE PGM_TYPE_REAL
269# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
270# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
271# include "PGMGstDefs.h"
272# include "PGMAllBth.h"
273# undef PGM_BTH_NAME
274# undef PGM_GST_TYPE
275# undef PGM_GST_NAME
276
277/* Guest - protected mode */
278# define PGM_GST_TYPE PGM_TYPE_PROT
279# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
280# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
281# include "PGMGstDefs.h"
282# include "PGMAllBth.h"
283# undef PGM_BTH_NAME
284# undef PGM_GST_TYPE
285# undef PGM_GST_NAME
286
287/* Guest - 32-bit mode */
288# define PGM_GST_TYPE PGM_TYPE_32BIT
289# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
290# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
291# include "PGMGstDefs.h"
292# include "PGMAllBth.h"
293# undef PGM_BTH_NAME
294# undef PGM_GST_TYPE
295# undef PGM_GST_NAME
296
297/* Guest - PAE mode */
298# define PGM_GST_TYPE PGM_TYPE_PAE
299# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
300# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
301# include "PGMGstDefs.h"
302# include "PGMAllBth.h"
303# undef PGM_BTH_NAME
304# undef PGM_GST_TYPE
305# undef PGM_GST_NAME
306
307# ifdef VBOX_WITH_64_BITS_GUESTS
308/* Guest - AMD64 mode */
309# define PGM_GST_TYPE PGM_TYPE_AMD64
310# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
311# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
312# include "PGMGstDefs.h"
313# include "PGMAllBth.h"
314# undef PGM_BTH_NAME
315# undef PGM_GST_TYPE
316# undef PGM_GST_NAME
317# endif /* VBOX_WITH_64_BITS_GUESTS */
318
319# undef PGM_SHW_TYPE
320# undef PGM_SHW_NAME
321
322
323/*
324 * Shadow - PAE nested paging mode.
325 */
326# define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
327# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
328# include "PGMAllShw.h"
329
330/* Guest - real mode */
331# define PGM_GST_TYPE PGM_TYPE_REAL
332# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
333# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
334# include "PGMGstDefs.h"
335# include "PGMAllBth.h"
336# undef PGM_BTH_NAME
337# undef PGM_GST_TYPE
338# undef PGM_GST_NAME
339
340/* Guest - protected mode */
341# define PGM_GST_TYPE PGM_TYPE_PROT
342# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
343# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef PGM_BTH_NAME
347# undef PGM_GST_TYPE
348# undef PGM_GST_NAME
349
350/* Guest - 32-bit mode */
351# define PGM_GST_TYPE PGM_TYPE_32BIT
352# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
353# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
354# include "PGMGstDefs.h"
355# include "PGMAllBth.h"
356# undef PGM_BTH_NAME
357# undef PGM_GST_TYPE
358# undef PGM_GST_NAME
359
360/* Guest - PAE mode */
361# define PGM_GST_TYPE PGM_TYPE_PAE
362# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
363# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
364# include "PGMGstDefs.h"
365# include "PGMAllBth.h"
366# undef PGM_BTH_NAME
367# undef PGM_GST_TYPE
368# undef PGM_GST_NAME
369
370# ifdef VBOX_WITH_64_BITS_GUESTS
371/* Guest - AMD64 mode */
372# define PGM_GST_TYPE PGM_TYPE_AMD64
373# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
374# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
375# include "PGMGstDefs.h"
376# include "PGMAllBth.h"
377# undef PGM_BTH_NAME
378# undef PGM_GST_TYPE
379# undef PGM_GST_NAME
380# endif /* VBOX_WITH_64_BITS_GUESTS */
381
382# undef PGM_SHW_TYPE
383# undef PGM_SHW_NAME
384
385
386/*
387 * Shadow - AMD64 nested paging mode.
388 */
389# define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
390# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
391# include "PGMAllShw.h"
392
393/* Guest - real mode */
394# define PGM_GST_TYPE PGM_TYPE_REAL
395# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
396# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
397# include "PGMGstDefs.h"
398# include "PGMAllBth.h"
399# undef PGM_BTH_NAME
400# undef PGM_GST_TYPE
401# undef PGM_GST_NAME
402
403/* Guest - protected mode */
404# define PGM_GST_TYPE PGM_TYPE_PROT
405# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
406# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
407# include "PGMGstDefs.h"
408# include "PGMAllBth.h"
409# undef PGM_BTH_NAME
410# undef PGM_GST_TYPE
411# undef PGM_GST_NAME
412
413/* Guest - 32-bit mode */
414# define PGM_GST_TYPE PGM_TYPE_32BIT
415# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
416# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
417# include "PGMGstDefs.h"
418# include "PGMAllBth.h"
419# undef PGM_BTH_NAME
420# undef PGM_GST_TYPE
421# undef PGM_GST_NAME
422
423/* Guest - PAE mode */
424# define PGM_GST_TYPE PGM_TYPE_PAE
425# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
426# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
427# include "PGMGstDefs.h"
428# include "PGMAllBth.h"
429# undef PGM_BTH_NAME
430# undef PGM_GST_TYPE
431# undef PGM_GST_NAME
432
433# ifdef VBOX_WITH_64_BITS_GUESTS
434/* Guest - AMD64 mode */
435# define PGM_GST_TYPE PGM_TYPE_AMD64
436# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
437# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
438# include "PGMGstDefs.h"
439# include "PGMAllBth.h"
440# undef PGM_BTH_NAME
441# undef PGM_GST_TYPE
442# undef PGM_GST_NAME
443# endif /* VBOX_WITH_64_BITS_GUESTS */
444
445# undef PGM_SHW_TYPE
446# undef PGM_SHW_NAME
447
448
449/*
450 * Shadow - EPT.
451 */
452# define PGM_SHW_TYPE PGM_TYPE_EPT
453# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
454# include "PGMAllShw.h"
455
456/* Guest - real mode */
457# define PGM_GST_TYPE PGM_TYPE_REAL
458# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
459# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
460# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
461# include "PGMGstDefs.h"
462# include "PGMAllBth.h"
463# undef BTH_PGMPOOLKIND_PT_FOR_PT
464# undef PGM_BTH_NAME
465# undef PGM_GST_TYPE
466# undef PGM_GST_NAME
467
468/* Guest - protected mode */
469# define PGM_GST_TYPE PGM_TYPE_PROT
470# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
471# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
472# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
473# include "PGMGstDefs.h"
474# include "PGMAllBth.h"
475# undef BTH_PGMPOOLKIND_PT_FOR_PT
476# undef PGM_BTH_NAME
477# undef PGM_GST_TYPE
478# undef PGM_GST_NAME
479
480/* Guest - 32-bit mode */
481# define PGM_GST_TYPE PGM_TYPE_32BIT
482# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
483# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
484# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
485# include "PGMGstDefs.h"
486# include "PGMAllBth.h"
487# undef BTH_PGMPOOLKIND_PT_FOR_PT
488# undef PGM_BTH_NAME
489# undef PGM_GST_TYPE
490# undef PGM_GST_NAME
491
492/* Guest - PAE mode */
493# define PGM_GST_TYPE PGM_TYPE_PAE
494# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
495# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
496# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
497# include "PGMGstDefs.h"
498# include "PGMAllBth.h"
499# undef BTH_PGMPOOLKIND_PT_FOR_PT
500# undef PGM_BTH_NAME
501# undef PGM_GST_TYPE
502# undef PGM_GST_NAME
503
504# ifdef VBOX_WITH_64_BITS_GUESTS
505/* Guest - AMD64 mode */
506# define PGM_GST_TYPE PGM_TYPE_AMD64
507# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
508# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
509# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
510# include "PGMGstDefs.h"
511# include "PGMAllBth.h"
512# undef BTH_PGMPOOLKIND_PT_FOR_PT
513# undef PGM_BTH_NAME
514# undef PGM_GST_TYPE
515# undef PGM_GST_NAME
516# endif /* VBOX_WITH_64_BITS_GUESTS */
517
518# undef PGM_SHW_TYPE
519# undef PGM_SHW_NAME
520
521#endif /* !IN_RC */
522
523
524/**
525 * Guest mode data array.
526 */
527PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
528{
529 { UINT32_MAX, NULL, NULL, NULL, NULL, NULL }, /* 0 */
530 {
531 PGM_TYPE_REAL,
532 PGM_GST_NAME_REAL(GetPage),
533 PGM_GST_NAME_REAL(ModifyPage),
534 PGM_GST_NAME_REAL(GetPDE),
535#ifdef IN_RING3
536 PGM_GST_NAME_REAL(Enter),
537 PGM_GST_NAME_REAL(Exit),
538 PGM_GST_NAME_REAL(Relocate),
539#else
540 NULL, NULL, NULL,
541#endif
542 },
543 {
544 PGM_TYPE_PROT,
545 PGM_GST_NAME_PROT(GetPage),
546 PGM_GST_NAME_PROT(ModifyPage),
547 PGM_GST_NAME_PROT(GetPDE),
548#ifdef IN_RING3
549 PGM_GST_NAME_PROT(Enter),
550 PGM_GST_NAME_PROT(Exit),
551 PGM_GST_NAME_PROT(Relocate),
552#else
553 NULL, NULL, NULL,
554#endif
555 },
556 {
557 PGM_TYPE_32BIT,
558 PGM_GST_NAME_32BIT(GetPage),
559 PGM_GST_NAME_32BIT(ModifyPage),
560 PGM_GST_NAME_32BIT(GetPDE),
561#ifdef IN_RING3
562 PGM_GST_NAME_32BIT(Enter),
563 PGM_GST_NAME_32BIT(Exit),
564 PGM_GST_NAME_32BIT(Relocate),
565#else
566 NULL, NULL, NULL,
567#endif
568 },
569 {
570 PGM_TYPE_PAE,
571 PGM_GST_NAME_PAE(GetPage),
572 PGM_GST_NAME_PAE(ModifyPage),
573 PGM_GST_NAME_PAE(GetPDE),
574#ifdef IN_RING3
575 PGM_GST_NAME_PAE(Enter),
576 PGM_GST_NAME_PAE(Exit),
577 PGM_GST_NAME_PAE(Relocate),
578#else
579 NULL, NULL, NULL,
580#endif
581 },
582#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
583 {
584 PGM_TYPE_AMD64,
585 PGM_GST_NAME_AMD64(GetPage),
586 PGM_GST_NAME_AMD64(ModifyPage),
587 PGM_GST_NAME_AMD64(GetPDE),
588# ifdef IN_RING3
589 PGM_GST_NAME_AMD64(Enter),
590 PGM_GST_NAME_AMD64(Exit),
591 PGM_GST_NAME_AMD64(Relocate),
592# else
593 NULL, NULL, NULL,
594# endif
595 },
596#endif
597};
598
599
600/**
601 * The shadow mode data array.
602 */
603PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
604{
605 { UINT8_MAX, NULL, NULL, NULL, NULL, NULL }, /* 0 */
606 { UINT8_MAX, NULL, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
607 { UINT8_MAX, NULL, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
608 {
609 PGM_TYPE_32BIT,
610 PGM_SHW_NAME_32BIT(GetPage),
611 PGM_SHW_NAME_32BIT(ModifyPage),
612#ifdef IN_RING3
613 PGM_SHW_NAME_32BIT(Enter),
614 PGM_SHW_NAME_32BIT(Exit),
615 PGM_SHW_NAME_32BIT(Relocate),
616#else
617 NULL, NULL, NULL,
618#endif
619 },
620 {
621 PGM_TYPE_PAE,
622 PGM_SHW_NAME_PAE(GetPage),
623 PGM_SHW_NAME_PAE(ModifyPage),
624#ifdef IN_RING3
625 PGM_SHW_NAME_PAE(Enter),
626 PGM_SHW_NAME_PAE(Exit),
627 PGM_SHW_NAME_PAE(Relocate),
628#else
629 NULL, NULL, NULL,
630#endif
631 },
632#ifndef IN_RC
633 {
634 PGM_TYPE_AMD64,
635 PGM_SHW_NAME_AMD64(GetPage),
636 PGM_SHW_NAME_AMD64(ModifyPage),
637# ifdef IN_RING3
638 PGM_SHW_NAME_AMD64(Enter),
639 PGM_SHW_NAME_AMD64(Exit),
640 PGM_SHW_NAME_AMD64(Relocate),
641# else
642 NULL, NULL, NULL,
643# endif
644 },
645 {
646 PGM_TYPE_NESTED_32BIT,
647 PGM_SHW_NAME_NESTED_32BIT(GetPage),
648 PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
649# ifdef IN_RING3
650 PGM_SHW_NAME_NESTED_32BIT(Enter),
651 PGM_SHW_NAME_NESTED_32BIT(Exit),
652 PGM_SHW_NAME_NESTED_32BIT(Relocate),
653# else
654 NULL, NULL, NULL,
655# endif
656 },
657 {
658 PGM_TYPE_NESTED_PAE,
659 PGM_SHW_NAME_NESTED_PAE(GetPage),
660 PGM_SHW_NAME_NESTED_PAE(ModifyPage),
661# ifdef IN_RING3
662 PGM_SHW_NAME_NESTED_PAE(Enter),
663 PGM_SHW_NAME_NESTED_PAE(Exit),
664 PGM_SHW_NAME_NESTED_PAE(Relocate),
665# else
666 NULL, NULL, NULL,
667# endif
668 },
669 {
670 PGM_TYPE_NESTED_AMD64,
671 PGM_SHW_NAME_NESTED_AMD64(GetPage),
672 PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
673# ifdef IN_RING3
674 PGM_SHW_NAME_NESTED_AMD64(Enter),
675 PGM_SHW_NAME_NESTED_AMD64(Exit),
676 PGM_SHW_NAME_NESTED_AMD64(Relocate),
677# else
678 NULL, NULL, NULL,
679# endif
680 },
681 {
682 PGM_TYPE_EPT,
683 PGM_SHW_NAME_EPT(GetPage),
684 PGM_SHW_NAME_EPT(ModifyPage),
685# ifdef IN_RING3
686 PGM_SHW_NAME_EPT(Enter),
687 PGM_SHW_NAME_EPT(Exit),
688 PGM_SHW_NAME_EPT(Relocate),
689# else
690 NULL, NULL, NULL,
691# endif
692 },
693#endif /* IN_RC */
694};
695
696
697/**
698 * The guest+shadow mode data array.
699 */
700PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
701{
702#if !defined(IN_RING3) && !defined(VBOX_STRICT)
703# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
704# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
705 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), /*Nm(Enter)*/ NULL, Nm(Trap0eHandler) }
706
707#elif !defined(IN_RING3) && defined(VBOX_STRICT)
708# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
709# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
710 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), /*Nm(Enter)*/ NULL, Nm(Trap0eHandler), Nm(AssertCR3) }
711
712#elif defined(IN_RING3) && !defined(VBOX_STRICT)
713# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
714# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
715 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Relocate), }
716
717#elif defined(IN_RING3) && defined(VBOX_STRICT)
718# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
719# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
720 { uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Relocate), Nm(AssertCR3) }
721
722#else
723# error "Misconfig."
724#endif
725
726 /* 32-bit shadow paging mode: */
727 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
728 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
729 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
730 PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
731 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
732 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
733 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
734 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
735 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
736 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
737
738 /* PAE shadow paging mode: */
739 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
740 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
741 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
742 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
743 PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
744 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
745 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
746 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
747 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
748 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
749
750#ifndef IN_RC
751 /* AMD64 shadow paging mode: */
752 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
753 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
754 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
755 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
756 PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
757# ifdef VBOX_WITH_64_BITS_GUESTS
758 PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
759# else
760 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
761# endif
762 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
763 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
764 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
765 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
766
767 /* 32-bit nested paging mode: */
768 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
769 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
770 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
771 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
772 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
773# ifdef VBOX_WITH_64_BITS_GUESTS
774 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
775# else
776 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
777# endif
778 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
779 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
780 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
781 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
782
783 /* PAE nested paging mode: */
784 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
785 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
786 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
787 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
788 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
789# ifdef VBOX_WITH_64_BITS_GUESTS
790 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
791# else
792 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
793# endif
794 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
795 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
796 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
797 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
798
799 /* AMD64 nested paging mode: */
800 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
801 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
802 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
803 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
804 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
805# ifdef VBOX_WITH_64_BITS_GUESTS
806 PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
807# else
808 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
809# endif
810 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
811 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
812 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
813 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
814
815 /* EPT nested paging mode: */
816 PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
817 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
818 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
819 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
820 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
821# ifdef VBOX_WITH_64_BITS_GUESTS
822 PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
823# else
824 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
825# endif
826 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
827 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
828 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
829 PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
830
831#endif /* IN_RC */
832
833#undef PGMMODEDATABTH_ENTRY
834#undef PGMMODEDATABTH_NULL_ENTRY
835};
836
837
838#ifndef IN_RING3
839/**
840 * #PF Handler.
841 *
842 * @returns VBox status code (appropriate for trap handling and GC return).
843 * @param pVCpu The cross context virtual CPU structure.
844 * @param uErr The trap error code.
845 * @param pRegFrame Trap register frame.
846 * @param pvFault The fault address.
847 */
848VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
849{
850 PVM pVM = pVCpu->CTX_SUFF(pVM);
851
852 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
853 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
854 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
855
856
857#ifdef VBOX_WITH_STATISTICS
858 /*
859 * Error code stats.
860 */
861 if (uErr & X86_TRAP_PF_US)
862 {
863 if (!(uErr & X86_TRAP_PF_P))
864 {
865 if (uErr & X86_TRAP_PF_RW)
866 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
867 else
868 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
869 }
870 else if (uErr & X86_TRAP_PF_RW)
871 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
872 else if (uErr & X86_TRAP_PF_RSVD)
873 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
874 else if (uErr & X86_TRAP_PF_ID)
875 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
876 else
877 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
878 }
879 else
880 { /* Supervisor */
881 if (!(uErr & X86_TRAP_PF_P))
882 {
883 if (uErr & X86_TRAP_PF_RW)
884 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
885 else
886 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
887 }
888 else if (uErr & X86_TRAP_PF_RW)
889 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
890 else if (uErr & X86_TRAP_PF_ID)
891 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
892 else if (uErr & X86_TRAP_PF_RSVD)
893 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
894 }
895#endif /* VBOX_WITH_STATISTICS */
896
897 /*
898 * Call the worker.
899 */
900 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
901 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
902 AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
903 bool fLockTaken = false;
904 int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
905 if (fLockTaken)
906 {
907 PGM_LOCK_ASSERT_OWNER(pVM);
908 pgmUnlock(pVM);
909 }
910 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
911
912 /*
913 * Return code tweaks.
914 */
915 if (rc != VINF_SUCCESS)
916 {
917 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
918 rc = VINF_SUCCESS;
919
920# ifdef IN_RING0
921 /* Note: hack alert for difficult to reproduce problem. */
922 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
923 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
924 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
925 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
926 {
927 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
928 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
929 rc = VINF_SUCCESS;
930 }
931# endif
932 }
933
934 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
935 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
936 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
937 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
938 return rc;
939}
940#endif /* !IN_RING3 */
941
942
943/**
944 * Prefetch a page
945 *
946 * Typically used to sync commonly used pages before entering raw mode
947 * after a CR3 reload.
948 *
949 * @returns VBox status code suitable for scheduling.
950 * @retval VINF_SUCCESS on success.
951 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
952 * @param pVCpu The cross context virtual CPU structure.
953 * @param GCPtrPage Page to invalidate.
954 */
955VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
956{
957 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
958
959 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
960 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
961 AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
962 int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
963
964 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
965 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
966 return rc;
967}
968
969
970/**
971 * Gets the mapping corresponding to the specified address (if any).
972 *
973 * @returns Pointer to the mapping.
974 * @returns NULL if not
975 *
976 * @param pVM The cross context VM structure.
977 * @param GCPtr The guest context pointer.
978 */
979PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
980{
981 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
982 while (pMapping)
983 {
984 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
985 break;
986 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
987 return pMapping;
988 pMapping = pMapping->CTX_SUFF(pNext);
989 }
990 return NULL;
991}
992
993
994/**
995 * Verifies a range of pages for read or write access
996 *
997 * Only checks the guest's page tables
998 *
999 * @returns VBox status code.
1000 * @param pVCpu The cross context virtual CPU structure.
1001 * @param Addr Guest virtual address to check
1002 * @param cbSize Access size
1003 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
1004 * @remarks Current not in use.
1005 */
1006VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
1007{
1008 /*
1009 * Validate input.
1010 */
1011 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
1012 {
1013 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
1014 return VERR_INVALID_PARAMETER;
1015 }
1016
1017 uint64_t fPage;
1018 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
1019 if (RT_FAILURE(rc))
1020 {
1021 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
1022 return VINF_EM_RAW_GUEST_TRAP;
1023 }
1024
1025 /*
1026 * Check if the access would cause a page fault
1027 *
1028 * Note that hypervisor page directories are not present in the guest's tables, so this check
1029 * is sufficient.
1030 */
1031 bool fWrite = !!(fAccess & X86_PTE_RW);
1032 bool fUser = !!(fAccess & X86_PTE_US);
1033 if ( !(fPage & X86_PTE_P)
1034 || (fWrite && !(fPage & X86_PTE_RW))
1035 || (fUser && !(fPage & X86_PTE_US)) )
1036 {
1037 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
1038 return VINF_EM_RAW_GUEST_TRAP;
1039 }
1040 if ( RT_SUCCESS(rc)
1041 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
1042 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
1043 return rc;
1044}
1045
1046
1047/**
1048 * Verifies a range of pages for read or write access
1049 *
1050 * Supports handling of pages marked for dirty bit tracking and CSAM
1051 *
1052 * @returns VBox status code.
1053 * @param pVCpu The cross context virtual CPU structure.
1054 * @param Addr Guest virtual address to check
1055 * @param cbSize Access size
1056 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
1057 */
1058VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
1059{
1060 PVM pVM = pVCpu->CTX_SUFF(pVM);
1061
1062 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
1063
1064 /*
1065 * Get going.
1066 */
1067 uint64_t fPageGst;
1068 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
1069 if (RT_FAILURE(rc))
1070 {
1071 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
1072 return VINF_EM_RAW_GUEST_TRAP;
1073 }
1074
1075 /*
1076 * Check if the access would cause a page fault
1077 *
1078 * Note that hypervisor page directories are not present in the guest's tables, so this check
1079 * is sufficient.
1080 */
1081 const bool fWrite = !!(fAccess & X86_PTE_RW);
1082 const bool fUser = !!(fAccess & X86_PTE_US);
1083 if ( !(fPageGst & X86_PTE_P)
1084 || (fWrite && !(fPageGst & X86_PTE_RW))
1085 || (fUser && !(fPageGst & X86_PTE_US)) )
1086 {
1087 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
1088 return VINF_EM_RAW_GUEST_TRAP;
1089 }
1090
1091 if (!pVM->pgm.s.fNestedPaging)
1092 {
1093 /*
1094 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
1095 */
1096 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
1097 if ( rc == VERR_PAGE_NOT_PRESENT
1098 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
1099 {
1100 /*
1101 * Page is not present in our page tables.
1102 * Try to sync it!
1103 */
1104 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
1105 uint32_t const uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
1106 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1107 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1108 AssertReturn(g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
1109 rc = g_aPgmBothModeData[idxBth].pfnVerifyAccessSyncPage(pVCpu, Addr, fPageGst, uErr);
1110 if (rc != VINF_SUCCESS)
1111 return rc;
1112 }
1113 else
1114 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
1115 }
1116
1117#if 0 /* def VBOX_STRICT; triggers too often now */
1118 /*
1119 * This check is a bit paranoid, but useful.
1120 */
1121 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
1122 uint64_t fPageShw;
1123 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
1124 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
1125 || (fWrite && !(fPageShw & X86_PTE_RW))
1126 || (fUser && !(fPageShw & X86_PTE_US)) )
1127 {
1128 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
1129 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
1130 return VINF_EM_RAW_GUEST_TRAP;
1131 }
1132#endif
1133
1134 if ( RT_SUCCESS(rc)
1135 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
1136 || Addr + cbSize < Addr))
1137 {
1138 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
1139 for (;;)
1140 {
1141 Addr += PAGE_SIZE;
1142 if (cbSize > PAGE_SIZE)
1143 cbSize -= PAGE_SIZE;
1144 else
1145 cbSize = 1;
1146 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
1147 if (rc != VINF_SUCCESS)
1148 break;
1149 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
1150 break;
1151 }
1152 }
1153 return rc;
1154}
1155
1156
1157/**
1158 * Emulation of the invlpg instruction (HC only actually).
1159 *
1160 * @returns Strict VBox status code, special care required.
1161 * @retval VINF_PGM_SYNC_CR3 - handled.
1162 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1163 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
1164 *
1165 * @param pVCpu The cross context virtual CPU structure.
1166 * @param GCPtrPage Page to invalidate.
1167 *
1168 * @remark ASSUMES the page table entry or page directory is valid. Fairly
1169 * safe, but there could be edge cases!
1170 *
1171 * @todo Flush page or page directory only if necessary!
1172 * @todo VBOXSTRICTRC
1173 */
1174VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1175{
1176 PVM pVM = pVCpu->CTX_SUFF(pVM);
1177 int rc;
1178 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1179
1180#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
1181 /*
1182 * Notify the recompiler so it can record this instruction.
1183 */
1184 REMNotifyInvalidatePage(pVM, GCPtrPage);
1185#endif /* !IN_RING3 */
1186 IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1187
1188
1189#ifdef IN_RC
1190 /*
1191 * Check for conflicts and pending CR3 monitoring updates.
1192 */
1193 if (pgmMapAreMappingsFloating(pVM))
1194 {
1195 if ( pgmGetMapping(pVM, GCPtrPage)
1196 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
1197 {
1198 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
1199 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1200 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
1201 return VINF_PGM_SYNC_CR3;
1202 }
1203
1204 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1205 {
1206 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
1207 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
1208 return VINF_EM_RAW_EMULATE_INSTR;
1209 }
1210 }
1211#endif /* IN_RC */
1212
1213 /*
1214 * Call paging mode specific worker.
1215 */
1216 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1217 pgmLock(pVM);
1218
1219 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1220 AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1221 AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, pgmUnlock(pVM), VERR_PGM_MODE_IPE);
1222 rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1223
1224 pgmUnlock(pVM);
1225 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
1226
1227#ifdef IN_RING3
1228 /*
1229 * Check if we have a pending update of the CR3 monitoring.
1230 */
1231 if ( RT_SUCCESS(rc)
1232 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
1233 {
1234 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1235 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
1236 }
1237
1238# ifdef VBOX_WITH_RAW_MODE
1239 /*
1240 * Inform CSAM about the flush
1241 *
1242 * Note: This is to check if monitored pages have been changed; when we implement
1243 * callbacks for virtual handlers, this is no longer required.
1244 */
1245 CSAMR3FlushPage(pVM, GCPtrPage);
1246# endif
1247#endif /* IN_RING3 */
1248
1249 /* Ignore all irrelevant error codes. */
1250 if ( rc == VERR_PAGE_NOT_PRESENT
1251 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1252 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1253 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1254 rc = VINF_SUCCESS;
1255
1256 return rc;
1257}
1258
1259
1260/**
1261 * Executes an instruction using the interpreter.
1262 *
1263 * @returns VBox status code (appropriate for trap handling and GC return).
1264 * @param pVM The cross context VM structure.
1265 * @param pVCpu The cross context virtual CPU structure.
1266 * @param pRegFrame Register frame.
1267 * @param pvFault Fault address.
1268 */
1269VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1270{
1271 NOREF(pVM);
1272 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
1273 if (rc == VERR_EM_INTERPRETER)
1274 rc = VINF_EM_RAW_EMULATE_INSTR;
1275 if (rc != VINF_SUCCESS)
1276 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1277 return rc;
1278}
1279
1280
1281/**
1282 * Gets effective page information (from the VMM page directory).
1283 *
1284 * @returns VBox status code.
1285 * @param pVCpu The cross context virtual CPU structure.
1286 * @param GCPtr Guest Context virtual address of the page.
1287 * @param pfFlags Where to store the flags. These are X86_PTE_*.
1288 * @param pHCPhys Where to store the HC physical address of the page.
1289 * This is page aligned.
1290 * @remark You should use PGMMapGetPage() for pages in a mapping.
1291 */
1292VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1293{
1294 PVM pVM = pVCpu->CTX_SUFF(pVM);
1295 pgmLock(pVM);
1296
1297 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1298 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1299 AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1300 int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1301
1302 pgmUnlock(pVM);
1303 return rc;
1304}
1305
1306
1307/**
1308 * Modify page flags for a range of pages in the shadow context.
1309 *
1310 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1311 *
1312 * @returns VBox status code.
1313 * @param pVCpu The cross context virtual CPU structure.
1314 * @param GCPtr Virtual address of the first page in the range.
1315 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1316 * @param fMask The AND mask - page flags X86_PTE_*.
1317 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1318 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1319 * @remark You must use PGMMapModifyPage() for pages in a mapping.
1320 */
1321DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1322{
1323 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1324 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
1325
1326 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
1327
1328 PVM pVM = pVCpu->CTX_SUFF(pVM);
1329 pgmLock(pVM);
1330
1331 uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1332 AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1333 AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1334 int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
1335
1336 pgmUnlock(pVM);
1337 return rc;
1338}
1339
1340
1341/**
1342 * Changing the page flags for a single page in the shadow page tables so as to
1343 * make it read-only.
1344 *
1345 * @returns VBox status code.
1346 * @param pVCpu The cross context virtual CPU structure.
1347 * @param GCPtr Virtual address of the first page in the range.
1348 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1349 */
1350VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1351{
1352 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1353}
1354
1355
1356/**
1357 * Changing the page flags for a single page in the shadow page tables so as to
1358 * make it writable.
1359 *
1360 * The call must know with 101% certainty that the guest page tables maps this
1361 * as writable too. This function will deal shared, zero and write monitored
1362 * pages.
1363 *
1364 * @returns VBox status code.
1365 * @param pVCpu The cross context virtual CPU structure.
1366 * @param GCPtr Virtual address of the first page in the range.
1367 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1368 */
1369VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1370{
1371 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1372}
1373
1374
1375/**
1376 * Changing the page flags for a single page in the shadow page tables so as to
1377 * make it not present.
1378 *
1379 * @returns VBox status code.
1380 * @param pVCpu The cross context virtual CPU structure.
1381 * @param GCPtr Virtual address of the first page in the range.
1382 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1383 */
1384VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1385{
1386 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1387}
1388
1389
1390/**
1391 * Changing the page flags for a single page in the shadow page tables so as to
1392 * make it supervisor and writable.
1393 *
1394 * This if for dealing with CR0.WP=0 and readonly user pages.
1395 *
1396 * @returns VBox status code.
1397 * @param pVCpu The cross context virtual CPU structure.
1398 * @param GCPtr Virtual address of the first page in the range.
1399 * @param fBigPage Whether or not this is a big page. If it is, we have to
1400 * change the shadow PDE as well. If it isn't, the caller
1401 * has checked that the shadow PDE doesn't need changing.
1402 * We ASSUME 4KB pages backing the big page here!
1403 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1404 */
1405int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1406{
1407 int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1408 if (rc == VINF_SUCCESS && fBigPage)
1409 {
1410 /* this is a bit ugly... */
1411 switch (pVCpu->pgm.s.enmShadowMode)
1412 {
1413 case PGMMODE_32_BIT:
1414 {
1415 PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1416 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1417 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1418 pPde->n.u1Write = 1;
1419 Log(("-> PDE=%#llx (32)\n", pPde->u));
1420 break;
1421 }
1422 case PGMMODE_PAE:
1423 case PGMMODE_PAE_NX:
1424 {
1425 PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1426 AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1427 Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1428 pPde->n.u1Write = 1;
1429 Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1430 break;
1431 }
1432 default:
1433 AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1434 }
1435 }
1436 return rc;
1437}
1438
1439
1440/**
1441 * Gets the shadow page directory for the specified address, PAE.
1442 *
1443 * @returns Pointer to the shadow PD.
1444 * @param pVCpu The cross context virtual CPU structure.
1445 * @param GCPtr The address.
1446 * @param uGstPdpe Guest PDPT entry. Valid.
1447 * @param ppPD Receives address of page directory
1448 */
1449int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1450{
1451 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1452 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1453 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1454 PVM pVM = pVCpu->CTX_SUFF(pVM);
1455 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1456 PPGMPOOLPAGE pShwPage;
1457 int rc;
1458
1459 PGM_LOCK_ASSERT_OWNER(pVM);
1460
1461 /* Allocate page directory if not present. */
1462 if ( !pPdpe->n.u1Present
1463 && !(pPdpe->u & X86_PDPE_PG_MASK))
1464 {
1465 RTGCPTR64 GCPdPt;
1466 PGMPOOLKIND enmKind;
1467
1468 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
1469 {
1470 /* AMD-V nested paging or real/protected mode without paging. */
1471 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1472 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1473 }
1474 else
1475 {
1476 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1477 {
1478 if (!(uGstPdpe & X86_PDPE_P))
1479 {
1480 /* PD not present; guest must reload CR3 to change it.
1481 * No need to monitor anything in this case.
1482 */
1483 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1484
1485 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1486 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1487 uGstPdpe |= X86_PDPE_P;
1488 }
1489 else
1490 {
1491 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1492 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1493 }
1494 }
1495 else
1496 {
1497 GCPdPt = CPUMGetGuestCR3(pVCpu);
1498 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1499 }
1500 }
1501
1502 /* Create a reference back to the PDPT by using the index in its shadow page. */
1503 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1504 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
1505 &pShwPage);
1506 AssertRCReturn(rc, rc);
1507
1508 /* The PD was cached or created; hook it up now. */
1509 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
1510
1511# if defined(IN_RC)
1512 /*
1513 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
1514 * PDPT entry; the CPU fetches them only during cr3 load, so any
1515 * non-present PDPT will continue to cause page faults.
1516 */
1517 ASMReloadCR3();
1518# endif
1519 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1520 }
1521 else
1522 {
1523 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1524 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1525 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1526
1527 pgmPoolCacheUsed(pPool, pShwPage);
1528 }
1529 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1530 return VINF_SUCCESS;
1531}
1532
1533
1534/**
1535 * Gets the pointer to the shadow page directory entry for an address, PAE.
1536 *
1537 * @returns Pointer to the PDE.
1538 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1539 * @param GCPtr The address.
1540 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1541 */
1542DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1543{
1544 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1545 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1546 PVM pVM = pVCpu->CTX_SUFF(pVM);
1547
1548 PGM_LOCK_ASSERT_OWNER(pVM);
1549
1550 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1551 if (!pPdpt->a[iPdPt].n.u1Present)
1552 {
1553 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1554 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1555 }
1556 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1557
1558 /* Fetch the pgm pool shadow descriptor. */
1559 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1560 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1561
1562 *ppShwPde = pShwPde;
1563 return VINF_SUCCESS;
1564}
1565
1566#ifndef IN_RC
1567
1568/**
1569 * Syncs the SHADOW page directory pointer for the specified address.
1570 *
1571 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1572 *
1573 * The caller is responsible for making sure the guest has a valid PD before
1574 * calling this function.
1575 *
1576 * @returns VBox status code.
1577 * @param pVCpu The cross context virtual CPU structure.
1578 * @param GCPtr The address.
1579 * @param uGstPml4e Guest PML4 entry (valid).
1580 * @param uGstPdpe Guest PDPT entry (valid).
1581 * @param ppPD Receives address of page directory
1582 */
1583static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1584{
1585 PVM pVM = pVCpu->CTX_SUFF(pVM);
1586 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1587 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1588 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1589 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1590 PPGMPOOLPAGE pShwPage;
1591 int rc;
1592
1593 PGM_LOCK_ASSERT_OWNER(pVM);
1594
1595 /* Allocate page directory pointer table if not present. */
1596 if ( !pPml4e->n.u1Present
1597 && !(pPml4e->u & X86_PML4E_PG_MASK))
1598 {
1599 RTGCPTR64 GCPml4;
1600 PGMPOOLKIND enmKind;
1601
1602 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1603
1604 if (fNestedPagingOrNoGstPaging)
1605 {
1606 /* AMD-V nested paging or real/protected mode without paging */
1607 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1608 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1609 }
1610 else
1611 {
1612 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1613 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1614 }
1615
1616 /* Create a reference back to the PDPT by using the index in its shadow page. */
1617 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1618 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1619 &pShwPage);
1620 AssertRCReturn(rc, rc);
1621 }
1622 else
1623 {
1624 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1625 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1626
1627 pgmPoolCacheUsed(pPool, pShwPage);
1628 }
1629 /* The PDPT was cached or created; hook it up now. */
1630 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1631
1632 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1633 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1634 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1635
1636 /* Allocate page directory if not present. */
1637 if ( !pPdpe->n.u1Present
1638 && !(pPdpe->u & X86_PDPE_PG_MASK))
1639 {
1640 RTGCPTR64 GCPdPt;
1641 PGMPOOLKIND enmKind;
1642
1643 if (fNestedPagingOrNoGstPaging)
1644 {
1645 /* AMD-V nested paging or real/protected mode without paging */
1646 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1647 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1648 }
1649 else
1650 {
1651 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1652 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1653 }
1654
1655 /* Create a reference back to the PDPT by using the index in its shadow page. */
1656 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1657 pShwPage->idx, iPdPt, false /*fLockPage*/,
1658 &pShwPage);
1659 AssertRCReturn(rc, rc);
1660 }
1661 else
1662 {
1663 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1664 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1665
1666 pgmPoolCacheUsed(pPool, pShwPage);
1667 }
1668 /* The PD was cached or created; hook it up now. */
1669 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1670
1671 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1672 return VINF_SUCCESS;
1673}
1674
1675
1676/**
1677 * Gets the SHADOW page directory pointer for the specified address (long mode).
1678 *
1679 * @returns VBox status code.
1680 * @param pVCpu The cross context virtual CPU structure.
1681 * @param GCPtr The address.
1682 * @param ppPdpt Receives address of pdpt
1683 * @param ppPD Receives address of page directory
1684 */
1685DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1686{
1687 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1688 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1689
1690 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1691
1692 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1693 if (ppPml4e)
1694 *ppPml4e = (PX86PML4E)pPml4e;
1695
1696 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1697
1698 if (!pPml4e->n.u1Present)
1699 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1700
1701 PVM pVM = pVCpu->CTX_SUFF(pVM);
1702 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1703 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1704 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1705
1706 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1707 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1708 if (!pPdpt->a[iPdPt].n.u1Present)
1709 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1710
1711 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1712 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1713
1714 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1715 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1716 return VINF_SUCCESS;
1717}
1718
1719
1720/**
1721 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1722 * backing pages in case the PDPT or PML4 entry is missing.
1723 *
1724 * @returns VBox status code.
1725 * @param pVCpu The cross context virtual CPU structure.
1726 * @param GCPtr The address.
1727 * @param ppPdpt Receives address of pdpt
1728 * @param ppPD Receives address of page directory
1729 */
1730static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1731{
1732 PVM pVM = pVCpu->CTX_SUFF(pVM);
1733 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1734 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1735 PEPTPML4 pPml4;
1736 PEPTPML4E pPml4e;
1737 PPGMPOOLPAGE pShwPage;
1738 int rc;
1739
1740 Assert(pVM->pgm.s.fNestedPaging);
1741 PGM_LOCK_ASSERT_OWNER(pVM);
1742
1743 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1744 Assert(pPml4);
1745
1746 /* Allocate page directory pointer table if not present. */
1747 pPml4e = &pPml4->a[iPml4];
1748 if ( !pPml4e->n.u1Present
1749 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1750 {
1751 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1752 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1753
1754 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1755 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1756 &pShwPage);
1757 AssertRCReturn(rc, rc);
1758 }
1759 else
1760 {
1761 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1762 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1763
1764 pgmPoolCacheUsed(pPool, pShwPage);
1765 }
1766 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1767 pPml4e->u = pShwPage->Core.Key;
1768 pPml4e->n.u1Present = 1;
1769 pPml4e->n.u1Write = 1;
1770 pPml4e->n.u1Execute = 1;
1771
1772 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1773 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1774 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1775
1776 if (ppPdpt)
1777 *ppPdpt = pPdpt;
1778
1779 /* Allocate page directory if not present. */
1780 if ( !pPdpe->n.u1Present
1781 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1782 {
1783 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1784 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1785 pShwPage->idx, iPdPt, false /*fLockPage*/,
1786 &pShwPage);
1787 AssertRCReturn(rc, rc);
1788 }
1789 else
1790 {
1791 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1792 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1793
1794 pgmPoolCacheUsed(pPool, pShwPage);
1795 }
1796 /* The PD was cached or created; hook it up now and fill with the default value. */
1797 pPdpe->u = pShwPage->Core.Key;
1798 pPdpe->n.u1Present = 1;
1799 pPdpe->n.u1Write = 1;
1800 pPdpe->n.u1Execute = 1;
1801
1802 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1803 return VINF_SUCCESS;
1804}
1805
1806#endif /* IN_RC */
1807
1808#ifdef IN_RING0
1809/**
1810 * Synchronizes a range of nested page table entries.
1811 *
1812 * The caller must own the PGM lock.
1813 *
1814 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1815 * @param GCPhys Where to start.
1816 * @param cPages How many pages which entries should be synced.
1817 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1818 * host paging mode for AMD-V).
1819 */
1820int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1821{
1822 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1823
1824/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1825 int rc;
1826 switch (enmShwPagingMode)
1827 {
1828 case PGMMODE_32_BIT:
1829 {
1830 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1831 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1832 break;
1833 }
1834
1835 case PGMMODE_PAE:
1836 case PGMMODE_PAE_NX:
1837 {
1838 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1839 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1840 break;
1841 }
1842
1843 case PGMMODE_AMD64:
1844 case PGMMODE_AMD64_NX:
1845 {
1846 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1847 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1848 break;
1849 }
1850
1851 case PGMMODE_EPT:
1852 {
1853 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1854 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /*uErr*/);
1855 break;
1856 }
1857
1858 default:
1859 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1860 }
1861 return rc;
1862}
1863#endif /* IN_RING0 */
1864
1865
1866/**
1867 * Gets effective Guest OS page information.
1868 *
1869 * When GCPtr is in a big page, the function will return as if it was a normal
1870 * 4KB page. If the need for distinguishing between big and normal page becomes
1871 * necessary at a later point, a PGMGstGetPage() will be created for that
1872 * purpose.
1873 *
1874 * @returns VBox status code.
1875 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1876 * @param GCPtr Guest Context virtual address of the page.
1877 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1878 * @param pGCPhys Where to store the GC physical address of the page.
1879 * This is page aligned. The fact that the
1880 */
1881VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1882{
1883 VMCPU_ASSERT_EMT(pVCpu);
1884 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1885 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1886 AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1887 return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pfFlags, pGCPhys);
1888}
1889
1890
1891/**
1892 * Performs a guest page table walk.
1893 *
1894 * The guest should be in paged protect mode or long mode when making a call to
1895 * this function.
1896 *
1897 * @returns VBox status code.
1898 * @retval VINF_SUCCESS on success.
1899 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1900 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1901 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1902 *
1903 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1904 * @param GCPtr The guest virtual address to walk by.
1905 * @param pWalk Where to return the walk result. This is valid for some
1906 * error codes as well.
1907 */
1908int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1909{
1910 VMCPU_ASSERT_EMT(pVCpu);
1911 switch (pVCpu->pgm.s.enmGuestMode)
1912 {
1913 case PGMMODE_32_BIT:
1914 pWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1915 return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, &pWalk->u.Legacy);
1916
1917 case PGMMODE_PAE:
1918 case PGMMODE_PAE_NX:
1919 pWalk->enmType = PGMPTWALKGSTTYPE_PAE;
1920 return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, &pWalk->u.Pae);
1921
1922#if !defined(IN_RC)
1923 case PGMMODE_AMD64:
1924 case PGMMODE_AMD64_NX:
1925 pWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
1926 return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, &pWalk->u.Amd64);
1927#endif
1928
1929 case PGMMODE_REAL:
1930 case PGMMODE_PROTECTED:
1931 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
1932 return VERR_PGM_NOT_USED_IN_MODE;
1933
1934#if defined(IN_RC)
1935 case PGMMODE_AMD64:
1936 case PGMMODE_AMD64_NX:
1937#endif
1938 case PGMMODE_NESTED_32BIT:
1939 case PGMMODE_NESTED_PAE:
1940 case PGMMODE_NESTED_AMD64:
1941 case PGMMODE_EPT:
1942 default:
1943 AssertFailed();
1944 pWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
1945 return VERR_PGM_NOT_USED_IN_MODE;
1946 }
1947}
1948
1949
1950/**
1951 * Tries to continue the previous walk.
1952 *
1953 * @note Requires the caller to hold the PGM lock from the first
1954 * pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
1955 * we cannot use the pointers.
1956 *
1957 * @returns VBox status code.
1958 * @retval VINF_SUCCESS on success.
1959 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1960 * @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1961 * not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1962 *
1963 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1964 * @param GCPtr The guest virtual address to walk by.
1965 * @param pWalk Pointer to the previous walk result and where to return
1966 * the result of this walk. This is valid for some error
1967 * codes as well.
1968 */
1969int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk)
1970{
1971 /*
1972 * We can only handle successfully walks.
1973 * We also limit ourselves to the next page.
1974 */
1975 if ( pWalk->u.Core.fSucceeded
1976 && GCPtr - pWalk->u.Core.GCPtr == PAGE_SIZE)
1977 {
1978 Assert(pWalk->u.Core.uLevel == 0);
1979 if (pWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
1980 {
1981 /*
1982 * AMD64
1983 */
1984 if (!pWalk->u.Core.fGigantPage && !pWalk->u.Core.fBigPage)
1985 {
1986 /*
1987 * We fall back to full walk if the PDE table changes, if any
1988 * reserved bits are set, or if the effective page access changes.
1989 */
1990 const uint64_t fPteSame = X86_PTE_P | X86_PTE_RW | X86_PTE_US | X86_PTE_PWT
1991 | X86_PTE_PCD | X86_PTE_A | X86_PTE_PAE_NX;
1992 const uint64_t fPdeSame = X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT
1993 | X86_PDE_PCD | X86_PDE_A | X86_PDE_PAE_NX | X86_PDE_PS;
1994
1995 if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PD_PAE_SHIFT))
1996 {
1997 if (pWalk->u.Amd64.pPte)
1998 {
1999 X86PTEPAE Pte;
2000 Pte.u = pWalk->u.Amd64.pPte[1].u;
2001 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
2002 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2003 {
2004
2005 pWalk->u.Core.GCPtr = GCPtr;
2006 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2007 pWalk->u.Amd64.Pte.u = Pte.u;
2008 pWalk->u.Amd64.pPte++;
2009 return VINF_SUCCESS;
2010 }
2011 }
2012 }
2013 else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->u.Core.GCPtr >> X86_PDPT_SHIFT))
2014 {
2015 Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
2016 if (pWalk->u.Amd64.pPde)
2017 {
2018 X86PDEPAE Pde;
2019 Pde.u = pWalk->u.Amd64.pPde[1].u;
2020 if ( (Pde.u & fPdeSame) == (pWalk->u.Amd64.Pde.u & fPdeSame)
2021 && !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
2022 {
2023 /* Get the new PTE and check out the first entry. */
2024 int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2025 &pWalk->u.Amd64.pPt);
2026 if (RT_SUCCESS(rc))
2027 {
2028 pWalk->u.Amd64.pPte = &pWalk->u.Amd64.pPt->a[0];
2029 X86PTEPAE Pte;
2030 Pte.u = pWalk->u.Amd64.pPte->u;
2031 if ( (Pte.u & fPteSame) == (pWalk->u.Amd64.Pte.u & fPteSame)
2032 && !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2033 {
2034 pWalk->u.Core.GCPtr = GCPtr;
2035 pWalk->u.Core.GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2036 pWalk->u.Amd64.Pte.u = Pte.u;
2037 pWalk->u.Amd64.Pde.u = Pde.u;
2038 pWalk->u.Amd64.pPde++;
2039 return VINF_SUCCESS;
2040 }
2041 }
2042 }
2043 }
2044 }
2045 }
2046 else if (!pWalk->u.Core.fGigantPage)
2047 {
2048 if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_2M_BASE_MASK))
2049 {
2050 pWalk->u.Core.GCPtr = GCPtr;
2051 pWalk->u.Core.GCPhys += PAGE_SIZE;
2052 return VINF_SUCCESS;
2053 }
2054 }
2055 else
2056 {
2057 if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->u.Core.GCPtr & X86_PAGE_1G_BASE_MASK))
2058 {
2059 pWalk->u.Core.GCPtr = GCPtr;
2060 pWalk->u.Core.GCPhys += PAGE_SIZE;
2061 return VINF_SUCCESS;
2062 }
2063 }
2064 }
2065 }
2066 /* Case we don't handle. Do full walk. */
2067 return pgmGstPtWalk(pVCpu, GCPtr, pWalk);
2068}
2069
2070
2071/**
2072 * Checks if the page is present.
2073 *
2074 * @returns true if the page is present.
2075 * @returns false if the page is not present.
2076 * @param pVCpu The cross context virtual CPU structure.
2077 * @param GCPtr Address within the page.
2078 */
2079VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
2080{
2081 VMCPU_ASSERT_EMT(pVCpu);
2082 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
2083 return RT_SUCCESS(rc);
2084}
2085
2086
2087/**
2088 * Sets (replaces) the page flags for a range of pages in the guest's tables.
2089 *
2090 * @returns VBox status code.
2091 * @param pVCpu The cross context virtual CPU structure.
2092 * @param GCPtr The address of the first page.
2093 * @param cb The size of the range in bytes.
2094 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
2095 */
2096VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
2097{
2098 VMCPU_ASSERT_EMT(pVCpu);
2099 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
2100}
2101
2102
2103/**
2104 * Modify page flags for a range of pages in the guest's tables
2105 *
2106 * The existing flags are ANDed with the fMask and ORed with the fFlags.
2107 *
2108 * @returns VBox status code.
2109 * @param pVCpu The cross context virtual CPU structure.
2110 * @param GCPtr Virtual address of the first page in the range.
2111 * @param cb Size (in bytes) of the range to apply the modification to.
2112 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2113 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2114 * Be very CAREFUL when ~'ing constants which could be 32-bit!
2115 */
2116VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2117{
2118 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2119 VMCPU_ASSERT_EMT(pVCpu);
2120
2121 /*
2122 * Validate input.
2123 */
2124 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2125 Assert(cb);
2126
2127 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2128
2129 /*
2130 * Adjust input.
2131 */
2132 cb += GCPtr & PAGE_OFFSET_MASK;
2133 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
2134 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
2135
2136 /*
2137 * Call worker.
2138 */
2139 uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2140 AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2141 AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2142 int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2143
2144 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
2145 return rc;
2146}
2147
2148
2149#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2150
2151/**
2152 * Performs the lazy mapping of the 32-bit guest PD.
2153 *
2154 * @returns VBox status code.
2155 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2156 * @param ppPd Where to return the pointer to the mapping. This is
2157 * always set.
2158 */
2159int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
2160{
2161 PVM pVM = pVCpu->CTX_SUFF(pVM);
2162 pgmLock(pVM);
2163
2164 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2165
2166 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
2167 PPGMPAGE pPage;
2168 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2169 if (RT_SUCCESS(rc))
2170 {
2171 RTHCPTR HCPtrGuestCR3;
2172 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2173 if (RT_SUCCESS(rc))
2174 {
2175 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
2176# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2177 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
2178# endif
2179 *ppPd = (PX86PD)HCPtrGuestCR3;
2180
2181 pgmUnlock(pVM);
2182 return VINF_SUCCESS;
2183 }
2184
2185 AssertRC(rc);
2186 }
2187 pgmUnlock(pVM);
2188
2189 *ppPd = NULL;
2190 return rc;
2191}
2192
2193
2194/**
2195 * Performs the lazy mapping of the PAE guest PDPT.
2196 *
2197 * @returns VBox status code.
2198 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2199 * @param ppPdpt Where to return the pointer to the mapping. This is
2200 * always set.
2201 */
2202int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
2203{
2204 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2205 PVM pVM = pVCpu->CTX_SUFF(pVM);
2206 pgmLock(pVM);
2207
2208 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
2209 PPGMPAGE pPage;
2210 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2211 if (RT_SUCCESS(rc))
2212 {
2213 RTHCPTR HCPtrGuestCR3;
2214 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2215 if (RT_SUCCESS(rc))
2216 {
2217 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2218# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2219 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
2220# endif
2221 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
2222
2223 pgmUnlock(pVM);
2224 return VINF_SUCCESS;
2225 }
2226
2227 AssertRC(rc);
2228 }
2229
2230 pgmUnlock(pVM);
2231 *ppPdpt = NULL;
2232 return rc;
2233}
2234
2235
2236/**
2237 * Performs the lazy mapping / updating of a PAE guest PD.
2238 *
2239 * @returns Pointer to the mapping.
2240 * @returns VBox status code.
2241 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2242 * @param iPdpt Which PD entry to map (0..3).
2243 * @param ppPd Where to return the pointer to the mapping. This is
2244 * always set.
2245 */
2246int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2247{
2248 PVM pVM = pVCpu->CTX_SUFF(pVM);
2249 pgmLock(pVM);
2250
2251 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2252 Assert(pGuestPDPT);
2253 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
2254 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2255 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2256
2257 PPGMPAGE pPage;
2258 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2259 if (RT_SUCCESS(rc))
2260 {
2261 RTRCPTR RCPtr = NIL_RTRCPTR;
2262 RTHCPTR HCPtr = NIL_RTHCPTR;
2263#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2264 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
2265 AssertRC(rc);
2266#endif
2267 if (RT_SUCCESS(rc) && fChanged)
2268 {
2269 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
2270 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
2271 }
2272 if (RT_SUCCESS(rc))
2273 {
2274 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
2275# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2276 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
2277# endif
2278 if (fChanged)
2279 {
2280 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2281 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
2282 }
2283
2284 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
2285 pgmUnlock(pVM);
2286 return VINF_SUCCESS;
2287 }
2288 }
2289
2290 /* Invalid page or some failure, invalidate the entry. */
2291 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2292 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
2293# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2294 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
2295# endif
2296 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
2297
2298 pgmUnlock(pVM);
2299 return rc;
2300}
2301
2302#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2303#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2304/**
2305 * Performs the lazy mapping of the 32-bit guest PD.
2306 *
2307 * @returns VBox status code.
2308 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2309 * @param ppPml4 Where to return the pointer to the mapping. This will
2310 * always be set.
2311 */
2312int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
2313{
2314 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2315 PVM pVM = pVCpu->CTX_SUFF(pVM);
2316 pgmLock(pVM);
2317
2318 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
2319 PPGMPAGE pPage;
2320 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2321 if (RT_SUCCESS(rc))
2322 {
2323 RTHCPTR HCPtrGuestCR3;
2324 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
2325 if (RT_SUCCESS(rc))
2326 {
2327 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
2328# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2329 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
2330# endif
2331 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
2332
2333 pgmUnlock(pVM);
2334 return VINF_SUCCESS;
2335 }
2336 }
2337
2338 pgmUnlock(pVM);
2339 *ppPml4 = NULL;
2340 return rc;
2341}
2342#endif
2343
2344
2345/**
2346 * Gets the PAE PDPEs values cached by the CPU.
2347 *
2348 * @returns VBox status code.
2349 * @param pVCpu The cross context virtual CPU structure.
2350 * @param paPdpes Where to return the four PDPEs. The array
2351 * pointed to must have 4 entries.
2352 */
2353VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
2354{
2355 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2356
2357 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
2358 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
2359 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
2360 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
2361 return VINF_SUCCESS;
2362}
2363
2364
2365/**
2366 * Sets the PAE PDPEs values cached by the CPU.
2367 *
2368 * @remarks This must be called *AFTER* PGMUpdateCR3.
2369 *
2370 * @param pVCpu The cross context virtual CPU structure.
2371 * @param paPdpes The four PDPE values. The array pointed to must
2372 * have exactly 4 entries.
2373 *
2374 * @remarks No-long-jump zone!!!
2375 */
2376VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
2377{
2378 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2379
2380 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
2381 {
2382 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
2383 {
2384 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
2385
2386 /* Force lazy remapping if it changed in any way. */
2387 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2388# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2389 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2390# endif
2391 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
2392 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2393 }
2394 }
2395
2396 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
2397}
2398
2399
2400/**
2401 * Gets the current CR3 register value for the shadow memory context.
2402 * @returns CR3 value.
2403 * @param pVCpu The cross context virtual CPU structure.
2404 */
2405VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2406{
2407 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2408 AssertPtrReturn(pPoolPage, 0);
2409 return pPoolPage->Core.Key;
2410}
2411
2412
2413/**
2414 * Gets the current CR3 register value for the nested memory context.
2415 * @returns CR3 value.
2416 * @param pVCpu The cross context virtual CPU structure.
2417 * @param enmShadowMode The shadow paging mode.
2418 */
2419VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
2420{
2421 NOREF(enmShadowMode);
2422 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
2423 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
2424}
2425
2426
2427/**
2428 * Gets the current CR3 register value for the HC intermediate memory context.
2429 * @returns CR3 value.
2430 * @param pVM The cross context VM structure.
2431 */
2432VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
2433{
2434 switch (pVM->pgm.s.enmHostMode)
2435 {
2436 case SUPPAGINGMODE_32_BIT:
2437 case SUPPAGINGMODE_32_BIT_GLOBAL:
2438 return pVM->pgm.s.HCPhysInterPD;
2439
2440 case SUPPAGINGMODE_PAE:
2441 case SUPPAGINGMODE_PAE_GLOBAL:
2442 case SUPPAGINGMODE_PAE_NX:
2443 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2444 return pVM->pgm.s.HCPhysInterPaePDPT;
2445
2446 case SUPPAGINGMODE_AMD64:
2447 case SUPPAGINGMODE_AMD64_GLOBAL:
2448 case SUPPAGINGMODE_AMD64_NX:
2449 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2450 return pVM->pgm.s.HCPhysInterPaePDPT;
2451
2452 default:
2453 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
2454 return NIL_RTHCPHYS;
2455 }
2456}
2457
2458
2459/**
2460 * Gets the current CR3 register value for the RC intermediate memory context.
2461 * @returns CR3 value.
2462 * @param pVM The cross context VM structure.
2463 * @param pVCpu The cross context virtual CPU structure.
2464 */
2465VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
2466{
2467 switch (pVCpu->pgm.s.enmShadowMode)
2468 {
2469 case PGMMODE_32_BIT:
2470 return pVM->pgm.s.HCPhysInterPD;
2471
2472 case PGMMODE_PAE:
2473 case PGMMODE_PAE_NX:
2474 return pVM->pgm.s.HCPhysInterPaePDPT;
2475
2476 case PGMMODE_AMD64:
2477 case PGMMODE_AMD64_NX:
2478 return pVM->pgm.s.HCPhysInterPaePML4;
2479
2480 case PGMMODE_NESTED_32BIT:
2481 case PGMMODE_NESTED_PAE:
2482 case PGMMODE_NESTED_AMD64:
2483 case PGMMODE_EPT:
2484 return 0; /* not relevant */
2485
2486 default:
2487 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
2488 return NIL_RTHCPHYS;
2489 }
2490}
2491
2492
2493/**
2494 * Gets the CR3 register value for the 32-Bit intermediate memory context.
2495 * @returns CR3 value.
2496 * @param pVM The cross context VM structure.
2497 */
2498VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
2499{
2500 return pVM->pgm.s.HCPhysInterPD;
2501}
2502
2503
2504/**
2505 * Gets the CR3 register value for the PAE intermediate memory context.
2506 * @returns CR3 value.
2507 * @param pVM The cross context VM structure.
2508 */
2509VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
2510{
2511 return pVM->pgm.s.HCPhysInterPaePDPT;
2512}
2513
2514
2515/**
2516 * Gets the CR3 register value for the AMD64 intermediate memory context.
2517 * @returns CR3 value.
2518 * @param pVM The cross context VM structure.
2519 */
2520VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
2521{
2522 return pVM->pgm.s.HCPhysInterPaePML4;
2523}
2524
2525
2526/**
2527 * Performs and schedules necessary updates following a CR3 load or reload.
2528 *
2529 * This will normally involve mapping the guest PD or nPDPT
2530 *
2531 * @returns VBox status code.
2532 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2533 * safely be ignored and overridden since the FF will be set too then.
2534 * @param pVCpu The cross context virtual CPU structure.
2535 * @param cr3 The new cr3.
2536 * @param fGlobal Indicates whether this is a global flush or not.
2537 */
2538VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
2539{
2540 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2541 PVM pVM = pVCpu->CTX_SUFF(pVM);
2542
2543 VMCPU_ASSERT_EMT(pVCpu);
2544
2545 /*
2546 * Always flag the necessary updates; necessary for hardware acceleration
2547 */
2548 /** @todo optimize this, it shouldn't always be necessary. */
2549 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2550 if (fGlobal)
2551 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2552 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
2553
2554 /*
2555 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2556 */
2557 int rc = VINF_SUCCESS;
2558 RTGCPHYS GCPhysCR3;
2559 switch (pVCpu->pgm.s.enmGuestMode)
2560 {
2561 case PGMMODE_PAE:
2562 case PGMMODE_PAE_NX:
2563 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2564 break;
2565 case PGMMODE_AMD64:
2566 case PGMMODE_AMD64_NX:
2567 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2568 break;
2569 default:
2570 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2571 break;
2572 }
2573 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2574
2575 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2576 {
2577 RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2578
2579 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2580 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2581 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2582
2583 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2584 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2585 if (RT_LIKELY(rc == VINF_SUCCESS))
2586 {
2587 if (pgmMapAreMappingsFloating(pVM))
2588 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2589 }
2590 else
2591 {
2592 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2593 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
2594 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2595 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
2596 if (pgmMapAreMappingsFloating(pVM))
2597 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
2598 }
2599
2600 if (fGlobal)
2601 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2602 else
2603 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
2604 }
2605 else
2606 {
2607# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2608 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2609 if (pPool->cDirtyPages)
2610 {
2611 pgmLock(pVM);
2612 pgmPoolResetDirtyPages(pVM);
2613 pgmUnlock(pVM);
2614 }
2615# endif
2616 /*
2617 * Check if we have a pending update of the CR3 monitoring.
2618 */
2619 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2620 {
2621 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2622 Assert(!pVM->pgm.s.fMappingsFixed); Assert(pgmMapAreMappingsEnabled(pVM));
2623 }
2624 if (fGlobal)
2625 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2626 else
2627 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
2628 }
2629
2630 IEMTlbInvalidateAll(pVCpu, false /*fVmm*/);
2631 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
2632 return rc;
2633}
2634
2635
2636/**
2637 * Performs and schedules necessary updates following a CR3 load or reload when
2638 * using nested or extended paging.
2639 *
2640 * This API is an alternative to PGMFlushTLB that avoids actually flushing the
2641 * TLB and triggering a SyncCR3.
2642 *
2643 * This will normally involve mapping the guest PD or nPDPT
2644 *
2645 * @returns VBox status code.
2646 * @retval VINF_SUCCESS.
2647 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2648 * paging modes). This can safely be ignored and overridden since the
2649 * FF will be set too then.
2650 * @param pVCpu The cross context virtual CPU structure.
2651 * @param cr3 The new cr3.
2652 */
2653VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
2654{
2655 VMCPU_ASSERT_EMT(pVCpu);
2656 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
2657
2658 /* We assume we're only called in nested paging mode. */
2659 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2660 Assert(!pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2661 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
2662
2663 /*
2664 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2665 */
2666 int rc = VINF_SUCCESS;
2667 RTGCPHYS GCPhysCR3;
2668 switch (pVCpu->pgm.s.enmGuestMode)
2669 {
2670 case PGMMODE_PAE:
2671 case PGMMODE_PAE_NX:
2672 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2673 break;
2674 case PGMMODE_AMD64:
2675 case PGMMODE_AMD64_NX:
2676 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2677 break;
2678 default:
2679 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2680 break;
2681 }
2682 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2683
2684 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2685 {
2686 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2687 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2688 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2689
2690 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2691 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2692
2693 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
2694 }
2695
2696 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2697 return rc;
2698}
2699
2700
2701/**
2702 * Synchronize the paging structures.
2703 *
2704 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2705 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2706 * in several places, most importantly whenever the CR3 is loaded.
2707 *
2708 * @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2709 * @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2710 * the VMM into guest context.
2711 * @param pVCpu The cross context virtual CPU structure.
2712 * @param cr0 Guest context CR0 register
2713 * @param cr3 Guest context CR3 register
2714 * @param cr4 Guest context CR4 register
2715 * @param fGlobal Including global page directories or not
2716 */
2717VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2718{
2719 int rc;
2720
2721 VMCPU_ASSERT_EMT(pVCpu);
2722
2723 /*
2724 * The pool may have pending stuff and even require a return to ring-3 to
2725 * clear the whole thing.
2726 */
2727 rc = pgmPoolSyncCR3(pVCpu);
2728 if (rc != VINF_SUCCESS)
2729 return rc;
2730
2731 /*
2732 * We might be called when we shouldn't.
2733 *
2734 * The mode switching will ensure that the PD is resynced after every mode
2735 * switch. So, if we find ourselves here when in protected or real mode
2736 * we can safely clear the FF and return immediately.
2737 */
2738 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2739 {
2740 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2741 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2742 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2743 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2744 return VINF_SUCCESS;
2745 }
2746
2747 /* If global pages are not supported, then all flushes are global. */
2748 if (!(cr4 & X86_CR4_PGE))
2749 fGlobal = true;
2750 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2751 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2752
2753 /*
2754 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2755 * This should be done before SyncCR3.
2756 */
2757 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2758 {
2759 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2760
2761 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2762 RTGCPHYS GCPhysCR3;
2763 switch (pVCpu->pgm.s.enmGuestMode)
2764 {
2765 case PGMMODE_PAE:
2766 case PGMMODE_PAE_NX:
2767 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2768 break;
2769 case PGMMODE_AMD64:
2770 case PGMMODE_AMD64_NX:
2771 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2772 break;
2773 default:
2774 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2775 break;
2776 }
2777 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2778
2779 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2780 {
2781 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2782 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2783 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2784 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2785 rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2786 }
2787
2788 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2789 if ( rc == VINF_PGM_SYNC_CR3
2790 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2791 {
2792 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2793#ifdef IN_RING3
2794 rc = pgmPoolSyncCR3(pVCpu);
2795#else
2796 if (rc == VINF_PGM_SYNC_CR3)
2797 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2798 return VINF_PGM_SYNC_CR3;
2799#endif
2800 }
2801 AssertRCReturn(rc, rc);
2802 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2803 }
2804
2805 /*
2806 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2807 */
2808 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2809
2810 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2811 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2812 AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2813 rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2814
2815 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2816 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2817 if (rc == VINF_SUCCESS)
2818 {
2819 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2820 {
2821 /* Go back to ring 3 if a pgm pool sync is again pending. */
2822 return VINF_PGM_SYNC_CR3;
2823 }
2824
2825 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2826 {
2827 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2828 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2829 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2830 }
2831
2832 /*
2833 * Check if we have a pending update of the CR3 monitoring.
2834 */
2835 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2836 {
2837 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2838 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2839 Assert(pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM)));
2840 }
2841 }
2842
2843 /*
2844 * Now flush the CR3 (guest context).
2845 */
2846 if (rc == VINF_SUCCESS)
2847 PGM_INVL_VCPU_TLBS(pVCpu);
2848 return rc;
2849}
2850
2851
2852/**
2853 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2854 *
2855 * @returns VBox status code, with the following informational code for
2856 * VM scheduling.
2857 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2858 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2859 * (I.e. not in R3.)
2860 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2861 *
2862 * @param pVCpu The cross context virtual CPU structure.
2863 * @param cr0 The new cr0.
2864 * @param cr4 The new cr4.
2865 * @param efer The new extended feature enable register.
2866 */
2867VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2868{
2869 VMCPU_ASSERT_EMT(pVCpu);
2870
2871 /*
2872 * Calc the new guest mode.
2873 *
2874 * Note! We check PG before PE and without requiring PE because of the
2875 * special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
2876 */
2877 PGMMODE enmGuestMode;
2878 if (cr0 & X86_CR0_PG)
2879 {
2880 if (!(cr4 & X86_CR4_PAE))
2881 {
2882 bool const fPse = !!(cr4 & X86_CR4_PSE);
2883 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2884 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2885 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2886 enmGuestMode = PGMMODE_32_BIT;
2887 }
2888 else if (!(efer & MSR_K6_EFER_LME))
2889 {
2890 if (!(efer & MSR_K6_EFER_NXE))
2891 enmGuestMode = PGMMODE_PAE;
2892 else
2893 enmGuestMode = PGMMODE_PAE_NX;
2894 }
2895 else
2896 {
2897 if (!(efer & MSR_K6_EFER_NXE))
2898 enmGuestMode = PGMMODE_AMD64;
2899 else
2900 enmGuestMode = PGMMODE_AMD64_NX;
2901 }
2902 }
2903 else if (!(cr0 & X86_CR0_PE))
2904 enmGuestMode = PGMMODE_REAL;
2905 else
2906 enmGuestMode = PGMMODE_PROTECTED;
2907
2908 /*
2909 * Did it change?
2910 */
2911 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2912 return VINF_SUCCESS;
2913
2914 /* Flush the TLB */
2915 PGM_INVL_VCPU_TLBS(pVCpu);
2916
2917#ifdef IN_RING3
2918 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2919#else
2920 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2921 return VINF_PGM_CHANGE_MODE;
2922#endif
2923}
2924
2925
2926/**
2927 * Called by CPUM or REM when CR0.WP changes to 1.
2928 *
2929 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2930 * @thread EMT
2931 */
2932VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu)
2933{
2934 /*
2935 * Netware WP0+RO+US hack cleanup when WP0 -> WP1.
2936 *
2937 * Use the counter to judge whether there might be pool pages with active
2938 * hacks in them. If there are, we will be running the risk of messing up
2939 * the guest by allowing it to write to read-only pages. Thus, we have to
2940 * clear the page pool ASAP if there is the slightest chance.
2941 */
2942 if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
2943 {
2944 Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
2945
2946 Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
2947 pVCpu->pgm.s.cNetwareWp0Hacks = 0;
2948 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
2949 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2950 }
2951}
2952
2953
2954/**
2955 * Gets the current guest paging mode.
2956 *
2957 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2958 *
2959 * @returns The current paging mode.
2960 * @param pVCpu The cross context virtual CPU structure.
2961 */
2962VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2963{
2964 return pVCpu->pgm.s.enmGuestMode;
2965}
2966
2967
2968/**
2969 * Gets the current shadow paging mode.
2970 *
2971 * @returns The current paging mode.
2972 * @param pVCpu The cross context virtual CPU structure.
2973 */
2974VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2975{
2976 return pVCpu->pgm.s.enmShadowMode;
2977}
2978
2979
2980/**
2981 * Gets the current host paging mode.
2982 *
2983 * @returns The current paging mode.
2984 * @param pVM The cross context VM structure.
2985 */
2986VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2987{
2988 switch (pVM->pgm.s.enmHostMode)
2989 {
2990 case SUPPAGINGMODE_32_BIT:
2991 case SUPPAGINGMODE_32_BIT_GLOBAL:
2992 return PGMMODE_32_BIT;
2993
2994 case SUPPAGINGMODE_PAE:
2995 case SUPPAGINGMODE_PAE_GLOBAL:
2996 return PGMMODE_PAE;
2997
2998 case SUPPAGINGMODE_PAE_NX:
2999 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3000 return PGMMODE_PAE_NX;
3001
3002 case SUPPAGINGMODE_AMD64:
3003 case SUPPAGINGMODE_AMD64_GLOBAL:
3004 return PGMMODE_AMD64;
3005
3006 case SUPPAGINGMODE_AMD64_NX:
3007 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3008 return PGMMODE_AMD64_NX;
3009
3010 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3011 }
3012
3013 return PGMMODE_INVALID;
3014}
3015
3016
3017/**
3018 * Get mode name.
3019 *
3020 * @returns read-only name string.
3021 * @param enmMode The mode which name is desired.
3022 */
3023VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3024{
3025 switch (enmMode)
3026 {
3027 case PGMMODE_REAL: return "Real";
3028 case PGMMODE_PROTECTED: return "Protected";
3029 case PGMMODE_32_BIT: return "32-bit";
3030 case PGMMODE_PAE: return "PAE";
3031 case PGMMODE_PAE_NX: return "PAE+NX";
3032 case PGMMODE_AMD64: return "AMD64";
3033 case PGMMODE_AMD64_NX: return "AMD64+NX";
3034 case PGMMODE_NESTED_32BIT: return "Nested-32";
3035 case PGMMODE_NESTED_PAE: return "Nested-PAE";
3036 case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3037 case PGMMODE_EPT: return "EPT";
3038 default: return "unknown mode value";
3039 }
3040}
3041
3042
3043/**
3044 * Gets the physical address represented in the guest CR3 as PGM sees it.
3045 *
3046 * This is mainly for logging and debugging.
3047 *
3048 * @returns PGM's guest CR3 value.
3049 * @param pVCpu The cross context virtual CPU structure.
3050 */
3051VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3052{
3053 return pVCpu->pgm.s.GCPhysCR3;
3054}
3055
3056
3057
3058/**
3059 * Notification from CPUM that the EFER.NXE bit has changed.
3060 *
3061 * @param pVCpu The cross context virtual CPU structure of the CPU for
3062 * which EFER changed.
3063 * @param fNxe The new NXE state.
3064 */
3065VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3066{
3067/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3068 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3069
3070 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3071 if (fNxe)
3072 {
3073 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3074 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3075 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3076 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3077 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
3078 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3079 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3080 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3081 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3082 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3083 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3084
3085 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
3086 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
3087 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
3088 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
3089 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
3090 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
3091 }
3092 else
3093 {
3094 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
3095 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
3096 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
3097 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
3098 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
3099 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
3100 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
3101 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
3102 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
3103 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
3104 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
3105
3106 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3107 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3108 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3109 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3110 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3111 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3112 }
3113}
3114
3115
3116/**
3117 * Check if any pgm pool pages are marked dirty (not monitored)
3118 *
3119 * @returns bool locked/not locked
3120 * @param pVM The cross context VM structure.
3121 */
3122VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3123{
3124 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3125}
3126
3127
3128/**
3129 * Check if this VCPU currently owns the PGM lock.
3130 *
3131 * @returns bool owner/not owner
3132 * @param pVM The cross context VM structure.
3133 */
3134VMMDECL(bool) PGMIsLockOwner(PVM pVM)
3135{
3136 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
3137}
3138
3139
3140/**
3141 * Enable or disable large page usage
3142 *
3143 * @returns VBox status code.
3144 * @param pVM The cross context VM structure.
3145 * @param fUseLargePages Use/not use large pages
3146 */
3147VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
3148{
3149 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3150
3151 pVM->fUseLargePages = fUseLargePages;
3152 return VINF_SUCCESS;
3153}
3154
3155
3156/**
3157 * Acquire the PGM lock.
3158 *
3159 * @returns VBox status code
3160 * @param pVM The cross context VM structure.
3161 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3162 */
3163#if (defined(VBOX_STRICT) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
3164int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL)
3165#else
3166int pgmLock(PVM pVM)
3167#endif
3168{
3169#if defined(VBOX_STRICT) && defined(IN_RING3)
3170 int rc = PDMCritSectEnterDebug(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3171#else
3172 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
3173#endif
3174#if defined(IN_RC) || defined(IN_RING0)
3175 if (rc == VERR_SEM_BUSY)
3176 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
3177#endif
3178 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3179 return rc;
3180}
3181
3182
3183/**
3184 * Release the PGM lock.
3185 *
3186 * @returns VBox status code
3187 * @param pVM The cross context VM structure.
3188 */
3189void pgmUnlock(PVM pVM)
3190{
3191 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3192 pVM->pgm.s.cDeprecatedPageLocks = 0;
3193 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
3194 if (rc == VINF_SEM_NESTED)
3195 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3196}
3197
3198#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3199
3200/**
3201 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
3202 *
3203 * @returns VBox status code.
3204 * @param pVM The cross context VM structure.
3205 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3206 * @param GCPhys The guest physical address of the page to map. The
3207 * offset bits are not ignored.
3208 * @param ppv Where to return the address corresponding to @a GCPhys.
3209 * @param SRC_POS The source position of the caller (RT_SRC_POS).
3210 */
3211int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
3212{
3213 pgmLock(pVM);
3214
3215 /*
3216 * Convert it to a writable page and it on to the dynamic mapper.
3217 */
3218 int rc;
3219 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
3220 if (RT_LIKELY(pPage))
3221 {
3222 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3223 if (RT_SUCCESS(rc))
3224 {
3225 void *pv;
3226 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
3227 if (RT_SUCCESS(rc))
3228 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
3229 }
3230 else
3231 AssertRC(rc);
3232 }
3233 else
3234 {
3235 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
3236 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3237 }
3238
3239 pgmUnlock(pVM);
3240 return rc;
3241}
3242
3243#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3244#if !defined(IN_R0) || defined(LOG_ENABLED)
3245
3246/** Format handler for PGMPAGE.
3247 * @copydoc FNRTSTRFORMATTYPE */
3248static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3249 const char *pszType, void const *pvValue,
3250 int cchWidth, int cchPrecision, unsigned fFlags,
3251 void *pvUser)
3252{
3253 size_t cch;
3254 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3255 if (RT_VALID_PTR(pPage))
3256 {
3257 char szTmp[64+80];
3258
3259 cch = 0;
3260
3261 /* The single char state stuff. */
3262 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3263 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3264
3265#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
3266 if (IS_PART_INCLUDED(5))
3267 {
3268 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
3269 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
3270 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
3271 }
3272
3273 /* The type. */
3274 if (IS_PART_INCLUDED(4))
3275 {
3276 szTmp[cch++] = ':';
3277 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3278 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3279 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3280 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3281 }
3282
3283 /* The numbers. */
3284 if (IS_PART_INCLUDED(3))
3285 {
3286 szTmp[cch++] = ':';
3287 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
3288 }
3289
3290 if (IS_PART_INCLUDED(2))
3291 {
3292 szTmp[cch++] = ':';
3293 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
3294 }
3295
3296 if (IS_PART_INCLUDED(6))
3297 {
3298 szTmp[cch++] = ':';
3299 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3300 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3301 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
3302 }
3303#undef IS_PART_INCLUDED
3304
3305 cch = pfnOutput(pvArgOutput, szTmp, cch);
3306 }
3307 else
3308 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3309 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3310 return cch;
3311}
3312
3313
3314/** Format handler for PGMRAMRANGE.
3315 * @copydoc FNRTSTRFORMATTYPE */
3316static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3317 const char *pszType, void const *pvValue,
3318 int cchWidth, int cchPrecision, unsigned fFlags,
3319 void *pvUser)
3320{
3321 size_t cch;
3322 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
3323 if (VALID_PTR(pRam))
3324 {
3325 char szTmp[80];
3326 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3327 cch = pfnOutput(pvArgOutput, szTmp, cch);
3328 }
3329 else
3330 cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3331 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3332 return cch;
3333}
3334
3335/** Format type andlers to be registered/deregistered. */
3336static const struct
3337{
3338 char szType[24];
3339 PFNRTSTRFORMATTYPE pfnHandler;
3340} g_aPgmFormatTypes[] =
3341{
3342 { "pgmpage", pgmFormatTypeHandlerPage },
3343 { "pgmramrange", pgmFormatTypeHandlerRamRange }
3344};
3345
3346#endif /* !IN_R0 || LOG_ENABLED */
3347
3348/**
3349 * Registers the global string format types.
3350 *
3351 * This should be called at module load time or in some other manner that ensure
3352 * that it's called exactly one time.
3353 *
3354 * @returns IPRT status code on RTStrFormatTypeRegister failure.
3355 */
3356VMMDECL(int) PGMRegisterStringFormatTypes(void)
3357{
3358#if !defined(IN_R0) || defined(LOG_ENABLED)
3359 int rc = VINF_SUCCESS;
3360 unsigned i;
3361 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3362 {
3363 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3364# ifdef IN_RING0
3365 if (rc == VERR_ALREADY_EXISTS)
3366 {
3367 /* in case of cleanup failure in ring-0 */
3368 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3369 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
3370 }
3371# endif
3372 }
3373 if (RT_FAILURE(rc))
3374 while (i-- > 0)
3375 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3376
3377 return rc;
3378#else
3379 return VINF_SUCCESS;
3380#endif
3381}
3382
3383
3384/**
3385 * Deregisters the global string format types.
3386 *
3387 * This should be called at module unload time or in some other manner that
3388 * ensure that it's called exactly one time.
3389 */
3390VMMDECL(void) PGMDeregisterStringFormatTypes(void)
3391{
3392#if !defined(IN_R0) || defined(LOG_ENABLED)
3393 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
3394 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
3395#endif
3396}
3397
3398#ifdef VBOX_STRICT
3399
3400/**
3401 * Asserts that there are no mapping conflicts.
3402 *
3403 * @returns Number of conflicts.
3404 * @param pVM The cross context VM structure.
3405 */
3406VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
3407{
3408 unsigned cErrors = 0;
3409
3410 /* Only applies to raw mode -> 1 VPCU */
3411 Assert(pVM->cCpus == 1);
3412 PVMCPU pVCpu = &pVM->aCpus[0];
3413
3414 /*
3415 * Check for mapping conflicts.
3416 */
3417 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3418 pMapping;
3419 pMapping = pMapping->CTX_SUFF(pNext))
3420 {
3421 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
3422 for (RTGCPTR GCPtr = pMapping->GCPtr;
3423 GCPtr <= pMapping->GCPtrLast;
3424 GCPtr += PAGE_SIZE)
3425 {
3426 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
3427 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
3428 {
3429 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
3430 cErrors++;
3431 break;
3432 }
3433 }
3434 }
3435
3436 return cErrors;
3437}
3438
3439
3440/**
3441 * Asserts that everything related to the guest CR3 is correctly shadowed.
3442 *
3443 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
3444 * and assert the correctness of the guest CR3 mapping before asserting that the
3445 * shadow page tables is in sync with the guest page tables.
3446 *
3447 * @returns Number of conflicts.
3448 * @param pVM The cross context VM structure.
3449 * @param pVCpu The cross context virtual CPU structure.
3450 * @param cr3 The current guest CR3 register value.
3451 * @param cr4 The current guest CR4 register value.
3452 */
3453VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
3454{
3455 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3456
3457 uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
3458 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
3459 AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
3460
3461 pgmLock(pVM);
3462 unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
3463 pgmUnlock(pVM);
3464
3465 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
3466 return cErrors;
3467}
3468
3469#endif /* VBOX_STRICT */
3470
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