VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 42699

Last change on this file since 42699 was 41965, checked in by vboxsync, 12 years ago

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1/* $Id: PGMAll.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/iom.h>
26#include <VBox/sup.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/vmm/csam.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/trpm.h>
32#ifdef VBOX_WITH_REM
33# include <VBox/vmm/rem.h>
34#endif
35#include <VBox/vmm/em.h>
36#include <VBox/vmm/hwaccm.h>
37#include <VBox/vmm/hwacc_vmx.h>
38#include "PGMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "PGMInline.h"
41#include <iprt/assert.h>
42#include <iprt/asm-amd64-x86.h>
43#include <iprt/string.h>
44#include <VBox/log.h>
45#include <VBox/param.h>
46#include <VBox/err.h>
47
48
49/*******************************************************************************
50* Structures and Typedefs *
51*******************************************************************************/
52/**
53 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
54 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
55 */
56typedef struct PGMHVUSTATE
57{
58 /** Pointer to the VM. */
59 PVM pVM;
60 /** Pointer to the VMCPU. */
61 PVMCPU pVCpu;
62 /** The todo flags. */
63 RTUINT fTodo;
64 /** The CR4 register value. */
65 uint32_t cr4;
66} PGMHVUSTATE, *PPGMHVUSTATE;
67
68
69/*******************************************************************************
70* Internal Functions *
71*******************************************************************************/
72DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
73DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
74#ifndef IN_RC
75static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
76static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
77#endif
78
79
80/*
81 * Shadow - 32-bit mode
82 */
83#define PGM_SHW_TYPE PGM_TYPE_32BIT
84#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
85#include "PGMAllShw.h"
86
87/* Guest - real mode */
88#define PGM_GST_TYPE PGM_TYPE_REAL
89#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
90#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
91#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
92#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
93#include "PGMGstDefs.h"
94#include "PGMAllGst.h"
95#include "PGMAllBth.h"
96#undef BTH_PGMPOOLKIND_PT_FOR_PT
97#undef BTH_PGMPOOLKIND_ROOT
98#undef PGM_BTH_NAME
99#undef PGM_GST_TYPE
100#undef PGM_GST_NAME
101
102/* Guest - protected mode */
103#define PGM_GST_TYPE PGM_TYPE_PROT
104#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
105#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
106#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
107#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
108#include "PGMGstDefs.h"
109#include "PGMAllGst.h"
110#include "PGMAllBth.h"
111#undef BTH_PGMPOOLKIND_PT_FOR_PT
112#undef BTH_PGMPOOLKIND_ROOT
113#undef PGM_BTH_NAME
114#undef PGM_GST_TYPE
115#undef PGM_GST_NAME
116
117/* Guest - 32-bit mode */
118#define PGM_GST_TYPE PGM_TYPE_32BIT
119#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
120#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
121#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
122#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
123#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
124#include "PGMGstDefs.h"
125#include "PGMAllGst.h"
126#include "PGMAllBth.h"
127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
128#undef BTH_PGMPOOLKIND_PT_FOR_PT
129#undef BTH_PGMPOOLKIND_ROOT
130#undef PGM_BTH_NAME
131#undef PGM_GST_TYPE
132#undef PGM_GST_NAME
133
134#undef PGM_SHW_TYPE
135#undef PGM_SHW_NAME
136
137
138/*
139 * Shadow - PAE mode
140 */
141#define PGM_SHW_TYPE PGM_TYPE_PAE
142#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
143#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
144#include "PGMAllShw.h"
145
146/* Guest - real mode */
147#define PGM_GST_TYPE PGM_TYPE_REAL
148#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
149#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
150#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
151#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
152#include "PGMGstDefs.h"
153#include "PGMAllBth.h"
154#undef BTH_PGMPOOLKIND_PT_FOR_PT
155#undef BTH_PGMPOOLKIND_ROOT
156#undef PGM_BTH_NAME
157#undef PGM_GST_TYPE
158#undef PGM_GST_NAME
159
160/* Guest - protected mode */
161#define PGM_GST_TYPE PGM_TYPE_PROT
162#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
163#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
164#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
165#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
166#include "PGMGstDefs.h"
167#include "PGMAllBth.h"
168#undef BTH_PGMPOOLKIND_PT_FOR_PT
169#undef BTH_PGMPOOLKIND_ROOT
170#undef PGM_BTH_NAME
171#undef PGM_GST_TYPE
172#undef PGM_GST_NAME
173
174/* Guest - 32-bit mode */
175#define PGM_GST_TYPE PGM_TYPE_32BIT
176#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
177#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
178#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
179#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
180#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
181#include "PGMGstDefs.h"
182#include "PGMAllBth.h"
183#undef BTH_PGMPOOLKIND_PT_FOR_BIG
184#undef BTH_PGMPOOLKIND_PT_FOR_PT
185#undef BTH_PGMPOOLKIND_ROOT
186#undef PGM_BTH_NAME
187#undef PGM_GST_TYPE
188#undef PGM_GST_NAME
189
190
191/* Guest - PAE mode */
192#define PGM_GST_TYPE PGM_TYPE_PAE
193#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
194#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
195#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
196#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
197#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
198#include "PGMGstDefs.h"
199#include "PGMAllGst.h"
200#include "PGMAllBth.h"
201#undef BTH_PGMPOOLKIND_PT_FOR_BIG
202#undef BTH_PGMPOOLKIND_PT_FOR_PT
203#undef BTH_PGMPOOLKIND_ROOT
204#undef PGM_BTH_NAME
205#undef PGM_GST_TYPE
206#undef PGM_GST_NAME
207
208#undef PGM_SHW_TYPE
209#undef PGM_SHW_NAME
210
211
212#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
213/*
214 * Shadow - AMD64 mode
215 */
216# define PGM_SHW_TYPE PGM_TYPE_AMD64
217# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
218# include "PGMAllShw.h"
219
220/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
221# define PGM_GST_TYPE PGM_TYPE_PROT
222# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
223# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
224# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
225# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
226# include "PGMGstDefs.h"
227# include "PGMAllBth.h"
228# undef BTH_PGMPOOLKIND_PT_FOR_PT
229# undef BTH_PGMPOOLKIND_ROOT
230# undef PGM_BTH_NAME
231# undef PGM_GST_TYPE
232# undef PGM_GST_NAME
233
234# ifdef VBOX_WITH_64_BITS_GUESTS
235/* Guest - AMD64 mode */
236# define PGM_GST_TYPE PGM_TYPE_AMD64
237# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
238# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
239# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
240# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
241# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
242# include "PGMGstDefs.h"
243# include "PGMAllGst.h"
244# include "PGMAllBth.h"
245# undef BTH_PGMPOOLKIND_PT_FOR_BIG
246# undef BTH_PGMPOOLKIND_PT_FOR_PT
247# undef BTH_PGMPOOLKIND_ROOT
248# undef PGM_BTH_NAME
249# undef PGM_GST_TYPE
250# undef PGM_GST_NAME
251# endif /* VBOX_WITH_64_BITS_GUESTS */
252
253# undef PGM_SHW_TYPE
254# undef PGM_SHW_NAME
255
256
257/*
258 * Shadow - Nested paging mode
259 */
260# define PGM_SHW_TYPE PGM_TYPE_NESTED
261# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
262# include "PGMAllShw.h"
263
264/* Guest - real mode */
265# define PGM_GST_TYPE PGM_TYPE_REAL
266# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
267# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
268# include "PGMGstDefs.h"
269# include "PGMAllBth.h"
270# undef PGM_BTH_NAME
271# undef PGM_GST_TYPE
272# undef PGM_GST_NAME
273
274/* Guest - protected mode */
275# define PGM_GST_TYPE PGM_TYPE_PROT
276# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
277# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
278# include "PGMGstDefs.h"
279# include "PGMAllBth.h"
280# undef PGM_BTH_NAME
281# undef PGM_GST_TYPE
282# undef PGM_GST_NAME
283
284/* Guest - 32-bit mode */
285# define PGM_GST_TYPE PGM_TYPE_32BIT
286# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
287# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
288# include "PGMGstDefs.h"
289# include "PGMAllBth.h"
290# undef PGM_BTH_NAME
291# undef PGM_GST_TYPE
292# undef PGM_GST_NAME
293
294/* Guest - PAE mode */
295# define PGM_GST_TYPE PGM_TYPE_PAE
296# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
297# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
298# include "PGMGstDefs.h"
299# include "PGMAllBth.h"
300# undef PGM_BTH_NAME
301# undef PGM_GST_TYPE
302# undef PGM_GST_NAME
303
304# ifdef VBOX_WITH_64_BITS_GUESTS
305/* Guest - AMD64 mode */
306# define PGM_GST_TYPE PGM_TYPE_AMD64
307# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
308# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
309# include "PGMGstDefs.h"
310# include "PGMAllBth.h"
311# undef PGM_BTH_NAME
312# undef PGM_GST_TYPE
313# undef PGM_GST_NAME
314# endif /* VBOX_WITH_64_BITS_GUESTS */
315
316# undef PGM_SHW_TYPE
317# undef PGM_SHW_NAME
318
319
320/*
321 * Shadow - EPT
322 */
323# define PGM_SHW_TYPE PGM_TYPE_EPT
324# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
325# include "PGMAllShw.h"
326
327/* Guest - real mode */
328# define PGM_GST_TYPE PGM_TYPE_REAL
329# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
330# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
331# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
332# include "PGMGstDefs.h"
333# include "PGMAllBth.h"
334# undef BTH_PGMPOOLKIND_PT_FOR_PT
335# undef PGM_BTH_NAME
336# undef PGM_GST_TYPE
337# undef PGM_GST_NAME
338
339/* Guest - protected mode */
340# define PGM_GST_TYPE PGM_TYPE_PROT
341# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
342# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
343# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
344# include "PGMGstDefs.h"
345# include "PGMAllBth.h"
346# undef BTH_PGMPOOLKIND_PT_FOR_PT
347# undef PGM_BTH_NAME
348# undef PGM_GST_TYPE
349# undef PGM_GST_NAME
350
351/* Guest - 32-bit mode */
352# define PGM_GST_TYPE PGM_TYPE_32BIT
353# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
354# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
355# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
356# include "PGMGstDefs.h"
357# include "PGMAllBth.h"
358# undef BTH_PGMPOOLKIND_PT_FOR_PT
359# undef PGM_BTH_NAME
360# undef PGM_GST_TYPE
361# undef PGM_GST_NAME
362
363/* Guest - PAE mode */
364# define PGM_GST_TYPE PGM_TYPE_PAE
365# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
366# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
367# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
368# include "PGMGstDefs.h"
369# include "PGMAllBth.h"
370# undef BTH_PGMPOOLKIND_PT_FOR_PT
371# undef PGM_BTH_NAME
372# undef PGM_GST_TYPE
373# undef PGM_GST_NAME
374
375# ifdef VBOX_WITH_64_BITS_GUESTS
376/* Guest - AMD64 mode */
377# define PGM_GST_TYPE PGM_TYPE_AMD64
378# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
379# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
380# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
381# include "PGMGstDefs.h"
382# include "PGMAllBth.h"
383# undef BTH_PGMPOOLKIND_PT_FOR_PT
384# undef PGM_BTH_NAME
385# undef PGM_GST_TYPE
386# undef PGM_GST_NAME
387# endif /* VBOX_WITH_64_BITS_GUESTS */
388
389# undef PGM_SHW_TYPE
390# undef PGM_SHW_NAME
391
392#endif /* !IN_RC */
393
394
395#ifndef IN_RING3
396/**
397 * #PF Handler.
398 *
399 * @returns VBox status code (appropriate for trap handling and GC return).
400 * @param pVCpu Pointer to the VMCPU.
401 * @param uErr The trap error code.
402 * @param pRegFrame Trap register frame.
403 * @param pvFault The fault address.
404 */
405VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
406{
407 PVM pVM = pVCpu->CTX_SUFF(pVM);
408
409 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
410 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
411 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
412
413
414#ifdef VBOX_WITH_STATISTICS
415 /*
416 * Error code stats.
417 */
418 if (uErr & X86_TRAP_PF_US)
419 {
420 if (!(uErr & X86_TRAP_PF_P))
421 {
422 if (uErr & X86_TRAP_PF_RW)
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
424 else
425 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
426 }
427 else if (uErr & X86_TRAP_PF_RW)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
429 else if (uErr & X86_TRAP_PF_RSVD)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
431 else if (uErr & X86_TRAP_PF_ID)
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
433 else
434 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
435 }
436 else
437 { /* Supervisor */
438 if (!(uErr & X86_TRAP_PF_P))
439 {
440 if (uErr & X86_TRAP_PF_RW)
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
442 else
443 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
444 }
445 else if (uErr & X86_TRAP_PF_RW)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
447 else if (uErr & X86_TRAP_PF_ID)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
449 else if (uErr & X86_TRAP_PF_RSVD)
450 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
451 }
452#endif /* VBOX_WITH_STATISTICS */
453
454 /*
455 * Call the worker.
456 */
457 bool fLockTaken = false;
458 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
459 if (fLockTaken)
460 {
461 PGM_LOCK_ASSERT_OWNER(pVM);
462 pgmUnlock(pVM);
463 }
464 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
465
466 /*
467 * Return code tweaks.
468 */
469 if (rc != VINF_SUCCESS)
470 {
471 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
472 rc = VINF_SUCCESS;
473
474# ifdef IN_RING0
475 /* Note: hack alert for difficult to reproduce problem. */
476 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
477 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
478 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
479 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
480 {
481 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
482 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
483 rc = VINF_SUCCESS;
484 }
485# endif
486 }
487
488 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
489 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
490 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
491 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
492 return rc;
493}
494#endif /* !IN_RING3 */
495
496
497/**
498 * Prefetch a page
499 *
500 * Typically used to sync commonly used pages before entering raw mode
501 * after a CR3 reload.
502 *
503 * @returns VBox status code suitable for scheduling.
504 * @retval VINF_SUCCESS on success.
505 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
506 * @param pVCpu Pointer to the VMCPU.
507 * @param GCPtrPage Page to invalidate.
508 */
509VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
510{
511 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
514 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
515 return rc;
516}
517
518
519/**
520 * Gets the mapping corresponding to the specified address (if any).
521 *
522 * @returns Pointer to the mapping.
523 * @returns NULL if not
524 *
525 * @param pVM Pointer to the VM.
526 * @param GCPtr The guest context pointer.
527 */
528PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
529{
530 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
531 while (pMapping)
532 {
533 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
534 break;
535 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
536 return pMapping;
537 pMapping = pMapping->CTX_SUFF(pNext);
538 }
539 return NULL;
540}
541
542
543/**
544 * Verifies a range of pages for read or write access
545 *
546 * Only checks the guest's page tables
547 *
548 * @returns VBox status code.
549 * @param pVCpu Pointer to the VMCPU.
550 * @param Addr Guest virtual address to check
551 * @param cbSize Access size
552 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
553 * @remarks Current not in use.
554 */
555VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
556{
557 /*
558 * Validate input.
559 */
560 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
561 {
562 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
563 return VERR_INVALID_PARAMETER;
564 }
565
566 uint64_t fPage;
567 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
568 if (RT_FAILURE(rc))
569 {
570 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
571 return VINF_EM_RAW_GUEST_TRAP;
572 }
573
574 /*
575 * Check if the access would cause a page fault
576 *
577 * Note that hypervisor page directories are not present in the guest's tables, so this check
578 * is sufficient.
579 */
580 bool fWrite = !!(fAccess & X86_PTE_RW);
581 bool fUser = !!(fAccess & X86_PTE_US);
582 if ( !(fPage & X86_PTE_P)
583 || (fWrite && !(fPage & X86_PTE_RW))
584 || (fUser && !(fPage & X86_PTE_US)) )
585 {
586 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
587 return VINF_EM_RAW_GUEST_TRAP;
588 }
589 if ( RT_SUCCESS(rc)
590 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
591 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
592 return rc;
593}
594
595
596/**
597 * Verifies a range of pages for read or write access
598 *
599 * Supports handling of pages marked for dirty bit tracking and CSAM
600 *
601 * @returns VBox status code.
602 * @param pVCpu Pointer to the VMCPU.
603 * @param Addr Guest virtual address to check
604 * @param cbSize Access size
605 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
606 */
607VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
608{
609 PVM pVM = pVCpu->CTX_SUFF(pVM);
610
611 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
612
613 /*
614 * Get going.
615 */
616 uint64_t fPageGst;
617 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
618 if (RT_FAILURE(rc))
619 {
620 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
621 return VINF_EM_RAW_GUEST_TRAP;
622 }
623
624 /*
625 * Check if the access would cause a page fault
626 *
627 * Note that hypervisor page directories are not present in the guest's tables, so this check
628 * is sufficient.
629 */
630 const bool fWrite = !!(fAccess & X86_PTE_RW);
631 const bool fUser = !!(fAccess & X86_PTE_US);
632 if ( !(fPageGst & X86_PTE_P)
633 || (fWrite && !(fPageGst & X86_PTE_RW))
634 || (fUser && !(fPageGst & X86_PTE_US)) )
635 {
636 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
637 return VINF_EM_RAW_GUEST_TRAP;
638 }
639
640 if (!pVM->pgm.s.fNestedPaging)
641 {
642 /*
643 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
644 */
645 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
646 if ( rc == VERR_PAGE_NOT_PRESENT
647 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
648 {
649 /*
650 * Page is not present in our page tables.
651 * Try to sync it!
652 */
653 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
654 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
655 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
656 if (rc != VINF_SUCCESS)
657 return rc;
658 }
659 else
660 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
661 }
662
663#if 0 /* def VBOX_STRICT; triggers too often now */
664 /*
665 * This check is a bit paranoid, but useful.
666 */
667 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
668 uint64_t fPageShw;
669 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
670 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
671 || (fWrite && !(fPageShw & X86_PTE_RW))
672 || (fUser && !(fPageShw & X86_PTE_US)) )
673 {
674 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
675 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
676 return VINF_EM_RAW_GUEST_TRAP;
677 }
678#endif
679
680 if ( RT_SUCCESS(rc)
681 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
682 || Addr + cbSize < Addr))
683 {
684 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
685 for (;;)
686 {
687 Addr += PAGE_SIZE;
688 if (cbSize > PAGE_SIZE)
689 cbSize -= PAGE_SIZE;
690 else
691 cbSize = 1;
692 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
693 if (rc != VINF_SUCCESS)
694 break;
695 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
696 break;
697 }
698 }
699 return rc;
700}
701
702
703/**
704 * Emulation of the invlpg instruction (HC only actually).
705 *
706 * @returns Strict VBox status code, special care required.
707 * @retval VINF_PGM_SYNC_CR3 - handled.
708 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
709 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
710 *
711 * @param pVCpu Pointer to the VMCPU.
712 * @param GCPtrPage Page to invalidate.
713 *
714 * @remark ASSUMES the page table entry or page directory is valid. Fairly
715 * safe, but there could be edge cases!
716 *
717 * @todo Flush page or page directory only if necessary!
718 * @todo VBOXSTRICTRC
719 */
720VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
721{
722 PVM pVM = pVCpu->CTX_SUFF(pVM);
723 int rc;
724 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
725
726#if !defined(IN_RING3) && defined(VBOX_WITH_REM)
727 /*
728 * Notify the recompiler so it can record this instruction.
729 */
730 REMNotifyInvalidatePage(pVM, GCPtrPage);
731#endif /* !IN_RING3 */
732
733
734#ifdef IN_RC
735 /*
736 * Check for conflicts and pending CR3 monitoring updates.
737 */
738 if (pgmMapAreMappingsFloating(pVM))
739 {
740 if ( pgmGetMapping(pVM, GCPtrPage)
741 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
742 {
743 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
744 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
745 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
746 return VINF_PGM_SYNC_CR3;
747 }
748
749 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
750 {
751 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
752 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
753 return VINF_EM_RAW_EMULATE_INSTR;
754 }
755 }
756#endif /* IN_RC */
757
758 /*
759 * Call paging mode specific worker.
760 */
761 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
762 pgmLock(pVM);
763 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
764 pgmUnlock(pVM);
765 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
766
767#ifdef IN_RING3
768 /*
769 * Check if we have a pending update of the CR3 monitoring.
770 */
771 if ( RT_SUCCESS(rc)
772 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
773 {
774 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
775 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
776 }
777
778 /*
779 * Inform CSAM about the flush
780 *
781 * Note: This is to check if monitored pages have been changed; when we implement
782 * callbacks for virtual handlers, this is no longer required.
783 */
784 CSAMR3FlushPage(pVM, GCPtrPage);
785#endif /* IN_RING3 */
786
787 /* Ignore all irrelevant error codes. */
788 if ( rc == VERR_PAGE_NOT_PRESENT
789 || rc == VERR_PAGE_TABLE_NOT_PRESENT
790 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
791 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
792 rc = VINF_SUCCESS;
793
794 return rc;
795}
796
797
798/**
799 * Executes an instruction using the interpreter.
800 *
801 * @returns VBox status code (appropriate for trap handling and GC return).
802 * @param pVM Pointer to the VM.
803 * @param pVCpu Pointer to the VMCPU.
804 * @param pRegFrame Register frame.
805 * @param pvFault Fault address.
806 */
807VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
808{
809 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, pRegFrame, pvFault);
810 if (rc == VERR_EM_INTERPRETER)
811 rc = VINF_EM_RAW_EMULATE_INSTR;
812 if (rc != VINF_SUCCESS)
813 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
814 return rc;
815}
816
817
818/**
819 * Gets effective page information (from the VMM page directory).
820 *
821 * @returns VBox status.
822 * @param pVCpu Pointer to the VMCPU.
823 * @param GCPtr Guest Context virtual address of the page.
824 * @param pfFlags Where to store the flags. These are X86_PTE_*.
825 * @param pHCPhys Where to store the HC physical address of the page.
826 * This is page aligned.
827 * @remark You should use PGMMapGetPage() for pages in a mapping.
828 */
829VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
830{
831 pgmLock(pVCpu->CTX_SUFF(pVM));
832 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
833 pgmUnlock(pVCpu->CTX_SUFF(pVM));
834 return rc;
835}
836
837
838/**
839 * Modify page flags for a range of pages in the shadow context.
840 *
841 * The existing flags are ANDed with the fMask and ORed with the fFlags.
842 *
843 * @returns VBox status code.
844 * @param pVCpu Pointer to the VMCPU.
845 * @param GCPtr Virtual address of the first page in the range.
846 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
847 * @param fMask The AND mask - page flags X86_PTE_*.
848 * Be very CAREFUL when ~'ing constants which could be 32-bit!
849 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
850 * @remark You must use PGMMapModifyPage() for pages in a mapping.
851 */
852DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
853{
854 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
855 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
856
857 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
858
859 PVM pVM = pVCpu->CTX_SUFF(pVM);
860 pgmLock(pVM);
861 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
862 pgmUnlock(pVM);
863 return rc;
864}
865
866
867/**
868 * Changing the page flags for a single page in the shadow page tables so as to
869 * make it read-only.
870 *
871 * @returns VBox status code.
872 * @param pVCpu Pointer to the VMCPU.
873 * @param GCPtr Virtual address of the first page in the range.
874 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
875 */
876VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
877{
878 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
879}
880
881
882/**
883 * Changing the page flags for a single page in the shadow page tables so as to
884 * make it writable.
885 *
886 * The call must know with 101% certainty that the guest page tables maps this
887 * as writable too. This function will deal shared, zero and write monitored
888 * pages.
889 *
890 * @returns VBox status code.
891 * @param pVCpu Pointer to the VMCPU.
892 * @param GCPtr Virtual address of the first page in the range.
893 * @param fMmio2 Set if it is an MMIO2 page.
894 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
895 */
896VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
897{
898 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
899}
900
901
902/**
903 * Changing the page flags for a single page in the shadow page tables so as to
904 * make it not present.
905 *
906 * @returns VBox status code.
907 * @param pVCpu Pointer to the VMCPU.
908 * @param GCPtr Virtual address of the first page in the range.
909 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
910 */
911VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
912{
913 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
914}
915
916
917/**
918 * Gets the shadow page directory for the specified address, PAE.
919 *
920 * @returns Pointer to the shadow PD.
921 * @param pVCpu Pointer to the VMCPU.
922 * @param GCPtr The address.
923 * @param uGstPdpe Guest PDPT entry. Valid.
924 * @param ppPD Receives address of page directory
925 */
926int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
927{
928 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
929 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
930 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
931 PVM pVM = pVCpu->CTX_SUFF(pVM);
932 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
933 PPGMPOOLPAGE pShwPage;
934 int rc;
935
936 PGM_LOCK_ASSERT_OWNER(pVM);
937
938 /* Allocate page directory if not present. */
939 if ( !pPdpe->n.u1Present
940 && !(pPdpe->u & X86_PDPE_PG_MASK))
941 {
942 RTGCPTR64 GCPdPt;
943 PGMPOOLKIND enmKind;
944
945 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
946 {
947 /* AMD-V nested paging or real/protected mode without paging. */
948 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
949 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
950 }
951 else
952 {
953 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
954 {
955 if (!(uGstPdpe & X86_PDPE_P))
956 {
957 /* PD not present; guest must reload CR3 to change it.
958 * No need to monitor anything in this case.
959 */
960 Assert(!HWACCMIsEnabled(pVM));
961
962 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
963 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
964 uGstPdpe |= X86_PDPE_P;
965 }
966 else
967 {
968 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
969 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
970 }
971 }
972 else
973 {
974 GCPdPt = CPUMGetGuestCR3(pVCpu);
975 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
976 }
977 }
978
979 /* Create a reference back to the PDPT by using the index in its shadow page. */
980 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
981 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /*fLockPage*/,
982 &pShwPage);
983 AssertRCReturn(rc, rc);
984
985 /* The PD was cached or created; hook it up now. */
986 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
987
988# if defined(IN_RC)
989 /*
990 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
991 * PDPT entry; the CPU fetches them only during cr3 load, so any
992 * non-present PDPT will continue to cause page faults.
993 */
994 ASMReloadCR3();
995# endif
996 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
997 }
998 else
999 {
1000 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1001 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1002 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1003
1004 pgmPoolCacheUsed(pPool, pShwPage);
1005 }
1006 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1007 return VINF_SUCCESS;
1008}
1009
1010
1011/**
1012 * Gets the pointer to the shadow page directory entry for an address, PAE.
1013 *
1014 * @returns Pointer to the PDE.
1015 * @param pVCpu The current CPU.
1016 * @param GCPtr The address.
1017 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1018 */
1019DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1020{
1021 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1022 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1023 PVM pVM = pVCpu->CTX_SUFF(pVM);
1024
1025 PGM_LOCK_ASSERT_OWNER(pVM);
1026
1027 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1028 if (!pPdpt->a[iPdPt].n.u1Present)
1029 {
1030 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1031 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1032 }
1033 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1034
1035 /* Fetch the pgm pool shadow descriptor. */
1036 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1037 AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1038
1039 *ppShwPde = pShwPde;
1040 return VINF_SUCCESS;
1041}
1042
1043#ifndef IN_RC
1044
1045/**
1046 * Syncs the SHADOW page directory pointer for the specified address.
1047 *
1048 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1049 *
1050 * The caller is responsible for making sure the guest has a valid PD before
1051 * calling this function.
1052 *
1053 * @returns VBox status.
1054 * @param pVCpu Pointer to the VMCPU.
1055 * @param GCPtr The address.
1056 * @param uGstPml4e Guest PML4 entry (valid).
1057 * @param uGstPdpe Guest PDPT entry (valid).
1058 * @param ppPD Receives address of page directory
1059 */
1060static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1061{
1062 PVM pVM = pVCpu->CTX_SUFF(pVM);
1063 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1064 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1065 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1066 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1067 PPGMPOOLPAGE pShwPage;
1068 int rc;
1069
1070 PGM_LOCK_ASSERT_OWNER(pVM);
1071
1072 /* Allocate page directory pointer table if not present. */
1073 if ( !pPml4e->n.u1Present
1074 && !(pPml4e->u & X86_PML4E_PG_MASK))
1075 {
1076 RTGCPTR64 GCPml4;
1077 PGMPOOLKIND enmKind;
1078
1079 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1080
1081 if (fNestedPagingOrNoGstPaging)
1082 {
1083 /* AMD-V nested paging or real/protected mode without paging */
1084 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1085 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1086 }
1087 else
1088 {
1089 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1090 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1091 }
1092
1093 /* Create a reference back to the PDPT by using the index in its shadow page. */
1094 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1095 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /*fLockPage*/,
1096 &pShwPage);
1097 AssertRCReturn(rc, rc);
1098 }
1099 else
1100 {
1101 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1102 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1103
1104 pgmPoolCacheUsed(pPool, pShwPage);
1105 }
1106 /* The PDPT was cached or created; hook it up now. */
1107 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1108
1109 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1110 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1111 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1112
1113 /* Allocate page directory if not present. */
1114 if ( !pPdpe->n.u1Present
1115 && !(pPdpe->u & X86_PDPE_PG_MASK))
1116 {
1117 RTGCPTR64 GCPdPt;
1118 PGMPOOLKIND enmKind;
1119
1120 if (fNestedPagingOrNoGstPaging)
1121 {
1122 /* AMD-V nested paging or real/protected mode without paging */
1123 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1124 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1125 }
1126 else
1127 {
1128 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1129 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1130 }
1131
1132 /* Create a reference back to the PDPT by using the index in its shadow page. */
1133 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1134 pShwPage->idx, iPdPt, false /*fLockPage*/,
1135 &pShwPage);
1136 AssertRCReturn(rc, rc);
1137 }
1138 else
1139 {
1140 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1141 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1142
1143 pgmPoolCacheUsed(pPool, pShwPage);
1144 }
1145 /* The PD was cached or created; hook it up now. */
1146 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1147
1148 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1149 return VINF_SUCCESS;
1150}
1151
1152
1153/**
1154 * Gets the SHADOW page directory pointer for the specified address (long mode).
1155 *
1156 * @returns VBox status.
1157 * @param pVCpu Pointer to the VMCPU.
1158 * @param GCPtr The address.
1159 * @param ppPdpt Receives address of pdpt
1160 * @param ppPD Receives address of page directory
1161 */
1162DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1163{
1164 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1165 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1166
1167 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1168
1169 AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1170 if (ppPml4e)
1171 *ppPml4e = (PX86PML4E)pPml4e;
1172
1173 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1174
1175 if (!pPml4e->n.u1Present)
1176 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1177
1178 PVM pVM = pVCpu->CTX_SUFF(pVM);
1179 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1180 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1181 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1182
1183 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1184 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1185 if (!pPdpt->a[iPdPt].n.u1Present)
1186 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1187
1188 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1189 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1190
1191 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1192 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1193 return VINF_SUCCESS;
1194}
1195
1196
1197/**
1198 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1199 * backing pages in case the PDPT or PML4 entry is missing.
1200 *
1201 * @returns VBox status.
1202 * @param pVCpu Pointer to the VMCPU.
1203 * @param GCPtr The address.
1204 * @param ppPdpt Receives address of pdpt
1205 * @param ppPD Receives address of page directory
1206 */
1207static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1208{
1209 PVM pVM = pVCpu->CTX_SUFF(pVM);
1210 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1211 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1212 PEPTPML4 pPml4;
1213 PEPTPML4E pPml4e;
1214 PPGMPOOLPAGE pShwPage;
1215 int rc;
1216
1217 Assert(pVM->pgm.s.fNestedPaging);
1218 PGM_LOCK_ASSERT_OWNER(pVM);
1219
1220 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1221 Assert(pPml4);
1222
1223 /* Allocate page directory pointer table if not present. */
1224 pPml4e = &pPml4->a[iPml4];
1225 if ( !pPml4e->n.u1Present
1226 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1227 {
1228 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1229 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1230
1231 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1232 PGMPOOL_IDX_NESTED_ROOT, iPml4, false /*fLockPage*/,
1233 &pShwPage);
1234 AssertRCReturn(rc, rc);
1235 }
1236 else
1237 {
1238 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1239 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1240
1241 pgmPoolCacheUsed(pPool, pShwPage);
1242 }
1243 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1244 pPml4e->u = pShwPage->Core.Key;
1245 pPml4e->n.u1Present = 1;
1246 pPml4e->n.u1Write = 1;
1247 pPml4e->n.u1Execute = 1;
1248
1249 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1250 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1251 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1252
1253 if (ppPdpt)
1254 *ppPdpt = pPdpt;
1255
1256 /* Allocate page directory if not present. */
1257 if ( !pPdpe->n.u1Present
1258 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1259 {
1260 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1261 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1262 pShwPage->idx, iPdPt, false /*fLockPage*/,
1263 &pShwPage);
1264 AssertRCReturn(rc, rc);
1265 }
1266 else
1267 {
1268 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1269 AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1270
1271 pgmPoolCacheUsed(pPool, pShwPage);
1272 }
1273 /* The PD was cached or created; hook it up now and fill with the default value. */
1274 pPdpe->u = pShwPage->Core.Key;
1275 pPdpe->n.u1Present = 1;
1276 pPdpe->n.u1Write = 1;
1277 pPdpe->n.u1Execute = 1;
1278
1279 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1280 return VINF_SUCCESS;
1281}
1282
1283#endif /* IN_RC */
1284
1285#ifdef IN_RING0
1286/**
1287 * Synchronizes a range of nested page table entries.
1288 *
1289 * The caller must own the PGM lock.
1290 *
1291 * @param pVCpu The current CPU.
1292 * @param GCPhys Where to start.
1293 * @param cPages How many pages which entries should be synced.
1294 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1295 * host paging mode for AMD-V).
1296 */
1297int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1298{
1299 PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1300
1301 int rc;
1302 switch (enmShwPagingMode)
1303 {
1304 case PGMMODE_32_BIT:
1305 {
1306 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1307 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1308 break;
1309 }
1310
1311 case PGMMODE_PAE:
1312 case PGMMODE_PAE_NX:
1313 {
1314 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1315 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1316 break;
1317 }
1318
1319 case PGMMODE_AMD64:
1320 case PGMMODE_AMD64_NX:
1321 {
1322 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1323 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1324 break;
1325 }
1326
1327 case PGMMODE_EPT:
1328 {
1329 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1330 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1331 break;
1332 }
1333
1334 default:
1335 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1336 }
1337 return rc;
1338}
1339#endif /* IN_RING0 */
1340
1341
1342/**
1343 * Gets effective Guest OS page information.
1344 *
1345 * When GCPtr is in a big page, the function will return as if it was a normal
1346 * 4KB page. If the need for distinguishing between big and normal page becomes
1347 * necessary at a later point, a PGMGstGetPage() will be created for that
1348 * purpose.
1349 *
1350 * @returns VBox status.
1351 * @param pVCpu The current CPU.
1352 * @param GCPtr Guest Context virtual address of the page.
1353 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1354 * @param pGCPhys Where to store the GC physical address of the page.
1355 * This is page aligned. The fact that the
1356 */
1357VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1358{
1359 VMCPU_ASSERT_EMT(pVCpu);
1360 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1361}
1362
1363
1364/**
1365 * Checks if the page is present.
1366 *
1367 * @returns true if the page is present.
1368 * @returns false if the page is not present.
1369 * @param pVCpu Pointer to the VMCPU.
1370 * @param GCPtr Address within the page.
1371 */
1372VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1373{
1374 VMCPU_ASSERT_EMT(pVCpu);
1375 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1376 return RT_SUCCESS(rc);
1377}
1378
1379
1380/**
1381 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1382 *
1383 * @returns VBox status.
1384 * @param pVCpu Pointer to the VMCPU.
1385 * @param GCPtr The address of the first page.
1386 * @param cb The size of the range in bytes.
1387 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1388 */
1389VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1390{
1391 VMCPU_ASSERT_EMT(pVCpu);
1392 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1393}
1394
1395
1396/**
1397 * Modify page flags for a range of pages in the guest's tables
1398 *
1399 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1400 *
1401 * @returns VBox status code.
1402 * @param pVCpu Pointer to the VMCPU.
1403 * @param GCPtr Virtual address of the first page in the range.
1404 * @param cb Size (in bytes) of the range to apply the modification to.
1405 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1406 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1407 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1408 */
1409VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1410{
1411 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1412 VMCPU_ASSERT_EMT(pVCpu);
1413
1414 /*
1415 * Validate input.
1416 */
1417 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1418 Assert(cb);
1419
1420 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1421
1422 /*
1423 * Adjust input.
1424 */
1425 cb += GCPtr & PAGE_OFFSET_MASK;
1426 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1427 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1428
1429 /*
1430 * Call worker.
1431 */
1432 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1433
1434 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1435 return rc;
1436}
1437
1438
1439#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1440
1441/**
1442 * Performs the lazy mapping of the 32-bit guest PD.
1443 *
1444 * @returns VBox status code.
1445 * @param pVCpu The current CPU.
1446 * @param ppPd Where to return the pointer to the mapping. This is
1447 * always set.
1448 */
1449int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1450{
1451 PVM pVM = pVCpu->CTX_SUFF(pVM);
1452 pgmLock(pVM);
1453
1454 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1455
1456 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1457 PPGMPAGE pPage;
1458 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1459 if (RT_SUCCESS(rc))
1460 {
1461 RTHCPTR HCPtrGuestCR3;
1462 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1463 if (RT_SUCCESS(rc))
1464 {
1465 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1466# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1467 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1468# endif
1469 *ppPd = (PX86PD)HCPtrGuestCR3;
1470
1471 pgmUnlock(pVM);
1472 return VINF_SUCCESS;
1473 }
1474
1475 AssertRC(rc);
1476 }
1477 pgmUnlock(pVM);
1478
1479 *ppPd = NULL;
1480 return rc;
1481}
1482
1483
1484/**
1485 * Performs the lazy mapping of the PAE guest PDPT.
1486 *
1487 * @returns VBox status code.
1488 * @param pVCpu The current CPU.
1489 * @param ppPdpt Where to return the pointer to the mapping. This is
1490 * always set.
1491 */
1492int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1493{
1494 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1495 PVM pVM = pVCpu->CTX_SUFF(pVM);
1496 pgmLock(pVM);
1497
1498 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1499 PPGMPAGE pPage;
1500 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1501 if (RT_SUCCESS(rc))
1502 {
1503 RTHCPTR HCPtrGuestCR3;
1504 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1505 if (RT_SUCCESS(rc))
1506 {
1507 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1508# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1509 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1510# endif
1511 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1512
1513 pgmUnlock(pVM);
1514 return VINF_SUCCESS;
1515 }
1516
1517 AssertRC(rc);
1518 }
1519
1520 pgmUnlock(pVM);
1521 *ppPdpt = NULL;
1522 return rc;
1523}
1524
1525
1526/**
1527 * Performs the lazy mapping / updating of a PAE guest PD.
1528 *
1529 * @returns Pointer to the mapping.
1530 * @returns VBox status code.
1531 * @param pVCpu The current CPU.
1532 * @param iPdpt Which PD entry to map (0..3).
1533 * @param ppPd Where to return the pointer to the mapping. This is
1534 * always set.
1535 */
1536int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1537{
1538 PVM pVM = pVCpu->CTX_SUFF(pVM);
1539 pgmLock(pVM);
1540
1541 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1542 Assert(pGuestPDPT);
1543 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1544 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1545 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1546
1547 PPGMPAGE pPage;
1548 int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1549 if (RT_SUCCESS(rc))
1550 {
1551 RTRCPTR RCPtr = NIL_RTRCPTR;
1552 RTHCPTR HCPtr = NIL_RTHCPTR;
1553#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1554 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, &HCPtr);
1555 AssertRC(rc);
1556#endif
1557 if (RT_SUCCESS(rc) && fChanged)
1558 {
1559 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1560 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1561 }
1562 if (RT_SUCCESS(rc))
1563 {
1564 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1565# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1566 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1567# endif
1568 if (fChanged)
1569 {
1570 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1571 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1572 }
1573
1574 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1575 pgmUnlock(pVM);
1576 return VINF_SUCCESS;
1577 }
1578 }
1579
1580 /* Invalid page or some failure, invalidate the entry. */
1581 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1582 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1583# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1584 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1585# endif
1586 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1587
1588 pgmUnlock(pVM);
1589 return rc;
1590}
1591
1592#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1593#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1594/**
1595 * Performs the lazy mapping of the 32-bit guest PD.
1596 *
1597 * @returns VBox status code.
1598 * @param pVCpu The current CPU.
1599 * @param ppPml4 Where to return the pointer to the mapping. This will
1600 * always be set.
1601 */
1602int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1603{
1604 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1605 PVM pVM = pVCpu->CTX_SUFF(pVM);
1606 pgmLock(pVM);
1607
1608 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1609 PPGMPAGE pPage;
1610 int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
1611 if (RT_SUCCESS(rc))
1612 {
1613 RTHCPTR HCPtrGuestCR3;
1614 rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1615 if (RT_SUCCESS(rc))
1616 {
1617 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1618# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1619 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1620# endif
1621 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1622
1623 pgmUnlock(pVM);
1624 return VINF_SUCCESS;
1625 }
1626 }
1627
1628 pgmUnlock(pVM);
1629 *ppPml4 = NULL;
1630 return rc;
1631}
1632#endif
1633
1634
1635/**
1636 * Gets the PAE PDPEs values cached by the CPU.
1637 *
1638 * @returns VBox status code.
1639 * @param pVCpu The virtual CPU.
1640 * @param paPdpes Where to return the four PDPEs. The array
1641 * pointed to must have 4 entries.
1642 */
1643VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes)
1644{
1645 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1646
1647 paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
1648 paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
1649 paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
1650 paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
1651 return VINF_SUCCESS;
1652}
1653
1654
1655/**
1656 * Sets the PAE PDPEs values cached by the CPU.
1657 *
1658 * @remarks This must be called *AFTER* PGMUpdateCR3.
1659 *
1660 * @returns VBox status code.
1661 * @param pVCpu The virtual CPU.
1662 * @param paPdpes The four PDPE values. The array pointed to
1663 * must have exactly 4 entries.
1664 */
1665VMM_INT_DECL(int) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes)
1666{
1667 Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1668
1669 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
1670 {
1671 if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
1672 {
1673 pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
1674
1675 /* Force lazy remapping if it changed in any way. */
1676 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
1677# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1678 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
1679# endif
1680 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
1681 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1682 }
1683 }
1684 return VINF_SUCCESS;
1685}
1686
1687
1688/**
1689 * Gets the current CR3 register value for the shadow memory context.
1690 * @returns CR3 value.
1691 * @param pVCpu Pointer to the VMCPU.
1692 */
1693VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1694{
1695 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1696 AssertPtrReturn(pPoolPage, 0);
1697 return pPoolPage->Core.Key;
1698}
1699
1700
1701/**
1702 * Gets the current CR3 register value for the nested memory context.
1703 * @returns CR3 value.
1704 * @param pVCpu Pointer to the VMCPU.
1705 */
1706VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1707{
1708 NOREF(enmShadowMode);
1709 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1710 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1711}
1712
1713
1714/**
1715 * Gets the current CR3 register value for the HC intermediate memory context.
1716 * @returns CR3 value.
1717 * @param pVM Pointer to the VM.
1718 */
1719VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1720{
1721 switch (pVM->pgm.s.enmHostMode)
1722 {
1723 case SUPPAGINGMODE_32_BIT:
1724 case SUPPAGINGMODE_32_BIT_GLOBAL:
1725 return pVM->pgm.s.HCPhysInterPD;
1726
1727 case SUPPAGINGMODE_PAE:
1728 case SUPPAGINGMODE_PAE_GLOBAL:
1729 case SUPPAGINGMODE_PAE_NX:
1730 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1731 return pVM->pgm.s.HCPhysInterPaePDPT;
1732
1733 case SUPPAGINGMODE_AMD64:
1734 case SUPPAGINGMODE_AMD64_GLOBAL:
1735 case SUPPAGINGMODE_AMD64_NX:
1736 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1737 return pVM->pgm.s.HCPhysInterPaePDPT;
1738
1739 default:
1740 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1741 return NIL_RTHCPHYS;
1742 }
1743}
1744
1745
1746/**
1747 * Gets the current CR3 register value for the RC intermediate memory context.
1748 * @returns CR3 value.
1749 * @param pVM Pointer to the VM.
1750 * @param pVCpu Pointer to the VMCPU.
1751 */
1752VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1753{
1754 switch (pVCpu->pgm.s.enmShadowMode)
1755 {
1756 case PGMMODE_32_BIT:
1757 return pVM->pgm.s.HCPhysInterPD;
1758
1759 case PGMMODE_PAE:
1760 case PGMMODE_PAE_NX:
1761 return pVM->pgm.s.HCPhysInterPaePDPT;
1762
1763 case PGMMODE_AMD64:
1764 case PGMMODE_AMD64_NX:
1765 return pVM->pgm.s.HCPhysInterPaePML4;
1766
1767 case PGMMODE_EPT:
1768 case PGMMODE_NESTED:
1769 return 0; /* not relevant */
1770
1771 default:
1772 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1773 return NIL_RTHCPHYS;
1774 }
1775}
1776
1777
1778/**
1779 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1780 * @returns CR3 value.
1781 * @param pVM Pointer to the VM.
1782 */
1783VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1784{
1785 return pVM->pgm.s.HCPhysInterPD;
1786}
1787
1788
1789/**
1790 * Gets the CR3 register value for the PAE intermediate memory context.
1791 * @returns CR3 value.
1792 * @param pVM Pointer to the VM.
1793 */
1794VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1795{
1796 return pVM->pgm.s.HCPhysInterPaePDPT;
1797}
1798
1799
1800/**
1801 * Gets the CR3 register value for the AMD64 intermediate memory context.
1802 * @returns CR3 value.
1803 * @param pVM Pointer to the VM.
1804 */
1805VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1806{
1807 return pVM->pgm.s.HCPhysInterPaePML4;
1808}
1809
1810
1811/**
1812 * Performs and schedules necessary updates following a CR3 load or reload.
1813 *
1814 * This will normally involve mapping the guest PD or nPDPT
1815 *
1816 * @returns VBox status code.
1817 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1818 * safely be ignored and overridden since the FF will be set too then.
1819 * @param pVCpu Pointer to the VMCPU.
1820 * @param cr3 The new cr3.
1821 * @param fGlobal Indicates whether this is a global flush or not.
1822 */
1823VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1824{
1825 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1826 PVM pVM = pVCpu->CTX_SUFF(pVM);
1827
1828 VMCPU_ASSERT_EMT(pVCpu);
1829
1830 /*
1831 * Always flag the necessary updates; necessary for hardware acceleration
1832 */
1833 /** @todo optimize this, it shouldn't always be necessary. */
1834 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1835 if (fGlobal)
1836 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1837 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1838
1839 /*
1840 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1841 */
1842 int rc = VINF_SUCCESS;
1843 RTGCPHYS GCPhysCR3;
1844 switch (pVCpu->pgm.s.enmGuestMode)
1845 {
1846 case PGMMODE_PAE:
1847 case PGMMODE_PAE_NX:
1848 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1849 break;
1850 case PGMMODE_AMD64:
1851 case PGMMODE_AMD64_NX:
1852 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1853 break;
1854 default:
1855 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1856 break;
1857 }
1858 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1859
1860 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1861 {
1862 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1863 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1864 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1865 if (RT_LIKELY(rc == VINF_SUCCESS))
1866 {
1867 if (pgmMapAreMappingsFloating(pVM))
1868 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1869 }
1870 else
1871 {
1872 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1873 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1874 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1875 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1876 if (pgmMapAreMappingsFloating(pVM))
1877 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1878 }
1879
1880 if (fGlobal)
1881 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1882 else
1883 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1884 }
1885 else
1886 {
1887# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1888 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1889 if (pPool->cDirtyPages)
1890 {
1891 pgmLock(pVM);
1892 pgmPoolResetDirtyPages(pVM);
1893 pgmUnlock(pVM);
1894 }
1895# endif
1896 /*
1897 * Check if we have a pending update of the CR3 monitoring.
1898 */
1899 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1900 {
1901 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1902 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1903 }
1904 if (fGlobal)
1905 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1906 else
1907 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1908 }
1909
1910 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1911 return rc;
1912}
1913
1914
1915/**
1916 * Performs and schedules necessary updates following a CR3 load or reload when
1917 * using nested or extended paging.
1918 *
1919 * This API is an alternative to PDMFlushTLB that avoids actually flushing the
1920 * TLB and triggering a SyncCR3.
1921 *
1922 * This will normally involve mapping the guest PD or nPDPT
1923 *
1924 * @returns VBox status code.
1925 * @retval VINF_SUCCESS.
1926 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1927 * requires a CR3 sync. This can safely be ignored and overridden since
1928 * the FF will be set too then.)
1929 * @param pVCpu Pointer to the VMCPU.
1930 * @param cr3 The new cr3.
1931 */
1932VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1933{
1934 VMCPU_ASSERT_EMT(pVCpu);
1935 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1936
1937 /* We assume we're only called in nested paging mode. */
1938 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1939 Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
1940 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1941
1942 /*
1943 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1944 */
1945 int rc = VINF_SUCCESS;
1946 RTGCPHYS GCPhysCR3;
1947 switch (pVCpu->pgm.s.enmGuestMode)
1948 {
1949 case PGMMODE_PAE:
1950 case PGMMODE_PAE_NX:
1951 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1952 break;
1953 case PGMMODE_AMD64:
1954 case PGMMODE_AMD64_NX:
1955 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1956 break;
1957 default:
1958 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1959 break;
1960 }
1961 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
1962
1963 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1964 {
1965 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1966 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1967 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1968 }
1969 return rc;
1970}
1971
1972
1973/**
1974 * Synchronize the paging structures.
1975 *
1976 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1977 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1978 * in several places, most importantly whenever the CR3 is loaded.
1979 *
1980 * @returns VBox status code.
1981 * @param pVCpu Pointer to the VMCPU.
1982 * @param cr0 Guest context CR0 register
1983 * @param cr3 Guest context CR3 register
1984 * @param cr4 Guest context CR4 register
1985 * @param fGlobal Including global page directories or not
1986 */
1987VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1988{
1989 int rc;
1990
1991 VMCPU_ASSERT_EMT(pVCpu);
1992
1993 /*
1994 * The pool may have pending stuff and even require a return to ring-3 to
1995 * clear the whole thing.
1996 */
1997 rc = pgmPoolSyncCR3(pVCpu);
1998 if (rc != VINF_SUCCESS)
1999 return rc;
2000
2001 /*
2002 * We might be called when we shouldn't.
2003 *
2004 * The mode switching will ensure that the PD is resynced after every mode
2005 * switch. So, if we find ourselves here when in protected or real mode
2006 * we can safely clear the FF and return immediately.
2007 */
2008 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2009 {
2010 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
2011 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2012 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2013 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2014 return VINF_SUCCESS;
2015 }
2016
2017 /* If global pages are not supported, then all flushes are global. */
2018 if (!(cr4 & X86_CR4_PGE))
2019 fGlobal = true;
2020 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2021 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2022
2023 /*
2024 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2025 * This should be done before SyncCR3.
2026 */
2027 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2028 {
2029 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2030
2031 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3; NOREF(GCPhysCR3Old);
2032 RTGCPHYS GCPhysCR3;
2033 switch (pVCpu->pgm.s.enmGuestMode)
2034 {
2035 case PGMMODE_PAE:
2036 case PGMMODE_PAE_NX:
2037 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
2038 break;
2039 case PGMMODE_AMD64:
2040 case PGMMODE_AMD64_NX:
2041 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
2042 break;
2043 default:
2044 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
2045 break;
2046 }
2047 PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2048
2049 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
2050 {
2051 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2052 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
2053 }
2054
2055 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2056 if ( rc == VINF_PGM_SYNC_CR3
2057 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2058 {
2059 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2060#ifdef IN_RING3
2061 rc = pgmPoolSyncCR3(pVCpu);
2062#else
2063 if (rc == VINF_PGM_SYNC_CR3)
2064 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2065 return VINF_PGM_SYNC_CR3;
2066#endif
2067 }
2068 AssertRCReturn(rc, rc);
2069 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2070 }
2071
2072 /*
2073 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2074 */
2075 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2076 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2077 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2078 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2079 if (rc == VINF_SUCCESS)
2080 {
2081 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2082 {
2083 /* Go back to ring 3 if a pgm pool sync is again pending. */
2084 return VINF_PGM_SYNC_CR3;
2085 }
2086
2087 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2088 {
2089 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2090 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2091 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2092 }
2093
2094 /*
2095 * Check if we have a pending update of the CR3 monitoring.
2096 */
2097 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2098 {
2099 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2100 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsFixed);
2101 Assert(!pVCpu->CTX_SUFF(pVM)->pgm.s.fMappingsDisabled);
2102 }
2103 }
2104
2105 /*
2106 * Now flush the CR3 (guest context).
2107 */
2108 if (rc == VINF_SUCCESS)
2109 PGM_INVL_VCPU_TLBS(pVCpu);
2110 return rc;
2111}
2112
2113
2114/**
2115 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2116 *
2117 * @returns VBox status code, with the following informational code for
2118 * VM scheduling.
2119 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2120 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2121 * (I.e. not in R3.)
2122 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2123 *
2124 * @param pVCpu Pointer to the VMCPU.
2125 * @param cr0 The new cr0.
2126 * @param cr4 The new cr4.
2127 * @param efer The new extended feature enable register.
2128 */
2129VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2130{
2131 PGMMODE enmGuestMode;
2132
2133 VMCPU_ASSERT_EMT(pVCpu);
2134
2135 /*
2136 * Calc the new guest mode.
2137 */
2138 if (!(cr0 & X86_CR0_PE))
2139 enmGuestMode = PGMMODE_REAL;
2140 else if (!(cr0 & X86_CR0_PG))
2141 enmGuestMode = PGMMODE_PROTECTED;
2142 else if (!(cr4 & X86_CR4_PAE))
2143 {
2144 bool const fPse = !!(cr4 & X86_CR4_PSE);
2145 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2146 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2147 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2148 enmGuestMode = PGMMODE_32_BIT;
2149 }
2150 else if (!(efer & MSR_K6_EFER_LME))
2151 {
2152 if (!(efer & MSR_K6_EFER_NXE))
2153 enmGuestMode = PGMMODE_PAE;
2154 else
2155 enmGuestMode = PGMMODE_PAE_NX;
2156 }
2157 else
2158 {
2159 if (!(efer & MSR_K6_EFER_NXE))
2160 enmGuestMode = PGMMODE_AMD64;
2161 else
2162 enmGuestMode = PGMMODE_AMD64_NX;
2163 }
2164
2165 /*
2166 * Did it change?
2167 */
2168 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2169 return VINF_SUCCESS;
2170
2171 /* Flush the TLB */
2172 PGM_INVL_VCPU_TLBS(pVCpu);
2173
2174#ifdef IN_RING3
2175 return PGMR3ChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode);
2176#else
2177 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2178 return VINF_PGM_CHANGE_MODE;
2179#endif
2180}
2181
2182
2183/**
2184 * Gets the current guest paging mode.
2185 *
2186 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2187 *
2188 * @returns The current paging mode.
2189 * @param pVCpu Pointer to the VMCPU.
2190 */
2191VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2192{
2193 return pVCpu->pgm.s.enmGuestMode;
2194}
2195
2196
2197/**
2198 * Gets the current shadow paging mode.
2199 *
2200 * @returns The current paging mode.
2201 * @param pVCpu Pointer to the VMCPU.
2202 */
2203VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2204{
2205 return pVCpu->pgm.s.enmShadowMode;
2206}
2207
2208
2209/**
2210 * Gets the current host paging mode.
2211 *
2212 * @returns The current paging mode.
2213 * @param pVM Pointer to the VM.
2214 */
2215VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2216{
2217 switch (pVM->pgm.s.enmHostMode)
2218 {
2219 case SUPPAGINGMODE_32_BIT:
2220 case SUPPAGINGMODE_32_BIT_GLOBAL:
2221 return PGMMODE_32_BIT;
2222
2223 case SUPPAGINGMODE_PAE:
2224 case SUPPAGINGMODE_PAE_GLOBAL:
2225 return PGMMODE_PAE;
2226
2227 case SUPPAGINGMODE_PAE_NX:
2228 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2229 return PGMMODE_PAE_NX;
2230
2231 case SUPPAGINGMODE_AMD64:
2232 case SUPPAGINGMODE_AMD64_GLOBAL:
2233 return PGMMODE_AMD64;
2234
2235 case SUPPAGINGMODE_AMD64_NX:
2236 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2237 return PGMMODE_AMD64_NX;
2238
2239 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2240 }
2241
2242 return PGMMODE_INVALID;
2243}
2244
2245
2246/**
2247 * Get mode name.
2248 *
2249 * @returns read-only name string.
2250 * @param enmMode The mode which name is desired.
2251 */
2252VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2253{
2254 switch (enmMode)
2255 {
2256 case PGMMODE_REAL: return "Real";
2257 case PGMMODE_PROTECTED: return "Protected";
2258 case PGMMODE_32_BIT: return "32-bit";
2259 case PGMMODE_PAE: return "PAE";
2260 case PGMMODE_PAE_NX: return "PAE+NX";
2261 case PGMMODE_AMD64: return "AMD64";
2262 case PGMMODE_AMD64_NX: return "AMD64+NX";
2263 case PGMMODE_NESTED: return "Nested";
2264 case PGMMODE_EPT: return "EPT";
2265 default: return "unknown mode value";
2266 }
2267}
2268
2269
2270
2271/**
2272 * Notification from CPUM that the EFER.NXE bit has changed.
2273 *
2274 * @param pVCpu The virtual CPU for which EFER changed.
2275 * @param fNxe The new NXE state.
2276 */
2277VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2278{
2279/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
2280 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2281
2282 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2283 if (fNxe)
2284 {
2285 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2286 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2287 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2288 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2289 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2290 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2291 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2292 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2293 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2294 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2295 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2296
2297 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2298 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2299 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2300 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2301 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2302 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2303 }
2304 else
2305 {
2306 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2307 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2308 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2309 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2310 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2311 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2312 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2313 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2314 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2315 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2316 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2317
2318 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2319 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2320 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2321 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2322 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2323 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2324 }
2325}
2326
2327
2328/**
2329 * Check if any pgm pool pages are marked dirty (not monitored)
2330 *
2331 * @returns bool locked/not locked
2332 * @param pVM Pointer to the VM.
2333 */
2334VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2335{
2336 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2337}
2338
2339
2340/**
2341 * Check if this VCPU currently owns the PGM lock.
2342 *
2343 * @returns bool owner/not owner
2344 * @param pVM Pointer to the VM.
2345 */
2346VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2347{
2348 return PDMCritSectIsOwner(&pVM->pgm.s.CritSectX);
2349}
2350
2351
2352/**
2353 * Enable or disable large page usage
2354 *
2355 * @returns VBox status code.
2356 * @param pVM Pointer to the VM.
2357 * @param fUseLargePages Use/not use large pages
2358 */
2359VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2360{
2361 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
2362
2363 pVM->fUseLargePages = fUseLargePages;
2364 return VINF_SUCCESS;
2365}
2366
2367
2368/**
2369 * Acquire the PGM lock.
2370 *
2371 * @returns VBox status code
2372 * @param pVM Pointer to the VM.
2373 */
2374int pgmLock(PVM pVM)
2375{
2376 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSectX, VERR_SEM_BUSY);
2377#if defined(IN_RC) || defined(IN_RING0)
2378 if (rc == VERR_SEM_BUSY)
2379 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2380#endif
2381 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2382 return rc;
2383}
2384
2385
2386/**
2387 * Release the PGM lock.
2388 *
2389 * @returns VBox status code
2390 * @param pVM Pointer to the VM.
2391 */
2392void pgmUnlock(PVM pVM)
2393{
2394 uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
2395 pVM->pgm.s.cDeprecatedPageLocks = 0;
2396 int rc = PDMCritSectLeave(&pVM->pgm.s.CritSectX);
2397 if (rc == VINF_SEM_NESTED)
2398 pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
2399}
2400
2401#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2402
2403/**
2404 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2405 *
2406 * @returns VBox status code.
2407 * @param pVM Pointer to the VM.
2408 * @param pVCpu The current CPU.
2409 * @param GCPhys The guest physical address of the page to map. The
2410 * offset bits are not ignored.
2411 * @param ppv Where to return the address corresponding to @a GCPhys.
2412 */
2413int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2414{
2415 pgmLock(pVM);
2416
2417 /*
2418 * Convert it to a writable page and it on to the dynamic mapper.
2419 */
2420 int rc;
2421 PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2422 if (RT_LIKELY(pPage))
2423 {
2424 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2425 if (RT_SUCCESS(rc))
2426 {
2427 void *pv;
2428 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2429 if (RT_SUCCESS(rc))
2430 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2431 }
2432 else
2433 AssertRC(rc);
2434 }
2435 else
2436 {
2437 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2438 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2439 }
2440
2441 pgmUnlock(pVM);
2442 return rc;
2443}
2444
2445#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2446#if !defined(IN_R0) || defined(LOG_ENABLED)
2447
2448/** Format handler for PGMPAGE.
2449 * @copydoc FNRTSTRFORMATTYPE */
2450static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2451 const char *pszType, void const *pvValue,
2452 int cchWidth, int cchPrecision, unsigned fFlags,
2453 void *pvUser)
2454{
2455 size_t cch;
2456 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2457 if (RT_VALID_PTR(pPage))
2458 {
2459 char szTmp[64+80];
2460
2461 cch = 0;
2462
2463 /* The single char state stuff. */
2464 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2465 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
2466
2467#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2468 if (IS_PART_INCLUDED(5))
2469 {
2470 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2471 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2472 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2473 }
2474
2475 /* The type. */
2476 if (IS_PART_INCLUDED(4))
2477 {
2478 szTmp[cch++] = ':';
2479 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2480 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
2481 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
2482 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
2483 }
2484
2485 /* The numbers. */
2486 if (IS_PART_INCLUDED(3))
2487 {
2488 szTmp[cch++] = ':';
2489 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2490 }
2491
2492 if (IS_PART_INCLUDED(2))
2493 {
2494 szTmp[cch++] = ':';
2495 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2496 }
2497
2498 if (IS_PART_INCLUDED(6))
2499 {
2500 szTmp[cch++] = ':';
2501 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2502 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
2503 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2504 }
2505#undef IS_PART_INCLUDED
2506
2507 cch = pfnOutput(pvArgOutput, szTmp, cch);
2508 }
2509 else
2510 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2511 NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
2512 return cch;
2513}
2514
2515
2516/** Format handler for PGMRAMRANGE.
2517 * @copydoc FNRTSTRFORMATTYPE */
2518static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2519 const char *pszType, void const *pvValue,
2520 int cchWidth, int cchPrecision, unsigned fFlags,
2521 void *pvUser)
2522{
2523 size_t cch;
2524 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2525 if (VALID_PTR(pRam))
2526 {
2527 char szTmp[80];
2528 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2529 cch = pfnOutput(pvArgOutput, szTmp, cch);
2530 }
2531 else
2532 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2533 NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
2534 return cch;
2535}
2536
2537/** Format type andlers to be registered/deregistered. */
2538static const struct
2539{
2540 char szType[24];
2541 PFNRTSTRFORMATTYPE pfnHandler;
2542} g_aPgmFormatTypes[] =
2543{
2544 { "pgmpage", pgmFormatTypeHandlerPage },
2545 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2546};
2547
2548#endif /* !IN_R0 || LOG_ENABLED */
2549
2550/**
2551 * Registers the global string format types.
2552 *
2553 * This should be called at module load time or in some other manner that ensure
2554 * that it's called exactly one time.
2555 *
2556 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2557 */
2558VMMDECL(int) PGMRegisterStringFormatTypes(void)
2559{
2560#if !defined(IN_R0) || defined(LOG_ENABLED)
2561 int rc = VINF_SUCCESS;
2562 unsigned i;
2563 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2564 {
2565 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2566# ifdef IN_RING0
2567 if (rc == VERR_ALREADY_EXISTS)
2568 {
2569 /* in case of cleanup failure in ring-0 */
2570 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2571 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2572 }
2573# endif
2574 }
2575 if (RT_FAILURE(rc))
2576 while (i-- > 0)
2577 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2578
2579 return rc;
2580#else
2581 return VINF_SUCCESS;
2582#endif
2583}
2584
2585
2586/**
2587 * Deregisters the global string format types.
2588 *
2589 * This should be called at module unload time or in some other manner that
2590 * ensure that it's called exactly one time.
2591 */
2592VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2593{
2594#if !defined(IN_R0) || defined(LOG_ENABLED)
2595 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2596 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2597#endif
2598}
2599
2600#ifdef VBOX_STRICT
2601
2602/**
2603 * Asserts that there are no mapping conflicts.
2604 *
2605 * @returns Number of conflicts.
2606 * @param pVM Pointer to the VM.
2607 */
2608VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2609{
2610 unsigned cErrors = 0;
2611
2612 /* Only applies to raw mode -> 1 VPCU */
2613 Assert(pVM->cCpus == 1);
2614 PVMCPU pVCpu = &pVM->aCpus[0];
2615
2616 /*
2617 * Check for mapping conflicts.
2618 */
2619 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2620 pMapping;
2621 pMapping = pMapping->CTX_SUFF(pNext))
2622 {
2623 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2624 for (RTGCPTR GCPtr = pMapping->GCPtr;
2625 GCPtr <= pMapping->GCPtrLast;
2626 GCPtr += PAGE_SIZE)
2627 {
2628 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2629 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2630 {
2631 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2632 cErrors++;
2633 break;
2634 }
2635 }
2636 }
2637
2638 return cErrors;
2639}
2640
2641
2642/**
2643 * Asserts that everything related to the guest CR3 is correctly shadowed.
2644 *
2645 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2646 * and assert the correctness of the guest CR3 mapping before asserting that the
2647 * shadow page tables is in sync with the guest page tables.
2648 *
2649 * @returns Number of conflicts.
2650 * @param pVM Pointer to the VM.
2651 * @param pVCpu Pointer to the VMCPU.
2652 * @param cr3 The current guest CR3 register value.
2653 * @param cr4 The current guest CR4 register value.
2654 */
2655VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2656{
2657 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2658 pgmLock(pVM);
2659 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2660 pgmUnlock(pVM);
2661 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2662 return cErrors;
2663}
2664
2665#endif /* VBOX_STRICT */
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