VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 32181

Last change on this file since 32181 was 32036, checked in by vboxsync, 14 years ago

Removed X86_PTE_PAE_PG_MASK, renamed X86_PTE_PAE_PG_MASK_FULL to X86_PTE_PAE_PG_MASK.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 84.6 KB
Line 
1/* $Id: PGMAll.cpp 32036 2010-08-27 10:14:39Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/pgm.h>
23#include <VBox/cpum.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/sup.h>
27#include <VBox/mm.h>
28#include <VBox/stam.h>
29#include <VBox/csam.h>
30#include <VBox/patm.h>
31#include <VBox/trpm.h>
32#include <VBox/rem.h>
33#include <VBox/em.h>
34#include <VBox/hwaccm.h>
35#include <VBox/hwacc_vmx.h>
36#include "../PGMInternal.h"
37#include <VBox/vm.h>
38#include "../PGMInline.h"
39#include <iprt/assert.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/string.h>
42#include <VBox/log.h>
43#include <VBox/param.h>
44#include <VBox/err.h>
45
46
47/*******************************************************************************
48* Structures and Typedefs *
49*******************************************************************************/
50/**
51 * Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
52 * passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
53 */
54typedef struct PGMHVUSTATE
55{
56 /** The VM handle. */
57 PVM pVM;
58 /** The VMCPU handle. */
59 PVMCPU pVCpu;
60 /** The todo flags. */
61 RTUINT fTodo;
62 /** The CR4 register value. */
63 uint32_t cr4;
64} PGMHVUSTATE, *PPGMHVUSTATE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
71DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
72#ifndef IN_RC
73static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
74static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
75#endif
76
77
78/*
79 * Shadow - 32-bit mode
80 */
81#define PGM_SHW_TYPE PGM_TYPE_32BIT
82#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
83#include "PGMAllShw.h"
84
85/* Guest - real mode */
86#define PGM_GST_TYPE PGM_TYPE_REAL
87#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
88#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
89#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
90#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
91#include "PGMGstDefs.h"
92#include "PGMAllGst.h"
93#include "PGMAllBth.h"
94#undef BTH_PGMPOOLKIND_PT_FOR_PT
95#undef BTH_PGMPOOLKIND_ROOT
96#undef PGM_BTH_NAME
97#undef PGM_GST_TYPE
98#undef PGM_GST_NAME
99
100/* Guest - protected mode */
101#define PGM_GST_TYPE PGM_TYPE_PROT
102#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
103#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
104#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
105#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
106#include "PGMGstDefs.h"
107#include "PGMAllGst.h"
108#include "PGMAllBth.h"
109#undef BTH_PGMPOOLKIND_PT_FOR_PT
110#undef BTH_PGMPOOLKIND_ROOT
111#undef PGM_BTH_NAME
112#undef PGM_GST_TYPE
113#undef PGM_GST_NAME
114
115/* Guest - 32-bit mode */
116#define PGM_GST_TYPE PGM_TYPE_32BIT
117#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
118#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
119#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
120#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
121#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
122#include "PGMGstDefs.h"
123#include "PGMAllGst.h"
124#include "PGMAllBth.h"
125#undef BTH_PGMPOOLKIND_PT_FOR_BIG
126#undef BTH_PGMPOOLKIND_PT_FOR_PT
127#undef BTH_PGMPOOLKIND_ROOT
128#undef PGM_BTH_NAME
129#undef PGM_GST_TYPE
130#undef PGM_GST_NAME
131
132#undef PGM_SHW_TYPE
133#undef PGM_SHW_NAME
134
135
136/*
137 * Shadow - PAE mode
138 */
139#define PGM_SHW_TYPE PGM_TYPE_PAE
140#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
141#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
142#include "PGMAllShw.h"
143
144/* Guest - real mode */
145#define PGM_GST_TYPE PGM_TYPE_REAL
146#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
147#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
148#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
149#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
150#include "PGMGstDefs.h"
151#include "PGMAllBth.h"
152#undef BTH_PGMPOOLKIND_PT_FOR_PT
153#undef BTH_PGMPOOLKIND_ROOT
154#undef PGM_BTH_NAME
155#undef PGM_GST_TYPE
156#undef PGM_GST_NAME
157
158/* Guest - protected mode */
159#define PGM_GST_TYPE PGM_TYPE_PROT
160#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
161#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
162#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
163#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
164#include "PGMGstDefs.h"
165#include "PGMAllBth.h"
166#undef BTH_PGMPOOLKIND_PT_FOR_PT
167#undef BTH_PGMPOOLKIND_ROOT
168#undef PGM_BTH_NAME
169#undef PGM_GST_TYPE
170#undef PGM_GST_NAME
171
172/* Guest - 32-bit mode */
173#define PGM_GST_TYPE PGM_TYPE_32BIT
174#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
175#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
176#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
177#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
178#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
179#include "PGMGstDefs.h"
180#include "PGMAllBth.h"
181#undef BTH_PGMPOOLKIND_PT_FOR_BIG
182#undef BTH_PGMPOOLKIND_PT_FOR_PT
183#undef BTH_PGMPOOLKIND_ROOT
184#undef PGM_BTH_NAME
185#undef PGM_GST_TYPE
186#undef PGM_GST_NAME
187
188
189/* Guest - PAE mode */
190#define PGM_GST_TYPE PGM_TYPE_PAE
191#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
192#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
193#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
194#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
195#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
196#include "PGMGstDefs.h"
197#include "PGMAllGst.h"
198#include "PGMAllBth.h"
199#undef BTH_PGMPOOLKIND_PT_FOR_BIG
200#undef BTH_PGMPOOLKIND_PT_FOR_PT
201#undef BTH_PGMPOOLKIND_ROOT
202#undef PGM_BTH_NAME
203#undef PGM_GST_TYPE
204#undef PGM_GST_NAME
205
206#undef PGM_SHW_TYPE
207#undef PGM_SHW_NAME
208
209
210#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
211/*
212 * Shadow - AMD64 mode
213 */
214# define PGM_SHW_TYPE PGM_TYPE_AMD64
215# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
216# include "PGMAllShw.h"
217
218/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
219# define PGM_GST_TYPE PGM_TYPE_PROT
220# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
221# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
222# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
223# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
224# include "PGMGstDefs.h"
225# include "PGMAllBth.h"
226# undef BTH_PGMPOOLKIND_PT_FOR_PT
227# undef BTH_PGMPOOLKIND_ROOT
228# undef PGM_BTH_NAME
229# undef PGM_GST_TYPE
230# undef PGM_GST_NAME
231
232# ifdef VBOX_WITH_64_BITS_GUESTS
233/* Guest - AMD64 mode */
234# define PGM_GST_TYPE PGM_TYPE_AMD64
235# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
236# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
237# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
238# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
239# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
240# include "PGMGstDefs.h"
241# include "PGMAllGst.h"
242# include "PGMAllBth.h"
243# undef BTH_PGMPOOLKIND_PT_FOR_BIG
244# undef BTH_PGMPOOLKIND_PT_FOR_PT
245# undef BTH_PGMPOOLKIND_ROOT
246# undef PGM_BTH_NAME
247# undef PGM_GST_TYPE
248# undef PGM_GST_NAME
249# endif /* VBOX_WITH_64_BITS_GUESTS */
250
251# undef PGM_SHW_TYPE
252# undef PGM_SHW_NAME
253
254
255/*
256 * Shadow - Nested paging mode
257 */
258# define PGM_SHW_TYPE PGM_TYPE_NESTED
259# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
260# include "PGMAllShw.h"
261
262/* Guest - real mode */
263# define PGM_GST_TYPE PGM_TYPE_REAL
264# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
265# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
266# include "PGMGstDefs.h"
267# include "PGMAllBth.h"
268# undef PGM_BTH_NAME
269# undef PGM_GST_TYPE
270# undef PGM_GST_NAME
271
272/* Guest - protected mode */
273# define PGM_GST_TYPE PGM_TYPE_PROT
274# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
275# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
276# include "PGMGstDefs.h"
277# include "PGMAllBth.h"
278# undef PGM_BTH_NAME
279# undef PGM_GST_TYPE
280# undef PGM_GST_NAME
281
282/* Guest - 32-bit mode */
283# define PGM_GST_TYPE PGM_TYPE_32BIT
284# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
285# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
286# include "PGMGstDefs.h"
287# include "PGMAllBth.h"
288# undef PGM_BTH_NAME
289# undef PGM_GST_TYPE
290# undef PGM_GST_NAME
291
292/* Guest - PAE mode */
293# define PGM_GST_TYPE PGM_TYPE_PAE
294# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
295# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
296# include "PGMGstDefs.h"
297# include "PGMAllBth.h"
298# undef PGM_BTH_NAME
299# undef PGM_GST_TYPE
300# undef PGM_GST_NAME
301
302# ifdef VBOX_WITH_64_BITS_GUESTS
303/* Guest - AMD64 mode */
304# define PGM_GST_TYPE PGM_TYPE_AMD64
305# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
306# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
307# include "PGMGstDefs.h"
308# include "PGMAllBth.h"
309# undef PGM_BTH_NAME
310# undef PGM_GST_TYPE
311# undef PGM_GST_NAME
312# endif /* VBOX_WITH_64_BITS_GUESTS */
313
314# undef PGM_SHW_TYPE
315# undef PGM_SHW_NAME
316
317
318/*
319 * Shadow - EPT
320 */
321# define PGM_SHW_TYPE PGM_TYPE_EPT
322# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
323# include "PGMAllShw.h"
324
325/* Guest - real mode */
326# define PGM_GST_TYPE PGM_TYPE_REAL
327# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
328# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
329# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
330# include "PGMGstDefs.h"
331# include "PGMAllBth.h"
332# undef BTH_PGMPOOLKIND_PT_FOR_PT
333# undef PGM_BTH_NAME
334# undef PGM_GST_TYPE
335# undef PGM_GST_NAME
336
337/* Guest - protected mode */
338# define PGM_GST_TYPE PGM_TYPE_PROT
339# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
340# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
341# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
342# include "PGMGstDefs.h"
343# include "PGMAllBth.h"
344# undef BTH_PGMPOOLKIND_PT_FOR_PT
345# undef PGM_BTH_NAME
346# undef PGM_GST_TYPE
347# undef PGM_GST_NAME
348
349/* Guest - 32-bit mode */
350# define PGM_GST_TYPE PGM_TYPE_32BIT
351# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
352# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
353# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
354# include "PGMGstDefs.h"
355# include "PGMAllBth.h"
356# undef BTH_PGMPOOLKIND_PT_FOR_PT
357# undef PGM_BTH_NAME
358# undef PGM_GST_TYPE
359# undef PGM_GST_NAME
360
361/* Guest - PAE mode */
362# define PGM_GST_TYPE PGM_TYPE_PAE
363# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
364# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
365# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
366# include "PGMGstDefs.h"
367# include "PGMAllBth.h"
368# undef BTH_PGMPOOLKIND_PT_FOR_PT
369# undef PGM_BTH_NAME
370# undef PGM_GST_TYPE
371# undef PGM_GST_NAME
372
373# ifdef VBOX_WITH_64_BITS_GUESTS
374/* Guest - AMD64 mode */
375# define PGM_GST_TYPE PGM_TYPE_AMD64
376# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
377# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
378# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
379# include "PGMGstDefs.h"
380# include "PGMAllBth.h"
381# undef BTH_PGMPOOLKIND_PT_FOR_PT
382# undef PGM_BTH_NAME
383# undef PGM_GST_TYPE
384# undef PGM_GST_NAME
385# endif /* VBOX_WITH_64_BITS_GUESTS */
386
387# undef PGM_SHW_TYPE
388# undef PGM_SHW_NAME
389
390#endif /* !IN_RC */
391
392
393#ifndef IN_RING3
394/**
395 * #PF Handler.
396 *
397 * @returns VBox status code (appropriate for trap handling and GC return).
398 * @param pVCpu VMCPU handle.
399 * @param uErr The trap error code.
400 * @param pRegFrame Trap register frame.
401 * @param pvFault The fault address.
402 */
403VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
404{
405 PVM pVM = pVCpu->CTX_SUFF(pVM);
406
407 Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
408 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, a);
409 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
410
411
412#ifdef VBOX_WITH_STATISTICS
413 /*
414 * Error code stats.
415 */
416 if (uErr & X86_TRAP_PF_US)
417 {
418 if (!(uErr & X86_TRAP_PF_P))
419 {
420 if (uErr & X86_TRAP_PF_RW)
421 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentWrite);
422 else
423 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNotPresentRead);
424 }
425 else if (uErr & X86_TRAP_PF_RW)
426 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSWrite);
427 else if (uErr & X86_TRAP_PF_RSVD)
428 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSReserved);
429 else if (uErr & X86_TRAP_PF_ID)
430 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSNXE);
431 else
432 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eUSRead);
433 }
434 else
435 { /* Supervisor */
436 if (!(uErr & X86_TRAP_PF_P))
437 {
438 if (uErr & X86_TRAP_PF_RW)
439 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentWrite);
440 else
441 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVNotPresentRead);
442 }
443 else if (uErr & X86_TRAP_PF_RW)
444 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVWrite);
445 else if (uErr & X86_TRAP_PF_ID)
446 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSNXE);
447 else if (uErr & X86_TRAP_PF_RSVD)
448 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eSVReserved);
449 }
450#endif /* VBOX_WITH_STATISTICS */
451
452 /*
453 * Call the worker.
454 */
455 bool fLockTaken = false;
456 int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault, &fLockTaken);
457 if (fLockTaken)
458 {
459 Assert(PGMIsLockOwner(pVM));
460 pgmUnlock(pVM);
461 }
462 LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
463
464 /*
465 * Return code tweaks.
466 */
467 if (rc != VINF_SUCCESS)
468 {
469 if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
470 rc = VINF_SUCCESS;
471
472# ifdef IN_RING0
473 /* Note: hack alert for difficult to reproduce problem. */
474 if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
475 || rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
476 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
477 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
478 {
479 Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
480 /* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
481 rc = VINF_SUCCESS;
482 }
483# endif
484 }
485
486 STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPF); });
487 STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
488 pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Misc; });
489 STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
490 return rc;
491}
492#endif /* !IN_RING3 */
493
494
495/**
496 * Prefetch a page
497 *
498 * Typically used to sync commonly used pages before entering raw mode
499 * after a CR3 reload.
500 *
501 * @returns VBox status code suitable for scheduling.
502 * @retval VINF_SUCCESS on success.
503 * @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
504 * @param pVCpu VMCPU handle.
505 * @param GCPtrPage Page to invalidate.
506 */
507VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
508{
509 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
510 int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
511 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Prefetch), a);
512 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
513 return rc;
514}
515
516
517/**
518 * Gets the mapping corresponding to the specified address (if any).
519 *
520 * @returns Pointer to the mapping.
521 * @returns NULL if not
522 *
523 * @param pVM The virtual machine.
524 * @param GCPtr The guest context pointer.
525 */
526PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
527{
528 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
529 while (pMapping)
530 {
531 if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
532 break;
533 if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
534 return pMapping;
535 pMapping = pMapping->CTX_SUFF(pNext);
536 }
537 return NULL;
538}
539
540
541/**
542 * Verifies a range of pages for read or write access
543 *
544 * Only checks the guest's page tables
545 *
546 * @returns VBox status code.
547 * @param pVCpu VMCPU handle.
548 * @param Addr Guest virtual address to check
549 * @param cbSize Access size
550 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
551 * @remarks Current not in use.
552 */
553VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
554{
555 /*
556 * Validate input.
557 */
558 if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
559 {
560 AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
561 return VERR_INVALID_PARAMETER;
562 }
563
564 uint64_t fPage;
565 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
566 if (RT_FAILURE(rc))
567 {
568 Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
569 return VINF_EM_RAW_GUEST_TRAP;
570 }
571
572 /*
573 * Check if the access would cause a page fault
574 *
575 * Note that hypervisor page directories are not present in the guest's tables, so this check
576 * is sufficient.
577 */
578 bool fWrite = !!(fAccess & X86_PTE_RW);
579 bool fUser = !!(fAccess & X86_PTE_US);
580 if ( !(fPage & X86_PTE_P)
581 || (fWrite && !(fPage & X86_PTE_RW))
582 || (fUser && !(fPage & X86_PTE_US)) )
583 {
584 Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
585 return VINF_EM_RAW_GUEST_TRAP;
586 }
587 if ( RT_SUCCESS(rc)
588 && PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
589 return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
590 return rc;
591}
592
593
594/**
595 * Verifies a range of pages for read or write access
596 *
597 * Supports handling of pages marked for dirty bit tracking and CSAM
598 *
599 * @returns VBox status code.
600 * @param pVCpu VMCPU handle.
601 * @param Addr Guest virtual address to check
602 * @param cbSize Access size
603 * @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
604 */
605VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
606{
607 PVM pVM = pVCpu->CTX_SUFF(pVM);
608
609 AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
610
611 /*
612 * Get going.
613 */
614 uint64_t fPageGst;
615 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
616 if (RT_FAILURE(rc))
617 {
618 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
619 return VINF_EM_RAW_GUEST_TRAP;
620 }
621
622 /*
623 * Check if the access would cause a page fault
624 *
625 * Note that hypervisor page directories are not present in the guest's tables, so this check
626 * is sufficient.
627 */
628 const bool fWrite = !!(fAccess & X86_PTE_RW);
629 const bool fUser = !!(fAccess & X86_PTE_US);
630 if ( !(fPageGst & X86_PTE_P)
631 || (fWrite && !(fPageGst & X86_PTE_RW))
632 || (fUser && !(fPageGst & X86_PTE_US)) )
633 {
634 Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
635 return VINF_EM_RAW_GUEST_TRAP;
636 }
637
638 if (!pVM->pgm.s.fNestedPaging)
639 {
640 /*
641 * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
642 */
643 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
644 if ( rc == VERR_PAGE_NOT_PRESENT
645 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
646 {
647 /*
648 * Page is not present in our page tables.
649 * Try to sync it!
650 */
651 Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
652 uint32_t uErr = fAccess & (X86_TRAP_PF_RW | X86_TRAP_PF_US);
653 rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
654 if (rc != VINF_SUCCESS)
655 return rc;
656 }
657 else
658 AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
659 }
660
661#if 0 /* def VBOX_STRICT; triggers too often now */
662 /*
663 * This check is a bit paranoid, but useful.
664 */
665 /* Note! This will assert when writing to monitored pages (a bit annoying actually). */
666 uint64_t fPageShw;
667 rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
668 if ( (rc == VERR_PAGE_NOT_PRESENT || RT_FAILURE(rc))
669 || (fWrite && !(fPageShw & X86_PTE_RW))
670 || (fUser && !(fPageShw & X86_PTE_US)) )
671 {
672 AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
673 Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
674 return VINF_EM_RAW_GUEST_TRAP;
675 }
676#endif
677
678 if ( RT_SUCCESS(rc)
679 && ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
680 || Addr + cbSize < Addr))
681 {
682 /* Don't recursively call PGMVerifyAccess as we might run out of stack. */
683 for (;;)
684 {
685 Addr += PAGE_SIZE;
686 if (cbSize > PAGE_SIZE)
687 cbSize -= PAGE_SIZE;
688 else
689 cbSize = 1;
690 rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
691 if (rc != VINF_SUCCESS)
692 break;
693 if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
694 break;
695 }
696 }
697 return rc;
698}
699
700
701/**
702 * Emulation of the invlpg instruction (HC only actually).
703 *
704 * @returns Strict VBox status code, special care required.
705 * @retval VINF_PGM_SYNC_CR3 - handled.
706 * @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
707 * @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
708 *
709 * @param pVCpu VMCPU handle.
710 * @param GCPtrPage Page to invalidate.
711 *
712 * @remark ASSUMES the page table entry or page directory is valid. Fairly
713 * safe, but there could be edge cases!
714 *
715 * @todo Flush page or page directory only if necessary!
716 * @todo VBOXSTRICTRC
717 */
718VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
719{
720 PVM pVM = pVCpu->CTX_SUFF(pVM);
721 int rc;
722 Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
723
724#ifndef IN_RING3
725 /*
726 * Notify the recompiler so it can record this instruction.
727 */
728 REMNotifyInvalidatePage(pVM, GCPtrPage);
729#endif /* !IN_RING3 */
730
731
732#ifdef IN_RC
733 /*
734 * Check for conflicts and pending CR3 monitoring updates.
735 */
736 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
737 {
738 if ( pgmGetMapping(pVM, GCPtrPage)
739 && PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
740 {
741 LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
742 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
743 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgConflict);
744 return VINF_PGM_SYNC_CR3;
745 }
746
747 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
748 {
749 LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
750 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatRCInvlPgSyncMonCR3);
751 return VINF_EM_RAW_EMULATE_INSTR;
752 }
753 }
754#endif /* IN_RC */
755
756 /*
757 * Call paging mode specific worker.
758 */
759 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
760 pgmLock(pVM);
761 rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
762 pgmUnlock(pVM);
763 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage), a);
764
765 /* Invalidate the TLB entry; might already be done by InvalidatePage (@todo) */
766 PGM_INVL_PG(pVCpu, GCPtrPage);
767
768#ifdef IN_RING3
769 /*
770 * Check if we have a pending update of the CR3 monitoring.
771 */
772 if ( RT_SUCCESS(rc)
773 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
774 {
775 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
776 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
777 }
778
779 /*
780 * Inform CSAM about the flush
781 *
782 * Note: This is to check if monitored pages have been changed; when we implement
783 * callbacks for virtual handlers, this is no longer required.
784 */
785 CSAMR3FlushPage(pVM, GCPtrPage);
786#endif /* IN_RING3 */
787
788 /* Ignore all irrelevant error codes. */
789 if ( rc == VERR_PAGE_NOT_PRESENT
790 || rc == VERR_PAGE_TABLE_NOT_PRESENT
791 || rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
792 || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
793 rc = VINF_SUCCESS;
794
795 return rc;
796}
797
798
799/**
800 * Executes an instruction using the interpreter.
801 *
802 * @returns VBox status code (appropriate for trap handling and GC return).
803 * @param pVM VM handle.
804 * @param pVCpu VMCPU handle.
805 * @param pRegFrame Register frame.
806 * @param pvFault Fault address.
807 */
808VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
809{
810 uint32_t cb;
811 VBOXSTRICTRC rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
812 if (rc == VERR_EM_INTERPRETER)
813 rc = VINF_EM_RAW_EMULATE_INSTR;
814 if (rc != VINF_SUCCESS)
815 Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
816 return rc;
817}
818
819
820/**
821 * Gets effective page information (from the VMM page directory).
822 *
823 * @returns VBox status.
824 * @param pVCpu VMCPU handle.
825 * @param GCPtr Guest Context virtual address of the page.
826 * @param pfFlags Where to store the flags. These are X86_PTE_*.
827 * @param pHCPhys Where to store the HC physical address of the page.
828 * This is page aligned.
829 * @remark You should use PGMMapGetPage() for pages in a mapping.
830 */
831VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
832{
833 pgmLock(pVCpu->CTX_SUFF(pVM));
834 int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
835 pgmUnlock(pVCpu->CTX_SUFF(pVM));
836 return rc;
837}
838
839
840/**
841 * Modify page flags for a range of pages in the shadow context.
842 *
843 * The existing flags are ANDed with the fMask and ORed with the fFlags.
844 *
845 * @returns VBox status code.
846 * @param pVCpu VMCPU handle.
847 * @param GCPtr Virtual address of the first page in the range.
848 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
849 * @param fMask The AND mask - page flags X86_PTE_*.
850 * Be very CAREFUL when ~'ing constants which could be 32-bit!
851 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
852 * @remark You must use PGMMapModifyPage() for pages in a mapping.
853 */
854DECLINLINE(int) pdmShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
855{
856 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
857 Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 | PGM_MK_PG_IS_WRITE_FAULT)));
858
859 GCPtr &= PAGE_BASE_GC_MASK; /** @todo this ain't necessary, right... */
860
861 PVM pVM = pVCpu->CTX_SUFF(pVM);
862 pgmLock(pVM);
863 int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, PAGE_SIZE, fFlags, fMask, fOpFlags);
864 pgmUnlock(pVM);
865 return rc;
866}
867
868
869/**
870 * Changing the page flags for a single page in the shadow page tables so as to
871 * make it read-only.
872 *
873 * @returns VBox status code.
874 * @param pVCpu VMCPU handle.
875 * @param GCPtr Virtual address of the first page in the range.
876 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
877 */
878VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
879{
880 return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
881}
882
883
884/**
885 * Changing the page flags for a single page in the shadow page tables so as to
886 * make it writable.
887 *
888 * The call must know with 101% certainty that the guest page tables maps this
889 * as writable too. This function will deal shared, zero and write monitored
890 * pages.
891 *
892 * @returns VBox status code.
893 * @param pVCpu VMCPU handle.
894 * @param GCPtr Virtual address of the first page in the range.
895 * @param fMmio2 Set if it is an MMIO2 page.
896 * @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
897 */
898VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
899{
900 return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
901}
902
903
904/**
905 * Changing the page flags for a single page in the shadow page tables so as to
906 * make it not present.
907 *
908 * @returns VBox status code.
909 * @param pVCpu VMCPU handle.
910 * @param GCPtr Virtual address of the first page in the range.
911 * @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
912 */
913VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
914{
915 return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
916}
917
918
919/**
920 * Gets the shadow page directory for the specified address, PAE.
921 *
922 * @returns Pointer to the shadow PD.
923 * @param pVCpu The VMCPU handle.
924 * @param GCPtr The address.
925 * @param uGstPdpe Guest PDPT entry. Valid.
926 * @param ppPD Receives address of page directory
927 */
928int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
929{
930 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
931 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
932 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
933 PVM pVM = pVCpu->CTX_SUFF(pVM);
934 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
935 PPGMPOOLPAGE pShwPage;
936 int rc;
937
938 Assert(PGMIsLockOwner(pVM));
939
940 /* Allocate page directory if not present. */
941 if ( !pPdpe->n.u1Present
942 && !(pPdpe->u & X86_PDPE_PG_MASK))
943 {
944 RTGCPTR64 GCPdPt;
945 PGMPOOLKIND enmKind;
946
947 if (pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu))
948 {
949 /* AMD-V nested paging or real/protected mode without paging. */
950 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
951 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
952 }
953 else
954 {
955 if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
956 {
957 if (!(uGstPdpe & X86_PDPE_P))
958 {
959 /* PD not present; guest must reload CR3 to change it.
960 * No need to monitor anything in this case.
961 */
962 Assert(!HWACCMIsEnabled(pVM));
963
964 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
965 enmKind = PGMPOOLKIND_PAE_PD_PHYS;
966 uGstPdpe |= X86_PDPE_P;
967 }
968 else
969 {
970 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
971 enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
972 }
973 }
974 else
975 {
976 GCPdPt = CPUMGetGuestCR3(pVCpu);
977 enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
978 }
979 }
980
981 /* Create a reference back to the PDPT by using the index in its shadow page. */
982 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
983 AssertRCReturn(rc, rc);
984
985 /* The PD was cached or created; hook it up now. */
986 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & (X86_PDPE_P | X86_PDPE_A));
987
988# if defined(IN_RC)
989 /*
990 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
991 * PDPT entry; the CPU fetches them only during cr3 load, so any
992 * non-present PDPT will continue to cause page faults.
993 */
994 ASMReloadCR3();
995# endif
996 PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
997 }
998 else
999 {
1000 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1001 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1002 Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1003
1004 pgmPoolCacheUsed(pPool, pShwPage);
1005 }
1006 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1007 return VINF_SUCCESS;
1008}
1009
1010
1011/**
1012 * Gets the pointer to the shadow page directory entry for an address, PAE.
1013 *
1014 * @returns Pointer to the PDE.
1015 * @param pVCpu The current CPU.
1016 * @param GCPtr The address.
1017 * @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1018 */
1019DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1020{
1021 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1022 PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1023 PVM pVM = pVCpu->CTX_SUFF(pVM);
1024
1025 Assert(PGMIsLockOwner(pVM));
1026
1027 AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1028 if (!pPdpt->a[iPdPt].n.u1Present)
1029 {
1030 LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
1031 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1032 }
1033 AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1034
1035 /* Fetch the pgm pool shadow descriptor. */
1036 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1037 AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
1038
1039 *ppShwPde = pShwPde;
1040 return VINF_SUCCESS;
1041}
1042
1043#ifndef IN_RC
1044
1045/**
1046 * Syncs the SHADOW page directory pointer for the specified address.
1047 *
1048 * Allocates backing pages in case the PDPT or PML4 entry is missing.
1049 *
1050 * The caller is responsible for making sure the guest has a valid PD before
1051 * calling this function.
1052 *
1053 * @returns VBox status.
1054 * @param pVCpu VMCPU handle.
1055 * @param GCPtr The address.
1056 * @param uGstPml4e Guest PML4 entry (valid).
1057 * @param uGstPdpe Guest PDPT entry (valid).
1058 * @param ppPD Receives address of page directory
1059 */
1060static int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1061{
1062 PPGMCPU pPGM = &pVCpu->pgm.s;
1063 PVM pVM = pVCpu->CTX_SUFF(pVM);
1064 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1065 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1066 PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1067 bool fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging || !CPUMIsGuestPagingEnabled(pVCpu);
1068 PPGMPOOLPAGE pShwPage;
1069 int rc;
1070
1071 Assert(PGMIsLockOwner(pVM));
1072
1073 /* Allocate page directory pointer table if not present. */
1074 if ( !pPml4e->n.u1Present
1075 && !(pPml4e->u & X86_PML4E_PG_MASK))
1076 {
1077 RTGCPTR64 GCPml4;
1078 PGMPOOLKIND enmKind;
1079
1080 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1081
1082 if (fNestedPagingOrNoGstPaging)
1083 {
1084 /* AMD-V nested paging or real/protected mode without paging */
1085 GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1086 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1087 }
1088 else
1089 {
1090 GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1091 enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1092 }
1093
1094 /* Create a reference back to the PDPT by using the index in its shadow page. */
1095 rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1096 AssertRCReturn(rc, rc);
1097 }
1098 else
1099 {
1100 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1101 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1102
1103 pgmPoolCacheUsed(pPool, pShwPage);
1104 }
1105 /* The PDPT was cached or created; hook it up now. */
1106 pPml4e->u |= pShwPage->Core.Key | (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask);
1107
1108 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1109 PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1110 PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1111
1112 /* Allocate page directory if not present. */
1113 if ( !pPdpe->n.u1Present
1114 && !(pPdpe->u & X86_PDPE_PG_MASK))
1115 {
1116 RTGCPTR64 GCPdPt;
1117 PGMPOOLKIND enmKind;
1118
1119 if (fNestedPagingOrNoGstPaging)
1120 {
1121 /* AMD-V nested paging or real/protected mode without paging */
1122 GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1123 enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1124 }
1125 else
1126 {
1127 GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1128 enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1129 }
1130
1131 /* Create a reference back to the PDPT by using the index in its shadow page. */
1132 rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1133 AssertRCReturn(rc, rc);
1134 }
1135 else
1136 {
1137 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1138 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1139
1140 pgmPoolCacheUsed(pPool, pShwPage);
1141 }
1142 /* The PD was cached or created; hook it up now. */
1143 pPdpe->u |= pShwPage->Core.Key | (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask);
1144
1145 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1146 return VINF_SUCCESS;
1147}
1148
1149
1150/**
1151 * Gets the SHADOW page directory pointer for the specified address (long mode).
1152 *
1153 * @returns VBox status.
1154 * @param pVCpu VMCPU handle.
1155 * @param GCPtr The address.
1156 * @param ppPdpt Receives address of pdpt
1157 * @param ppPD Receives address of page directory
1158 */
1159DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPT *ppPdpt, PX86PDPAE *ppPD)
1160{
1161 PPGMCPU pPGM = &pVCpu->pgm.s;
1162 const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1163 PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1164
1165 Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1166
1167 AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1168 if (ppPml4e)
1169 *ppPml4e = (PX86PML4E)pPml4e;
1170
1171 Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1172
1173 if (!pPml4e->n.u1Present)
1174 return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1175
1176 PVM pVM = pVCpu->CTX_SUFF(pVM);
1177 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1178 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1179 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1180
1181 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1182 PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1183 if (!pPdpt->a[iPdPt].n.u1Present)
1184 return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1185
1186 pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1187 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1188
1189 *ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1190 Log4(("pgmShwGetLongModePDPtr %RGv -> *ppPD=%p PDE=%p/%RX64\n", GCPtr, *ppPD, &(*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (*ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1191 return VINF_SUCCESS;
1192}
1193
1194
1195/**
1196 * Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1197 * backing pages in case the PDPT or PML4 entry is missing.
1198 *
1199 * @returns VBox status.
1200 * @param pVCpu VMCPU handle.
1201 * @param GCPtr The address.
1202 * @param ppPdpt Receives address of pdpt
1203 * @param ppPD Receives address of page directory
1204 */
1205static int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD)
1206{
1207 PVM pVM = pVCpu->CTX_SUFF(pVM);
1208 const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1209 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1210 PEPTPML4 pPml4;
1211 PEPTPML4E pPml4e;
1212 PPGMPOOLPAGE pShwPage;
1213 int rc;
1214
1215 Assert(pVM->pgm.s.fNestedPaging);
1216 Assert(PGMIsLockOwner(pVM));
1217
1218 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1219 Assert(pPml4);
1220
1221 /* Allocate page directory pointer table if not present. */
1222 pPml4e = &pPml4->a[iPml4];
1223 if ( !pPml4e->n.u1Present
1224 && !(pPml4e->u & EPT_PML4E_PG_MASK))
1225 {
1226 Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1227 RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1228
1229 rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1230 AssertRCReturn(rc, rc);
1231 }
1232 else
1233 {
1234 pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1235 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1236
1237 pgmPoolCacheUsed(pPool, pShwPage);
1238 }
1239 /* The PDPT was cached or created; hook it up now and fill with the default value. */
1240 pPml4e->u = pShwPage->Core.Key;
1241 pPml4e->n.u1Present = 1;
1242 pPml4e->n.u1Write = 1;
1243 pPml4e->n.u1Execute = 1;
1244
1245 const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1246 PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1247 PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1248
1249 if (ppPdpt)
1250 *ppPdpt = pPdpt;
1251
1252 /* Allocate page directory if not present. */
1253 if ( !pPdpe->n.u1Present
1254 && !(pPdpe->u & EPT_PDPTE_PG_MASK))
1255 {
1256 RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1257
1258 rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1259 AssertRCReturn(rc, rc);
1260 }
1261 else
1262 {
1263 pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1264 AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1265
1266 pgmPoolCacheUsed(pPool, pShwPage);
1267 }
1268 /* The PD was cached or created; hook it up now and fill with the default value. */
1269 pPdpe->u = pShwPage->Core.Key;
1270 pPdpe->n.u1Present = 1;
1271 pPdpe->n.u1Write = 1;
1272 pPdpe->n.u1Execute = 1;
1273
1274 *ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1275 return VINF_SUCCESS;
1276}
1277
1278#endif /* IN_RC */
1279
1280#ifdef IN_RING0
1281/**
1282 * Synchronizes a range of nested page table entries.
1283 *
1284 * The caller must own the PGM lock.
1285 *
1286 * @param pVCpu The current CPU.
1287 * @param GCPhys Where to start.
1288 * @param cPages How many pages which entries should be synced.
1289 * @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1290 * host paging mode for AMD-V).
1291 */
1292int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode)
1293{
1294 Assert(PGMIsLockOwner(pVCpu->CTX_SUFF(pVM)));
1295
1296 int rc;
1297 switch (enmShwPagingMode)
1298 {
1299 case PGMMODE_32_BIT:
1300 {
1301 X86PDE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1302 rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1303 break;
1304 }
1305
1306 case PGMMODE_PAE:
1307 case PGMMODE_PAE_NX:
1308 {
1309 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1310 rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1311 break;
1312 }
1313
1314 case PGMMODE_AMD64:
1315 case PGMMODE_AMD64_NX:
1316 {
1317 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1318 rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1319 break;
1320 }
1321
1322 case PGMMODE_EPT:
1323 {
1324 X86PDEPAE PdeDummy = { X86_PDE_P | X86_PDE_US | X86_PDE_RW | X86_PDE_A };
1325 rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhysFault, cPages, ~0U /*uErr*/);
1326 break;
1327 }
1328
1329 default:
1330 AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_INTERNAL_ERROR_5);
1331 }
1332 return rc;
1333}
1334#endif /* IN_RING0 */
1335
1336
1337/**
1338 * Gets effective Guest OS page information.
1339 *
1340 * When GCPtr is in a big page, the function will return as if it was a normal
1341 * 4KB page. If the need for distinguishing between big and normal page becomes
1342 * necessary at a later point, a PGMGstGetPage() will be created for that
1343 * purpose.
1344 *
1345 * @returns VBox status.
1346 * @param pVCpu VMCPU handle.
1347 * @param GCPtr Guest Context virtual address of the page.
1348 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1349 * @param pGCPhys Where to store the GC physical address of the page.
1350 * This is page aligned. The fact that the
1351 */
1352VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1353{
1354 return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1355}
1356
1357
1358/**
1359 * Checks if the page is present.
1360 *
1361 * @returns true if the page is present.
1362 * @returns false if the page is not present.
1363 * @param pVCpu VMCPU handle.
1364 * @param GCPtr Address within the page.
1365 */
1366VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1367{
1368 int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1369 return RT_SUCCESS(rc);
1370}
1371
1372
1373/**
1374 * Sets (replaces) the page flags for a range of pages in the guest's tables.
1375 *
1376 * @returns VBox status.
1377 * @param pVCpu VMCPU handle.
1378 * @param GCPtr The address of the first page.
1379 * @param cb The size of the range in bytes.
1380 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1381 */
1382VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1383{
1384 return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1385}
1386
1387
1388/**
1389 * Modify page flags for a range of pages in the guest's tables
1390 *
1391 * The existing flags are ANDed with the fMask and ORed with the fFlags.
1392 *
1393 * @returns VBox status code.
1394 * @param pVCpu VMCPU handle.
1395 * @param GCPtr Virtual address of the first page in the range.
1396 * @param cb Size (in bytes) of the range to apply the modification to.
1397 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1398 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1399 * Be very CAREFUL when ~'ing constants which could be 32-bit!
1400 */
1401VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1402{
1403 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1404
1405 /*
1406 * Validate input.
1407 */
1408 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1409 Assert(cb);
1410
1411 LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1412
1413 /*
1414 * Adjust input.
1415 */
1416 cb += GCPtr & PAGE_OFFSET_MASK;
1417 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1418 GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1419
1420 /*
1421 * Call worker.
1422 */
1423 int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1424
1425 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,GstModifyPage), a);
1426 return rc;
1427}
1428
1429
1430#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1431
1432/**
1433 * Performs the lazy mapping of the 32-bit guest PD.
1434 *
1435 * @returns VBox status code.
1436 * @param pVCpu The current CPU.
1437 * @param ppPd Where to return the pointer to the mapping. This is
1438 * always set.
1439 */
1440int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd)
1441{
1442 PVM pVM = pVCpu->CTX_SUFF(pVM);
1443 pgmLock(pVM);
1444
1445 Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
1446
1447 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAGE_MASK;
1448 PPGMPAGE pPage;
1449 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1450 if (RT_SUCCESS(rc))
1451 {
1452 RTHCPTR HCPtrGuestCR3;
1453 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1454 if (RT_SUCCESS(rc))
1455 {
1456 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1457# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1458 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1459# endif
1460 *ppPd = (PX86PD)HCPtrGuestCR3;
1461
1462 pgmUnlock(pVM);
1463 return VINF_SUCCESS;
1464 }
1465
1466 AssertRC(rc);
1467 }
1468 pgmUnlock(pVM);
1469
1470 *ppPd = NULL;
1471 return rc;
1472}
1473
1474
1475/**
1476 * Performs the lazy mapping of the PAE guest PDPT.
1477 *
1478 * @returns VBox status code.
1479 * @param pVCpu The current CPU.
1480 * @param ppPdpt Where to return the pointer to the mapping. This is
1481 * always set.
1482 */
1483int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt)
1484{
1485 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
1486 PVM pVM = pVCpu->CTX_SUFF(pVM);
1487 pgmLock(pVM);
1488
1489 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
1490 PPGMPAGE pPage;
1491 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1492 if (RT_SUCCESS(rc))
1493 {
1494 RTHCPTR HCPtrGuestCR3;
1495 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1496 if (RT_SUCCESS(rc))
1497 {
1498 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1499# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1500 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1501# endif
1502 *ppPdpt = (PX86PDPT)HCPtrGuestCR3;
1503
1504 pgmUnlock(pVM);
1505 return VINF_SUCCESS;
1506 }
1507
1508 AssertRC(rc);
1509 }
1510
1511 pgmUnlock(pVM);
1512 *ppPdpt = NULL;
1513 return rc;
1514}
1515
1516
1517/**
1518 * Performs the lazy mapping / updating of a PAE guest PD.
1519 *
1520 * @returns Pointer to the mapping.
1521 * @returns VBox status code.
1522 * @param pVCpu The current CPU.
1523 * @param iPdpt Which PD entry to map (0..3).
1524 * @param ppPd Where to return the pointer to the mapping. This is
1525 * always set.
1526 */
1527int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
1528{
1529 PVM pVM = pVCpu->CTX_SUFF(pVM);
1530 pgmLock(pVM);
1531
1532 PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
1533 Assert(pGuestPDPT);
1534 Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1535 RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1536 bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
1537
1538 PPGMPAGE pPage;
1539 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1540 if (RT_SUCCESS(rc))
1541 {
1542 RTRCPTR RCPtr = NIL_RTRCPTR;
1543 RTHCPTR HCPtr = NIL_RTHCPTR;
1544#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1545 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1546 AssertRC(rc);
1547#endif
1548 if (RT_SUCCESS(rc) && fChanged)
1549 {
1550 RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1551 rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1552 }
1553 if (RT_SUCCESS(rc))
1554 {
1555 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1556# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1557 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1558# endif
1559 if (fChanged)
1560 {
1561 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
1562 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1563 }
1564
1565 *ppPd = pVCpu->pgm.s.CTX_SUFF(apGstPaePDs)[iPdpt];
1566 pgmUnlock(pVM);
1567 return VINF_SUCCESS;
1568 }
1569 }
1570
1571 /* Invalid page or some failure, invalidate the entry. */
1572 pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1573 pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = 0;
1574# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1575 pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = 0;
1576# endif
1577 pVCpu->pgm.s.apGstPaePDsRC[iPdpt] = 0;
1578
1579 pgmUnlock(pVM);
1580 return rc;
1581}
1582
1583#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1584#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1585/**
1586 * Performs the lazy mapping of the 32-bit guest PD.
1587 *
1588 * @returns VBox status code.
1589 * @param pVCpu The current CPU.
1590 * @param ppPml4 Where to return the pointer to the mapping. This will
1591 * always be set.
1592 */
1593int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4)
1594{
1595 Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
1596 PVM pVM = pVCpu->CTX_SUFF(pVM);
1597 pgmLock(pVM);
1598
1599 RTGCPHYS GCPhysCR3 = pVCpu->pgm.s.GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK;
1600 PPGMPAGE pPage;
1601 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysCR3, &pPage);
1602 if (RT_SUCCESS(rc))
1603 {
1604 RTHCPTR HCPtrGuestCR3;
1605 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3, (void **)&HCPtrGuestCR3);
1606 if (RT_SUCCESS(rc))
1607 {
1608 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1609# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1610 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1611# endif
1612 *ppPml4 = (PX86PML4)HCPtrGuestCR3;
1613
1614 pgmUnlock(pVM);
1615 return VINF_SUCCESS;
1616 }
1617 }
1618
1619 pgmUnlock(pVM);
1620 *ppPml4 = NULL;
1621 return rc;
1622}
1623#endif
1624
1625/**
1626 * Gets the specified page directory pointer table entry.
1627 *
1628 * @returns PDP entry
1629 * @param pVCpu VMCPU handle.
1630 * @param iPdpt PDPT index
1631 */
1632VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1633{
1634 Assert(iPdpt <= 3);
1635 return pgmGstGetPaePDPTPtr(pVCpu)->a[iPdpt & 3];
1636}
1637
1638
1639/**
1640 * Gets the current CR3 register value for the shadow memory context.
1641 * @returns CR3 value.
1642 * @param pVCpu VMCPU handle.
1643 */
1644VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1645{
1646 PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1647 AssertPtrReturn(pPoolPage, 0);
1648 return pPoolPage->Core.Key;
1649}
1650
1651
1652/**
1653 * Gets the current CR3 register value for the nested memory context.
1654 * @returns CR3 value.
1655 * @param pVCpu VMCPU handle.
1656 */
1657VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1658{
1659 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1660 return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1661}
1662
1663
1664/**
1665 * Gets the current CR3 register value for the HC intermediate memory context.
1666 * @returns CR3 value.
1667 * @param pVM The VM handle.
1668 */
1669VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1670{
1671 switch (pVM->pgm.s.enmHostMode)
1672 {
1673 case SUPPAGINGMODE_32_BIT:
1674 case SUPPAGINGMODE_32_BIT_GLOBAL:
1675 return pVM->pgm.s.HCPhysInterPD;
1676
1677 case SUPPAGINGMODE_PAE:
1678 case SUPPAGINGMODE_PAE_GLOBAL:
1679 case SUPPAGINGMODE_PAE_NX:
1680 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1681 return pVM->pgm.s.HCPhysInterPaePDPT;
1682
1683 case SUPPAGINGMODE_AMD64:
1684 case SUPPAGINGMODE_AMD64_GLOBAL:
1685 case SUPPAGINGMODE_AMD64_NX:
1686 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1687 return pVM->pgm.s.HCPhysInterPaePDPT;
1688
1689 default:
1690 AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1691 return ~0;
1692 }
1693}
1694
1695
1696/**
1697 * Gets the current CR3 register value for the RC intermediate memory context.
1698 * @returns CR3 value.
1699 * @param pVM The VM handle.
1700 * @param pVCpu VMCPU handle.
1701 */
1702VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1703{
1704 switch (pVCpu->pgm.s.enmShadowMode)
1705 {
1706 case PGMMODE_32_BIT:
1707 return pVM->pgm.s.HCPhysInterPD;
1708
1709 case PGMMODE_PAE:
1710 case PGMMODE_PAE_NX:
1711 return pVM->pgm.s.HCPhysInterPaePDPT;
1712
1713 case PGMMODE_AMD64:
1714 case PGMMODE_AMD64_NX:
1715 return pVM->pgm.s.HCPhysInterPaePML4;
1716
1717 case PGMMODE_EPT:
1718 case PGMMODE_NESTED:
1719 return 0; /* not relevant */
1720
1721 default:
1722 AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1723 return ~0;
1724 }
1725}
1726
1727
1728/**
1729 * Gets the CR3 register value for the 32-Bit intermediate memory context.
1730 * @returns CR3 value.
1731 * @param pVM The VM handle.
1732 */
1733VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1734{
1735 return pVM->pgm.s.HCPhysInterPD;
1736}
1737
1738
1739/**
1740 * Gets the CR3 register value for the PAE intermediate memory context.
1741 * @returns CR3 value.
1742 * @param pVM The VM handle.
1743 */
1744VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1745{
1746 return pVM->pgm.s.HCPhysInterPaePDPT;
1747}
1748
1749
1750/**
1751 * Gets the CR3 register value for the AMD64 intermediate memory context.
1752 * @returns CR3 value.
1753 * @param pVM The VM handle.
1754 */
1755VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1756{
1757 return pVM->pgm.s.HCPhysInterPaePML4;
1758}
1759
1760
1761/**
1762 * Performs and schedules necessary updates following a CR3 load or reload.
1763 *
1764 * This will normally involve mapping the guest PD or nPDPT
1765 *
1766 * @returns VBox status code.
1767 * @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1768 * safely be ignored and overridden since the FF will be set too then.
1769 * @param pVCpu VMCPU handle.
1770 * @param cr3 The new cr3.
1771 * @param fGlobal Indicates whether this is a global flush or not.
1772 */
1773VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1774{
1775 PVM pVM = pVCpu->CTX_SUFF(pVM);
1776
1777 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1778
1779 /*
1780 * Always flag the necessary updates; necessary for hardware acceleration
1781 */
1782 /** @todo optimize this, it shouldn't always be necessary. */
1783 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1784 if (fGlobal)
1785 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1786 LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1787
1788 /*
1789 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1790 */
1791 int rc = VINF_SUCCESS;
1792 RTGCPHYS GCPhysCR3;
1793 switch (pVCpu->pgm.s.enmGuestMode)
1794 {
1795 case PGMMODE_PAE:
1796 case PGMMODE_PAE_NX:
1797 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1798 break;
1799 case PGMMODE_AMD64:
1800 case PGMMODE_AMD64_NX:
1801 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1802 break;
1803 default:
1804 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1805 break;
1806 }
1807
1808 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1809 {
1810 RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1811 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1812 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1813 if (RT_LIKELY(rc == VINF_SUCCESS))
1814 {
1815 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1816 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1817 }
1818 else
1819 {
1820 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1821 Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));
1822 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1823 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3;
1824 if (pgmMapAreMappingsFloating(&pVM->pgm.s))
1825 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1826 }
1827
1828 if (fGlobal)
1829 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1830 else
1831 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBNewCR3));
1832 }
1833 else
1834 {
1835# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1836 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1837 if (pPool->cDirtyPages)
1838 {
1839 pgmLock(pVM);
1840 pgmPoolResetDirtyPages(pVM);
1841 pgmUnlock(pVM);
1842 }
1843# endif
1844 /*
1845 * Check if we have a pending update of the CR3 monitoring.
1846 */
1847 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1848 {
1849 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1850 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
1851 }
1852 if (fGlobal)
1853 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1854 else
1855 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLBSameCR3));
1856 }
1857
1858 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FlushTLB), a);
1859 return rc;
1860}
1861
1862
1863/**
1864 * Performs and schedules necessary updates following a CR3 load or reload when
1865 * using nested or extended paging.
1866 *
1867 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1868 * TLB and triggering a SyncCR3.
1869 *
1870 * This will normally involve mapping the guest PD or nPDPT
1871 *
1872 * @returns VBox status code.
1873 * @retval VINF_SUCCESS.
1874 * @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1875 * requires a CR3 sync. This can safely be ignored and overridden since
1876 * the FF will be set too then.)
1877 * @param pVCpu VMCPU handle.
1878 * @param cr3 The new cr3.
1879 */
1880VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1881{
1882 PVM pVM = pVCpu->CTX_SUFF(pVM);
1883
1884 LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1885
1886 /* We assume we're only called in nested paging mode. */
1887 Assert(pVM->pgm.s.fNestedPaging || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1888 Assert(pVM->pgm.s.fMappingsDisabled);
1889 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1890
1891 /*
1892 * Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1893 */
1894 int rc = VINF_SUCCESS;
1895 RTGCPHYS GCPhysCR3;
1896 switch (pVCpu->pgm.s.enmGuestMode)
1897 {
1898 case PGMMODE_PAE:
1899 case PGMMODE_PAE_NX:
1900 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1901 break;
1902 case PGMMODE_AMD64:
1903 case PGMMODE_AMD64_NX:
1904 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1905 break;
1906 default:
1907 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1908 break;
1909 }
1910 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1911 {
1912 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1913 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1914 AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
1915 }
1916 return rc;
1917}
1918
1919
1920/**
1921 * Synchronize the paging structures.
1922 *
1923 * This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1924 * VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1925 * in several places, most importantly whenever the CR3 is loaded.
1926 *
1927 * @returns VBox status code.
1928 * @param pVCpu VMCPU handle.
1929 * @param cr0 Guest context CR0 register
1930 * @param cr3 Guest context CR3 register
1931 * @param cr4 Guest context CR4 register
1932 * @param fGlobal Including global page directories or not
1933 */
1934VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1935{
1936 PVM pVM = pVCpu->CTX_SUFF(pVM);
1937 int rc;
1938
1939 /*
1940 * The pool may have pending stuff and even require a return to ring-3 to
1941 * clear the whole thing.
1942 */
1943 rc = pgmPoolSyncCR3(pVCpu);
1944 if (rc != VINF_SUCCESS)
1945 return rc;
1946
1947 /*
1948 * We might be called when we shouldn't.
1949 *
1950 * The mode switching will ensure that the PD is resynced
1951 * after every mode switch. So, if we find ourselves here
1952 * when in protected or real mode we can safely disable the
1953 * FF and return immediately.
1954 */
1955 if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1956 {
1957 Assert((cr0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE));
1958 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
1959 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1960 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1961 return VINF_SUCCESS;
1962 }
1963
1964 /* If global pages are not supported, then all flushes are global. */
1965 if (!(cr4 & X86_CR4_PGE))
1966 fGlobal = true;
1967 LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1968 VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1969
1970 /*
1971 * Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1972 * This should be done before SyncCR3.
1973 */
1974 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1975 {
1976 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1977
1978 RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1979 RTGCPHYS GCPhysCR3;
1980 switch (pVCpu->pgm.s.enmGuestMode)
1981 {
1982 case PGMMODE_PAE:
1983 case PGMMODE_PAE_NX:
1984 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1985 break;
1986 case PGMMODE_AMD64:
1987 case PGMMODE_AMD64_NX:
1988 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1989 break;
1990 default:
1991 GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1992 break;
1993 }
1994
1995 if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1996 {
1997 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1998 rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1999 }
2000 /* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2001 if ( rc == VINF_PGM_SYNC_CR3
2002 || (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2003 {
2004 Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2005#ifdef IN_RING3
2006 rc = pgmPoolSyncCR3(pVCpu);
2007#else
2008 if (rc == VINF_PGM_SYNC_CR3)
2009 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
2010 return VINF_PGM_SYNC_CR3;
2011#endif
2012 }
2013 AssertRCReturn(rc, rc);
2014 AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
2015 }
2016
2017 /*
2018 * Let the 'Bth' function do the work and we'll just keep track of the flags.
2019 */
2020 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2021 rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
2022 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2023 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2024 if (rc == VINF_SUCCESS)
2025 {
2026 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2027 {
2028 /* Go back to ring 3 if a pgm pool sync is again pending. */
2029 return VINF_PGM_SYNC_CR3;
2030 }
2031
2032 if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2033 {
2034 Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2035 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2036 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2037 }
2038
2039 /*
2040 * Check if we have a pending update of the CR3 monitoring.
2041 */
2042 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
2043 {
2044 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
2045 Assert(!pVM->pgm.s.fMappingsFixed); Assert(!pVM->pgm.s.fMappingsDisabled);
2046 }
2047 }
2048
2049 /*
2050 * Now flush the CR3 (guest context).
2051 */
2052 if (rc == VINF_SUCCESS)
2053 PGM_INVL_VCPU_TLBS(pVCpu);
2054 return rc;
2055}
2056
2057
2058/**
2059 * Called whenever CR0 or CR4 in a way which may affect the paging mode.
2060 *
2061 * @returns VBox status code, with the following informational code for
2062 * VM scheduling.
2063 * @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
2064 * @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
2065 * (I.e. not in R3.)
2066 * @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
2067 *
2068 * @param pVCpu VMCPU handle.
2069 * @param cr0 The new cr0.
2070 * @param cr4 The new cr4.
2071 * @param efer The new extended feature enable register.
2072 */
2073VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
2074{
2075 PVM pVM = pVCpu->CTX_SUFF(pVM);
2076 PGMMODE enmGuestMode;
2077
2078 /*
2079 * Calc the new guest mode.
2080 */
2081 if (!(cr0 & X86_CR0_PE))
2082 enmGuestMode = PGMMODE_REAL;
2083 else if (!(cr0 & X86_CR0_PG))
2084 enmGuestMode = PGMMODE_PROTECTED;
2085 else if (!(cr4 & X86_CR4_PAE))
2086 {
2087 bool const fPse = !!(cr4 & X86_CR4_PSE);
2088 if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
2089 Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
2090 pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
2091 enmGuestMode = PGMMODE_32_BIT;
2092 }
2093 else if (!(efer & MSR_K6_EFER_LME))
2094 {
2095 if (!(efer & MSR_K6_EFER_NXE))
2096 enmGuestMode = PGMMODE_PAE;
2097 else
2098 enmGuestMode = PGMMODE_PAE_NX;
2099 }
2100 else
2101 {
2102 if (!(efer & MSR_K6_EFER_NXE))
2103 enmGuestMode = PGMMODE_AMD64;
2104 else
2105 enmGuestMode = PGMMODE_AMD64_NX;
2106 }
2107
2108 /*
2109 * Did it change?
2110 */
2111 if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
2112 return VINF_SUCCESS;
2113
2114 /* Flush the TLB */
2115 PGM_INVL_VCPU_TLBS(pVCpu);
2116
2117#ifdef IN_RING3
2118 return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
2119#else
2120 LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
2121 return VINF_PGM_CHANGE_MODE;
2122#endif
2123}
2124
2125
2126/**
2127 * Gets the current guest paging mode.
2128 *
2129 * If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
2130 *
2131 * @returns The current paging mode.
2132 * @param pVCpu VMCPU handle.
2133 */
2134VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
2135{
2136 return pVCpu->pgm.s.enmGuestMode;
2137}
2138
2139
2140/**
2141 * Gets the current shadow paging mode.
2142 *
2143 * @returns The current paging mode.
2144 * @param pVCpu VMCPU handle.
2145 */
2146VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2147{
2148 return pVCpu->pgm.s.enmShadowMode;
2149}
2150
2151/**
2152 * Gets the current host paging mode.
2153 *
2154 * @returns The current paging mode.
2155 * @param pVM The VM handle.
2156 */
2157VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2158{
2159 switch (pVM->pgm.s.enmHostMode)
2160 {
2161 case SUPPAGINGMODE_32_BIT:
2162 case SUPPAGINGMODE_32_BIT_GLOBAL:
2163 return PGMMODE_32_BIT;
2164
2165 case SUPPAGINGMODE_PAE:
2166 case SUPPAGINGMODE_PAE_GLOBAL:
2167 return PGMMODE_PAE;
2168
2169 case SUPPAGINGMODE_PAE_NX:
2170 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2171 return PGMMODE_PAE_NX;
2172
2173 case SUPPAGINGMODE_AMD64:
2174 case SUPPAGINGMODE_AMD64_GLOBAL:
2175 return PGMMODE_AMD64;
2176
2177 case SUPPAGINGMODE_AMD64_NX:
2178 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2179 return PGMMODE_AMD64_NX;
2180
2181 default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2182 }
2183
2184 return PGMMODE_INVALID;
2185}
2186
2187
2188/**
2189 * Get mode name.
2190 *
2191 * @returns read-only name string.
2192 * @param enmMode The mode which name is desired.
2193 */
2194VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2195{
2196 switch (enmMode)
2197 {
2198 case PGMMODE_REAL: return "Real";
2199 case PGMMODE_PROTECTED: return "Protected";
2200 case PGMMODE_32_BIT: return "32-bit";
2201 case PGMMODE_PAE: return "PAE";
2202 case PGMMODE_PAE_NX: return "PAE+NX";
2203 case PGMMODE_AMD64: return "AMD64";
2204 case PGMMODE_AMD64_NX: return "AMD64+NX";
2205 case PGMMODE_NESTED: return "Nested";
2206 case PGMMODE_EPT: return "EPT";
2207 default: return "unknown mode value";
2208 }
2209}
2210
2211
2212
2213/**
2214 * Notification from CPUM that the EFER.NXE bit has changed.
2215 *
2216 * @param pVCpu The virtual CPU for which EFER changed.
2217 * @param fNxe The new NXE state.
2218 */
2219VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
2220{
2221 Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
2222 pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
2223 if (fNxe)
2224 {
2225 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2226 pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
2227 pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
2228 pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2229 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A */
2230 pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
2231 pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
2232 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
2233 pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
2234 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
2235 pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
2236
2237 pVCpu->pgm.s.fGst64ShadowedPteMask |= X86_PTE_PAE_NX;
2238 pVCpu->pgm.s.fGst64ShadowedPdeMask |= X86_PDE_PAE_NX;
2239 pVCpu->pgm.s.fGst64ShadowedBigPdeMask |= X86_PDE2M_PAE_NX;
2240 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask |= X86_PDE2M_PAE_NX;
2241 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask |= X86_PDPE_LM_NX;
2242 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask |= X86_PML4E_NX;
2243 }
2244 else
2245 {
2246 /*pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A */
2247 pVCpu->pgm.s.fGstPaeMbzPteMask |= X86_PTE_PAE_NX;
2248 pVCpu->pgm.s.fGstPaeMbzPdeMask |= X86_PDE_PAE_NX;
2249 pVCpu->pgm.s.fGstPaeMbzBigPdeMask |= X86_PDE2M_PAE_NX;
2250 /*pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A */
2251 pVCpu->pgm.s.fGstAmd64MbzPteMask |= X86_PTE_PAE_NX;
2252 pVCpu->pgm.s.fGstAmd64MbzPdeMask |= X86_PDE_PAE_NX;
2253 pVCpu->pgm.s.fGstAmd64MbzBigPdeMask |= X86_PDE2M_PAE_NX;
2254 pVCpu->pgm.s.fGstAmd64MbzPdpeMask |= X86_PDPE_LM_NX;
2255 pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask |= X86_PDPE_LM_NX;
2256 pVCpu->pgm.s.fGstAmd64MbzPml4eMask |= X86_PML4E_NX;
2257
2258 pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
2259 pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
2260 pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
2261 pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
2262 pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
2263 pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
2264 }
2265}
2266
2267
2268/**
2269 * Check if any pgm pool pages are marked dirty (not monitored)
2270 *
2271 * @returns bool locked/not locked
2272 * @param pVM The VM to operate on.
2273 */
2274VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
2275{
2276 return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
2277}
2278
2279/**
2280 * Check if the PGM lock is currently taken.
2281 *
2282 * @returns bool locked/not locked
2283 * @param pVM The VM to operate on.
2284 */
2285VMMDECL(bool) PGMIsLocked(PVM pVM)
2286{
2287 return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2288}
2289
2290
2291/**
2292 * Check if this VCPU currently owns the PGM lock.
2293 *
2294 * @returns bool owner/not owner
2295 * @param pVM The VM to operate on.
2296 */
2297VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2298{
2299 return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2300}
2301
2302
2303/**
2304 * Enable or disable large page usage
2305 *
2306 * @param pVM The VM to operate on.
2307 * @param fUseLargePages Use/not use large pages
2308 */
2309VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages)
2310{
2311 pVM->fUseLargePages = fUseLargePages;
2312}
2313
2314/**
2315 * Acquire the PGM lock.
2316 *
2317 * @returns VBox status code
2318 * @param pVM The VM to operate on.
2319 */
2320int pgmLock(PVM pVM)
2321{
2322 int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2323#if defined(IN_RC) || defined(IN_RING0)
2324 if (rc == VERR_SEM_BUSY)
2325 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2326#endif
2327 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2328 return rc;
2329}
2330
2331
2332/**
2333 * Release the PGM lock.
2334 *
2335 * @returns VBox status code
2336 * @param pVM The VM to operate on.
2337 */
2338void pgmUnlock(PVM pVM)
2339{
2340 PDMCritSectLeave(&pVM->pgm.s.CritSect);
2341}
2342
2343#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2344
2345/**
2346 * Common worker for pgmRZDynMapGCPageOffInlined and pgmRZDynMapGCPageV2Inlined.
2347 *
2348 * @returns VBox status code.
2349 * @param pVM The VM handle.
2350 * @param pVCpu The current CPU.
2351 * @param GCPhys The guest physical address of the page to map. The
2352 * offset bits are not ignored.
2353 * @param ppv Where to return the address corresponding to @a GCPhys.
2354 */
2355int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL)
2356{
2357 pgmLock(pVM);
2358
2359 /*
2360 * Convert it to a writable page and it on to the dynamic mapper.
2361 */
2362 int rc;
2363 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2364 if (RT_LIKELY(pPage))
2365 {
2366 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2367 if (RT_SUCCESS(rc))
2368 {
2369 void *pv;
2370 rc = pgmRZDynMapHCPageInlined(pVCpu, PGM_PAGE_GET_HCPHYS(pPage), &pv RTLOG_COMMA_SRC_POS_ARGS);
2371 if (RT_SUCCESS(rc))
2372 *ppv = (void *)((uintptr_t)pv | ((uintptr_t)GCPhys & PAGE_OFFSET_MASK));
2373 }
2374 else
2375 AssertRC(rc);
2376 }
2377 else
2378 {
2379 AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2380 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2381 }
2382
2383 pgmUnlock(pVM);
2384 return rc;
2385}
2386
2387#endif /* IN_RC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2388#if !defined(IN_R0) || defined(LOG_ENABLED)
2389
2390/** Format handler for PGMPAGE.
2391 * @copydoc FNRTSTRFORMATTYPE */
2392static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2393 const char *pszType, void const *pvValue,
2394 int cchWidth, int cchPrecision, unsigned fFlags,
2395 void *pvUser)
2396{
2397 size_t cch;
2398 PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2399 if (VALID_PTR(pPage))
2400 {
2401 char szTmp[64+80];
2402
2403 cch = 0;
2404
2405 /* The single char state stuff. */
2406 static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2407 szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2408
2409#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) || cchPrecision == (lvl) || cchPrecision >= (lvl)+10 )
2410 if (IS_PART_INCLUDED(5))
2411 {
2412 static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2413 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2414 szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2415 }
2416
2417 /* The type. */
2418 if (IS_PART_INCLUDED(4))
2419 {
2420 szTmp[cch++] = ':';
2421 static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2422 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2423 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2424 szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2425 }
2426
2427 /* The numbers. */
2428 if (IS_PART_INCLUDED(3))
2429 {
2430 szTmp[cch++] = ':';
2431 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD | RTSTR_F_64BIT);
2432 }
2433
2434 if (IS_PART_INCLUDED(2))
2435 {
2436 szTmp[cch++] = ':';
2437 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD | RTSTR_F_32BIT);
2438 }
2439
2440 if (IS_PART_INCLUDED(6))
2441 {
2442 szTmp[cch++] = ':';
2443 static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2444 szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2445 cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD | RTSTR_F_16BIT);
2446 }
2447#undef IS_PART_INCLUDED
2448
2449 cch = pfnOutput(pvArgOutput, szTmp, cch);
2450 }
2451 else
2452 cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2453 return cch;
2454}
2455
2456
2457/** Format handler for PGMRAMRANGE.
2458 * @copydoc FNRTSTRFORMATTYPE */
2459static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2460 const char *pszType, void const *pvValue,
2461 int cchWidth, int cchPrecision, unsigned fFlags,
2462 void *pvUser)
2463{
2464 size_t cch;
2465 PGMRAMRANGE const *pRam = (PGMRAMRANGE const *)pvValue;
2466 if (VALID_PTR(pRam))
2467 {
2468 char szTmp[80];
2469 cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2470 cch = pfnOutput(pvArgOutput, szTmp, cch);
2471 }
2472 else
2473 cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2474 return cch;
2475}
2476
2477/** Format type andlers to be registered/deregistered. */
2478static const struct
2479{
2480 char szType[24];
2481 PFNRTSTRFORMATTYPE pfnHandler;
2482} g_aPgmFormatTypes[] =
2483{
2484 { "pgmpage", pgmFormatTypeHandlerPage },
2485 { "pgmramrange", pgmFormatTypeHandlerRamRange }
2486};
2487
2488#endif /* !IN_R0 || LOG_ENABLED */
2489
2490/**
2491 * Registers the global string format types.
2492 *
2493 * This should be called at module load time or in some other manner that ensure
2494 * that it's called exactly one time.
2495 *
2496 * @returns IPRT status code on RTStrFormatTypeRegister failure.
2497 */
2498VMMDECL(int) PGMRegisterStringFormatTypes(void)
2499{
2500#if !defined(IN_R0) || defined(LOG_ENABLED)
2501 int rc = VINF_SUCCESS;
2502 unsigned i;
2503 for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2504 {
2505 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2506# ifdef IN_RING0
2507 if (rc == VERR_ALREADY_EXISTS)
2508 {
2509 /* in case of cleanup failure in ring-0 */
2510 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2511 rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2512 }
2513# endif
2514 }
2515 if (RT_FAILURE(rc))
2516 while (i-- > 0)
2517 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2518
2519 return rc;
2520#else
2521 return VINF_SUCCESS;
2522#endif
2523}
2524
2525
2526/**
2527 * Deregisters the global string format types.
2528 *
2529 * This should be called at module unload time or in some other manner that
2530 * ensure that it's called exactly one time.
2531 */
2532VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2533{
2534#if !defined(IN_R0) || defined(LOG_ENABLED)
2535 for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2536 RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2537#endif
2538}
2539
2540#ifdef VBOX_STRICT
2541
2542/**
2543 * Asserts that there are no mapping conflicts.
2544 *
2545 * @returns Number of conflicts.
2546 * @param pVM The VM Handle.
2547 */
2548VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2549{
2550 unsigned cErrors = 0;
2551
2552 /* Only applies to raw mode -> 1 VPCU */
2553 Assert(pVM->cCpus == 1);
2554 PVMCPU pVCpu = &pVM->aCpus[0];
2555
2556 /*
2557 * Check for mapping conflicts.
2558 */
2559 for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2560 pMapping;
2561 pMapping = pMapping->CTX_SUFF(pNext))
2562 {
2563 /** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2564 for (RTGCPTR GCPtr = pMapping->GCPtr;
2565 GCPtr <= pMapping->GCPtrLast;
2566 GCPtr += PAGE_SIZE)
2567 {
2568 int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2569 if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2570 {
2571 AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2572 cErrors++;
2573 break;
2574 }
2575 }
2576 }
2577
2578 return cErrors;
2579}
2580
2581
2582/**
2583 * Asserts that everything related to the guest CR3 is correctly shadowed.
2584 *
2585 * This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2586 * and assert the correctness of the guest CR3 mapping before asserting that the
2587 * shadow page tables is in sync with the guest page tables.
2588 *
2589 * @returns Number of conflicts.
2590 * @param pVM The VM Handle.
2591 * @param pVCpu VMCPU handle.
2592 * @param cr3 The current guest CR3 register value.
2593 * @param cr4 The current guest CR4 register value.
2594 */
2595VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2596{
2597 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2598 pgmLock(pVM);
2599 unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2600 pgmUnlock(pVM);
2601 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3), a);
2602 return cErrors;
2603}
2604
2605#endif /* VBOX_STRICT */
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