PGMAll.cpp@ 24125

Last change on this file since 24125 was 23087, checked in by vboxsync, 15 years ago
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1	/* $Id: PGMAll.cpp 23087 2009-09-17 11:44:45Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include <VBox/cpum.h>
28	#include <VBox/selm.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/csam.h>
34	#include <VBox/patm.h>
35	#include <VBox/trpm.h>
36	#include <VBox/rem.h>
37	#include <VBox/em.h>
38	#include <VBox/hwaccm.h>
39	#include <VBox/hwacc_vmx.h>
40	#include "PGMInternal.h"
41	#include <VBox/vm.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <VBox/log.h>
46	#include <VBox/param.h>
47	#include <VBox/err.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	/**
54	* Stated structure for PGM_GST_NAME(HandlerVirtualUpdate) that's
55	* passed to PGM_GST_NAME(VirtHandlerUpdateOne) during enumeration.
56	*/
57	typedef struct PGMHVUSTATE
58	{
59	/** The VM handle. */
60	PVM pVM;
61	/** The VMCPU handle. */
62	PVMCPU pVCpu;
63	/** The todo flags. */
64	RTUINT fTodo;
65	/** The CR4 register value. */
66	uint32_t cr4;
67	} PGMHVUSTATE, *PPGMHVUSTATE;
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
74	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
75
76	/*
77	* Shadow - 32-bit mode
78	*/
79	#define PGM_SHW_TYPE PGM_TYPE_32BIT
80	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
81	#include "PGMAllShw.h"
82
83	/* Guest - real mode */
84	#define PGM_GST_TYPE PGM_TYPE_REAL
85	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
86	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
87	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
88	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
89	#include "PGMGstDefs.h"
90	#include "PGMAllGst.h"
91	#include "PGMAllBth.h"
92	#undef BTH_PGMPOOLKIND_PT_FOR_PT
93	#undef BTH_PGMPOOLKIND_ROOT
94	#undef PGM_BTH_NAME
95	#undef PGM_GST_TYPE
96	#undef PGM_GST_NAME
97
98	/* Guest - protected mode */
99	#define PGM_GST_TYPE PGM_TYPE_PROT
100	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
102	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
103	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
104	#include "PGMGstDefs.h"
105	#include "PGMAllGst.h"
106	#include "PGMAllBth.h"
107	#undef BTH_PGMPOOLKIND_PT_FOR_PT
108	#undef BTH_PGMPOOLKIND_ROOT
109	#undef PGM_BTH_NAME
110	#undef PGM_GST_TYPE
111	#undef PGM_GST_NAME
112
113	/* Guest - 32-bit mode */
114	#define PGM_GST_TYPE PGM_TYPE_32BIT
115	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
117	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
118	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
119	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
120	#include "PGMGstDefs.h"
121	#include "PGMAllGst.h"
122	#include "PGMAllBth.h"
123	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
124	#undef BTH_PGMPOOLKIND_PT_FOR_PT
125	#undef BTH_PGMPOOLKIND_ROOT
126	#undef PGM_BTH_NAME
127	#undef PGM_GST_TYPE
128	#undef PGM_GST_NAME
129
130	#undef PGM_SHW_TYPE
131	#undef PGM_SHW_NAME
132
133
134	/*
135	* Shadow - PAE mode
136	*/
137	#define PGM_SHW_TYPE PGM_TYPE_PAE
138	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
139	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
140	#include "PGMAllShw.h"
141
142	/* Guest - real mode */
143	#define PGM_GST_TYPE PGM_TYPE_REAL
144	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
145	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
146	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
147	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
148	#include "PGMGstDefs.h"
149	#include "PGMAllBth.h"
150	#undef BTH_PGMPOOLKIND_PT_FOR_PT
151	#undef BTH_PGMPOOLKIND_ROOT
152	#undef PGM_BTH_NAME
153	#undef PGM_GST_TYPE
154	#undef PGM_GST_NAME
155
156	/* Guest - protected mode */
157	#define PGM_GST_TYPE PGM_TYPE_PROT
158	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - 32-bit mode */
171	#define PGM_GST_TYPE PGM_TYPE_32BIT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
175	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
176	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
177	#include "PGMGstDefs.h"
178	#include "PGMAllBth.h"
179	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
180	#undef BTH_PGMPOOLKIND_PT_FOR_PT
181	#undef BTH_PGMPOOLKIND_ROOT
182	#undef PGM_BTH_NAME
183	#undef PGM_GST_TYPE
184	#undef PGM_GST_NAME
185
186
187	/* Guest - PAE mode */
188	#define PGM_GST_TYPE PGM_TYPE_PAE
189	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
190	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
191	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
192	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
193	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
194	#include "PGMGstDefs.h"
195	#include "PGMAllGst.h"
196	#include "PGMAllBth.h"
197	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
198	#undef BTH_PGMPOOLKIND_PT_FOR_PT
199	#undef BTH_PGMPOOLKIND_ROOT
200	#undef PGM_BTH_NAME
201	#undef PGM_GST_TYPE
202	#undef PGM_GST_NAME
203
204	#undef PGM_SHW_TYPE
205	#undef PGM_SHW_NAME
206
207
208	#ifndef IN_RC /* AMD64 implies VT-x/AMD-V */
209	/*
210	* Shadow - AMD64 mode
211	*/
212	# define PGM_SHW_TYPE PGM_TYPE_AMD64
213	# define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
214	# include "PGMAllShw.h"
215
216	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
217	# define PGM_GST_TYPE PGM_TYPE_PROT
218	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
219	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
220	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
221	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
222	# include "PGMGstDefs.h"
223	# include "PGMAllBth.h"
224	# undef BTH_PGMPOOLKIND_PT_FOR_PT
225	# undef BTH_PGMPOOLKIND_ROOT
226	# undef PGM_BTH_NAME
227	# undef PGM_GST_TYPE
228	# undef PGM_GST_NAME
229
230	# ifdef VBOX_WITH_64_BITS_GUESTS
231	/* Guest - AMD64 mode */
232	# define PGM_GST_TYPE PGM_TYPE_AMD64
233	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
234	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
235	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
236	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
237	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
238	# include "PGMGstDefs.h"
239	# include "PGMAllGst.h"
240	# include "PGMAllBth.h"
241	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
242	# undef BTH_PGMPOOLKIND_PT_FOR_PT
243	# undef BTH_PGMPOOLKIND_ROOT
244	# undef PGM_BTH_NAME
245	# undef PGM_GST_TYPE
246	# undef PGM_GST_NAME
247	# endif /* VBOX_WITH_64_BITS_GUESTS */
248
249	# undef PGM_SHW_TYPE
250	# undef PGM_SHW_NAME
251
252
253	/*
254	* Shadow - Nested paging mode
255	*/
256	# define PGM_SHW_TYPE PGM_TYPE_NESTED
257	# define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
258	# include "PGMAllShw.h"
259
260	/* Guest - real mode */
261	# define PGM_GST_TYPE PGM_TYPE_REAL
262	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
263	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
264	# include "PGMGstDefs.h"
265	# include "PGMAllBth.h"
266	# undef PGM_BTH_NAME
267	# undef PGM_GST_TYPE
268	# undef PGM_GST_NAME
269
270	/* Guest - protected mode */
271	# define PGM_GST_TYPE PGM_TYPE_PROT
272	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
273	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
274	# include "PGMGstDefs.h"
275	# include "PGMAllBth.h"
276	# undef PGM_BTH_NAME
277	# undef PGM_GST_TYPE
278	# undef PGM_GST_NAME
279
280	/* Guest - 32-bit mode */
281	# define PGM_GST_TYPE PGM_TYPE_32BIT
282	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
283	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
284	# include "PGMGstDefs.h"
285	# include "PGMAllBth.h"
286	# undef PGM_BTH_NAME
287	# undef PGM_GST_TYPE
288	# undef PGM_GST_NAME
289
290	/* Guest - PAE mode */
291	# define PGM_GST_TYPE PGM_TYPE_PAE
292	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
293	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
294	# include "PGMGstDefs.h"
295	# include "PGMAllBth.h"
296	# undef PGM_BTH_NAME
297	# undef PGM_GST_TYPE
298	# undef PGM_GST_NAME
299
300	# ifdef VBOX_WITH_64_BITS_GUESTS
301	/* Guest - AMD64 mode */
302	# define PGM_GST_TYPE PGM_TYPE_AMD64
303	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
304	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
305	# include "PGMGstDefs.h"
306	# include "PGMAllBth.h"
307	# undef PGM_BTH_NAME
308	# undef PGM_GST_TYPE
309	# undef PGM_GST_NAME
310	# endif /* VBOX_WITH_64_BITS_GUESTS */
311
312	# undef PGM_SHW_TYPE
313	# undef PGM_SHW_NAME
314
315
316	/*
317	* Shadow - EPT
318	*/
319	# define PGM_SHW_TYPE PGM_TYPE_EPT
320	# define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
321	# include "PGMAllShw.h"
322
323	/* Guest - real mode */
324	# define PGM_GST_TYPE PGM_TYPE_REAL
325	# define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
326	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
327	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
328	# include "PGMGstDefs.h"
329	# include "PGMAllBth.h"
330	# undef BTH_PGMPOOLKIND_PT_FOR_PT
331	# undef PGM_BTH_NAME
332	# undef PGM_GST_TYPE
333	# undef PGM_GST_NAME
334
335	/* Guest - protected mode */
336	# define PGM_GST_TYPE PGM_TYPE_PROT
337	# define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
338	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
339	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
340	# include "PGMGstDefs.h"
341	# include "PGMAllBth.h"
342	# undef BTH_PGMPOOLKIND_PT_FOR_PT
343	# undef PGM_BTH_NAME
344	# undef PGM_GST_TYPE
345	# undef PGM_GST_NAME
346
347	/* Guest - 32-bit mode */
348	# define PGM_GST_TYPE PGM_TYPE_32BIT
349	# define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
350	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
351	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
352	# include "PGMGstDefs.h"
353	# include "PGMAllBth.h"
354	# undef BTH_PGMPOOLKIND_PT_FOR_PT
355	# undef PGM_BTH_NAME
356	# undef PGM_GST_TYPE
357	# undef PGM_GST_NAME
358
359	/* Guest - PAE mode */
360	# define PGM_GST_TYPE PGM_TYPE_PAE
361	# define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
362	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
363	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
364	# include "PGMGstDefs.h"
365	# include "PGMAllBth.h"
366	# undef BTH_PGMPOOLKIND_PT_FOR_PT
367	# undef PGM_BTH_NAME
368	# undef PGM_GST_TYPE
369	# undef PGM_GST_NAME
370
371	# ifdef VBOX_WITH_64_BITS_GUESTS
372	/* Guest - AMD64 mode */
373	# define PGM_GST_TYPE PGM_TYPE_AMD64
374	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
375	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
376	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
377	# include "PGMGstDefs.h"
378	# include "PGMAllBth.h"
379	# undef BTH_PGMPOOLKIND_PT_FOR_PT
380	# undef PGM_BTH_NAME
381	# undef PGM_GST_TYPE
382	# undef PGM_GST_NAME
383	# endif /* VBOX_WITH_64_BITS_GUESTS */
384
385	# undef PGM_SHW_TYPE
386	# undef PGM_SHW_NAME
387
388	#endif /* !IN_RC */
389
390
391	#ifndef IN_RING3
392	/**
393	* #PF Handler.
394	*
395	* @returns VBox status code (appropriate for trap handling and GC return).
396	* @param pVCpu VMCPU handle.
397	* @param uErr The trap error code.
398	* @param pRegFrame Trap register frame.
399	* @param pvFault The fault address.
400	*/
401	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
402	{
403	PVM pVM = pVCpu->CTX_SUFF(pVM);
404
405	Log(("PGMTrap0eHandler: uErr=%RGu pvFault=%RGv eip=%04x:%RGv\n", uErr, pvFault, pRegFrame->cs, (RTGCPTR)pRegFrame->rip));
406	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0e, a);
407	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = NULL; } );
408
409
410	#ifdef VBOX_WITH_STATISTICS
411	/*
412	* Error code stats.
413	*/
414	if (uErr & X86_TRAP_PF_US)
415	{
416	if (!(uErr & X86_TRAP_PF_P))
417	{
418	if (uErr & X86_TRAP_PF_RW)
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentWrite);
420	else
421	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNotPresentRead);
422	}
423	else if (uErr & X86_TRAP_PF_RW)
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSWrite);
425	else if (uErr & X86_TRAP_PF_RSVD)
426	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSReserved);
427	else if (uErr & X86_TRAP_PF_ID)
428	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSNXE);
429	else
430	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eUSRead);
431	}
432	else
433	{ /* Supervisor */
434	if (!(uErr & X86_TRAP_PF_P))
435	{
436	if (uErr & X86_TRAP_PF_RW)
437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentWrite);
438	else
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVNotPresentRead);
440	}
441	else if (uErr & X86_TRAP_PF_RW)
442	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVWrite);
443	else if (uErr & X86_TRAP_PF_ID)
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSNXE);
445	else if (uErr & X86_TRAP_PF_RSVD)
446	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eSVReserved);
447	}
448	#endif /* VBOX_WITH_STATISTICS */
449
450	/*
451	* Call the worker.
452	*/
453	pgmLock(pVM);
454	int rc = PGM_BTH_PFN(Trap0eHandler, pVCpu)(pVCpu, uErr, pRegFrame, pvFault);
455	Assert(PGMIsLockOwner(pVM));
456	pgmUnlock(pVM);
457	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
458	rc = VINF_SUCCESS;
459
460	# ifdef IN_RING0
461	/* Note: hack alert for difficult to reproduce problem. */
462	if ( rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
463	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
464	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
465	{
466	Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pRegFrame->rip));
467	/* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
468	rc = VINF_SUCCESS;
469	}
470	# endif
471
472	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPF); });
473	STAM_STATS({ if (!pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution))
474	pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2Misc; });
475	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.StatRZTrap0e, pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution), a);
476	return rc;
477	}
478	#endif /* !IN_RING3 */
479
480
481	/**
482	* Prefetch a page
483	*
484	* Typically used to sync commonly used pages before entering raw mode
485	* after a CR3 reload.
486	*
487	* @returns VBox status code suitable for scheduling.
488	* @retval VINF_SUCCESS on success.
489	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
490	* @param pVCpu VMCPU handle.
491	* @param GCPtrPage Page to invalidate.
492	*/
493	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
494	{
495	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
496	int rc = PGM_BTH_PFN(PrefetchPage, pVCpu)(pVCpu, GCPtrPage);
497	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,Prefetch), a);
498	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
499	return rc;
500	}
501
502
503	/**
504	* Gets the mapping corresponding to the specified address (if any).
505	*
506	* @returns Pointer to the mapping.
507	* @returns NULL if not
508	*
509	* @param pVM The virtual machine.
510	* @param GCPtr The guest context pointer.
511	*/
512	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr)
513	{
514	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
515	while (pMapping)
516	{
517	if ((uintptr_t)GCPtr < (uintptr_t)pMapping->GCPtr)
518	break;
519	if ((uintptr_t)GCPtr - (uintptr_t)pMapping->GCPtr < pMapping->cb)
520	return pMapping;
521	pMapping = pMapping->CTX_SUFF(pNext);
522	}
523	return NULL;
524	}
525
526
527	/**
528	* Verifies a range of pages for read or write access
529	*
530	* Only checks the guest's page tables
531	*
532	* @returns VBox status code.
533	* @param pVCpu VMCPU handle.
534	* @param Addr Guest virtual address to check
535	* @param cbSize Access size
536	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
537	* @remarks Current not in use.
538	*/
539	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
540	{
541	/*
542	* Validate input.
543	*/
544	if (fAccess & ~(X86_PTE_US \| X86_PTE_RW))
545	{
546	AssertMsgFailed(("PGMIsValidAccess: invalid access type %08x\n", fAccess));
547	return VERR_INVALID_PARAMETER;
548	}
549
550	uint64_t fPage;
551	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPage, NULL);
552	if (RT_FAILURE(rc))
553	{
554	Log(("PGMIsValidAccess: access violation for %RGv rc=%d\n", Addr, rc));
555	return VINF_EM_RAW_GUEST_TRAP;
556	}
557
558	/*
559	* Check if the access would cause a page fault
560	*
561	* Note that hypervisor page directories are not present in the guest's tables, so this check
562	* is sufficient.
563	*/
564	bool fWrite = !!(fAccess & X86_PTE_RW);
565	bool fUser = !!(fAccess & X86_PTE_US);
566	if ( !(fPage & X86_PTE_P)
567	\|\| (fWrite && !(fPage & X86_PTE_RW))
568	\|\| (fUser && !(fPage & X86_PTE_US)) )
569	{
570	Log(("PGMIsValidAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPage, fWrite, fUser));
571	return VINF_EM_RAW_GUEST_TRAP;
572	}
573	if ( RT_SUCCESS(rc)
574	&& PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize))
575	return PGMIsValidAccess(pVCpu, Addr + PAGE_SIZE, (cbSize > PAGE_SIZE) ? cbSize - PAGE_SIZE : 1, fAccess);
576	return rc;
577	}
578
579
580	/**
581	* Verifies a range of pages for read or write access
582	*
583	* Supports handling of pages marked for dirty bit tracking and CSAM
584	*
585	* @returns VBox status code.
586	* @param pVCpu VMCPU handle.
587	* @param Addr Guest virtual address to check
588	* @param cbSize Access size
589	* @param fAccess Access type (r/w, user/supervisor (X86_PTE_*))
590	*/
591	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess)
592	{
593	PVM pVM = pVCpu->CTX_SUFF(pVM);
594
595	AssertMsg(!(fAccess & ~(X86_PTE_US \| X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
596
597	/*
598	* Get going.
599	*/
600	uint64_t fPageGst;
601	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)Addr, &fPageGst, NULL);
602	if (RT_FAILURE(rc))
603	{
604	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", Addr, rc));
605	return VINF_EM_RAW_GUEST_TRAP;
606	}
607
608	/*
609	* Check if the access would cause a page fault
610	*
611	* Note that hypervisor page directories are not present in the guest's tables, so this check
612	* is sufficient.
613	*/
614	const bool fWrite = !!(fAccess & X86_PTE_RW);
615	const bool fUser = !!(fAccess & X86_PTE_US);
616	if ( !(fPageGst & X86_PTE_P)
617	\|\| (fWrite && !(fPageGst & X86_PTE_RW))
618	\|\| (fUser && !(fPageGst & X86_PTE_US)) )
619	{
620	Log(("PGMVerifyAccess: access violation for %RGv attr %#llx vs %d:%d\n", Addr, fPageGst, fWrite, fUser));
621	return VINF_EM_RAW_GUEST_TRAP;
622	}
623
624	if (!HWACCMIsNestedPagingActive(pVM))
625	{
626	/*
627	* Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
628	*/
629	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, NULL, NULL);
630	if ( rc == VERR_PAGE_NOT_PRESENT
631	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
632	{
633	/*
634	* Page is not present in our page tables.
635	* Try to sync it!
636	*/
637	Assert(X86_TRAP_PF_RW == X86_PTE_RW && X86_TRAP_PF_US == X86_PTE_US);
638	uint32_t uErr = fAccess & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
639	rc = PGM_BTH_PFN(VerifyAccessSyncPage, pVCpu)(pVCpu, Addr, fPageGst, uErr);
640	if (rc != VINF_SUCCESS)
641	return rc;
642	}
643	else
644	AssertMsg(rc == VINF_SUCCESS, ("PGMShwGetPage %RGv failed with %Rrc\n", Addr, rc));
645	}
646
647	#if 0 /* def VBOX_STRICT; triggers too often now */
648	/*
649	* This check is a bit paranoid, but useful.
650	*/
651	/** @note this will assert when writing to monitored pages (a bit annoying actually) */
652	uint64_t fPageShw;
653	rc = PGMShwGetPage(pVCpu, (RTGCPTR)Addr, &fPageShw, NULL);
654	if ( (rc == VERR_PAGE_NOT_PRESENT \|\| RT_FAILURE(rc))
655	\|\| (fWrite && !(fPageShw & X86_PTE_RW))
656	\|\| (fUser && !(fPageShw & X86_PTE_US)) )
657	{
658	AssertMsgFailed(("Unexpected access violation for %RGv! rc=%Rrc write=%d user=%d\n",
659	Addr, rc, fWrite && !(fPageShw & X86_PTE_RW), fUser && !(fPageShw & X86_PTE_US)));
660	return VINF_EM_RAW_GUEST_TRAP;
661	}
662	#endif
663
664	if ( RT_SUCCESS(rc)
665	&& ( PAGE_ADDRESS(Addr) != PAGE_ADDRESS(Addr + cbSize - 1)
666	\|\| Addr + cbSize < Addr))
667	{
668	/* Don't recursively call PGMVerifyAccess as we might run out of stack. */
669	for (;;)
670	{
671	Addr += PAGE_SIZE;
672	if (cbSize > PAGE_SIZE)
673	cbSize -= PAGE_SIZE;
674	else
675	cbSize = 1;
676	rc = PGMVerifyAccess(pVCpu, Addr, 1, fAccess);
677	if (rc != VINF_SUCCESS)
678	break;
679	if (PAGE_ADDRESS(Addr) == PAGE_ADDRESS(Addr + cbSize - 1))
680	break;
681	}
682	}
683	return rc;
684	}
685
686
687	/**
688	* Emulation of the invlpg instruction (HC only actually).
689	*
690	* @returns VBox status code, special care required.
691	* @retval VINF_PGM_SYNC_CR3 - handled.
692	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
693	* @retval VERR_REM_FLUSHED_PAGES_OVERFLOW - not handled.
694	*
695	* @param pVCpu VMCPU handle.
696	* @param GCPtrPage Page to invalidate.
697	*
698	* @remark ASSUMES the page table entry or page directory is valid. Fairly
699	* safe, but there could be edge cases!
700	*
701	* @todo Flush page or page directory only if necessary!
702	*/
703	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage)
704	{
705	PVM pVM = pVCpu->CTX_SUFF(pVM);
706	int rc;
707	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
708
709	#ifndef IN_RING3
710	/*
711	* Notify the recompiler so it can record this instruction.
712	* Failure happens when it's out of space. We'll return to HC in that case.
713	*/
714	rc = REMNotifyInvalidatePage(pVM, GCPtrPage);
715	if (rc != VINF_SUCCESS)
716	return rc;
717	#endif /* !IN_RING3 */
718
719
720	#ifdef IN_RC
721	/*
722	* Check for conflicts and pending CR3 monitoring updates.
723	*/
724	if (!pVM->pgm.s.fMappingsFixed)
725	{
726	if ( pgmGetMapping(pVM, GCPtrPage)
727	&& PGMGstGetPage(pVCpu, GCPtrPage, NULL, NULL) != VERR_PAGE_TABLE_NOT_PRESENT)
728	{
729	LogFlow(("PGMGCInvalidatePage: Conflict!\n"));
730	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
731	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgConflict);
732	return VINF_PGM_SYNC_CR3;
733	}
734
735	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
736	{
737	LogFlow(("PGMGCInvalidatePage: PGM_SYNC_MONITOR_CR3 -> reinterpret instruction in R3\n"));
738	STAM_COUNTER_INC(&pVM->pgm.s.StatRCInvlPgSyncMonCR3);
739	return VINF_EM_RAW_EMULATE_INSTR;
740	}
741	}
742	#endif /* IN_RC */
743
744	/*
745	* Call paging mode specific worker.
746	*/
747	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
748	pgmLock(pVM);
749	rc = PGM_BTH_PFN(InvalidatePage, pVCpu)(pVCpu, GCPtrPage);
750	pgmUnlock(pVM);
751	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage), a);
752
753	#ifdef IN_RING3
754	/*
755	* Check if we have a pending update of the CR3 monitoring.
756	*/
757	if ( RT_SUCCESS(rc)
758	&& (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3))
759	{
760	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
761	Assert(!pVM->pgm.s.fMappingsFixed);
762	}
763
764	/*
765	* Inform CSAM about the flush
766	*
767	* Note: This is to check if monitored pages have been changed; when we implement
768	* callbacks for virtual handlers, this is no longer required.
769	*/
770	CSAMR3FlushPage(pVM, GCPtrPage);
771	#endif /* IN_RING3 */
772	return rc;
773	}
774
775
776	/**
777	* Executes an instruction using the interpreter.
778	*
779	* @returns VBox status code (appropriate for trap handling and GC return).
780	* @param pVM VM handle.
781	* @param pVCpu VMCPU handle.
782	* @param pRegFrame Register frame.
783	* @param pvFault Fault address.
784	*/
785	VMMDECL(int) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
786	{
787	uint32_t cb;
788	int rc = EMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault, &cb);
789	if (rc == VERR_EM_INTERPRETER)
790	rc = VINF_EM_RAW_EMULATE_INSTR;
791	if (rc != VINF_SUCCESS)
792	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", rc, pvFault));
793	return rc;
794	}
795
796
797	/**
798	* Gets effective page information (from the VMM page directory).
799	*
800	* @returns VBox status.
801	* @param pVCpu VMCPU handle.
802	* @param GCPtr Guest Context virtual address of the page.
803	* @param pfFlags Where to store the flags. These are X86_PTE_*.
804	* @param pHCPhys Where to store the HC physical address of the page.
805	* This is page aligned.
806	* @remark You should use PGMMapGetPage() for pages in a mapping.
807	*/
808	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
809	{
810	pgmLock(pVCpu->CTX_SUFF(pVM));
811	int rc = PGM_SHW_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pHCPhys);
812	pgmUnlock(pVCpu->CTX_SUFF(pVM));
813	return rc;
814	}
815
816
817	/**
818	* Sets (replaces) the page flags for a range of pages in the shadow context.
819	*
820	* @returns VBox status.
821	* @param pVCpu VMCPU handle.
822	* @param GCPtr The address of the first page.
823	* @param cb The size of the range in bytes.
824	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
825	* @remark You must use PGMMapSetPage() for pages in a mapping.
826	*/
827	VMMDECL(int) PGMShwSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
828	{
829	return PGMShwModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
830	}
831
832
833	/**
834	* Modify page flags for a range of pages in the shadow context.
835	*
836	* The existing flags are ANDed with the fMask and ORed with the fFlags.
837	*
838	* @returns VBox status code.
839	* @param pVCpu VMCPU handle.
840	* @param GCPtr Virtual address of the first page in the range.
841	* @param cb Size (in bytes) of the range to apply the modification to.
842	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
843	* @param fMask The AND mask - page flags X86_PTE_*.
844	* Be very CAREFUL when ~'ing constants which could be 32-bit!
845	* @remark You must use PGMMapModifyPage() for pages in a mapping.
846	*/
847	VMMDECL(int) PGMShwModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
848	{
849	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
850	Assert(cb);
851
852	/*
853	* Align the input.
854	*/
855	cb += GCPtr & PAGE_OFFSET_MASK;
856	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
857	GCPtr = (GCPtr & PAGE_BASE_GC_MASK); /** @todo this ain't necessary, right... */
858
859	/*
860	* Call worker.
861	*/
862	PVM pVM = pVCpu->CTX_SUFF(pVM);
863	pgmLock(pVM);
864	int rc = PGM_SHW_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
865	pgmUnlock(pVM);
866	return rc;
867	}
868
869	/**
870	* Gets the shadow page directory for the specified address, PAE.
871	*
872	* @returns Pointer to the shadow PD.
873	* @param pVCpu The VMCPU handle.
874	* @param GCPtr The address.
875	* @param pGstPdpe Guest PDPT entry
876	* @param ppPD Receives address of page directory
877	*/
878	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
879	{
880	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
881	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
882	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
883	PVM pVM = pVCpu->CTX_SUFF(pVM);
884	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
885	PPGMPOOLPAGE pShwPage;
886	int rc;
887
888	Assert(PGMIsLockOwner(pVM));
889
890	/* Allocate page directory if not present. */
891	if ( !pPdpe->n.u1Present
892	&& !(pPdpe->u & X86_PDPE_PG_MASK))
893	{
894	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
895	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
896	RTGCPTR64 GCPdPt;
897	PGMPOOLKIND enmKind;
898
899	# if defined(IN_RC)
900	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
901	PGMDynLockHCPage(pVM, (uint8_t *)pPdpe);
902	# endif
903
904	if (fNestedPaging \|\| !fPaging)
905	{
906	/* AMD-V nested paging or real/protected mode without paging */
907	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
908	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
909	}
910	else
911	{
912	Assert(pGstPdpe);
913
914	if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
915	{
916	if (!pGstPdpe->n.u1Present)
917	{
918	/* PD not present; guest must reload CR3 to change it.
919	* No need to monitor anything in this case.
920	*/
921	Assert(!HWACCMIsEnabled(pVM));
922
923	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
924	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
925	pGstPdpe->n.u1Present = 1;
926	}
927	else
928	{
929	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
930	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
931	}
932	}
933	else
934	{
935	GCPdPt = CPUMGetGuestCR3(pVCpu);
936	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
937	}
938	}
939
940	/* Create a reference back to the PDPT by using the index in its shadow page. */
941	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, &pShwPage);
942	AssertRCReturn(rc, rc);
943
944	/* The PD was cached or created; hook it up now. */
945	pPdpe->u \|= pShwPage->Core.Key
946	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
947
948	# if defined(IN_RC)
949	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
950	* non-present PDPT will continue to cause page faults.
951	*/
952	ASMReloadCR3();
953	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdpe);
954	# endif
955	}
956	else
957	{
958	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
959	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
960	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
961
962	pgmPoolCacheUsed(pPool, pShwPage);
963	}
964	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
965	return VINF_SUCCESS;
966	}
967
968
969	/**
970	* Gets the pointer to the shadow page directory entry for an address, PAE.
971	*
972	* @returns Pointer to the PDE.
973	* @param pPGM Pointer to the PGMCPU instance data.
974	* @param GCPtr The address.
975	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
976	*/
977	DECLINLINE(int) pgmShwGetPaePoolPagePD(PPGMCPU pPGM, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
978	{
979	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
980	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
981
982	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
983
984	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
985	if (!pPdpt->a[iPdPt].n.u1Present)
986	{
987	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, pPdpt->a[iPdPt].u));
988	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
989	}
990	AssertMsg(pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
991
992	/* Fetch the pgm pool shadow descriptor. */
993	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(PGMCPU2PGM(pPGM)->CTX_SUFF(pPool), pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
994	AssertReturn(pShwPde, VERR_INTERNAL_ERROR);
995
996	*ppShwPde = pShwPde;
997	return VINF_SUCCESS;
998	}
999
1000	#ifndef IN_RC
1001
1002	/**
1003	* Syncs the SHADOW page directory pointer for the specified address.
1004	*
1005	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1006	*
1007	* The caller is responsible for making sure the guest has a valid PD before
1008	* calling this function.
1009	*
1010	* @returns VBox status.
1011	* @param pVCpu VMCPU handle.
1012	* @param GCPtr The address.
1013	* @param pGstPml4e Guest PML4 entry
1014	* @param pGstPdpe Guest PDPT entry
1015	* @param ppPD Receives address of page directory
1016	*/
1017	int pgmShwSyncLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
1018	{
1019	PPGMCPU pPGM = &pVCpu->pgm.s;
1020	PVM pVM = pVCpu->CTX_SUFF(pVM);
1021	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1022	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1023	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1024	bool fNestedPaging = HWACCMIsNestedPagingActive(pVM);
1025	bool fPaging = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_PG);
1026	PPGMPOOLPAGE pShwPage;
1027	int rc;
1028
1029	Assert(PGMIsLockOwner(pVM));
1030
1031	/* Allocate page directory pointer table if not present. */
1032	if ( !pPml4e->n.u1Present
1033	&& !(pPml4e->u & X86_PML4E_PG_MASK))
1034	{
1035	RTGCPTR64 GCPml4;
1036	PGMPOOLKIND enmKind;
1037
1038	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1039
1040	if (fNestedPaging \|\| !fPaging)
1041	{
1042	/* AMD-V nested paging or real/protected mode without paging */
1043	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT;
1044	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1045	}
1046	else
1047	{
1048	Assert(pGstPml4e && pGstPdpe);
1049
1050	GCPml4 = pGstPml4e->u & X86_PML4E_PG_MASK;
1051	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1052	}
1053
1054	/* Create a reference back to the PDPT by using the index in its shadow page. */
1055	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, &pShwPage);
1056	AssertRCReturn(rc, rc);
1057	}
1058	else
1059	{
1060	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1061	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1062
1063	pgmPoolCacheUsed(pPool, pShwPage);
1064	}
1065	/* The PDPT was cached or created; hook it up now. */
1066	pPml4e->u \|= pShwPage->Core.Key
1067	\| (pGstPml4e->u & ~(X86_PML4E_PG_MASK \| X86_PML4E_AVL_MASK \| X86_PML4E_PCD \| X86_PML4E_PWT));
1068
1069	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1070	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1071	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1072
1073	/* Allocate page directory if not present. */
1074	if ( !pPdpe->n.u1Present
1075	&& !(pPdpe->u & X86_PDPE_PG_MASK))
1076	{
1077	RTGCPTR64 GCPdPt;
1078	PGMPOOLKIND enmKind;
1079
1080	if (fNestedPaging \|\| !fPaging)
1081	{
1082	/* AMD-V nested paging or real/protected mode without paging */
1083	GCPdPt = (RTGCPTR64)iPdPt << X86_PDPT_SHIFT;
1084	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1085	}
1086	else
1087	{
1088	Assert(pGstPdpe);
1089
1090	GCPdPt = pGstPdpe->u & X86_PDPE_PG_MASK;
1091	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1092	}
1093
1094	/* Create a reference back to the PDPT by using the index in its shadow page. */
1095	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, pShwPage->idx, iPdPt, &pShwPage);
1096	AssertRCReturn(rc, rc);
1097	}
1098	else
1099	{
1100	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
1101	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1102
1103	pgmPoolCacheUsed(pPool, pShwPage);
1104	}
1105	/* The PD was cached or created; hook it up now. */
1106	pPdpe->u \|= pShwPage->Core.Key
1107	\| (pGstPdpe->u & ~(X86_PDPE_PG_MASK \| X86_PDPE_AVL_MASK \| X86_PDPE_PCD \| X86_PDPE_PWT));
1108
1109	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1110	return VINF_SUCCESS;
1111	}
1112
1113
1114	/**
1115	* Gets the SHADOW page directory pointer for the specified address (long mode).
1116	*
1117	* @returns VBox status.
1118	* @param pVCpu VMCPU handle.
1119	* @param GCPtr The address.
1120	* @param ppPdpt Receives address of pdpt
1121	* @param ppPD Receives address of page directory
1122	*/
1123	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1124	{
1125	PPGMCPU pPGM = &pVCpu->pgm.s;
1126	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1127	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pPGM, iPml4);
1128
1129	Assert(PGMIsLockOwner(PGMCPU2VM(pPGM)));
1130
1131	AssertReturn(pPml4e, VERR_INTERNAL_ERROR);
1132	if (ppPml4e)
1133	*ppPml4e = (PX86PML4E)pPml4e;
1134
1135	Log4(("pgmShwGetLongModePDPtr %VGv (%VHv) %RX64\n", GCPtr, pPml4e, pPml4e->u));
1136
1137	if (!pPml4e->n.u1Present)
1138	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1139
1140	PVM pVM = pVCpu->CTX_SUFF(pVM);
1141	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1142	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
1143	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1144
1145	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1146	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1147	if (!pPdpt->a[iPdPt].n.u1Present)
1148	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1149
1150	pShwPage = pgmPoolGetPage(pPool, pPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
1151	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1152
1153	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1154	return VINF_SUCCESS;
1155	}
1156
1157
1158	/**
1159	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1160	* backing pages in case the PDPT or PML4 entry is missing.
1161	*
1162	* @returns VBox status.
1163	* @param pVCpu VMCPU handle.
1164	* @param GCPtr The address.
1165	* @param ppPdpt Receives address of pdpt
1166	* @param ppPD Receives address of page directory
1167	*/
1168	int pgmShwGetEPTPDPtr(PVMCPU pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1169	{
1170	PPGMCPU pPGM = &pVCpu->pgm.s;
1171	PVM pVM = pVCpu->CTX_SUFF(pVM);
1172	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1173	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1174	PEPTPML4 pPml4;
1175	PEPTPML4E pPml4e;
1176	PPGMPOOLPAGE pShwPage;
1177	int rc;
1178
1179	Assert(HWACCMIsNestedPagingActive(pVM));
1180	Assert(PGMIsLockOwner(pVM));
1181
1182	pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_BY_PGMCPU(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
1183	Assert(pPml4);
1184
1185	/* Allocate page directory pointer table if not present. */
1186	pPml4e = &pPml4->a[iPml4];
1187	if ( !pPml4e->n.u1Present
1188	&& !(pPml4e->u & EPT_PML4E_PG_MASK))
1189	{
1190	Assert(!(pPml4e->u & EPT_PML4E_PG_MASK));
1191	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1192
1193	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4, &pShwPage);
1194	AssertRCReturn(rc, rc);
1195	}
1196	else
1197	{
1198	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1199	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1200
1201	pgmPoolCacheUsed(pPool, pShwPage);
1202	}
1203	/* The PDPT was cached or created; hook it up now and fill with the default value. */
1204	pPml4e->u = pShwPage->Core.Key;
1205	pPml4e->n.u1Present = 1;
1206	pPml4e->n.u1Write = 1;
1207	pPml4e->n.u1Execute = 1;
1208
1209	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1210	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1211	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1212
1213	if (ppPdpt)
1214	*ppPdpt = pPdpt;
1215
1216	/* Allocate page directory if not present. */
1217	if ( !pPdpe->n.u1Present
1218	&& !(pPdpe->u & EPT_PDPTE_PG_MASK))
1219	{
1220	RTGCPTR64 GCPdPt = (RTGCPTR64)iPdPt << EPT_PDPT_SHIFT;
1221
1222	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_64BIT_PD_FOR_PHYS, pShwPage->idx, iPdPt, &pShwPage);
1223	AssertRCReturn(rc, rc);
1224	}
1225	else
1226	{
1227	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1228	AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
1229
1230	pgmPoolCacheUsed(pPool, pShwPage);
1231	}
1232	/* The PD was cached or created; hook it up now and fill with the default value. */
1233	pPdpe->u = pShwPage->Core.Key;
1234	pPdpe->n.u1Present = 1;
1235	pPdpe->n.u1Write = 1;
1236	pPdpe->n.u1Execute = 1;
1237
1238	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1239	return VINF_SUCCESS;
1240	}
1241
1242	#endif /* IN_RC */
1243
1244	/**
1245	* Gets effective Guest OS page information.
1246	*
1247	* When GCPtr is in a big page, the function will return as if it was a normal
1248	* 4KB page. If the need for distinguishing between big and normal page becomes
1249	* necessary at a later point, a PGMGstGetPage() will be created for that
1250	* purpose.
1251	*
1252	* @returns VBox status.
1253	* @param pVCpu VMCPU handle.
1254	* @param GCPtr Guest Context virtual address of the page.
1255	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
1256	* @param pGCPhys Where to store the GC physical address of the page.
1257	* This is page aligned. The fact that the
1258	*/
1259	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
1260	{
1261	return PGM_GST_PFN(GetPage, pVCpu)(pVCpu, GCPtr, pfFlags, pGCPhys);
1262	}
1263
1264
1265	/**
1266	* Checks if the page is present.
1267	*
1268	* @returns true if the page is present.
1269	* @returns false if the page is not present.
1270	* @param pVCpu VMCPU handle.
1271	* @param GCPtr Address within the page.
1272	*/
1273	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr)
1274	{
1275	int rc = PGMGstGetPage(pVCpu, GCPtr, NULL, NULL);
1276	return RT_SUCCESS(rc);
1277	}
1278
1279
1280	/**
1281	* Sets (replaces) the page flags for a range of pages in the guest's tables.
1282	*
1283	* @returns VBox status.
1284	* @param pVCpu VMCPU handle.
1285	* @param GCPtr The address of the first page.
1286	* @param cb The size of the range in bytes.
1287	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
1288	*/
1289	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags)
1290	{
1291	return PGMGstModifyPage(pVCpu, GCPtr, cb, fFlags, 0);
1292	}
1293
1294
1295	/**
1296	* Modify page flags for a range of pages in the guest's tables
1297	*
1298	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1299	*
1300	* @returns VBox status code.
1301	* @param pVCpu VMCPU handle.
1302	* @param GCPtr Virtual address of the first page in the range.
1303	* @param cb Size (in bytes) of the range to apply the modification to.
1304	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1305	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
1306	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1307	*/
1308	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
1309	{
1310	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1311
1312	/*
1313	* Validate input.
1314	*/
1315	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1316	Assert(cb);
1317
1318	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
1319
1320	/*
1321	* Adjust input.
1322	*/
1323	cb += GCPtr & PAGE_OFFSET_MASK;
1324	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
1325	GCPtr = (GCPtr & PAGE_BASE_GC_MASK);
1326
1327	/*
1328	* Call worker.
1329	*/
1330	int rc = PGM_GST_PFN(ModifyPage, pVCpu)(pVCpu, GCPtr, cb, fFlags, fMask);
1331
1332	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
1333	return rc;
1334	}
1335
1336	#ifdef IN_RING3
1337
1338	/**
1339	* Performs the lazy mapping of the 32-bit guest PD.
1340	*
1341	* @returns Pointer to the mapping.
1342	* @param pPGM The PGM instance data.
1343	*/
1344	PX86PD pgmGstLazyMap32BitPD(PPGMCPU pPGM)
1345	{
1346	Assert(!pPGM->CTX_SUFF(pGst32BitPd));
1347	PVM pVM = PGMCPU2VM(pPGM);
1348	pgmLock(pVM);
1349
1350	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1351	AssertReturn(pPage, NULL);
1352
1353	RTHCPTR HCPtrGuestCR3;
1354	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
1355	AssertRCReturn(rc, NULL);
1356
1357	pPGM->pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
1358	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1359	pPGM->pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
1360	# endif
1361
1362	pgmUnlock(pVM);
1363	return pPGM->CTX_SUFF(pGst32BitPd);
1364	}
1365
1366
1367	/**
1368	* Performs the lazy mapping of the PAE guest PDPT.
1369	*
1370	* @returns Pointer to the mapping.
1371	* @param pPGM The PGM instance data.
1372	*/
1373	PX86PDPT pgmGstLazyMapPaePDPT(PPGMCPU pPGM)
1374	{
1375	Assert(!pPGM->CTX_SUFF(pGstPaePdpt));
1376	PVM pVM = PGMCPU2VM(pPGM);
1377	pgmLock(pVM);
1378
1379	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1380	AssertReturn(pPage, NULL);
1381
1382	RTHCPTR HCPtrGuestCR3;
1383	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_PAE_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysR3 masking isn't necessary. */
1384	AssertRCReturn(rc, NULL);
1385
1386	pPGM->pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1387	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1388	pPGM->pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
1389	# endif
1390
1391	pgmUnlock(pVM);
1392	return pPGM->CTX_SUFF(pGstPaePdpt);
1393	}
1394
1395	#endif /* IN_RING3 */
1396
1397	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1398	/**
1399	* Performs the lazy mapping / updating of a PAE guest PD.
1400	*
1401	* @returns Pointer to the mapping.
1402	* @param pPGM The PGM instance data.
1403	* @param iPdpt Which PD entry to map (0..3).
1404	*/
1405	PX86PDPAE pgmGstLazyMapPaePD(PPGMCPU pPGM, uint32_t iPdpt)
1406	{
1407	PVM pVM = PGMCPU2VM(pPGM);
1408	pgmLock(pVM);
1409
1410	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
1411	Assert(pGuestPDPT);
1412	Assert(pGuestPDPT->a[iPdpt].n.u1Present);
1413	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
1414	bool const fChanged = pPGM->aGCPhysGstPaePDs[iPdpt] != GCPhys;
1415
1416	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
1417	if (RT_LIKELY(pPage))
1418	{
1419	int rc = VINF_SUCCESS;
1420	RTRCPTR RCPtr = NIL_RTRCPTR;
1421	RTHCPTR HCPtr = NIL_RTHCPTR;
1422	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1423	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &HCPtr);
1424	AssertRC(rc);
1425	#endif
1426	if (RT_SUCCESS(rc) && fChanged)
1427	{
1428	RCPtr = (RTRCPTR)(RTRCUINTPTR)(pVM->pgm.s.GCPtrCR3Mapping + (1 + iPdpt) * PAGE_SIZE);
1429	rc = PGMMap(pVM, (RTRCUINTPTR)RCPtr, PGM_PAGE_GET_HCPHYS(pPage), PAGE_SIZE, 0);
1430	}
1431	if (RT_SUCCESS(rc))
1432	{
1433	pPGM->apGstPaePDsR3[iPdpt] = (R3PTRTYPE(PX86PDPAE))HCPtr;
1434	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1435	pPGM->apGstPaePDsR0[iPdpt] = (R0PTRTYPE(PX86PDPAE))HCPtr;
1436	# endif
1437	if (fChanged)
1438	{
1439	pPGM->aGCPhysGstPaePDs[iPdpt] = GCPhys;
1440	pPGM->apGstPaePDsRC[iPdpt] = (RCPTRTYPE(PX86PDPAE))RCPtr;
1441	}
1442
1443	pgmUnlock(pVM);
1444	return pPGM->CTX_SUFF(apGstPaePDs)[iPdpt];
1445	}
1446	}
1447
1448	/* Invalid page or some failure, invalidate the entry. */
1449	pPGM->aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
1450	pPGM->apGstPaePDsR3[iPdpt] = 0;
1451	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1452	pPGM->apGstPaePDsR0[iPdpt] = 0;
1453	# endif
1454	pPGM->apGstPaePDsRC[iPdpt] = 0;
1455
1456	pgmUnlock(pVM);
1457	return NULL;
1458	}
1459	#endif /* !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
1460
1461
1462	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3
1463	/**
1464	* Performs the lazy mapping of the 32-bit guest PD.
1465	*
1466	* @returns Pointer to the mapping.
1467	* @param pPGM The PGM instance data.
1468	*/
1469	PX86PML4 pgmGstLazyMapPml4(PPGMCPU pPGM)
1470	{
1471	Assert(!pPGM->CTX_SUFF(pGstAmd64Pml4));
1472	PVM pVM = PGMCPU2VM(pPGM);
1473	pgmLock(pVM);
1474
1475	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPGM->GCPhysCR3);
1476	AssertReturn(pPage, NULL);
1477
1478	RTHCPTR HCPtrGuestCR3;
1479	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pPGM->GCPhysCR3 & X86_CR3_AMD64_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
1480	AssertRCReturn(rc, NULL);
1481
1482	pPGM->pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
1483	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1484	pPGM->pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
1485	# endif
1486
1487	pgmUnlock(pVM);
1488	return pPGM->CTX_SUFF(pGstAmd64Pml4);
1489	}
1490	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R3 */
1491
1492
1493	/**
1494	* Gets the specified page directory pointer table entry.
1495	*
1496	* @returns PDP entry
1497	* @param pVCpu VMCPU handle.
1498	* @param iPdpt PDPT index
1499	*/
1500	VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVMCPU pVCpu, unsigned iPdpt)
1501	{
1502	Assert(iPdpt <= 3);
1503	return pgmGstGetPaePDPTPtr(&pVCpu->pgm.s)->a[iPdpt & 3];
1504	}
1505
1506
1507	/**
1508	* Gets the current CR3 register value for the shadow memory context.
1509	* @returns CR3 value.
1510	* @param pVCpu VMCPU handle.
1511	*/
1512	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
1513	{
1514	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1515	AssertPtrReturn(pPoolPage, 0);
1516	return pPoolPage->Core.Key;
1517	}
1518
1519
1520	/**
1521	* Gets the current CR3 register value for the nested memory context.
1522	* @returns CR3 value.
1523	* @param pVCpu VMCPU handle.
1524	*/
1525	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode)
1526	{
1527	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1528	return pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
1529	}
1530
1531
1532	/**
1533	* Gets the current CR3 register value for the HC intermediate memory context.
1534	* @returns CR3 value.
1535	* @param pVM The VM handle.
1536	*/
1537	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM)
1538	{
1539	switch (pVM->pgm.s.enmHostMode)
1540	{
1541	case SUPPAGINGMODE_32_BIT:
1542	case SUPPAGINGMODE_32_BIT_GLOBAL:
1543	return pVM->pgm.s.HCPhysInterPD;
1544
1545	case SUPPAGINGMODE_PAE:
1546	case SUPPAGINGMODE_PAE_GLOBAL:
1547	case SUPPAGINGMODE_PAE_NX:
1548	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1549	return pVM->pgm.s.HCPhysInterPaePDPT;
1550
1551	case SUPPAGINGMODE_AMD64:
1552	case SUPPAGINGMODE_AMD64_GLOBAL:
1553	case SUPPAGINGMODE_AMD64_NX:
1554	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1555	return pVM->pgm.s.HCPhysInterPaePDPT;
1556
1557	default:
1558	AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode));
1559	return ~0;
1560	}
1561	}
1562
1563
1564	/**
1565	* Gets the current CR3 register value for the RC intermediate memory context.
1566	* @returns CR3 value.
1567	* @param pVM The VM handle.
1568	* @param pVCpu VMCPU handle.
1569	*/
1570	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu)
1571	{
1572	switch (pVCpu->pgm.s.enmShadowMode)
1573	{
1574	case PGMMODE_32_BIT:
1575	return pVM->pgm.s.HCPhysInterPD;
1576
1577	case PGMMODE_PAE:
1578	case PGMMODE_PAE_NX:
1579	return pVM->pgm.s.HCPhysInterPaePDPT;
1580
1581	case PGMMODE_AMD64:
1582	case PGMMODE_AMD64_NX:
1583	return pVM->pgm.s.HCPhysInterPaePML4;
1584
1585	case PGMMODE_EPT:
1586	case PGMMODE_NESTED:
1587	return 0; /* not relevant */
1588
1589	default:
1590	AssertMsgFailed(("enmShadowMode=%d\n", pVCpu->pgm.s.enmShadowMode));
1591	return ~0;
1592	}
1593	}
1594
1595
1596	/**
1597	* Gets the CR3 register value for the 32-Bit intermediate memory context.
1598	* @returns CR3 value.
1599	* @param pVM The VM handle.
1600	*/
1601	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM)
1602	{
1603	return pVM->pgm.s.HCPhysInterPD;
1604	}
1605
1606
1607	/**
1608	* Gets the CR3 register value for the PAE intermediate memory context.
1609	* @returns CR3 value.
1610	* @param pVM The VM handle.
1611	*/
1612	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM)
1613	{
1614	return pVM->pgm.s.HCPhysInterPaePDPT;
1615	}
1616
1617
1618	/**
1619	* Gets the CR3 register value for the AMD64 intermediate memory context.
1620	* @returns CR3 value.
1621	* @param pVM The VM handle.
1622	*/
1623	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM)
1624	{
1625	return pVM->pgm.s.HCPhysInterPaePML4;
1626	}
1627
1628
1629	/**
1630	* Performs and schedules necessary updates following a CR3 load or reload.
1631	*
1632	* This will normally involve mapping the guest PD or nPDPT
1633	*
1634	* @returns VBox status code.
1635	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
1636	* safely be ignored and overridden since the FF will be set too then.
1637	* @param pVCpu VMCPU handle.
1638	* @param cr3 The new cr3.
1639	* @param fGlobal Indicates whether this is a global flush or not.
1640	*/
1641	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal)
1642	{
1643	PVM pVM = pVCpu->CTX_SUFF(pVM);
1644
1645	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1646
1647	/*
1648	* Always flag the necessary updates; necessary for hardware acceleration
1649	*/
1650	/** @todo optimize this, it shouldn't always be necessary. */
1651	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1652	if (fGlobal)
1653	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1654	LogFlow(("PGMFlushTLB: cr3=%RX64 OldCr3=%RX64 fGlobal=%d\n", cr3, pVCpu->pgm.s.GCPhysCR3, fGlobal));
1655
1656	/*
1657	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1658	*/
1659	int rc = VINF_SUCCESS;
1660	RTGCPHYS GCPhysCR3;
1661	switch (pVCpu->pgm.s.enmGuestMode)
1662	{
1663	case PGMMODE_PAE:
1664	case PGMMODE_PAE_NX:
1665	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1666	break;
1667	case PGMMODE_AMD64:
1668	case PGMMODE_AMD64_NX:
1669	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1670	break;
1671	default:
1672	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1673	break;
1674	}
1675
1676	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1677	{
1678	RTGCPHYS GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
1679	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1680	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1681	if (RT_LIKELY(rc == VINF_SUCCESS))
1682	{
1683	if (!pVM->pgm.s.fMappingsFixed)
1684	{
1685	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1686	}
1687	}
1688	else
1689	{
1690	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
1691	Assert(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
1692	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
1693	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
1694	if (!pVM->pgm.s.fMappingsFixed)
1695	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1696	}
1697
1698	if (fGlobal)
1699	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
1700	else
1701	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBNewCR3));
1702	}
1703	else
1704	{
1705	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1706	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1707	if (pPool->cDirtyPages)
1708	{
1709	pgmLock(pVM);
1710	pgmPoolResetDirtyPages(pVM);
1711	pgmUnlock(pVM);
1712	}
1713	# endif
1714	/*
1715	* Check if we have a pending update of the CR3 monitoring.
1716	*/
1717	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1718	{
1719	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1720	Assert(!pVM->pgm.s.fMappingsFixed);
1721	}
1722	if (fGlobal)
1723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
1724	else
1725	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLBSameCR3));
1726	}
1727
1728	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,FlushTLB), a);
1729	return rc;
1730	}
1731
1732
1733	/**
1734	* Performs and schedules necessary updates following a CR3 load or reload when
1735	* using nested or extended paging.
1736	*
1737	* This API is an alterantive to PDMFlushTLB that avoids actually flushing the
1738	* TLB and triggering a SyncCR3.
1739	*
1740	* This will normally involve mapping the guest PD or nPDPT
1741	*
1742	* @returns VBox status code.
1743	* @retval VINF_SUCCESS.
1744	* @retval (If applied when not in nested mode: VINF_PGM_SYNC_CR3 if monitoring
1745	* requires a CR3 sync. This can safely be ignored and overridden since
1746	* the FF will be set too then.)
1747	* @param pVCpu VMCPU handle.
1748	* @param cr3 The new cr3.
1749	*/
1750	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3)
1751	{
1752	PVM pVM = pVCpu->CTX_SUFF(pVM);
1753
1754	LogFlow(("PGMUpdateCR3: cr3=%RX64 OldCr3=%RX64\n", cr3, pVCpu->pgm.s.GCPhysCR3));
1755
1756	/* We assume we're only called in nested paging mode. */
1757	Assert(pVM->pgm.s.fMappingsFixed);
1758	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3));
1759	Assert(HWACCMIsNestedPagingActive(pVM) \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
1760
1761	/*
1762	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
1763	*/
1764	int rc = VINF_SUCCESS;
1765	RTGCPHYS GCPhysCR3;
1766	switch (pVCpu->pgm.s.enmGuestMode)
1767	{
1768	case PGMMODE_PAE:
1769	case PGMMODE_PAE_NX:
1770	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1771	break;
1772	case PGMMODE_AMD64:
1773	case PGMMODE_AMD64_NX:
1774	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1775	break;
1776	default:
1777	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1778	break;
1779	}
1780	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1781	{
1782	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1783	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1784	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
1785	}
1786	return rc;
1787	}
1788
1789
1790	/**
1791	* Synchronize the paging structures.
1792	*
1793	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
1794	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
1795	* in several places, most importantly whenever the CR3 is loaded.
1796	*
1797	* @returns VBox status code.
1798	* @param pVCpu VMCPU handle.
1799	* @param cr0 Guest context CR0 register
1800	* @param cr3 Guest context CR3 register
1801	* @param cr4 Guest context CR4 register
1802	* @param fGlobal Including global page directories or not
1803	*/
1804	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
1805	{
1806	PVM pVM = pVCpu->CTX_SUFF(pVM);
1807	int rc;
1808
1809	#ifdef PGMPOOL_WITH_MONITORING
1810	/*
1811	* The pool may have pending stuff and even require a return to ring-3 to
1812	* clear the whole thing.
1813	*/
1814	rc = pgmPoolSyncCR3(pVCpu);
1815	if (rc != VINF_SUCCESS)
1816	return rc;
1817	#endif
1818
1819	/*
1820	* We might be called when we shouldn't.
1821	*
1822	* The mode switching will ensure that the PD is resynced
1823	* after every mode switch. So, if we find ourselves here
1824	* when in protected or real mode we can safely disable the
1825	* FF and return immediately.
1826	*/
1827	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
1828	{
1829	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
1830	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1831	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1832	return VINF_SUCCESS;
1833	}
1834
1835	/* If global pages are not supported, then all flushes are global. */
1836	if (!(cr4 & X86_CR4_PGE))
1837	fGlobal = true;
1838	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
1839	VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
1840
1841	/*
1842	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
1843	* This should be done before SyncCR3.
1844	*/
1845	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
1846	{
1847	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
1848
1849	RTGCPHYS GCPhysCR3Old = pVCpu->pgm.s.GCPhysCR3;
1850	RTGCPHYS GCPhysCR3;
1851	switch (pVCpu->pgm.s.enmGuestMode)
1852	{
1853	case PGMMODE_PAE:
1854	case PGMMODE_PAE_NX:
1855	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAE_PAGE_MASK);
1856	break;
1857	case PGMMODE_AMD64:
1858	case PGMMODE_AMD64_NX:
1859	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_AMD64_PAGE_MASK);
1860	break;
1861	default:
1862	GCPhysCR3 = (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK);
1863	break;
1864	}
1865
1866	if (pVCpu->pgm.s.GCPhysCR3 != GCPhysCR3)
1867	{
1868	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
1869	rc = PGM_BTH_PFN(MapCR3, pVCpu)(pVCpu, GCPhysCR3);
1870	}
1871	#ifdef IN_RING3
1872	if (rc == VINF_PGM_SYNC_CR3)
1873	rc = pgmPoolSyncCR3(pVCpu);
1874	#else
1875	if (rc == VINF_PGM_SYNC_CR3)
1876	{
1877	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3Old;
1878	return rc;
1879	}
1880	#endif
1881	AssertRCReturn(rc, rc);
1882	AssertRCSuccessReturn(rc, VERR_INTERNAL_ERROR);
1883	}
1884
1885	/*
1886	* Let the 'Bth' function do the work and we'll just keep track of the flags.
1887	*/
1888	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1889	rc = PGM_BTH_PFN(SyncCR3, pVCpu)(pVCpu, cr0, cr3, cr4, fGlobal);
1890	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
1891	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1892	if (rc == VINF_SUCCESS)
1893	{
1894	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
1895	{
1896	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
1897	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
1898	}
1899
1900	/*
1901	* Check if we have a pending update of the CR3 monitoring.
1902	*/
1903	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MONITOR_CR3)
1904	{
1905	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MONITOR_CR3;
1906	Assert(!pVM->pgm.s.fMappingsFixed);
1907	}
1908	}
1909
1910	/*
1911	* Now flush the CR3 (guest context).
1912	*/
1913	if (rc == VINF_SUCCESS)
1914	PGM_INVL_VCPU_TLBS(pVCpu);
1915	return rc;
1916	}
1917
1918
1919	/**
1920	* Called whenever CR0 or CR4 in a way which may change
1921	* the paging mode.
1922	*
1923	* @returns VBox status code, with the following informational code for
1924	* VM scheduling.
1925	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
1926	* @retval VINF_PGM_CHANGE_MODE if we're in RC or R0 and the mode changes.
1927	* (I.e. not in R3.)
1928	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
1929	*
1930	* @param pVCpu VMCPU handle.
1931	* @param cr0 The new cr0.
1932	* @param cr4 The new cr4.
1933	* @param efer The new extended feature enable register.
1934	*/
1935	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer)
1936	{
1937	PVM pVM = pVCpu->CTX_SUFF(pVM);
1938	PGMMODE enmGuestMode;
1939
1940	/*
1941	* Calc the new guest mode.
1942	*/
1943	if (!(cr0 & X86_CR0_PE))
1944	enmGuestMode = PGMMODE_REAL;
1945	else if (!(cr0 & X86_CR0_PG))
1946	enmGuestMode = PGMMODE_PROTECTED;
1947	else if (!(cr4 & X86_CR4_PAE))
1948	enmGuestMode = PGMMODE_32_BIT;
1949	else if (!(efer & MSR_K6_EFER_LME))
1950	{
1951	if (!(efer & MSR_K6_EFER_NXE))
1952	enmGuestMode = PGMMODE_PAE;
1953	else
1954	enmGuestMode = PGMMODE_PAE_NX;
1955	}
1956	else
1957	{
1958	if (!(efer & MSR_K6_EFER_NXE))
1959	enmGuestMode = PGMMODE_AMD64;
1960	else
1961	enmGuestMode = PGMMODE_AMD64_NX;
1962	}
1963
1964	/*
1965	* Did it change?
1966	*/
1967	if (pVCpu->pgm.s.enmGuestMode == enmGuestMode)
1968	return VINF_SUCCESS;
1969
1970	/* Flush the TLB */
1971	PGM_INVL_VCPU_TLBS(pVCpu);
1972
1973	#ifdef IN_RING3
1974	return PGMR3ChangeMode(pVM, pVCpu, enmGuestMode);
1975	#else
1976	LogFlow(("PGMChangeMode: returns VINF_PGM_CHANGE_MODE.\n"));
1977	return VINF_PGM_CHANGE_MODE;
1978	#endif
1979	}
1980
1981
1982	/**
1983	* Gets the current guest paging mode.
1984	*
1985	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
1986	*
1987	* @returns The current paging mode.
1988	* @param pVCpu VMCPU handle.
1989	*/
1990	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
1991	{
1992	return pVCpu->pgm.s.enmGuestMode;
1993	}
1994
1995
1996	/**
1997	* Gets the current shadow paging mode.
1998	*
1999	* @returns The current paging mode.
2000	* @param pVCpu VMCPU handle.
2001	*/
2002	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
2003	{
2004	return pVCpu->pgm.s.enmShadowMode;
2005	}
2006
2007	/**
2008	* Gets the current host paging mode.
2009	*
2010	* @returns The current paging mode.
2011	* @param pVM The VM handle.
2012	*/
2013	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
2014	{
2015	switch (pVM->pgm.s.enmHostMode)
2016	{
2017	case SUPPAGINGMODE_32_BIT:
2018	case SUPPAGINGMODE_32_BIT_GLOBAL:
2019	return PGMMODE_32_BIT;
2020
2021	case SUPPAGINGMODE_PAE:
2022	case SUPPAGINGMODE_PAE_GLOBAL:
2023	return PGMMODE_PAE;
2024
2025	case SUPPAGINGMODE_PAE_NX:
2026	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2027	return PGMMODE_PAE_NX;
2028
2029	case SUPPAGINGMODE_AMD64:
2030	case SUPPAGINGMODE_AMD64_GLOBAL:
2031	return PGMMODE_AMD64;
2032
2033	case SUPPAGINGMODE_AMD64_NX:
2034	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2035	return PGMMODE_AMD64_NX;
2036
2037	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
2038	}
2039
2040	return PGMMODE_INVALID;
2041	}
2042
2043
2044	/**
2045	* Get mode name.
2046	*
2047	* @returns read-only name string.
2048	* @param enmMode The mode which name is desired.
2049	*/
2050	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
2051	{
2052	switch (enmMode)
2053	{
2054	case PGMMODE_REAL: return "Real";
2055	case PGMMODE_PROTECTED: return "Protected";
2056	case PGMMODE_32_BIT: return "32-bit";
2057	case PGMMODE_PAE: return "PAE";
2058	case PGMMODE_PAE_NX: return "PAE+NX";
2059	case PGMMODE_AMD64: return "AMD64";
2060	case PGMMODE_AMD64_NX: return "AMD64+NX";
2061	case PGMMODE_NESTED: return "Nested";
2062	case PGMMODE_EPT: return "EPT";
2063	default: return "unknown mode value";
2064	}
2065	}
2066
2067
2068	/**
2069	* Check if the PGM lock is currently taken.
2070	*
2071	* @returns bool locked/not locked
2072	* @param pVM The VM to operate on.
2073	*/
2074	VMMDECL(bool) PGMIsLocked(PVM pVM)
2075	{
2076	return PDMCritSectIsOwned(&pVM->pgm.s.CritSect);
2077	}
2078
2079
2080	/**
2081	* Check if this VCPU currently owns the PGM lock.
2082	*
2083	* @returns bool owner/not owner
2084	* @param pVM The VM to operate on.
2085	*/
2086	VMMDECL(bool) PGMIsLockOwner(PVM pVM)
2087	{
2088	return PDMCritSectIsOwner(&pVM->pgm.s.CritSect);
2089	}
2090
2091
2092	/**
2093	* Acquire the PGM lock.
2094	*
2095	* @returns VBox status code
2096	* @param pVM The VM to operate on.
2097	*/
2098	int pgmLock(PVM pVM)
2099	{
2100	int rc = PDMCritSectEnter(&pVM->pgm.s.CritSect, VERR_SEM_BUSY);
2101	#if defined(IN_RC) \|\| defined(IN_RING0)
2102	if (rc == VERR_SEM_BUSY)
2103	rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_LOCK, 0);
2104	#endif
2105	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
2106	return rc;
2107	}
2108
2109
2110	/**
2111	* Release the PGM lock.
2112	*
2113	* @returns VBox status code
2114	* @param pVM The VM to operate on.
2115	*/
2116	void pgmUnlock(PVM pVM)
2117	{
2118	PDMCritSectLeave(&pVM->pgm.s.CritSect);
2119	}
2120
2121	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2122
2123	/**
2124	* Temporarily maps one guest page specified by GC physical address.
2125	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2126	*
2127	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2128	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2129	*
2130	* @returns VBox status.
2131	* @param pVM VM handle.
2132	* @param GCPhys GC Physical address of the page.
2133	* @param ppv Where to store the address of the mapping.
2134	*/
2135	VMMDECL(int) PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2136	{
2137	AssertMsg(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp\n", GCPhys));
2138
2139	/*
2140	* Get the ram range.
2141	*/
2142	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2143	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2144	pRam = pRam->CTX_SUFF(pNext);
2145	if (!pRam)
2146	{
2147	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2148	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2149	}
2150
2151	/*
2152	* Pass it on to PGMDynMapHCPage.
2153	*/
2154	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2155	//Log(("PGMDynMapGCPage: GCPhys=%RGp HCPhys=%RHp\n", GCPhys, HCPhys));
2156	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2157	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2158	#else
2159	PGMDynMapHCPage(pVM, HCPhys, ppv);
2160	#endif
2161	return VINF_SUCCESS;
2162	}
2163
2164
2165	/**
2166	* Temporarily maps one guest page specified by unaligned GC physical address.
2167	* These pages must have a physical mapping in HC, i.e. they cannot be MMIO pages.
2168	*
2169	* Be WARNED that the dynamic page mapping area is small, 8 pages, thus the space is
2170	* reused after 8 mappings (or perhaps a few more if you score with the cache).
2171	*
2172	* The caller is aware that only the speicifed page is mapped and that really bad things
2173	* will happen if writing beyond the page!
2174	*
2175	* @returns VBox status.
2176	* @param pVM VM handle.
2177	* @param GCPhys GC Physical address within the page to be mapped.
2178	* @param ppv Where to store the address of the mapping address corresponding to GCPhys.
2179	*/
2180	VMMDECL(int) PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv)
2181	{
2182	/*
2183	* Get the ram range.
2184	*/
2185	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2186	while (pRam && GCPhys - pRam->GCPhys >= pRam->cb)
2187	pRam = pRam->CTX_SUFF(pNext);
2188	if (!pRam)
2189	{
2190	AssertMsgFailed(("Invalid physical address %RGp!\n", GCPhys));
2191	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2192	}
2193
2194	/*
2195	* Pass it on to PGMDynMapHCPage.
2196	*/
2197	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT]);
2198	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2199	pgmR0DynMapHCPageInlined(&pVM->pgm.s, HCPhys, ppv);
2200	#else
2201	PGMDynMapHCPage(pVM, HCPhys, ppv);
2202	#endif
2203	ppv = (void )((uintptr_t)*ppv \| (GCPhys & PAGE_OFFSET_MASK));
2204	return VINF_SUCCESS;
2205	}
2206
2207	# ifdef IN_RC
2208
2209	/**
2210	* Temporarily maps one host page specified by HC physical address.
2211	*
2212	* Be WARNED that the dynamic page mapping area is small, 16 pages, thus the space is
2213	* reused after 16 mappings (or perhaps a few more if you score with the cache).
2214	*
2215	* @returns VINF_SUCCESS, will bail out to ring-3 on failure.
2216	* @param pVM VM handle.
2217	* @param HCPhys HC Physical address of the page.
2218	* @param ppv Where to store the address of the mapping. This is the
2219	* address of the PAGE not the exact address corresponding
2220	* to HCPhys. Use PGMDynMapHCPageOff if you care for the
2221	* page offset.
2222	*/
2223	VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
2224	{
2225	AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
2226
2227	/*
2228	* Check the cache.
2229	*/
2230	register unsigned iCache;
2231	for (iCache = 0;iCache < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache);iCache++)
2232	{
2233	static const uint8_t au8Trans[MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT][RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache)] =
2234	{
2235	{ 0, 9, 10, 11, 12, 13, 14, 15},
2236	{ 0, 1, 10, 11, 12, 13, 14, 15},
2237	{ 0, 1, 2, 11, 12, 13, 14, 15},
2238	{ 0, 1, 2, 3, 12, 13, 14, 15},
2239	{ 0, 1, 2, 3, 4, 13, 14, 15},
2240	{ 0, 1, 2, 3, 4, 5, 14, 15},
2241	{ 0, 1, 2, 3, 4, 5, 6, 15},
2242	{ 0, 1, 2, 3, 4, 5, 6, 7},
2243	{ 8, 1, 2, 3, 4, 5, 6, 7},
2244	{ 8, 9, 2, 3, 4, 5, 6, 7},
2245	{ 8, 9, 10, 3, 4, 5, 6, 7},
2246	{ 8, 9, 10, 11, 4, 5, 6, 7},
2247	{ 8, 9, 10, 11, 12, 5, 6, 7},
2248	{ 8, 9, 10, 11, 12, 13, 6, 7},
2249	{ 8, 9, 10, 11, 12, 13, 14, 7},
2250	{ 8, 9, 10, 11, 12, 13, 14, 15},
2251	};
2252	AssertCompile(RT_ELEMENTS(au8Trans) == 16);
2253	AssertCompile(RT_ELEMENTS(au8Trans[0]) == 8);
2254
2255	if (pVM->pgm.s.aHCPhysDynPageMapCache[iCache] == HCPhys)
2256	{
2257	int iPage = au8Trans[pVM->pgm.s.iDynPageMapLast][iCache];
2258
2259	/* The cache can get out of sync with locked entries. (10 locked, 2 overwrites its cache position, last = 11, lookup 2 -> page 10 instead of 2) */
2260	if ((pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u & X86_PTE_PG_MASK) == HCPhys)
2261	{
2262	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2263	*ppv = pv;
2264	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheHits);
2265	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d iCache=%d\n", HCPhys, pv, iPage, iCache));
2266	return VINF_SUCCESS;
2267	}
2268	LogFlow(("Out of sync entry %d\n", iPage));
2269	}
2270	}
2271	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) == 8);
2272	AssertCompile((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) == 16);
2273	STAM_COUNTER_INC(&pVM->pgm.s.StatRCDynMapCacheMisses);
2274
2275	/*
2276	* Update the page tables.
2277	*/
2278	unsigned iPage = pVM->pgm.s.iDynPageMapLast;
2279	unsigned i;
2280	for (i = 0; i < (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT); i++)
2281	{
2282	pVM->pgm.s.iDynPageMapLast = iPage = (iPage + 1) & ((MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT) - 1);
2283	if (!pVM->pgm.s.aLockedDynPageMapCache[iPage])
2284	break;
2285	iPage++;
2286	}
2287	AssertRelease(i != (MM_HYPER_DYNAMIC_SIZE >> PAGE_SHIFT));
2288
2289	pVM->pgm.s.aHCPhysDynPageMapCache[iPage & (RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache) - 1)] = HCPhys;
2290	pVM->pgm.s.paDynPageMap32BitPTEsGC[iPage].u = (uint32_t)HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2291	pVM->pgm.s.paDynPageMapPaePTEsGC[iPage].u = HCPhys \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
2292	pVM->pgm.s.aLockedDynPageMapCache[iPage] = 0;
2293
2294	void *pv = pVM->pgm.s.pbDynPageMapBaseGC + (iPage << PAGE_SHIFT);
2295	*ppv = pv;
2296	ASMInvalidatePage(pv);
2297	Log4(("PGMGCDynMapHCPage: HCPhys=%RHp pv=%p iPage=%d\n", HCPhys, pv, iPage));
2298	return VINF_SUCCESS;
2299	}
2300
2301
2302	/**
2303	* Temporarily lock a dynamic page to prevent it from being reused.
2304	*
2305	* @param pVM VM handle.
2306	* @param GCPage GC address of page
2307	*/
2308	VMMDECL(void) PGMDynLockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2309	{
2310	unsigned iPage;
2311
2312	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2313	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2314	ASMAtomicIncU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2315	Log4(("PGMDynLockHCPage %RRv iPage=%d\n", GCPage, iPage));
2316	}
2317
2318
2319	/**
2320	* Unlock a dynamic page
2321	*
2322	* @param pVM VM handle.
2323	* @param GCPage GC address of page
2324	*/
2325	VMMDECL(void) PGMDynUnlockHCPage(PVM pVM, RCPTRTYPE(uint8_t *) GCPage)
2326	{
2327	unsigned iPage;
2328
2329	AssertCompile(RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache) == 2* RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache));
2330	AssertCompileMemberSize(VM, pgm.s.aLockedDynPageMapCache, sizeof(uint32_t) * (MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT)));
2331
2332	Assert(GCPage >= pVM->pgm.s.pbDynPageMapBaseGC && GCPage < (pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE));
2333	iPage = ((uintptr_t)(GCPage - pVM->pgm.s.pbDynPageMapBaseGC)) >> PAGE_SHIFT;
2334	Assert(pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2335	ASMAtomicDecU32(&pVM->pgm.s.aLockedDynPageMapCache[iPage]);
2336	Log4(("PGMDynUnlockHCPage %RRv iPage=%d\n", GCPage, iPage));
2337	}
2338
2339
2340	# ifdef VBOX_STRICT
2341	/**
2342	* Check for lock leaks.
2343	*
2344	* @param pVM VM handle.
2345	*/
2346	VMMDECL(void) PGMDynCheckLocks(PVM pVM)
2347	{
2348	for (unsigned i=0;i<RT_ELEMENTS(pVM->pgm.s.aLockedDynPageMapCache);i++)
2349	Assert(!pVM->pgm.s.aLockedDynPageMapCache[i]);
2350	}
2351	# endif /* VBOX_STRICT */
2352
2353	# endif /* IN_RC */
2354	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
2355
2356	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2357
2358	/** Format handler for PGMPAGE.
2359	* @copydoc FNRTSTRFORMATTYPE */
2360	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2361	const char pszType, void const pvValue,
2362	int cchWidth, int cchPrecision, unsigned fFlags,
2363	void *pvUser)
2364	{
2365	size_t cch;
2366	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
2367	if (VALID_PTR(pPage))
2368	{
2369	char szTmp[64+80];
2370
2371	cch = 0;
2372
2373	/* The single char state stuff. */
2374	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
2375	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE(pPage)];
2376
2377	#define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
2378	if (IS_PART_INCLUDED(5))
2379	{
2380	static const char s_achHandlerStates[4] = { '-', 't', 'w', 'a' };
2381	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)];
2382	szTmp[cch++] = s_achHandlerStates[PGM_PAGE_GET_HNDL_VIRT_STATE(pPage)];
2383	}
2384
2385	/* The type. */
2386	if (IS_PART_INCLUDED(4))
2387	{
2388	szTmp[cch++] = ':';
2389	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
2390	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][0];
2391	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][1];
2392	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE(pPage)][2];
2393	}
2394
2395	/* The numbers. */
2396	if (IS_PART_INCLUDED(3))
2397	{
2398	szTmp[cch++] = ':';
2399	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
2400	}
2401
2402	if (IS_PART_INCLUDED(2))
2403	{
2404	szTmp[cch++] = ':';
2405	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
2406	}
2407
2408	if (IS_PART_INCLUDED(6))
2409	{
2410	szTmp[cch++] = ':';
2411	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
2412	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS(pPage)];
2413	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
2414	}
2415	#undef IS_PART_INCLUDED
2416
2417	cch = pfnOutput(pvArgOutput, szTmp, cch);
2418	}
2419	else
2420	cch = pfnOutput(pvArgOutput, "<bad-pgmpage-ptr>", sizeof("<bad-pgmpage-ptr>") - 1);
2421	return cch;
2422	}
2423
2424
2425	/** Format handler for PGMRAMRANGE.
2426	* @copydoc FNRTSTRFORMATTYPE */
2427	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
2428	const char pszType, void const pvValue,
2429	int cchWidth, int cchPrecision, unsigned fFlags,
2430	void *pvUser)
2431	{
2432	size_t cch;
2433	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
2434	if (VALID_PTR(pRam))
2435	{
2436	char szTmp[80];
2437	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
2438	cch = pfnOutput(pvArgOutput, szTmp, cch);
2439	}
2440	else
2441	cch = pfnOutput(pvArgOutput, "<bad-pgmramrange-ptr>", sizeof("<bad-pgmramrange-ptr>") - 1);
2442	return cch;
2443	}
2444
2445	/** Format type andlers to be registered/deregistered. */
2446	static const struct
2447	{
2448	char szType[24];
2449	PFNRTSTRFORMATTYPE pfnHandler;
2450	} g_aPgmFormatTypes[] =
2451	{
2452	{ "pgmpage", pgmFormatTypeHandlerPage },
2453	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
2454	};
2455
2456	#endif /* !IN_R0 \|\| LOG_ENABLED */
2457
2458
2459	/**
2460	* Registers the global string format types.
2461	*
2462	* This should be called at module load time or in some other manner that ensure
2463	* that it's called exactly one time.
2464	*
2465	* @returns IPRT status code on RTStrFormatTypeRegister failure.
2466	*/
2467	VMMDECL(int) PGMRegisterStringFormatTypes(void)
2468	{
2469	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2470	int rc = VINF_SUCCESS;
2471	unsigned i;
2472	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2473	{
2474	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2475	# ifdef IN_RING0
2476	if (rc == VERR_ALREADY_EXISTS)
2477	{
2478	/* in case of cleanup failure in ring-0 */
2479	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2480	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
2481	}
2482	# endif
2483	}
2484	if (RT_FAILURE(rc))
2485	while (i-- > 0)
2486	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2487
2488	return rc;
2489	#else
2490	return VINF_SUCCESS;
2491	#endif
2492	}
2493
2494
2495	/**
2496	* Deregisters the global string format types.
2497	*
2498	* This should be called at module unload time or in some other manner that
2499	* ensure that it's called exactly one time.
2500	*/
2501	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
2502	{
2503	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
2504	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
2505	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
2506	#endif
2507	}
2508
2509	#ifdef VBOX_STRICT
2510
2511	/**
2512	* Asserts that there are no mapping conflicts.
2513	*
2514	* @returns Number of conflicts.
2515	* @param pVM The VM Handle.
2516	*/
2517	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM)
2518	{
2519	unsigned cErrors = 0;
2520
2521	/* Only applies to raw mode -> 1 VPCU */
2522	Assert(pVM->cCpus == 1);
2523	PVMCPU pVCpu = &pVM->aCpus[0];
2524
2525	/*
2526	* Check for mapping conflicts.
2527	*/
2528	for (PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
2529	pMapping;
2530	pMapping = pMapping->CTX_SUFF(pNext))
2531	{
2532	/** @todo This is slow and should be optimized, but since it's just assertions I don't care now. */
2533	for (RTGCPTR GCPtr = pMapping->GCPtr;
2534	GCPtr <= pMapping->GCPtrLast;
2535	GCPtr += PAGE_SIZE)
2536	{
2537	int rc = PGMGstGetPage(pVCpu, (RTGCPTR)GCPtr, NULL, NULL);
2538	if (rc != VERR_PAGE_TABLE_NOT_PRESENT)
2539	{
2540	AssertMsgFailed(("Conflict at %RGv with %s\n", GCPtr, R3STRING(pMapping->pszDesc)));
2541	cErrors++;
2542	break;
2543	}
2544	}
2545	}
2546
2547	return cErrors;
2548	}
2549
2550
2551	/**
2552	* Asserts that everything related to the guest CR3 is correctly shadowed.
2553	*
2554	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
2555	* and assert the correctness of the guest CR3 mapping before asserting that the
2556	* shadow page tables is in sync with the guest page tables.
2557	*
2558	* @returns Number of conflicts.
2559	* @param pVM The VM Handle.
2560	* @param pVCpu VMCPU handle.
2561	* @param cr3 The current guest CR3 register value.
2562	* @param cr4 The current guest CR4 register value.
2563	*/
2564	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4)
2565	{
2566	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2567	pgmLock(pVM);
2568	unsigned cErrors = PGM_BTH_PFN(AssertCR3, pVCpu)(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
2569	pgmUnlock(pVM);
2570	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3), a);
2571	return cErrors;
2572	}
2573
2574	#endif /* VBOX_STRICT */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 24125

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