PGMAll.cpp@ 103025

Last change on this file since 103025 was 100964, checked in by vboxsync, 15 months ago
VMM/PGM: Some experiments wrt preseving ZERO page status as the (windows) guest zero's all memory prior to use. bugref:6385 bugref:10509
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 152.7 KB

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1	/* $Id: PGMAll.cpp 100964 2023-08-24 14:45:42Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PGM
33	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
34	#include <VBox/vmm/pgm.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/selm.h>
37	#include <VBox/vmm/iem.h>
38	#include <VBox/vmm/iom.h>
39	#include <VBox/sup.h>
40	#include <VBox/vmm/mm.h>
41	#include <VBox/vmm/stam.h>
42	#include <VBox/vmm/trpm.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/hm.h>
45	#include <VBox/vmm/hm_vmx.h>
46	#include "PGMInternal.h"
47	#include <VBox/vmm/vmcc.h>
48	#include "PGMInline.h"
49	#include <iprt/assert.h>
50	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
51	# include <iprt/asm-amd64-x86.h>
52	#endif
53	#include <iprt/string.h>
54	#include <VBox/log.h>
55	#include <VBox/param.h>
56	#include <VBox/err.h>
57
58
59	/*********************************************************************************************************************************
60	* Internal Functions *
61	*********************************************************************************************************************************/
62	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD);
63	DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde);
64	DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3);
65	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
66	static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
67	PPGMPTWALKGST pGstWalk);
68	static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3);
69	static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT ppPdpt, PEPTPD ppPD,
70	PPGMPTWALKGST pGstWalkAll);
71	#endif
72	static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
73	static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD);
74	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
75	static bool pgmHandlePageZeroingCode(PVMCPUCC pVCpu, PCPUMCTX pCtx);
76	#endif
77
78
79	/*
80	* Second level transation - EPT.
81	*/
82	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
83	# define PGM_SLAT_TYPE PGM_SLAT_TYPE_EPT
84	# include "PGMSlatDefs.h"
85	# include "PGMAllGstSlatEpt.cpp.h"
86	# undef PGM_SLAT_TYPE
87	#endif
88
89
90	/*
91	* Shadow - 32-bit mode
92	*/
93	#define PGM_SHW_TYPE PGM_TYPE_32BIT
94	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
95	#include "PGMAllShw.h"
96
97	/* Guest - real mode */
98	#define PGM_GST_TYPE PGM_TYPE_REAL
99	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
100	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
102	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
103	#include "PGMGstDefs.h"
104	#include "PGMAllGst.h"
105	#include "PGMAllBth.h"
106	#undef BTH_PGMPOOLKIND_PT_FOR_PT
107	#undef BTH_PGMPOOLKIND_ROOT
108	#undef PGM_BTH_NAME
109	#undef PGM_GST_TYPE
110	#undef PGM_GST_NAME
111
112	/* Guest - protected mode */
113	#define PGM_GST_TYPE PGM_TYPE_PROT
114	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
115	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
116	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
117	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
118	#include "PGMGstDefs.h"
119	#include "PGMAllGst.h"
120	#include "PGMAllBth.h"
121	#undef BTH_PGMPOOLKIND_PT_FOR_PT
122	#undef BTH_PGMPOOLKIND_ROOT
123	#undef PGM_BTH_NAME
124	#undef PGM_GST_TYPE
125	#undef PGM_GST_NAME
126
127	/* Guest - 32-bit mode */
128	#define PGM_GST_TYPE PGM_TYPE_32BIT
129	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
130	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
131	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
132	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
133	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
134	#include "PGMGstDefs.h"
135	#include "PGMAllGst.h"
136	#include "PGMAllBth.h"
137	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
138	#undef BTH_PGMPOOLKIND_PT_FOR_PT
139	#undef BTH_PGMPOOLKIND_ROOT
140	#undef PGM_BTH_NAME
141	#undef PGM_GST_TYPE
142	#undef PGM_GST_NAME
143
144	#undef PGM_SHW_TYPE
145	#undef PGM_SHW_NAME
146
147
148	/*
149	* Shadow - PAE mode
150	*/
151	#define PGM_SHW_TYPE PGM_TYPE_PAE
152	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
153	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
154	#include "PGMAllShw.h"
155
156	/* Guest - real mode */
157	#define PGM_GST_TYPE PGM_TYPE_REAL
158	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
159	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
160	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
161	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
162	#include "PGMGstDefs.h"
163	#include "PGMAllBth.h"
164	#undef BTH_PGMPOOLKIND_PT_FOR_PT
165	#undef BTH_PGMPOOLKIND_ROOT
166	#undef PGM_BTH_NAME
167	#undef PGM_GST_TYPE
168	#undef PGM_GST_NAME
169
170	/* Guest - protected mode */
171	#define PGM_GST_TYPE PGM_TYPE_PROT
172	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
173	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
174	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
175	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
176	#include "PGMGstDefs.h"
177	#include "PGMAllBth.h"
178	#undef BTH_PGMPOOLKIND_PT_FOR_PT
179	#undef BTH_PGMPOOLKIND_ROOT
180	#undef PGM_BTH_NAME
181	#undef PGM_GST_TYPE
182	#undef PGM_GST_NAME
183
184	/* Guest - 32-bit mode */
185	#define PGM_GST_TYPE PGM_TYPE_32BIT
186	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
187	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
188	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
189	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
190	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
191	#include "PGMGstDefs.h"
192	#include "PGMAllBth.h"
193	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
194	#undef BTH_PGMPOOLKIND_PT_FOR_PT
195	#undef BTH_PGMPOOLKIND_ROOT
196	#undef PGM_BTH_NAME
197	#undef PGM_GST_TYPE
198	#undef PGM_GST_NAME
199
200
201	/* Guest - PAE mode */
202	#define PGM_GST_TYPE PGM_TYPE_PAE
203	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
204	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
205	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
206	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
207	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
208	#include "PGMGstDefs.h"
209	#include "PGMAllGst.h"
210	#include "PGMAllBth.h"
211	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
212	#undef BTH_PGMPOOLKIND_PT_FOR_PT
213	#undef BTH_PGMPOOLKIND_ROOT
214	#undef PGM_BTH_NAME
215	#undef PGM_GST_TYPE
216	#undef PGM_GST_NAME
217
218	#undef PGM_SHW_TYPE
219	#undef PGM_SHW_NAME
220
221
222	/*
223	* Shadow - AMD64 mode
224	*/
225	#define PGM_SHW_TYPE PGM_TYPE_AMD64
226	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
227	#include "PGMAllShw.h"
228
229	/* Guest - protected mode (only used for AMD-V nested paging in 64 bits mode) */
230	/** @todo retire this hack. */
231	#define PGM_GST_TYPE PGM_TYPE_PROT
232	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
233	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
234	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
235	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PD_PHYS
236	#include "PGMGstDefs.h"
237	#include "PGMAllBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef BTH_PGMPOOLKIND_ROOT
240	#undef PGM_BTH_NAME
241	#undef PGM_GST_TYPE
242	#undef PGM_GST_NAME
243
244	#ifdef VBOX_WITH_64_BITS_GUESTS
245	/* Guest - AMD64 mode */
246	# define PGM_GST_TYPE PGM_TYPE_AMD64
247	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
248	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
249	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
250	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
251	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
252	# include "PGMGstDefs.h"
253	# include "PGMAllGst.h"
254	# include "PGMAllBth.h"
255	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
256	# undef BTH_PGMPOOLKIND_PT_FOR_PT
257	# undef BTH_PGMPOOLKIND_ROOT
258	# undef PGM_BTH_NAME
259	# undef PGM_GST_TYPE
260	# undef PGM_GST_NAME
261	#endif /* VBOX_WITH_64_BITS_GUESTS */
262
263	#undef PGM_SHW_TYPE
264	#undef PGM_SHW_NAME
265
266
267	/*
268	* Shadow - 32-bit nested paging mode.
269	*/
270	#define PGM_SHW_TYPE PGM_TYPE_NESTED_32BIT
271	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_32BIT(name)
272	#include "PGMAllShw.h"
273
274	/* Guest - real mode */
275	#define PGM_GST_TYPE PGM_TYPE_REAL
276	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
277	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_REAL(name)
278	#include "PGMGstDefs.h"
279	#include "PGMAllBth.h"
280	#undef PGM_BTH_NAME
281	#undef PGM_GST_TYPE
282	#undef PGM_GST_NAME
283
284	/* Guest - protected mode */
285	#define PGM_GST_TYPE PGM_TYPE_PROT
286	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
287	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PROT(name)
288	#include "PGMGstDefs.h"
289	#include "PGMAllBth.h"
290	#undef PGM_BTH_NAME
291	#undef PGM_GST_TYPE
292	#undef PGM_GST_NAME
293
294	/* Guest - 32-bit mode */
295	#define PGM_GST_TYPE PGM_TYPE_32BIT
296	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
297	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_32BIT(name)
298	#include "PGMGstDefs.h"
299	#include "PGMAllBth.h"
300	#undef PGM_BTH_NAME
301	#undef PGM_GST_TYPE
302	#undef PGM_GST_NAME
303
304	/* Guest - PAE mode */
305	#define PGM_GST_TYPE PGM_TYPE_PAE
306	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
307	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_PAE(name)
308	#include "PGMGstDefs.h"
309	#include "PGMAllBth.h"
310	#undef PGM_BTH_NAME
311	#undef PGM_GST_TYPE
312	#undef PGM_GST_NAME
313
314	#ifdef VBOX_WITH_64_BITS_GUESTS
315	/* Guest - AMD64 mode */
316	# define PGM_GST_TYPE PGM_TYPE_AMD64
317	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
318	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT_AMD64(name)
319	# include "PGMGstDefs.h"
320	# include "PGMAllBth.h"
321	# undef PGM_BTH_NAME
322	# undef PGM_GST_TYPE
323	# undef PGM_GST_NAME
324	#endif /* VBOX_WITH_64_BITS_GUESTS */
325
326	#undef PGM_SHW_TYPE
327	#undef PGM_SHW_NAME
328
329
330	/*
331	* Shadow - PAE nested paging mode.
332	*/
333	#define PGM_SHW_TYPE PGM_TYPE_NESTED_PAE
334	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_PAE(name)
335	#include "PGMAllShw.h"
336
337	/* Guest - real mode */
338	#define PGM_GST_TYPE PGM_TYPE_REAL
339	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
340	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_REAL(name)
341	#include "PGMGstDefs.h"
342	#include "PGMAllBth.h"
343	#undef PGM_BTH_NAME
344	#undef PGM_GST_TYPE
345	#undef PGM_GST_NAME
346
347	/* Guest - protected mode */
348	#define PGM_GST_TYPE PGM_TYPE_PROT
349	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PROT(name)
351	#include "PGMGstDefs.h"
352	#include "PGMAllBth.h"
353	#undef PGM_BTH_NAME
354	#undef PGM_GST_TYPE
355	#undef PGM_GST_NAME
356
357	/* Guest - 32-bit mode */
358	#define PGM_GST_TYPE PGM_TYPE_32BIT
359	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
360	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_32BIT(name)
361	#include "PGMGstDefs.h"
362	#include "PGMAllBth.h"
363	#undef PGM_BTH_NAME
364	#undef PGM_GST_TYPE
365	#undef PGM_GST_NAME
366
367	/* Guest - PAE mode */
368	#define PGM_GST_TYPE PGM_TYPE_PAE
369	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
370	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_PAE(name)
371	#include "PGMGstDefs.h"
372	#include "PGMAllBth.h"
373	#undef PGM_BTH_NAME
374	#undef PGM_GST_TYPE
375	#undef PGM_GST_NAME
376
377	#ifdef VBOX_WITH_64_BITS_GUESTS
378	/* Guest - AMD64 mode */
379	# define PGM_GST_TYPE PGM_TYPE_AMD64
380	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
381	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE_AMD64(name)
382	# include "PGMGstDefs.h"
383	# include "PGMAllBth.h"
384	# undef PGM_BTH_NAME
385	# undef PGM_GST_TYPE
386	# undef PGM_GST_NAME
387	#endif /* VBOX_WITH_64_BITS_GUESTS */
388
389	#undef PGM_SHW_TYPE
390	#undef PGM_SHW_NAME
391
392
393	/*
394	* Shadow - AMD64 nested paging mode.
395	*/
396	#define PGM_SHW_TYPE PGM_TYPE_NESTED_AMD64
397	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED_AMD64(name)
398	#include "PGMAllShw.h"
399
400	/* Guest - real mode */
401	#define PGM_GST_TYPE PGM_TYPE_REAL
402	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
403	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_REAL(name)
404	#include "PGMGstDefs.h"
405	#include "PGMAllBth.h"
406	#undef PGM_BTH_NAME
407	#undef PGM_GST_TYPE
408	#undef PGM_GST_NAME
409
410	/* Guest - protected mode */
411	#define PGM_GST_TYPE PGM_TYPE_PROT
412	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
413	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PROT(name)
414	#include "PGMGstDefs.h"
415	#include "PGMAllBth.h"
416	#undef PGM_BTH_NAME
417	#undef PGM_GST_TYPE
418	#undef PGM_GST_NAME
419
420	/* Guest - 32-bit mode */
421	#define PGM_GST_TYPE PGM_TYPE_32BIT
422	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
423	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_32BIT(name)
424	#include "PGMGstDefs.h"
425	#include "PGMAllBth.h"
426	#undef PGM_BTH_NAME
427	#undef PGM_GST_TYPE
428	#undef PGM_GST_NAME
429
430	/* Guest - PAE mode */
431	#define PGM_GST_TYPE PGM_TYPE_PAE
432	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
433	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_PAE(name)
434	#include "PGMGstDefs.h"
435	#include "PGMAllBth.h"
436	#undef PGM_BTH_NAME
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439
440	#ifdef VBOX_WITH_64_BITS_GUESTS
441	/* Guest - AMD64 mode */
442	# define PGM_GST_TYPE PGM_TYPE_AMD64
443	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
444	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64_AMD64(name)
445	# include "PGMGstDefs.h"
446	# include "PGMAllBth.h"
447	# undef PGM_BTH_NAME
448	# undef PGM_GST_TYPE
449	# undef PGM_GST_NAME
450	#endif /* VBOX_WITH_64_BITS_GUESTS */
451
452	#undef PGM_SHW_TYPE
453	#undef PGM_SHW_NAME
454
455
456	/*
457	* Shadow - EPT.
458	*/
459	#define PGM_SHW_TYPE PGM_TYPE_EPT
460	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
461	#include "PGMAllShw.h"
462
463	/* Guest - real mode */
464	#define PGM_GST_TYPE PGM_TYPE_REAL
465	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
466	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
467	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
468	#include "PGMGstDefs.h"
469	#include "PGMAllBth.h"
470	#undef BTH_PGMPOOLKIND_PT_FOR_PT
471	#undef PGM_BTH_NAME
472	#undef PGM_GST_TYPE
473	#undef PGM_GST_NAME
474
475	/* Guest - protected mode */
476	#define PGM_GST_TYPE PGM_TYPE_PROT
477	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
478	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
479	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
480	#include "PGMGstDefs.h"
481	#include "PGMAllBth.h"
482	#undef BTH_PGMPOOLKIND_PT_FOR_PT
483	#undef PGM_BTH_NAME
484	#undef PGM_GST_TYPE
485	#undef PGM_GST_NAME
486
487	/* Guest - 32-bit mode */
488	#define PGM_GST_TYPE PGM_TYPE_32BIT
489	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
490	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
491	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
492	#include "PGMGstDefs.h"
493	#include "PGMAllBth.h"
494	#undef BTH_PGMPOOLKIND_PT_FOR_PT
495	#undef PGM_BTH_NAME
496	#undef PGM_GST_TYPE
497	#undef PGM_GST_NAME
498
499	/* Guest - PAE mode */
500	#define PGM_GST_TYPE PGM_TYPE_PAE
501	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
502	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
503	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
504	#include "PGMGstDefs.h"
505	#include "PGMAllBth.h"
506	#undef BTH_PGMPOOLKIND_PT_FOR_PT
507	#undef PGM_BTH_NAME
508	#undef PGM_GST_TYPE
509	#undef PGM_GST_NAME
510
511	#ifdef VBOX_WITH_64_BITS_GUESTS
512	/* Guest - AMD64 mode */
513	# define PGM_GST_TYPE PGM_TYPE_AMD64
514	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
515	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
516	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_EPT_PT_FOR_PHYS
517	# include "PGMGstDefs.h"
518	# include "PGMAllBth.h"
519	# undef BTH_PGMPOOLKIND_PT_FOR_PT
520	# undef PGM_BTH_NAME
521	# undef PGM_GST_TYPE
522	# undef PGM_GST_NAME
523	#endif /* VBOX_WITH_64_BITS_GUESTS */
524
525	#undef PGM_SHW_TYPE
526	#undef PGM_SHW_NAME
527
528
529	/*
530	* Shadow - NEM / None.
531	*/
532	#define PGM_SHW_TYPE PGM_TYPE_NONE
533	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NONE(name)
534	#include "PGMAllShw.h"
535
536	/* Guest - real mode */
537	#define PGM_GST_TYPE PGM_TYPE_REAL
538	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
539	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_REAL(name)
540	#include "PGMGstDefs.h"
541	#include "PGMAllBth.h"
542	#undef PGM_BTH_NAME
543	#undef PGM_GST_TYPE
544	#undef PGM_GST_NAME
545
546	/* Guest - protected mode */
547	#define PGM_GST_TYPE PGM_TYPE_PROT
548	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
549	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PROT(name)
550	#include "PGMGstDefs.h"
551	#include "PGMAllBth.h"
552	#undef PGM_BTH_NAME
553	#undef PGM_GST_TYPE
554	#undef PGM_GST_NAME
555
556	/* Guest - 32-bit mode */
557	#define PGM_GST_TYPE PGM_TYPE_32BIT
558	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
559	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_32BIT(name)
560	#include "PGMGstDefs.h"
561	#include "PGMAllBth.h"
562	#undef PGM_BTH_NAME
563	#undef PGM_GST_TYPE
564	#undef PGM_GST_NAME
565
566	/* Guest - PAE mode */
567	#define PGM_GST_TYPE PGM_TYPE_PAE
568	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
569	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_PAE(name)
570	#include "PGMGstDefs.h"
571	#include "PGMAllBth.h"
572	#undef PGM_BTH_NAME
573	#undef PGM_GST_TYPE
574	#undef PGM_GST_NAME
575
576	#ifdef VBOX_WITH_64_BITS_GUESTS
577	/* Guest - AMD64 mode */
578	# define PGM_GST_TYPE PGM_TYPE_AMD64
579	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
580	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NONE_AMD64(name)
581	# include "PGMGstDefs.h"
582	# include "PGMAllBth.h"
583	# undef PGM_BTH_NAME
584	# undef PGM_GST_TYPE
585	# undef PGM_GST_NAME
586	#endif /* VBOX_WITH_64_BITS_GUESTS */
587
588	#undef PGM_SHW_TYPE
589	#undef PGM_SHW_NAME
590
591
592
593	/**
594	* Guest mode data array.
595	*/
596	PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
597	{
598	{ UINT32_MAX, NULL, NULL, NULL, NULL }, /* 0 */
599	{
600	PGM_TYPE_REAL,
601	PGM_GST_NAME_REAL(GetPage),
602	PGM_GST_NAME_REAL(ModifyPage),
603	PGM_GST_NAME_REAL(Enter),
604	PGM_GST_NAME_REAL(Exit),
605	#ifdef IN_RING3
606	PGM_GST_NAME_REAL(Relocate),
607	#endif
608	},
609	{
610	PGM_TYPE_PROT,
611	PGM_GST_NAME_PROT(GetPage),
612	PGM_GST_NAME_PROT(ModifyPage),
613	PGM_GST_NAME_PROT(Enter),
614	PGM_GST_NAME_PROT(Exit),
615	#ifdef IN_RING3
616	PGM_GST_NAME_PROT(Relocate),
617	#endif
618	},
619	{
620	PGM_TYPE_32BIT,
621	PGM_GST_NAME_32BIT(GetPage),
622	PGM_GST_NAME_32BIT(ModifyPage),
623	PGM_GST_NAME_32BIT(Enter),
624	PGM_GST_NAME_32BIT(Exit),
625	#ifdef IN_RING3
626	PGM_GST_NAME_32BIT(Relocate),
627	#endif
628	},
629	{
630	PGM_TYPE_PAE,
631	PGM_GST_NAME_PAE(GetPage),
632	PGM_GST_NAME_PAE(ModifyPage),
633	PGM_GST_NAME_PAE(Enter),
634	PGM_GST_NAME_PAE(Exit),
635	#ifdef IN_RING3
636	PGM_GST_NAME_PAE(Relocate),
637	#endif
638	},
639	#ifdef VBOX_WITH_64_BITS_GUESTS
640	{
641	PGM_TYPE_AMD64,
642	PGM_GST_NAME_AMD64(GetPage),
643	PGM_GST_NAME_AMD64(ModifyPage),
644	PGM_GST_NAME_AMD64(Enter),
645	PGM_GST_NAME_AMD64(Exit),
646	# ifdef IN_RING3
647	PGM_GST_NAME_AMD64(Relocate),
648	# endif
649	},
650	#endif
651	};
652
653
654	/**
655	* The shadow mode data array.
656	*/
657	PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE] =
658	{
659	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* 0 */
660	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_REAL */
661	{ UINT8_MAX, NULL, NULL, NULL, NULL }, /* PGM_TYPE_PROT */
662	{
663	PGM_TYPE_32BIT,
664	PGM_SHW_NAME_32BIT(GetPage),
665	PGM_SHW_NAME_32BIT(ModifyPage),
666	PGM_SHW_NAME_32BIT(Enter),
667	PGM_SHW_NAME_32BIT(Exit),
668	#ifdef IN_RING3
669	PGM_SHW_NAME_32BIT(Relocate),
670	#endif
671	},
672	{
673	PGM_TYPE_PAE,
674	PGM_SHW_NAME_PAE(GetPage),
675	PGM_SHW_NAME_PAE(ModifyPage),
676	PGM_SHW_NAME_PAE(Enter),
677	PGM_SHW_NAME_PAE(Exit),
678	#ifdef IN_RING3
679	PGM_SHW_NAME_PAE(Relocate),
680	#endif
681	},
682	{
683	PGM_TYPE_AMD64,
684	PGM_SHW_NAME_AMD64(GetPage),
685	PGM_SHW_NAME_AMD64(ModifyPage),
686	PGM_SHW_NAME_AMD64(Enter),
687	PGM_SHW_NAME_AMD64(Exit),
688	#ifdef IN_RING3
689	PGM_SHW_NAME_AMD64(Relocate),
690	#endif
691	},
692	{
693	PGM_TYPE_NESTED_32BIT,
694	PGM_SHW_NAME_NESTED_32BIT(GetPage),
695	PGM_SHW_NAME_NESTED_32BIT(ModifyPage),
696	PGM_SHW_NAME_NESTED_32BIT(Enter),
697	PGM_SHW_NAME_NESTED_32BIT(Exit),
698	#ifdef IN_RING3
699	PGM_SHW_NAME_NESTED_32BIT(Relocate),
700	#endif
701	},
702	{
703	PGM_TYPE_NESTED_PAE,
704	PGM_SHW_NAME_NESTED_PAE(GetPage),
705	PGM_SHW_NAME_NESTED_PAE(ModifyPage),
706	PGM_SHW_NAME_NESTED_PAE(Enter),
707	PGM_SHW_NAME_NESTED_PAE(Exit),
708	#ifdef IN_RING3
709	PGM_SHW_NAME_NESTED_PAE(Relocate),
710	#endif
711	},
712	{
713	PGM_TYPE_NESTED_AMD64,
714	PGM_SHW_NAME_NESTED_AMD64(GetPage),
715	PGM_SHW_NAME_NESTED_AMD64(ModifyPage),
716	PGM_SHW_NAME_NESTED_AMD64(Enter),
717	PGM_SHW_NAME_NESTED_AMD64(Exit),
718	#ifdef IN_RING3
719	PGM_SHW_NAME_NESTED_AMD64(Relocate),
720	#endif
721	},
722	{
723	PGM_TYPE_EPT,
724	PGM_SHW_NAME_EPT(GetPage),
725	PGM_SHW_NAME_EPT(ModifyPage),
726	PGM_SHW_NAME_EPT(Enter),
727	PGM_SHW_NAME_EPT(Exit),
728	#ifdef IN_RING3
729	PGM_SHW_NAME_EPT(Relocate),
730	#endif
731	},
732	{
733	PGM_TYPE_NONE,
734	PGM_SHW_NAME_NONE(GetPage),
735	PGM_SHW_NAME_NONE(ModifyPage),
736	PGM_SHW_NAME_NONE(Enter),
737	PGM_SHW_NAME_NONE(Exit),
738	#ifdef IN_RING3
739	PGM_SHW_NAME_NONE(Relocate),
740	#endif
741	},
742	};
743
744
745	/**
746	* The guest+shadow mode data array.
747	*/
748	PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE] =
749	{
750	#if !defined(IN_RING3) && !defined(VBOX_STRICT)
751	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
752	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
753	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler) }
754
755	#elif !defined(IN_RING3) && defined(VBOX_STRICT)
756	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
757	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
758	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(Trap0eHandler), Nm(NestedTrap0eHandler), Nm(AssertCR3) }
759
760	#elif defined(IN_RING3) && !defined(VBOX_STRICT)
761	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL }
762	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
763	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), }
764
765	#elif defined(IN_RING3) && defined(VBOX_STRICT)
766	# define PGMMODEDATABTH_NULL_ENTRY() { UINT32_MAX, UINT32_MAX, NULL, NULL, NULL, NULL, NULL, NULL, NULL }
767	# define PGMMODEDATABTH_ENTRY(uShwT, uGstT, Nm) \
768	{ uShwT, uGstT, Nm(InvalidatePage), Nm(SyncCR3), Nm(PrefetchPage), Nm(VerifyAccessSyncPage), Nm(MapCR3), Nm(UnmapCR3), Nm(Enter), Nm(AssertCR3) }
769
770	#else
771	# error "Misconfig."
772	#endif
773
774	/* 32-bit shadow paging mode: */
775	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
776	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_32BIT_REAL),
777	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_32BIT_PROT),
778	PGMMODEDATABTH_ENTRY(PGM_TYPE_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_32BIT_32BIT),
779	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_PAE - illegal */
780	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_AMD64 - illegal */
781	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
782	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_PAE - illegal */
783	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
784	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT - illegal */
785	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NONE - illegal */
786
787	/* PAE shadow paging mode: */
788	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
789	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_PAE_REAL),
790	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_PAE_PROT),
791	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_PAE_32BIT),
792	PGMMODEDATABTH_ENTRY(PGM_TYPE_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_PAE_PAE),
793	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_AMD64 - illegal */
794	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_32BIT - illegal */
795	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_PAE - illegal */
796	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
797	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT - illegal */
798	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NONE - illegal */
799
800	/* AMD64 shadow paging mode: */
801	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
802	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_AMD64_REAL),
803	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_AMD64_PROT),
804	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_AMD64_32BIT),
805	PGMMODEDATABTH_NULL_ENTRY(), //PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_AMD64_PAE),
806	#ifdef VBOX_WITH_64_BITS_GUESTS
807	PGMMODEDATABTH_ENTRY(PGM_TYPE_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_AMD64_AMD64),
808	#else
809	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_AMD64 - illegal */
810	#endif
811	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
812	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_PAE - illegal */
813	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
814	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT - illegal */
815	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NONE - illegal */
816
817	/* 32-bit nested paging mode: */
818	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
819	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_32BIT_REAL),
820	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_32BIT_PROT),
821	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_32BIT_32BIT),
822	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_32BIT_PAE),
823	#ifdef VBOX_WITH_64_BITS_GUESTS
824	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_32BIT_AMD64),
825	#else
826	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_AMD64 - illegal */
827	#endif
828	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_32BIT - illegal */
829	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_PAE - illegal */
830	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
831	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT - illegal */
832	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NONE - illegal */
833
834	/* PAE nested paging mode: */
835	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
836	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_PAE_REAL),
837	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_PAE_PROT),
838	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_PAE_32BIT),
839	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_PAE_PAE),
840	#ifdef VBOX_WITH_64_BITS_GUESTS
841	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_PAE_AMD64),
842	#else
843	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_AMD64 - illegal */
844	#endif
845	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_32BIT - illegal */
846	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_PAE - illegal */
847	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
848	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT - illegal */
849	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NONE - illegal */
850
851	/* AMD64 nested paging mode: */
852	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
853	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_REAL, PGM_BTH_NAME_NESTED_AMD64_REAL),
854	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PROT, PGM_BTH_NAME_NESTED_AMD64_PROT),
855	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_32BIT, PGM_BTH_NAME_NESTED_AMD64_32BIT),
856	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_PAE, PGM_BTH_NAME_NESTED_AMD64_PAE),
857	#ifdef VBOX_WITH_64_BITS_GUESTS
858	PGMMODEDATABTH_ENTRY(PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64, PGM_BTH_NAME_NESTED_AMD64_AMD64),
859	#else
860	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_AMD64 - illegal */
861	#endif
862	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_32BIT - illegal */
863	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_PAE - illegal */
864	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
865	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT - illegal */
866	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NONE - illegal */
867
868	/* EPT nested paging mode: */
869	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
870	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
871	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
872	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
873	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
874	#ifdef VBOX_WITH_64_BITS_GUESTS
875	PGMMODEDATABTH_ENTRY(PGM_TYPE_EPT, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
876	#else
877	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_AMD64 - illegal */
878	#endif
879	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_32BIT - illegal */
880	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_PAE - illegal */
881	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
882	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT - illegal */
883	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NONE - illegal */
884
885	/* NONE / NEM: */
886	PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
887	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_REAL, PGM_BTH_NAME_EPT_REAL),
888	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PROT, PGM_BTH_NAME_EPT_PROT),
889	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
890	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PAE, PGM_BTH_NAME_EPT_PAE),
891	#ifdef VBOX_WITH_64_BITS_GUESTS
892	PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
893	#else
894	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_AMD64 - illegal */
895	#endif
896	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_32BIT - illegal */
897	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_PAE - illegal */
898	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_AMD64 - illegal */
899	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_EPT - illegal */
900	PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NONE - illegal */
901
902
903	#undef PGMMODEDATABTH_ENTRY
904	#undef PGMMODEDATABTH_NULL_ENTRY
905	};
906
907
908	/** Mask array used by pgmGetCr3MaskForMode.
909	* X86_CR3_AMD64_PAGE_MASK is used for modes that doesn't have a CR3 or EPTP. */
910	static uint64_t const g_auCr3MaskForMode[PGMMODE_MAX] =
911	{
912	/* [PGMMODE_INVALID] = */ X86_CR3_AMD64_PAGE_MASK,
913	/* [PGMMODE_REAL] = */ X86_CR3_AMD64_PAGE_MASK,
914	/* [PGMMODE_PROTECTED] = */ X86_CR3_AMD64_PAGE_MASK,
915	/* [PGMMODE_32_BIT] = */ X86_CR3_PAGE_MASK,
916	/* [PGMMODE_PAE] = */ X86_CR3_PAE_PAGE_MASK,
917	/* [PGMMODE_PAE_NX] = */ X86_CR3_PAE_PAGE_MASK,
918	/* [PGMMODE_AMD64] = */ X86_CR3_AMD64_PAGE_MASK,
919	/* [PGMMODE_AMD64_NX] = */ X86_CR3_AMD64_PAGE_MASK,
920	/* [PGMMODE_NESTED_32BIT = */ X86_CR3_PAGE_MASK,
921	/* [PGMMODE_NESTED_PAE] = */ X86_CR3_PAE_PAGE_MASK,
922	/* [PGMMODE_NESTED_AMD64] = */ X86_CR3_AMD64_PAGE_MASK,
923	/* [PGMMODE_EPT] = */ X86_CR3_EPT_PAGE_MASK,
924	/* [PGMMODE_NONE] = */ X86_CR3_AMD64_PAGE_MASK,
925	};
926
927
928	/**
929	* Gets the physical address mask for CR3 in the given paging mode.
930	*
931	* The mask is for eliminating flags and other stuff in CR3/EPTP when
932	* extracting the physical address. It is not for validating whether there are
933	* reserved bits set. PGM ASSUMES that whoever loaded the CR3 value and passed
934	* it to PGM checked for reserved bits, including reserved physical address
935	* bits.
936	*
937	* @returns The CR3 mask.
938	* @param enmMode The paging mode.
939	* @param enmSlatMode The second-level address translation mode.
940	*/
941	DECLINLINE(uint64_t) pgmGetCr3MaskForMode(PGMMODE enmMode, PGMSLAT enmSlatMode)
942	{
943	if (enmSlatMode == PGMSLAT_DIRECT)
944	{
945	Assert(enmMode != PGMMODE_EPT);
946	return g_auCr3MaskForMode[(unsigned)enmMode < (unsigned)PGMMODE_MAX ? enmMode : 0];
947	}
948	Assert(enmSlatMode == PGMSLAT_EPT);
949	return X86_CR3_EPT_PAGE_MASK;
950	}
951
952
953	/**
954	* Gets the masked CR3 value according to the current guest paging mode.
955	*
956	* See disclaimer in pgmGetCr3MaskForMode.
957	*
958	* @returns The masked PGM CR3 value.
959	* @param pVCpu The cross context virtual CPU structure.
960	* @param uCr3 The raw guest CR3 value.
961	*/
962	DECLINLINE(RTGCPHYS) pgmGetGuestMaskedCr3(PVMCPUCC pVCpu, uint64_t uCr3)
963	{
964	uint64_t const fCr3Mask = pgmGetCr3MaskForMode(pVCpu->pgm.s.enmGuestMode, pVCpu->pgm.s.enmGuestSlatMode);
965	RTGCPHYS GCPhysCR3 = (RTGCPHYS)(uCr3 & fCr3Mask);
966	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
967	return GCPhysCR3;
968	}
969
970
971	#ifdef IN_RING0
972	/**
973	* #PF Handler.
974	*
975	* @returns VBox status code (appropriate for trap handling and GC return).
976	* @param pVCpu The cross context virtual CPU structure.
977	* @param uErr The trap error code.
978	* @param pCtx Pointer to the register context for the CPU.
979	* @param pvFault The fault address.
980	*/
981	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault)
982	{
983	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
984
985	Log(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv eip=%04x:%RGv cr3=%RGp\n", uErr, pvFault, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPHYS)CPUMGetGuestCR3(pVCpu)));
986	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.StatRZTrap0e, a);
987	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = NULL; } );
988
989
990	# ifdef VBOX_WITH_STATISTICS
991	/*
992	* Error code stats.
993	*/
994	if (uErr & X86_TRAP_PF_US)
995	{
996	if (!(uErr & X86_TRAP_PF_P))
997	{
998	if (uErr & X86_TRAP_PF_RW)
999	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentWrite);
1000	else
1001	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNotPresentRead);
1002	}
1003	else if (uErr & X86_TRAP_PF_RW)
1004	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSWrite);
1005	else if (uErr & X86_TRAP_PF_RSVD)
1006	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSReserved);
1007	else if (uErr & X86_TRAP_PF_ID)
1008	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSNXE);
1009	else
1010	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eUSRead);
1011	}
1012	else
1013	{ /* Supervisor */
1014	if (!(uErr & X86_TRAP_PF_P))
1015	{
1016	if (uErr & X86_TRAP_PF_RW)
1017	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentWrite);
1018	else
1019	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVNotPresentRead);
1020	}
1021	else if (uErr & X86_TRAP_PF_RW)
1022	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVWrite);
1023	else if (uErr & X86_TRAP_PF_ID)
1024	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSNXE);
1025	else if (uErr & X86_TRAP_PF_RSVD)
1026	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eSVReserved);
1027	}
1028	# endif /* VBOX_WITH_STATISTICS */
1029
1030	/*
1031	* Call the worker.
1032	*/
1033	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1034	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1035	AssertReturn(g_aPgmBothModeData[idxBth].pfnTrap0eHandler, VERR_PGM_MODE_IPE);
1036	bool fLockTaken = false;
1037	int rc = g_aPgmBothModeData[idxBth].pfnTrap0eHandler(pVCpu, uErr, pCtx, pvFault, &fLockTaken);
1038	if (fLockTaken)
1039	{
1040	PGM_LOCK_ASSERT_OWNER(pVM);
1041	PGM_UNLOCK(pVM);
1042	}
1043	LogFlow(("PGMTrap0eHandler: uErr=%RGx pvFault=%RGv rc=%Rrc\n", uErr, pvFault, rc));
1044
1045	/*
1046	* Return code tweaks.
1047	*/
1048	if (rc != VINF_SUCCESS)
1049	{
1050	if (rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
1051	rc = VINF_SUCCESS;
1052
1053	/* Note: hack alert for difficult to reproduce problem. */
1054	if ( rc == VERR_PAGE_NOT_PRESENT /* SMP only ; disassembly might fail. */
1055	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT /* seen with UNI & SMP */
1056	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT /* seen with SMP */
1057	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT) /* precaution */
1058	{
1059	Log(("WARNING: Unexpected VERR_PAGE_TABLE_NOT_PRESENT (%d) for page fault at %RGv error code %x (rip=%RGv)\n", rc, pvFault, uErr, pCtx->rip));
1060	/* Some kind of inconsistency in the SMP case; it's safe to just execute the instruction again; not sure about single VCPU VMs though. */
1061	rc = VINF_SUCCESS;
1062	}
1063	}
1064
1065	STAM_STATS({ if (rc == VINF_EM_RAW_GUEST_TRAP) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eGuestPF); });
1066	STAM_STATS({ if (!pVCpu->pgmr0.s.pStatTrap0eAttributionR0)
1067	pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Misc; });
1068	STAM_PROFILE_STOP_EX(&pVCpu->pgm.s.Stats.StatRZTrap0e, pVCpu->pgmr0.s.pStatTrap0eAttributionR0, a);
1069	return rc;
1070	}
1071	#endif /* IN_RING0 */
1072
1073
1074	/**
1075	* Prefetch a page
1076	*
1077	* Typically used to sync commonly used pages before entering raw mode
1078	* after a CR3 reload.
1079	*
1080	* @returns VBox status code suitable for scheduling.
1081	* @retval VINF_SUCCESS on success.
1082	* @retval VINF_PGM_SYNC_CR3 if we're out of shadow pages or something like that.
1083	* @param pVCpu The cross context virtual CPU structure.
1084	* @param GCPtrPage Page to invalidate.
1085	*/
1086	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1087	{
1088	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1089
1090	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1091	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1092	AssertReturn(g_aPgmBothModeData[idxBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
1093	int rc = g_aPgmBothModeData[idxBth].pfnPrefetchPage(pVCpu, GCPtrPage);
1094
1095	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,Prefetch), a);
1096	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
1097	return rc;
1098	}
1099
1100
1101	/**
1102	* Emulation of the invlpg instruction (HC only actually).
1103	*
1104	* @returns Strict VBox status code, special care required.
1105	* @retval VINF_PGM_SYNC_CR3 - handled.
1106	* @retval VINF_EM_RAW_EMULATE_INSTR - not handled (RC only).
1107	*
1108	* @param pVCpu The cross context virtual CPU structure.
1109	* @param GCPtrPage Page to invalidate.
1110	*
1111	* @remark ASSUMES the page table entry or page directory is valid. Fairly
1112	* safe, but there could be edge cases!
1113	*
1114	* @todo Flush page or page directory only if necessary!
1115	* @todo VBOXSTRICTRC
1116	*/
1117	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1118	{
1119	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1120	int rc;
1121	Log3(("PGMInvalidatePage: GCPtrPage=%RGv\n", GCPtrPage));
1122
1123	IEMTlbInvalidatePage(pVCpu, GCPtrPage);
1124
1125	/*
1126	* Call paging mode specific worker.
1127	*/
1128	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1129	PGM_LOCK_VOID(pVM);
1130
1131	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1132	AssertReturnStmt(idxBth < RT_ELEMENTS(g_aPgmBothModeData), PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1133	AssertReturnStmt(g_aPgmBothModeData[idxBth].pfnInvalidatePage, PGM_UNLOCK(pVM), VERR_PGM_MODE_IPE);
1134	rc = g_aPgmBothModeData[idxBth].pfnInvalidatePage(pVCpu, GCPtrPage);
1135
1136	PGM_UNLOCK(pVM);
1137	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage), a);
1138
1139	/* Ignore all irrelevant error codes. */
1140	if ( rc == VERR_PAGE_NOT_PRESENT
1141	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1142	\|\| rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT
1143	\|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
1144	rc = VINF_SUCCESS;
1145
1146	return rc;
1147	}
1148
1149
1150	/**
1151	* Executes an instruction using the interpreter.
1152	*
1153	* @returns VBox status code (appropriate for trap handling and GC return).
1154	* @param pVCpu The cross context virtual CPU structure.
1155	* @param pvFault Fault address.
1156	*/
1157	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault)
1158	{
1159	RT_NOREF(pvFault);
1160	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu);
1161	if (rc == VERR_EM_INTERPRETER)
1162	rc = VINF_EM_RAW_EMULATE_INSTR;
1163	if (rc != VINF_SUCCESS)
1164	Log(("PGMInterpretInstruction: returns %Rrc (pvFault=%RGv)\n", VBOXSTRICTRC_VAL(rc), pvFault));
1165	return rc;
1166	}
1167
1168
1169	/**
1170	* Gets effective page information (from the VMM page directory).
1171	*
1172	* @returns VBox status code.
1173	* @param pVCpu The cross context virtual CPU structure.
1174	* @param GCPtr Guest Context virtual address of the page.
1175	* @param pfFlags Where to store the flags. These are X86_PTE_*.
1176	* @param pHCPhys Where to store the HC physical address of the page.
1177	* This is page aligned.
1178	* @remark You should use PGMMapGetPage() for pages in a mapping.
1179	*/
1180	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
1181	{
1182	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1183	PGM_LOCK_VOID(pVM);
1184
1185	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1186	AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1187	AssertReturn(g_aPgmShadowModeData[idxShw].pfnGetPage, VERR_PGM_MODE_IPE);
1188	int rc = g_aPgmShadowModeData[idxShw].pfnGetPage(pVCpu, GCPtr, pfFlags, pHCPhys);
1189
1190	PGM_UNLOCK(pVM);
1191	return rc;
1192	}
1193
1194
1195	/**
1196	* Modify page flags for a range of pages in the shadow context.
1197	*
1198	* The existing flags are ANDed with the fMask and ORed with the fFlags.
1199	*
1200	* @returns VBox status code.
1201	* @param pVCpu The cross context virtual CPU structure.
1202	* @param GCPtr Virtual address of the first page in the range.
1203	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
1204	* @param fMask The AND mask - page flags X86_PTE_*.
1205	* Be very CAREFUL when ~'ing constants which could be 32-bit!
1206	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1207	* @remark You must use PGMMapModifyPage() for pages in a mapping.
1208	*/
1209	DECLINLINE(int) pdmShwModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
1210	{
1211	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
1212	Assert(!(fOpFlags & ~(PGM_MK_PG_IS_MMIO2 \| PGM_MK_PG_IS_WRITE_FAULT)));
1213
1214	GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK; /** @todo this ain't necessary, right... */
1215
1216	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1217	PGM_LOCK_VOID(pVM);
1218
1219	uintptr_t idxShw = pVCpu->pgm.s.idxShadowModeData;
1220	AssertReturn(idxShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
1221	AssertReturn(g_aPgmShadowModeData[idxShw].pfnModifyPage, VERR_PGM_MODE_IPE);
1222	int rc = g_aPgmShadowModeData[idxShw].pfnModifyPage(pVCpu, GCPtr, GUEST_PAGE_SIZE, fFlags, fMask, fOpFlags);
1223
1224	PGM_UNLOCK(pVM);
1225	return rc;
1226	}
1227
1228
1229	/**
1230	* Changing the page flags for a single page in the shadow page tables so as to
1231	* make it read-only.
1232	*
1233	* @returns VBox status code.
1234	* @param pVCpu The cross context virtual CPU structure.
1235	* @param GCPtr Virtual address of the first page in the range.
1236	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1237	*/
1238	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1239	{
1240	return pdmShwModifyPage(pVCpu, GCPtr, 0, ~(uint64_t)X86_PTE_RW, fOpFlags);
1241	}
1242
1243
1244	/**
1245	* Changing the page flags for a single page in the shadow page tables so as to
1246	* make it writable.
1247	*
1248	* The call must know with 101% certainty that the guest page tables maps this
1249	* as writable too. This function will deal shared, zero and write monitored
1250	* pages.
1251	*
1252	* @returns VBox status code.
1253	* @param pVCpu The cross context virtual CPU structure.
1254	* @param GCPtr Virtual address of the first page in the range.
1255	* @param fOpFlags A combination of the PGM_MK_PK_XXX flags.
1256	*/
1257	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1258	{
1259	if (pVCpu->pgm.s.enmShadowMode != PGMMODE_NONE) /* avoid assertions */
1260	return pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)0, fOpFlags);
1261	return VINF_SUCCESS;
1262	}
1263
1264
1265	/**
1266	* Changing the page flags for a single page in the shadow page tables so as to
1267	* make it not present.
1268	*
1269	* @returns VBox status code.
1270	* @param pVCpu The cross context virtual CPU structure.
1271	* @param GCPtr Virtual address of the first page in the range.
1272	* @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1273	*/
1274	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fOpFlags)
1275	{
1276	return pdmShwModifyPage(pVCpu, GCPtr, 0, 0, fOpFlags);
1277	}
1278
1279
1280	/**
1281	* Changing the page flags for a single page in the shadow page tables so as to
1282	* make it supervisor and writable.
1283	*
1284	* This if for dealing with CR0.WP=0 and readonly user pages.
1285	*
1286	* @returns VBox status code.
1287	* @param pVCpu The cross context virtual CPU structure.
1288	* @param GCPtr Virtual address of the first page in the range.
1289	* @param fBigPage Whether or not this is a big page. If it is, we have to
1290	* change the shadow PDE as well. If it isn't, the caller
1291	* has checked that the shadow PDE doesn't need changing.
1292	* We ASSUME 4KB pages backing the big page here!
1293	* @param fOpFlags A combination of the PGM_MK_PG_XXX flags.
1294	*/
1295	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags)
1296	{
1297	int rc = pdmShwModifyPage(pVCpu, GCPtr, X86_PTE_RW, ~(uint64_t)X86_PTE_US, fOpFlags);
1298	if (rc == VINF_SUCCESS && fBigPage)
1299	{
1300	/* this is a bit ugly... */
1301	switch (pVCpu->pgm.s.enmShadowMode)
1302	{
1303	case PGMMODE_32_BIT:
1304	{
1305	PX86PDE pPde = pgmShwGet32BitPDEPtr(pVCpu, GCPtr);
1306	AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1307	Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1308	pPde->u \|= X86_PDE_RW;
1309	Log(("-> PDE=%#llx (32)\n", pPde->u));
1310	break;
1311	}
1312	case PGMMODE_PAE:
1313	case PGMMODE_PAE_NX:
1314	{
1315	PX86PDEPAE pPde = pgmShwGetPaePDEPtr(pVCpu, GCPtr);
1316	AssertReturn(pPde, VERR_INTERNAL_ERROR_3);
1317	Log(("pgmShwMakePageSupervisorAndWritable: PDE=%#llx", pPde->u));
1318	pPde->u \|= X86_PDE_RW;
1319	Log(("-> PDE=%#llx (PAE)\n", pPde->u));
1320	break;
1321	}
1322	default:
1323	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
1324	}
1325	}
1326	return rc;
1327	}
1328
1329
1330	/**
1331	* Gets the shadow page directory for the specified address, PAE.
1332	*
1333	* @returns Pointer to the shadow PD.
1334	* @param pVCpu The cross context virtual CPU structure.
1335	* @param GCPtr The address.
1336	* @param uGstPdpe Guest PDPT entry. Valid.
1337	* @param ppPD Receives address of page directory
1338	*/
1339	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1340	{
1341	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1342	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1343	PPGMPOOLPAGE pShwPage;
1344	int rc;
1345	PGM_LOCK_ASSERT_OWNER(pVM);
1346
1347
1348	/* Allocate page directory if not present. */
1349	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1350	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1351	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1352	X86PGPAEUINT const uPdpe = pPdpe->u;
1353	if (uPdpe & (X86_PDPE_P \| X86_PDPE_PG_MASK))
1354	{
1355	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1356	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1357	Assert((pPdpe->u & X86_PDPE_PG_MASK) == pShwPage->Core.Key);
1358
1359	pgmPoolCacheUsed(pPool, pShwPage);
1360
1361	/* Update the entry if necessary. */
1362	X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key \| (uGstPdpe & (X86_PDPE_P \| X86_PDPE_A)) \| (uPdpe & PGM_PDPT_FLAGS);
1363	if (uPdpeNew == uPdpe)
1364	{ /* likely */ }
1365	else
1366	ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1367	}
1368	else
1369	{
1370	RTGCPTR64 GCPdPt;
1371	PGMPOOLKIND enmKind;
1372	if (pVM->pgm.s.fNestedPaging \|\| !CPUMIsGuestPagingEnabled(pVCpu))
1373	{
1374	/* AMD-V nested paging or real/protected mode without paging. */
1375	GCPdPt = GCPtr & ~(RT_BIT_64(X86_PDPT_SHIFT) - 1);
1376	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1377	}
1378	else if (CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE)
1379	{
1380	if (uGstPdpe & X86_PDPE_P)
1381	{
1382	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1383	enmKind = PGMPOOLKIND_PAE_PD_FOR_PAE_PD;
1384	}
1385	else
1386	{
1387	/* PD not present; guest must reload CR3 to change it.
1388	* No need to monitor anything in this case. */
1389	/** @todo r=bird: WTF is hit?!? */
1390	/Assert(VM_IS_RAW_MODE_ENABLED(pVM)); - ??? /
1391	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1392	enmKind = PGMPOOLKIND_PAE_PD_PHYS;
1393	Assert(uGstPdpe & X86_PDPE_P); /* caller should do this already */
1394	}
1395	}
1396	else
1397	{
1398	GCPdPt = CPUMGetGuestCR3(pVCpu);
1399	enmKind = (PGMPOOLKIND)(PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD + iPdPt);
1400	}
1401
1402	/* Create a reference back to the PDPT by using the index in its shadow page. */
1403	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1404	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPdPt, false /fLockPage/,
1405	&pShwPage);
1406	AssertRCReturn(rc, rc);
1407
1408	/* Hook it up. */
1409	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| (uGstPdpe & (X86_PDPE_P \| X86_PDPE_A)) \| (uPdpe & PGM_PDPT_FLAGS));
1410	}
1411	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdpe);
1412
1413	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/**
1419	* Gets the pointer to the shadow page directory entry for an address, PAE.
1420	*
1421	* @returns Pointer to the PDE.
1422	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1423	* @param GCPtr The address.
1424	* @param ppShwPde Receives the address of the pgm pool page for the shadow page directory
1425	*/
1426	DECLINLINE(int) pgmShwGetPaePoolPagePD(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPOOLPAGE *ppShwPde)
1427	{
1428	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1429	PGM_LOCK_ASSERT_OWNER(pVM);
1430
1431	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pVCpu);
1432	AssertReturn(pPdpt, VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT); /* can't happen */
1433	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
1434	X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1435	if (!(uPdpe & X86_PDPE_P))
1436	{
1437	LogFlow(("pgmShwGetPaePoolPagePD: PD %d not present (%RX64)\n", iPdPt, uPdpe));
1438	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1439	}
1440	AssertMsg(uPdpe & X86_PDPE_PG_MASK, ("GCPtr=%RGv\n", GCPtr));
1441
1442	/* Fetch the pgm pool shadow descriptor. */
1443	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pVM->pgm.s.CTX_SUFF(pPool), uPdpe & X86_PDPE_PG_MASK);
1444	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1445
1446	*ppShwPde = pShwPde;
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* Syncs the SHADOW page directory pointer for the specified address.
1453	*
1454	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1455	*
1456	* The caller is responsible for making sure the guest has a valid PD before
1457	* calling this function.
1458	*
1459	* @returns VBox status code.
1460	* @param pVCpu The cross context virtual CPU structure.
1461	* @param GCPtr The address.
1462	* @param uGstPml4e Guest PML4 entry (valid).
1463	* @param uGstPdpe Guest PDPT entry (valid).
1464	* @param ppPD Receives address of page directory
1465	*/
1466	static int pgmShwSyncLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, X86PGPAEUINT uGstPml4e, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD)
1467	{
1468	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1469	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1470	bool const fNestedPagingOrNoGstPaging = pVM->pgm.s.fNestedPaging \|\| !CPUMIsGuestPagingEnabled(pVCpu);
1471	int rc;
1472
1473	PGM_LOCK_ASSERT_OWNER(pVM);
1474
1475	/*
1476	* PML4.
1477	*/
1478	PPGMPOOLPAGE pShwPage;
1479	{
1480	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1481	PX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1482	X86PGPAEUINT const uPml4e = pPml4e->u;
1483
1484	/* Allocate page directory pointer table if not present. */
1485	if (uPml4e & (X86_PML4E_P \| X86_PML4E_PG_MASK))
1486	{
1487	pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1488	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1489
1490	pgmPoolCacheUsed(pPool, pShwPage);
1491
1492	/* Update the entry if needed. */
1493	X86PGPAEUINT const uPml4eNew = pShwPage->Core.Key \| (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1494	\| (uPml4e & PGM_PML4_FLAGS);
1495	if (uPml4e == uPml4eNew)
1496	{ /* likely */ }
1497	else
1498	ASMAtomicWriteU64(&pPml4e->u, uPml4eNew);
1499	}
1500	else
1501	{
1502	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1503
1504	RTGCPTR64 GCPml4;
1505	PGMPOOLKIND enmKind;
1506	if (fNestedPagingOrNoGstPaging)
1507	{
1508	/* AMD-V nested paging or real/protected mode without paging */
1509	GCPml4 = (RTGCPTR64)iPml4 << X86_PML4_SHIFT; /** @todo bogus calculation for PML5 */
1510	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_PHYS;
1511	}
1512	else
1513	{
1514	GCPml4 = uGstPml4e & X86_PML4E_PG_MASK;
1515	enmKind = PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT;
1516	}
1517
1518	/* Create a reference back to the PDPT by using the index in its shadow page. */
1519	rc = pgmPoolAlloc(pVM, GCPml4, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1520	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /fLockPage/,
1521	&pShwPage);
1522	AssertRCReturn(rc, rc);
1523
1524	/* Hook it up. */
1525	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| (uGstPml4e & pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask)
1526	\| (uPml4e & PGM_PML4_FLAGS));
1527	}
1528	}
1529
1530	/*
1531	* PDPT.
1532	*/
1533	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1534	PX86PDPT pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1535	PX86PDPE pPdpe = &pPdpt->a[iPdPt];
1536	X86PGPAEUINT const uPdpe = pPdpe->u;
1537
1538	/* Allocate page directory if not present. */
1539	if (uPdpe & (X86_PDPE_P \| X86_PDPE_PG_MASK))
1540	{
1541	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1542	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1543
1544	pgmPoolCacheUsed(pPool, pShwPage);
1545
1546	/* Update the entry if needed. */
1547	X86PGPAEUINT const uPdpeNew = pShwPage->Core.Key \| (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask)
1548	\| (uPdpe & PGM_PDPT_FLAGS);
1549	if (uPdpe == uPdpeNew)
1550	{ /* likely */ }
1551	else
1552	ASMAtomicWriteU64(&pPdpe->u, uPdpeNew);
1553	}
1554	else
1555	{
1556	RTGCPTR64 GCPdPt;
1557	PGMPOOLKIND enmKind;
1558	if (fNestedPagingOrNoGstPaging)
1559	{
1560	/* AMD-V nested paging or real/protected mode without paging */
1561	GCPdPt = GCPtr & ~(RT_BIT_64(iPdPt << X86_PDPT_SHIFT) - 1);
1562	enmKind = PGMPOOLKIND_64BIT_PD_FOR_PHYS;
1563	}
1564	else
1565	{
1566	GCPdPt = uGstPdpe & X86_PDPE_PG_MASK;
1567	enmKind = PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD;
1568	}
1569
1570	/* Create a reference back to the PDPT by using the index in its shadow page. */
1571	rc = pgmPoolAlloc(pVM, GCPdPt, enmKind, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1572	pShwPage->idx, iPdPt, false /fLockPage/,
1573	&pShwPage);
1574	AssertRCReturn(rc, rc);
1575
1576	/* Hook it up. */
1577	ASMAtomicWriteU64(&pPdpe->u,
1578	pShwPage->Core.Key \| (uGstPdpe & pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask) \| (uPdpe & PGM_PDPT_FLAGS));
1579	}
1580
1581	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1582	return VINF_SUCCESS;
1583	}
1584
1585
1586	/**
1587	* Gets the SHADOW page directory pointer for the specified address (long mode).
1588	*
1589	* @returns VBox status code.
1590	* @param pVCpu The cross context virtual CPU structure.
1591	* @param GCPtr The address.
1592	* @param ppPml4e Receives the address of the page map level 4 entry.
1593	* @param ppPdpt Receives the address of the page directory pointer table.
1594	* @param ppPD Receives the address of the page directory.
1595	*/
1596	DECLINLINE(int) pgmShwGetLongModePDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPT ppPdpt, PX86PDPAE *ppPD)
1597	{
1598	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1599	PGM_LOCK_ASSERT_OWNER(pVM);
1600
1601	/*
1602	* PML4
1603	*/
1604	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
1605	PCX86PML4E pPml4e = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
1606	AssertReturn(pPml4e, VERR_PGM_PML4_MAPPING);
1607	if (ppPml4e)
1608	*ppPml4e = (PX86PML4E)pPml4e;
1609	X86PGPAEUINT const uPml4e = pPml4e->u;
1610	Log4(("pgmShwGetLongModePDPtr %RGv (%RHv) %RX64\n", GCPtr, pPml4e, uPml4e));
1611	if (!(uPml4e & X86_PML4E_P)) /** @todo other code is check for NULL page frame number! */
1612	return VERR_PAGE_MAP_LEVEL4_NOT_PRESENT;
1613
1614	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1615	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, uPml4e & X86_PML4E_PG_MASK);
1616	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1617
1618	/*
1619	* PDPT
1620	*/
1621	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1622	PCX86PDPT pPdpt = *ppPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1623	X86PGPAEUINT const uPdpe = pPdpt->a[iPdPt].u;
1624	if (!(uPdpe & X86_PDPE_P)) /** @todo other code is check for NULL page frame number! */
1625	return VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT;
1626
1627	pShwPage = pgmPoolGetPage(pPool, uPdpe & X86_PDPE_PG_MASK);
1628	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1629
1630	*ppPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1631	Log4(("pgmShwGetLongModePDPtr %RGv -> ppPD=%p PDE=%p/%RX64\n", GCPtr, ppPD, &(ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK], (ppPD)->a[(GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK].u));
1632	return VINF_SUCCESS;
1633	}
1634
1635
1636	/**
1637	* Syncs the SHADOW EPT page directory pointer for the specified address. Allocates
1638	* backing pages in case the PDPT or PML4 entry is missing.
1639	*
1640	* @returns VBox status code.
1641	* @param pVCpu The cross context virtual CPU structure.
1642	* @param GCPtr The address.
1643	* @param ppPdpt Receives address of pdpt
1644	* @param ppPD Receives address of page directory
1645	*/
1646	static int pgmShwGetEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPtr, PEPTPDPT ppPdpt, PEPTPD ppPD)
1647	{
1648	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1649	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1650	int rc;
1651
1652	Assert(pVM->pgm.s.fNestedPaging);
1653	PGM_LOCK_ASSERT_OWNER(pVM);
1654
1655	/*
1656	* PML4 level.
1657	*/
1658	PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1659	Assert(pPml4);
1660
1661	/* Allocate page directory pointer table if not present. */
1662	PPGMPOOLPAGE pShwPage;
1663	{
1664	const unsigned iPml4 = (GCPtr >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1665	PEPTPML4E pPml4e = &pPml4->a[iPml4];
1666	EPTPML4E Pml4e;
1667	Pml4e.u = pPml4e->u;
1668	if (!(Pml4e.u & (EPT_E_PG_MASK \| EPT_E_READ)))
1669	{
1670	RTGCPTR64 GCPml4 = (RTGCPTR64)iPml4 << EPT_PML4_SHIFT;
1671	rc = pgmPoolAlloc(pVM, GCPml4, PGMPOOLKIND_EPT_PDPT_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1672	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4, false /fLockPage/,
1673	&pShwPage);
1674	AssertRCReturn(rc, rc);
1675
1676	/* Hook up the new PDPT now. */
1677	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1678	}
1679	else
1680	{
1681	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1682	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1683
1684	pgmPoolCacheUsed(pPool, pShwPage);
1685
1686	/* Hook up the cached PDPT if needed (probably not given 512512 PTs to sync). /
1687	if (Pml4e.u == (pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE))
1688	{ }
1689	else
1690	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1691	}
1692	}
1693
1694	/*
1695	* PDPT level.
1696	*/
1697	const unsigned iPdPt = (GCPtr >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1698	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1699	PEPTPDPTE pPdpe = &pPdpt->a[iPdPt];
1700
1701	if (ppPdpt)
1702	*ppPdpt = pPdpt;
1703
1704	/* Allocate page directory if not present. */
1705	EPTPDPTE Pdpe;
1706	Pdpe.u = pPdpe->u;
1707	if (!(Pdpe.u & (EPT_E_PG_MASK \| EPT_E_READ)))
1708	{
1709	RTGCPTR64 const GCPdPt = GCPtr & ~(RT_BIT_64(EPT_PDPT_SHIFT) - 1);
1710	rc = pgmPoolAlloc(pVM, GCPdPt, PGMPOOLKIND_EPT_PD_FOR_PHYS, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1711	pShwPage->idx, iPdPt, false /fLockPage/,
1712	&pShwPage);
1713	AssertRCReturn(rc, rc);
1714
1715	/* Hook up the new PD now. */
1716	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1717	}
1718	else
1719	{
1720	pShwPage = pgmPoolGetPage(pPool, pPdpe->u & EPT_PDPTE_PG_MASK);
1721	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1722
1723	pgmPoolCacheUsed(pPool, pShwPage);
1724
1725	/* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1726	if (Pdpe.u == (pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE))
1727	{ }
1728	else
1729	ASMAtomicWriteU64(&pPdpe->u, pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE);
1730	}
1731
1732	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1733	return VINF_SUCCESS;
1734	}
1735
1736
1737	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1738	/**
1739	* Syncs the SHADOW nested-guest page directory pointer for the specified address.
1740	* Allocates backing pages in case the PDPT or PML4 entry is missing.
1741	*
1742	* @returns VBox status code.
1743	* @param pVCpu The cross context virtual CPU structure.
1744	* @param GCPhysNested The nested-guest physical address.
1745	* @param ppPdpt Where to store the PDPT. Optional, can be NULL.
1746	* @param ppPD Where to store the PD. Optional, can be NULL.
1747	* @param pGstWalkAll The guest walk info.
1748	*/
1749	static int pgmShwGetNestedEPTPDPtr(PVMCPUCC pVCpu, RTGCPTR64 GCPhysNested, PEPTPDPT ppPdpt, PEPTPD ppPD,
1750	PPGMPTWALKGST pGstWalkAll)
1751	{
1752	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1753	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1754	int rc;
1755
1756	PPGMPOOLPAGE pShwPage;
1757	Assert(pVM->pgm.s.fNestedPaging);
1758	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
1759	PGM_LOCK_ASSERT_OWNER(pVM);
1760
1761	/*
1762	* PML4 level.
1763	*/
1764	{
1765	PEPTPML4 pPml4 = (PEPTPML4)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
1766	Assert(pPml4);
1767
1768	/* Allocate page directory pointer table if not present. */
1769	{
1770	uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pml4e.u & pVCpu->pgm.s.fGstEptShadowedPml4eMask;
1771	const unsigned iPml4e = (GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK;
1772	PEPTPML4E pPml4e = &pPml4->a[iPml4e];
1773
1774	if (!(pPml4e->u & (EPT_E_PG_MASK \| EPT_PRESENT_MASK)))
1775	{
1776	RTGCPHYS const GCPhysPdpt = pGstWalkAll->u.Ept.Pml4e.u & EPT_PML4E_PG_MASK;
1777	rc = pgmPoolAlloc(pVM, GCPhysPdpt, PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT, PGMPOOLACCESS_DONTCARE,
1778	PGM_A20_IS_ENABLED(pVCpu), pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4e, false /fLockPage/,
1779	&pShwPage);
1780	AssertRCReturn(rc, rc);
1781
1782	/* Hook up the new PDPT now. */
1783	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| fShwFlags);
1784	}
1785	else
1786	{
1787	pShwPage = pgmPoolGetPage(pPool, pPml4e->u & EPT_PML4E_PG_MASK);
1788	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1789
1790	pgmPoolCacheUsed(pPool, pShwPage);
1791
1792	/* Hook up the cached PDPT if needed (probably not given 512512 PTs to sync). /
1793	if (pPml4e->u != (pShwPage->Core.Key \| fShwFlags))
1794	ASMAtomicWriteU64(&pPml4e->u, pShwPage->Core.Key \| fShwFlags);
1795	}
1796	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1797	Log7Func(("GstPml4e=%RX64 ShwPml4e=%RX64 iPml4e=%u\n", pGstWalkAll->u.Ept.Pml4e.u, pPml4e->u, iPml4e));
1798	}
1799	}
1800
1801	/*
1802	* PDPT level.
1803	*/
1804	{
1805	AssertReturn(!(pGstWalkAll->u.Ept.Pdpte.u & EPT_E_LEAF), VERR_NOT_SUPPORTED); /* shadowing 1GB pages not supported yet. */
1806
1807	PEPTPDPT pPdpt = (PEPTPDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1808	if (ppPdpt)
1809	*ppPdpt = pPdpt;
1810
1811	uint64_t const fShwFlags = pGstWalkAll->u.Ept.Pdpte.u & pVCpu->pgm.s.fGstEptShadowedPdpteMask;
1812	const unsigned iPdPte = (GCPhysNested >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
1813	PEPTPDPTE pPdpte = &pPdpt->a[iPdPte];
1814
1815	if (!(pPdpte->u & (EPT_E_PG_MASK \| EPT_PRESENT_MASK)))
1816	{
1817	RTGCPHYS const GCPhysPd = pGstWalkAll->u.Ept.Pdpte.u & EPT_PDPTE_PG_MASK;
1818	rc = pgmPoolAlloc(pVM, GCPhysPd, PGMPOOLKIND_EPT_PD_FOR_EPT_PD, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
1819	pShwPage->idx, iPdPte, false /fLockPage/, &pShwPage);
1820	AssertRCReturn(rc, rc);
1821
1822	/* Hook up the new PD now. */
1823	ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key \| fShwFlags);
1824	}
1825	else
1826	{
1827	pShwPage = pgmPoolGetPage(pPool, pPdpte->u & EPT_PDPTE_PG_MASK);
1828	AssertReturn(pShwPage, VERR_PGM_POOL_GET_PAGE_FAILED);
1829
1830	pgmPoolCacheUsed(pPool, pShwPage);
1831
1832	/* Hook up the cached PD if needed (probably not given there are 512 PTs we may need sync). */
1833	if (pPdpte->u != (pShwPage->Core.Key \| fShwFlags))
1834	ASMAtomicWriteU64(&pPdpte->u, pShwPage->Core.Key \| fShwFlags);
1835	}
1836	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
1837	Log7Func(("GstPdpte=%RX64 ShwPdpte=%RX64 iPdPte=%u \n", pGstWalkAll->u.Ept.Pdpte.u, pPdpte->u, iPdPte));
1838
1839	*ppPD = (PEPTPD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1840	}
1841
1842	return VINF_SUCCESS;
1843	}
1844	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1845
1846
1847	#ifdef IN_RING0
1848	/**
1849	* Synchronizes a range of nested page table entries.
1850	*
1851	* The caller must own the PGM lock.
1852	*
1853	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1854	* @param GCPhys Where to start.
1855	* @param cPages How many pages which entries should be synced.
1856	* @param enmShwPagingMode The shadow paging mode (PGMMODE_EPT for VT-x,
1857	* host paging mode for AMD-V).
1858	*/
1859	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint32_t cPages, PGMMODE enmShwPagingMode)
1860	{
1861	PGM_LOCK_ASSERT_OWNER(pVCpu->CTX_SUFF(pVM));
1862
1863	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
1864	int rc;
1865	switch (enmShwPagingMode)
1866	{
1867	case PGMMODE_32_BIT:
1868	{
1869	X86PDE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1870	rc = PGM_BTH_NAME_32BIT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1871	break;
1872	}
1873
1874	case PGMMODE_PAE:
1875	case PGMMODE_PAE_NX:
1876	{
1877	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1878	rc = PGM_BTH_NAME_PAE_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1879	break;
1880	}
1881
1882	case PGMMODE_AMD64:
1883	case PGMMODE_AMD64_NX:
1884	{
1885	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1886	rc = PGM_BTH_NAME_AMD64_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1887	break;
1888	}
1889
1890	case PGMMODE_EPT:
1891	{
1892	X86PDEPAE PdeDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
1893	rc = PGM_BTH_NAME_EPT_PROT(SyncPage)(pVCpu, PdeDummy, GCPhys, cPages, ~0U /uErr/);
1894	break;
1895	}
1896
1897	default:
1898	AssertMsgFailedReturn(("%d\n", enmShwPagingMode), VERR_IPE_NOT_REACHED_DEFAULT_CASE);
1899	}
1900	return rc;
1901	}
1902	#endif /* IN_RING0 */
1903
1904
1905	/**
1906	* Gets effective Guest OS page information.
1907	*
1908	* When GCPtr is in a big page, the function will return as if it was a normal
1909	* 4KB page. If the need for distinguishing between big and normal page becomes
1910	* necessary at a later point, a PGMGstGetPage() will be created for that
1911	* purpose.
1912	*
1913	* @returns VBox status code.
1914	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1915	* @param GCPtr Guest Context virtual address of the page.
1916	* @param pWalk Where to store the page walk information.
1917	*/
1918	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
1919	{
1920	VMCPU_ASSERT_EMT(pVCpu);
1921	Assert(pWalk);
1922	uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
1923	AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
1924	AssertReturn(g_aPgmGuestModeData[idx].pfnGetPage, VERR_PGM_MODE_IPE);
1925	return g_aPgmGuestModeData[idx].pfnGetPage(pVCpu, GCPtr, pWalk);
1926	}
1927
1928
1929	/**
1930	* Maps the guest CR3.
1931	*
1932	* @returns VBox status code.
1933	* @param pVCpu The cross context virtual CPU structure.
1934	* @param GCPhysCr3 The guest CR3 value.
1935	* @param pHCPtrGuestCr3 Where to store the mapped memory.
1936	*/
1937	DECLINLINE(int) pgmGstMapCr3(PVMCPUCC pVCpu, RTGCPHYS GCPhysCr3, PRTHCPTR pHCPtrGuestCr3)
1938	{
1939	/** @todo this needs some reworking wrt. locking? */
1940	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1941	PGM_LOCK_VOID(pVM);
1942	PPGMPAGE pPageCr3 = pgmPhysGetPage(pVM, GCPhysCr3);
1943	AssertReturnStmt(pPageCr3, PGM_UNLOCK(pVM), VERR_PGM_INVALID_CR3_ADDR);
1944
1945	RTHCPTR HCPtrGuestCr3;
1946	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCr3, GCPhysCr3, (void **)&HCPtrGuestCr3);
1947	PGM_UNLOCK(pVM);
1948
1949	*pHCPtrGuestCr3 = HCPtrGuestCr3;
1950	return rc;
1951	}
1952
1953
1954	/**
1955	* Unmaps the guest CR3.
1956	*
1957	* @returns VBox status code.
1958	* @param pVCpu The cross context virtual CPU structure.
1959	*/
1960	DECLINLINE(int) pgmGstUnmapCr3(PVMCPUCC pVCpu)
1961	{
1962	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
1963	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
1964	AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
1965	return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
1966	}
1967
1968
1969	/**
1970	* Performs a guest page table walk.
1971	*
1972	* The guest should be in paged protect mode or long mode when making a call to
1973	* this function.
1974	*
1975	* @returns VBox status code.
1976	* @retval VINF_SUCCESS on success.
1977	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
1978	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
1979	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
1980	*
1981	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1982	* @param GCPtr The guest virtual address to walk by.
1983	* @param pWalk Where to return the walk result. This is valid for some
1984	* error codes as well.
1985	* @param pGstWalk The guest mode specific page walk information.
1986	*/
1987	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
1988	{
1989	VMCPU_ASSERT_EMT(pVCpu);
1990	switch (pVCpu->pgm.s.enmGuestMode)
1991	{
1992	case PGMMODE_32_BIT:
1993	pGstWalk->enmType = PGMPTWALKGSTTYPE_32BIT;
1994	return PGM_GST_NAME_32BIT(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Legacy);
1995
1996	case PGMMODE_PAE:
1997	case PGMMODE_PAE_NX:
1998	pGstWalk->enmType = PGMPTWALKGSTTYPE_PAE;
1999	return PGM_GST_NAME_PAE(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Pae);
2000
2001	case PGMMODE_AMD64:
2002	case PGMMODE_AMD64_NX:
2003	pGstWalk->enmType = PGMPTWALKGSTTYPE_AMD64;
2004	return PGM_GST_NAME_AMD64(Walk)(pVCpu, GCPtr, pWalk, &pGstWalk->u.Amd64);
2005
2006	case PGMMODE_REAL:
2007	case PGMMODE_PROTECTED:
2008	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2009	return VERR_PGM_NOT_USED_IN_MODE;
2010
2011	case PGMMODE_EPT:
2012	case PGMMODE_NESTED_32BIT:
2013	case PGMMODE_NESTED_PAE:
2014	case PGMMODE_NESTED_AMD64:
2015	default:
2016	AssertFailed();
2017	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2018	return VERR_PGM_NOT_USED_IN_MODE;
2019	}
2020	}
2021
2022
2023	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2024	/**
2025	* Performs a guest second-level address translation (SLAT).
2026	*
2027	* @returns VBox status code.
2028	* @retval VINF_SUCCESS on success.
2029	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2030	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2031	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2032	*
2033	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2034	* @param GCPhysNested The nested-guest physical address being translated.
2035	* @param fIsLinearAddrValid Whether the linear address in @a GCPtrNested is the
2036	* cause for this translation.
2037	* @param GCPtrNested The nested-guest virtual address that initiated the
2038	* SLAT. If none, pass 0 (and not NIL_RTGCPTR).
2039	* @param pWalk Where to return the walk result. This is updated for
2040	* all error codes other than
2041	* VERR_PGM_NOT_USED_IN_MODE.
2042	* @param pGstWalk Where to store the second-level paging-mode specific
2043	* walk info.
2044	*/
2045	static int pgmGstSlatWalk(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
2046	PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2047	{
2048	/* SLAT mode must be valid at this point as this should only be used -after- we have determined SLAT mode. */
2049	Assert( pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT
2050	&& pVCpu->pgm.s.enmGuestSlatMode != PGMSLAT_INVALID);
2051	AssertPtr(pWalk);
2052	AssertPtr(pGstWalk);
2053	switch (pVCpu->pgm.s.enmGuestSlatMode)
2054	{
2055	case PGMSLAT_EPT:
2056	pGstWalk->enmType = PGMPTWALKGSTTYPE_EPT;
2057	return PGM_GST_SLAT_NAME_EPT(Walk)(pVCpu, GCPhysNested, fIsLinearAddrValid, GCPtrNested, pWalk, &pGstWalk->u.Ept);
2058
2059	default:
2060	AssertFailed();
2061	pGstWalk->enmType = PGMPTWALKGSTTYPE_INVALID;
2062	return VERR_PGM_NOT_USED_IN_MODE;
2063	}
2064	}
2065	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
2066
2067
2068	/**
2069	* Tries to continue the previous walk.
2070	*
2071	* @note Requires the caller to hold the PGM lock from the first
2072	* pgmGstPtWalk() call to the last pgmGstPtWalkNext() call. Otherwise
2073	* we cannot use the pointers.
2074	*
2075	* @returns VBox status code.
2076	* @retval VINF_SUCCESS on success.
2077	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
2078	* @retval VERR_PGM_NOT_USED_IN_MODE if not paging isn't enabled. @a pWalk is
2079	* not valid, except enmType is PGMPTWALKGSTTYPE_INVALID.
2080	*
2081	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2082	* @param GCPtr The guest virtual address to walk by.
2083	* @param pWalk Pointer to the previous walk result and where to return
2084	* the result of this walk. This is valid for some error
2085	* codes as well.
2086	* @param pGstWalk The guest-mode specific walk information.
2087	*/
2088	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk)
2089	{
2090	/*
2091	* We can only handle successfully walks.
2092	* We also limit ourselves to the next page.
2093	*/
2094	if ( pWalk->fSucceeded
2095	&& GCPtr - pWalk->GCPtr == GUEST_PAGE_SIZE)
2096	{
2097	Assert(pWalk->uLevel == 0);
2098	if (pGstWalk->enmType == PGMPTWALKGSTTYPE_AMD64)
2099	{
2100	/*
2101	* AMD64
2102	*/
2103	if (!pWalk->fGigantPage && !pWalk->fBigPage)
2104	{
2105	/*
2106	* We fall back to full walk if the PDE table changes, if any
2107	* reserved bits are set, or if the effective page access changes.
2108	*/
2109	const uint64_t fPteSame = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT
2110	\| X86_PTE_PCD \| X86_PTE_A \| X86_PTE_PAE_NX;
2111	const uint64_t fPdeSame = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT
2112	\| X86_PDE_PCD \| X86_PDE_A \| X86_PDE_PAE_NX \| X86_PDE_PS;
2113
2114	if ((GCPtr >> X86_PD_PAE_SHIFT) == (pWalk->GCPtr >> X86_PD_PAE_SHIFT))
2115	{
2116	if (pGstWalk->u.Amd64.pPte)
2117	{
2118	X86PTEPAE Pte;
2119	Pte.u = pGstWalk->u.Amd64.pPte[1].u;
2120	if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2121	&& !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2122	{
2123	pWalk->GCPtr = GCPtr;
2124	pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2125	pGstWalk->u.Amd64.Pte.u = Pte.u;
2126	pGstWalk->u.Amd64.pPte++;
2127	return VINF_SUCCESS;
2128	}
2129	}
2130	}
2131	else if ((GCPtr >> X86_PDPT_SHIFT) == (pWalk->GCPtr >> X86_PDPT_SHIFT))
2132	{
2133	Assert(!((GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK)); /* Must be first PT entry. */
2134	if (pGstWalk->u.Amd64.pPde)
2135	{
2136	X86PDEPAE Pde;
2137	Pde.u = pGstWalk->u.Amd64.pPde[1].u;
2138	if ( (Pde.u & fPdeSame) == (pGstWalk->u.Amd64.Pde.u & fPdeSame)
2139	&& !(Pde.u & (pVCpu)->pgm.s.fGstAmd64MbzPdeMask))
2140	{
2141	/* Get the new PTE and check out the first entry. */
2142	int rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, PGM_A20_APPLY(pVCpu, (Pde.u & X86_PDE_PAE_PG_MASK)),
2143	&pGstWalk->u.Amd64.pPt);
2144	if (RT_SUCCESS(rc))
2145	{
2146	pGstWalk->u.Amd64.pPte = &pGstWalk->u.Amd64.pPt->a[0];
2147	X86PTEPAE Pte;
2148	Pte.u = pGstWalk->u.Amd64.pPte->u;
2149	if ( (Pte.u & fPteSame) == (pGstWalk->u.Amd64.Pte.u & fPteSame)
2150	&& !(Pte.u & (pVCpu)->pgm.s.fGstAmd64MbzPteMask))
2151	{
2152	pWalk->GCPtr = GCPtr;
2153	pWalk->GCPhys = Pte.u & X86_PTE_PAE_PG_MASK;
2154	pGstWalk->u.Amd64.Pte.u = Pte.u;
2155	pGstWalk->u.Amd64.Pde.u = Pde.u;
2156	pGstWalk->u.Amd64.pPde++;
2157	return VINF_SUCCESS;
2158	}
2159	}
2160	}
2161	}
2162	}
2163	}
2164	else if (!pWalk->fGigantPage)
2165	{
2166	if ((GCPtr & X86_PAGE_2M_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_2M_BASE_MASK))
2167	{
2168	pWalk->GCPtr = GCPtr;
2169	pWalk->GCPhys += GUEST_PAGE_SIZE;
2170	return VINF_SUCCESS;
2171	}
2172	}
2173	else
2174	{
2175	if ((GCPtr & X86_PAGE_1G_BASE_MASK) == (pWalk->GCPtr & X86_PAGE_1G_BASE_MASK))
2176	{
2177	pWalk->GCPtr = GCPtr;
2178	pWalk->GCPhys += GUEST_PAGE_SIZE;
2179	return VINF_SUCCESS;
2180	}
2181	}
2182	}
2183	}
2184	/* Case we don't handle. Do full walk. */
2185	return pgmGstPtWalk(pVCpu, GCPtr, pWalk, pGstWalk);
2186	}
2187
2188
2189	/**
2190	* Modify page flags for a range of pages in the guest's tables
2191	*
2192	* The existing flags are ANDed with the fMask and ORed with the fFlags.
2193	*
2194	* @returns VBox status code.
2195	* @param pVCpu The cross context virtual CPU structure.
2196	* @param GCPtr Virtual address of the first page in the range.
2197	* @param cb Size (in bytes) of the range to apply the modification to.
2198	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
2199	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
2200	* Be very CAREFUL when ~'ing constants which could be 32-bit!
2201	*/
2202	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
2203	{
2204	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2205	VMCPU_ASSERT_EMT(pVCpu);
2206
2207	/*
2208	* Validate input.
2209	*/
2210	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
2211	Assert(cb);
2212
2213	LogFlow(("PGMGstModifyPage %RGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
2214
2215	/*
2216	* Adjust input.
2217	*/
2218	cb += GCPtr & GUEST_PAGE_OFFSET_MASK;
2219	cb = RT_ALIGN_Z(cb, GUEST_PAGE_SIZE);
2220	GCPtr &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
2221
2222	/*
2223	* Call worker.
2224	*/
2225	uintptr_t idx = pVCpu->pgm.s.idxGuestModeData;
2226	AssertReturn(idx < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
2227	AssertReturn(g_aPgmGuestModeData[idx].pfnModifyPage, VERR_PGM_MODE_IPE);
2228	int rc = g_aPgmGuestModeData[idx].pfnModifyPage(pVCpu, GCPtr, cb, fFlags, fMask);
2229
2230	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,GstModifyPage), a);
2231	return rc;
2232	}
2233
2234
2235	/**
2236	* Checks whether the given PAE PDPEs are potentially valid for the guest.
2237	*
2238	* @returns @c true if the PDPE is valid, @c false otherwise.
2239	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2240	* @param paPaePdpes The PAE PDPEs to validate.
2241	*
2242	* @remarks This function -only- checks the reserved bits in the PDPE entries.
2243	*/
2244	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2245	{
2246	Assert(paPaePdpes);
2247	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2248	{
2249	X86PDPE const PaePdpe = paPaePdpes[i];
2250	if ( !(PaePdpe.u & X86_PDPE_P)
2251	\|\| !(PaePdpe.u & pVCpu->pgm.s.fGstPaeMbzPdpeMask))
2252	{ /* likely */ }
2253	else
2254	return false;
2255	}
2256	return true;
2257	}
2258
2259
2260	/**
2261	* Performs the lazy mapping of the 32-bit guest PD.
2262	*
2263	* @returns VBox status code.
2264	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2265	* @param ppPd Where to return the pointer to the mapping. This is
2266	* always set.
2267	*/
2268	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd)
2269	{
2270	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2271	PGM_LOCK_VOID(pVM);
2272
2273	Assert(!pVCpu->pgm.s.CTX_SUFF(pGst32BitPd));
2274
2275	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2276	PPGMPAGE pPage;
2277	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2278	if (RT_SUCCESS(rc))
2279	{
2280	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPd);
2281	if (RT_SUCCESS(rc))
2282	{
2283	# ifdef IN_RING3
2284	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
2285	pVCpu->pgm.s.pGst32BitPdR3 = *ppPd;
2286	# else
2287	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR0PTR;
2288	pVCpu->pgm.s.pGst32BitPdR0 = *ppPd;
2289	# endif
2290	PGM_UNLOCK(pVM);
2291	return VINF_SUCCESS;
2292	}
2293	AssertRC(rc);
2294	}
2295	PGM_UNLOCK(pVM);
2296
2297	*ppPd = NULL;
2298	return rc;
2299	}
2300
2301
2302	/**
2303	* Performs the lazy mapping of the PAE guest PDPT.
2304	*
2305	* @returns VBox status code.
2306	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2307	* @param ppPdpt Where to return the pointer to the mapping. This is
2308	* always set.
2309	*/
2310	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt)
2311	{
2312	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt));
2313	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2314	PGM_LOCK_VOID(pVM);
2315
2316	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2317	PPGMPAGE pPage;
2318	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2319	if (RT_SUCCESS(rc))
2320	{
2321	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPdpt);
2322	if (RT_SUCCESS(rc))
2323	{
2324	# ifdef IN_RING3
2325	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
2326	pVCpu->pgm.s.pGstPaePdptR3 = *ppPdpt;
2327	# else
2328	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
2329	pVCpu->pgm.s.pGstPaePdptR0 = *ppPdpt;
2330	# endif
2331	PGM_UNLOCK(pVM);
2332	return VINF_SUCCESS;
2333	}
2334	AssertRC(rc);
2335	}
2336
2337	PGM_UNLOCK(pVM);
2338	*ppPdpt = NULL;
2339	return rc;
2340	}
2341
2342
2343	/**
2344	* Performs the lazy mapping / updating of a PAE guest PD.
2345	*
2346	* @returns Pointer to the mapping.
2347	* @returns VBox status code.
2348	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2349	* @param iPdpt Which PD entry to map (0..3).
2350	* @param ppPd Where to return the pointer to the mapping. This is
2351	* always set.
2352	*/
2353	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd)
2354	{
2355	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2356	PGM_LOCK_VOID(pVM);
2357
2358	PX86PDPT pGuestPDPT = pVCpu->pgm.s.CTX_SUFF(pGstPaePdpt);
2359	Assert(pGuestPDPT);
2360	Assert(pGuestPDPT->a[iPdpt].u & X86_PDPE_P);
2361	RTGCPHYS GCPhys = pGuestPDPT->a[iPdpt].u & X86_PDPE_PG_MASK;
2362	bool const fChanged = pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] != GCPhys;
2363
2364	PPGMPAGE pPage;
2365	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2366	if (RT_SUCCESS(rc))
2367	{
2368	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)ppPd);
2369	AssertRC(rc);
2370	if (RT_SUCCESS(rc))
2371	{
2372	# ifdef IN_RING3
2373	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2374	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = *ppPd;
2375	# else
2376	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2377	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = *ppPd;
2378	# endif
2379	if (fChanged)
2380	pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = GCPhys;
2381	PGM_UNLOCK(pVM);
2382	return VINF_SUCCESS;
2383	}
2384	}
2385
2386	/* Invalid page or some failure, invalidate the entry. */
2387	pVCpu->pgm.s.aGCPhysGstPaePDs[iPdpt] = NIL_RTGCPHYS;
2388	pVCpu->pgm.s.apGstPaePDsR3[iPdpt] = NIL_RTR3PTR;
2389	pVCpu->pgm.s.apGstPaePDsR0[iPdpt] = NIL_RTR0PTR;
2390
2391	PGM_UNLOCK(pVM);
2392	return rc;
2393	}
2394
2395
2396	/**
2397	* Performs the lazy mapping of the 32-bit guest PD.
2398	*
2399	* @returns VBox status code.
2400	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2401	* @param ppPml4 Where to return the pointer to the mapping. This will
2402	* always be set.
2403	*/
2404	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4)
2405	{
2406	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstAmd64Pml4));
2407	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2408	PGM_LOCK_VOID(pVM);
2409
2410	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, pVCpu->pgm.s.GCPhysCR3);
2411	PPGMPAGE pPage;
2412	int rc = pgmPhysGetPageEx(pVM, GCPhysCR3, &pPage);
2413	if (RT_SUCCESS(rc))
2414	{
2415	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysCR3, (void **)ppPml4);
2416	if (RT_SUCCESS(rc))
2417	{
2418	# ifdef IN_RING3
2419	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
2420	pVCpu->pgm.s.pGstAmd64Pml4R3 = *ppPml4;
2421	# else
2422	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
2423	pVCpu->pgm.s.pGstAmd64Pml4R0 = *ppPml4;
2424	# endif
2425	PGM_UNLOCK(pVM);
2426	return VINF_SUCCESS;
2427	}
2428	}
2429
2430	PGM_UNLOCK(pVM);
2431	*ppPml4 = NULL;
2432	return rc;
2433	}
2434
2435
2436	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2437	/**
2438	* Performs the lazy mapping of the guest PML4 table when using EPT paging.
2439	*
2440	* @returns VBox status code.
2441	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2442	* @param ppEptPml4 Where to return the pointer to the mapping. This will
2443	* always be set.
2444	*/
2445	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppEptPml4)
2446	{
2447	Assert(!pVCpu->pgm.s.CTX_SUFF(pGstEptPml4));
2448	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2449	PGM_LOCK_VOID(pVM);
2450
2451	RTGCPHYS const GCPhysEpt = pVCpu->pgm.s.uEptPtr & EPT_EPTP_PG_MASK;
2452	PPGMPAGE pPage;
2453	int rc = pgmPhysGetPageEx(pVM, GCPhysEpt, &pPage);
2454	if (RT_SUCCESS(rc))
2455	{
2456	rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhysEpt, (void **)ppEptPml4);
2457	if (RT_SUCCESS(rc))
2458	{
2459	# ifdef IN_RING3
2460	pVCpu->pgm.s.pGstEptPml4R0 = NIL_RTR0PTR;
2461	pVCpu->pgm.s.pGstEptPml4R3 = *ppEptPml4;
2462	# else
2463	pVCpu->pgm.s.pGstEptPml4R3 = NIL_RTR3PTR;
2464	pVCpu->pgm.s.pGstEptPml4R0 = *ppEptPml4;
2465	# endif
2466	PGM_UNLOCK(pVM);
2467	return VINF_SUCCESS;
2468	}
2469	}
2470
2471	PGM_UNLOCK(pVM);
2472	*ppEptPml4 = NULL;
2473	return rc;
2474	}
2475	#endif
2476
2477
2478	/**
2479	* Gets the current CR3 register value for the shadow memory context.
2480	* @returns CR3 value.
2481	* @param pVCpu The cross context virtual CPU structure.
2482	*/
2483	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu)
2484	{
2485	PPGMPOOLPAGE pPoolPage = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2486	AssertPtrReturn(pPoolPage, NIL_RTHCPHYS);
2487	return pPoolPage->Core.Key;
2488	}
2489
2490
2491	/**
2492	* Forces lazy remapping of the guest's PAE page-directory structures.
2493	*
2494	* @param pVCpu The cross context virtual CPU structure.
2495	*/
2496	static void pgmGstFlushPaePdpes(PVMCPU pVCpu)
2497	{
2498	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGCPhysGstPaePDs); i++)
2499	{
2500	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2501	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2502	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2503	}
2504	}
2505
2506
2507	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2508	/**
2509	* Performs second-level address translation for the given CR3 and updates the
2510	* nested-guest CR3 when successful.
2511	*
2512	* @returns VBox status code.
2513	* @param pVCpu The cross context virtual CPU structure.
2514	* @param uCr3 The masked nested-guest CR3 value.
2515	* @param pGCPhysCR3 Where to store the translated CR3.
2516	*
2517	* @warning This updates PGMCPU::GCPhysNstGstCR3 when the translation succeeds. Be
2518	* mindful of this in code that's hyper sensitive to the order of
2519	* operations.
2520	*/
2521	static int pgmGstSlatTranslateCr3(PVMCPUCC pVCpu, uint64_t uCr3, PRTGCPHYS pGCPhysCr3)
2522	{
2523	if (uCr3 != pVCpu->pgm.s.GCPhysNstGstCR3)
2524	{
2525	PGMPTWALK Walk;
2526	PGMPTWALKGST GstWalk;
2527	int const rc = pgmGstSlatWalk(pVCpu, uCr3, false /* fIsLinearAddrValid /, 0 / GCPtrNested */, &Walk, &GstWalk);
2528	if (RT_SUCCESS(rc))
2529	{
2530	/* Update nested-guest CR3. */
2531	pVCpu->pgm.s.GCPhysNstGstCR3 = uCr3;
2532
2533	/* Pass back the translated result. */
2534	*pGCPhysCr3 = Walk.GCPhys;
2535	return VINF_SUCCESS;
2536	}
2537
2538	/* Translation failed. */
2539	*pGCPhysCr3 = NIL_RTGCPHYS;
2540	return rc;
2541	}
2542
2543	/*
2544	* If the nested-guest CR3 has not changed, then the previously
2545	* translated CR3 result (i.e. GCPhysCR3) is passed back.
2546	*/
2547	*pGCPhysCr3 = pVCpu->pgm.s.GCPhysCR3;
2548	return VINF_SUCCESS;
2549	}
2550	#endif
2551
2552
2553	/**
2554	* Performs and schedules necessary updates following a CR3 load or reload.
2555	*
2556	* This will normally involve mapping the guest PD or nPDPT
2557	*
2558	* @returns VBox status code.
2559	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync. This can
2560	* safely be ignored and overridden since the FF will be set too then.
2561	* @param pVCpu The cross context virtual CPU structure.
2562	* @param cr3 The new cr3.
2563	* @param fGlobal Indicates whether this is a global flush or not.
2564	*/
2565	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal)
2566	{
2567	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2568	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2569
2570	VMCPU_ASSERT_EMT(pVCpu);
2571
2572	/*
2573	* Always flag the necessary updates; necessary for hardware acceleration
2574	*/
2575	/** @todo optimize this, it shouldn't always be necessary. */
2576	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2577	if (fGlobal)
2578	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2579
2580	/*
2581	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2582	*/
2583	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2584	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2585	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2586	if ( pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT
2587	&& PGMMODE_WITH_PAGING(pVCpu->pgm.s.enmGuestMode))
2588	{
2589	RTGCPHYS GCPhysOut;
2590	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2591	if (RT_SUCCESS(rc))
2592	GCPhysCR3 = GCPhysOut;
2593	else
2594	{
2595	/* CR3 SLAT translation failed but we try to pretend it
2596	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2597	AssertMsgFailed(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2598	int const rc2 = pgmGstUnmapCr3(pVCpu);
2599	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2600	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2601	return rc2;
2602	}
2603	}
2604	#endif
2605
2606	LogFlowFunc(("cr3=%RX64 old=%RX64 fGlobal=%d\n", cr3, GCPhysOldCR3, fGlobal));
2607	int rc = VINF_SUCCESS;
2608	if (GCPhysOldCR3 != GCPhysCR3)
2609	{
2610	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2611	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2612	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2613
2614	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2615	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2616	if (RT_LIKELY(rc == VINF_SUCCESS))
2617	{ }
2618	else
2619	{
2620	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc));
2621	Assert(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_PGM_SYNC_CR3));
2622	pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped) = false;
2623	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
2624	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2625	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_MAP_CR3;
2626	}
2627
2628	if (fGlobal)
2629	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3Global));
2630	else
2631	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBNewCR3));
2632	}
2633	else
2634	{
2635	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2636	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2637	if (pPool->cDirtyPages)
2638	{
2639	PGM_LOCK_VOID(pVM);
2640	pgmPoolResetDirtyPages(pVM);
2641	PGM_UNLOCK(pVM);
2642	}
2643	#endif
2644	if (fGlobal)
2645	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3Global));
2646	else
2647	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3));
2648
2649	/*
2650	* Flush PAE PDPTEs.
2651	*/
2652	if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2653	pgmGstFlushPaePdpes(pVCpu);
2654	}
2655
2656	IEMTlbInvalidateAll(pVCpu);
2657	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLB), a);
2658	return rc;
2659	}
2660
2661
2662	/**
2663	* Performs and schedules necessary updates following a CR3 load or reload when
2664	* using nested or extended paging.
2665	*
2666	* This API is an alternative to PGMFlushTLB that avoids actually flushing the
2667	* TLB and triggering a SyncCR3.
2668	*
2669	* This will normally involve mapping the guest PD or nPDPT
2670	*
2671	* @returns VBox status code.
2672	* @retval VINF_SUCCESS.
2673	* @retval VINF_PGM_SYNC_CR3 if monitoring requires a CR3 sync (not for nested
2674	* paging modes). This can safely be ignored and overridden since the
2675	* FF will be set too then.
2676	* @param pVCpu The cross context virtual CPU structure.
2677	* @param cr3 The new CR3.
2678	*/
2679	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3)
2680	{
2681	VMCPU_ASSERT_EMT(pVCpu);
2682
2683	/* We assume we're only called in nested paging mode. */
2684	Assert(pVCpu->CTX_SUFF(pVM)->pgm.s.fNestedPaging \|\| pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
2685
2686	/*
2687	* Remap the CR3 content and adjust the monitoring if CR3 was actually changed.
2688	*/
2689	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2690	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2691	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2692	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2693	{
2694	RTGCPHYS GCPhysOut;
2695	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2696	if (RT_SUCCESS(rc))
2697	GCPhysCR3 = GCPhysOut;
2698	else
2699	{
2700	/* CR3 SLAT translation failed but we try to pretend it
2701	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2702	Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", cr3, rc));
2703	int const rc2 = pgmGstUnmapCr3(pVCpu);
2704	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2705	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2706	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2707	return rc2;
2708	}
2709	}
2710	#endif
2711
2712	LogFlowFunc(("cr3=%RX64 old=%RX64\n", cr3, GCPhysOldCR3));
2713	int rc = VINF_SUCCESS;
2714	if (GCPhysOldCR3 != GCPhysCR3)
2715	{
2716	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2717	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2718	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2719
2720	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2721	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2722
2723	AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. / /* @todo this isn't true for the mac, but we need hw to test/fix this. */
2724	}
2725	/*
2726	* Flush PAE PDPTEs.
2727	*/
2728	else if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
2729	pgmGstFlushPaePdpes(pVCpu);
2730
2731	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2732	return rc;
2733	}
2734
2735
2736	/**
2737	* Synchronize the paging structures.
2738	*
2739	* This function is called in response to the VM_FF_PGM_SYNC_CR3 and
2740	* VM_FF_PGM_SYNC_CR3_NONGLOBAL. Those two force action flags are set
2741	* in several places, most importantly whenever the CR3 is loaded.
2742	*
2743	* @returns VBox status code. May return VINF_PGM_SYNC_CR3 in RC/R0.
2744	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
2745	* the VMM into guest context.
2746	* @param pVCpu The cross context virtual CPU structure.
2747	* @param cr0 Guest context CR0 register
2748	* @param cr3 Guest context CR3 register
2749	* @param cr4 Guest context CR4 register
2750	* @param fGlobal Including global page directories or not
2751	*/
2752	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2753	{
2754	int rc;
2755
2756	VMCPU_ASSERT_EMT(pVCpu);
2757
2758	/*
2759	* The pool may have pending stuff and even require a return to ring-3 to
2760	* clear the whole thing.
2761	*/
2762	rc = pgmPoolSyncCR3(pVCpu);
2763	if (rc != VINF_SUCCESS)
2764	return rc;
2765
2766	/*
2767	* We might be called when we shouldn't.
2768	*
2769	* The mode switching will ensure that the PD is resynced after every mode
2770	* switch. So, if we find ourselves here when in protected or real mode
2771	* we can safely clear the FF and return immediately.
2772	*/
2773	if (pVCpu->pgm.s.enmGuestMode <= PGMMODE_PROTECTED)
2774	{
2775	Assert((cr0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE));
2776	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2777	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2778	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2779	return VINF_SUCCESS;
2780	}
2781
2782	/* If global pages are not supported, then all flushes are global. */
2783	if (!(cr4 & X86_CR4_PGE))
2784	fGlobal = true;
2785	LogFlow(("PGMSyncCR3: cr0=%RX64 cr3=%RX64 cr4=%RX64 fGlobal=%d[%d,%d]\n", cr0, cr3, cr4, fGlobal,
2786	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)));
2787
2788	/*
2789	* Check if we need to finish an aborted MapCR3 call (see PGMFlushTLB).
2790	* This should be done before SyncCR3.
2791	*/
2792	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_MAP_CR3)
2793	{
2794	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_MAP_CR3;
2795
2796	RTGCPHYS const GCPhysOldCR3 = pVCpu->pgm.s.GCPhysCR3;
2797	RTGCPHYS GCPhysCR3 = pgmGetGuestMaskedCr3(pVCpu, cr3);
2798	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2799	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2800	{
2801	RTGCPHYS GCPhysOut;
2802	int rc2 = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2803	if (RT_SUCCESS(rc2))
2804	GCPhysCR3 = GCPhysOut;
2805	else
2806	{
2807	/* CR3 SLAT translation failed but we try to pretend it
2808	succeeded for the reasons mentioned in PGMHCChangeMode(). */
2809	AssertMsgFailed(("Failed to translate CR3 %#RX64. rc=%Rrc\n", cr3, rc2));
2810	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
2811	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
2812	return rc2;
2813	}
2814	}
2815	#endif
2816	Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
2817	if (GCPhysOldCR3 != GCPhysCR3)
2818	{
2819	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2820	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2821	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
2822	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
2823	rc = g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3);
2824	}
2825
2826	/* Make sure we check for pending pgm pool syncs as we clear VMCPU_FF_PGM_SYNC_CR3 later on! */
2827	if ( rc == VINF_PGM_SYNC_CR3
2828	\|\| (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2829	{
2830	Log(("PGMSyncCR3: pending pgm pool sync after MapCR3!\n"));
2831	#ifdef IN_RING3
2832	rc = pgmPoolSyncCR3(pVCpu);
2833	#else
2834	if (rc == VINF_PGM_SYNC_CR3)
2835	pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3;
2836	return VINF_PGM_SYNC_CR3;
2837	#endif
2838	}
2839	AssertRCReturn(rc, rc);
2840	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
2841	}
2842
2843	/*
2844	* Let the 'Bth' function do the work and we'll just keep track of the flags.
2845	*/
2846	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2847
2848	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
2849	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
2850	AssertReturn(g_aPgmBothModeData[idxBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
2851	rc = g_aPgmBothModeData[idxBth].pfnSyncCR3(pVCpu, cr0, cr3, cr4, fGlobal);
2852
2853	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
2854	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("rc=%Rrc\n", rc));
2855	if (rc == VINF_SUCCESS)
2856	{
2857	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2858	{
2859	/* Go back to ring 3 if a pgm pool sync is again pending. */
2860	return VINF_PGM_SYNC_CR3;
2861	}
2862
2863	if (!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS))
2864	{
2865	Assert(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL));
2866	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2867	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2868	}
2869	}
2870
2871	/*
2872	* Now flush the CR3 (guest context).
2873	*/
2874	if (rc == VINF_SUCCESS)
2875	PGM_INVL_VCPU_TLBS(pVCpu);
2876	return rc;
2877	}
2878
2879
2880	/**
2881	* Maps all the PAE PDPE entries.
2882	*
2883	* @returns VBox status code.
2884	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2885	* @param paPaePdpes The new PAE PDPE values.
2886	*
2887	* @remarks This function may be invoked during the process of changing the guest
2888	* paging mode to PAE, hence the guest state (CR0, CR4 etc.) may not
2889	* reflect PAE paging just yet.
2890	*/
2891	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes)
2892	{
2893	Assert(paPaePdpes);
2894	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
2895	{
2896	X86PDPE const PaePdpe = paPaePdpes[i];
2897
2898	/*
2899	* In some cases (e.g. in SVM with nested paging) the validation of the PAE PDPEs
2900	* are deferred.[1] Also, different situations require different handling of invalid
2901	* PDPE entries. Here we assume the caller has already validated or doesn't require
2902	* validation of the PDPEs.
2903	*
2904	* In the case of nested EPT (i.e. for nested-guests), the PAE PDPEs have been
2905	* validated by the VMX transition.
2906	*
2907	* [1] -- See AMD spec. 15.25.10 "Legacy PAE Mode".
2908	*/
2909	if ((PaePdpe.u & (pVCpu->pgm.s.fGstPaeMbzPdpeMask \| X86_PDPE_P)) == X86_PDPE_P)
2910	{
2911	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2912	RTHCPTR HCPtr;
2913
2914	RTGCPHYS GCPhys;
2915	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2916	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2917	{
2918	PGMPTWALK Walk;
2919	PGMPTWALKGST GstWalk;
2920	RTGCPHYS const GCPhysNested = PaePdpe.u & X86_PDPE_PG_MASK;
2921	int const rc = pgmGstSlatWalk(pVCpu, GCPhysNested, false /* fIsLinearAddrValid /, 0 / GCPtrNested */,
2922	&Walk, &GstWalk);
2923	if (RT_SUCCESS(rc))
2924	GCPhys = Walk.GCPhys;
2925	else
2926	{
2927	/*
2928	* Second-level address translation of the PAE PDPE has failed but we must -NOT-
2929	* abort and return a failure now. This is because we're called from a Mov CRx
2930	* instruction (or similar operation). Let's just pretend success but flag that
2931	* we need to map this PDPE lazily later.
2932	*
2933	* See Intel spec. 25.3 "Changes to instruction behavior in VMX non-root operation".
2934	* See Intel spec. 28.3.1 "EPT Overview".
2935	*/
2936	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2937	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2938	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2939	continue;
2940	}
2941	}
2942	else
2943	#endif
2944	{
2945	GCPhys = PGM_A20_APPLY(pVCpu, PaePdpe.u & X86_PDPE_PG_MASK);
2946	}
2947
2948	PGM_LOCK_VOID(pVM);
2949	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
2950	AssertReturnStmt(pPage, PGM_UNLOCK(pVM), VERR_PGM_INVALID_PDPE_ADDR);
2951	int const rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
2952	PGM_UNLOCK(pVM);
2953	if (RT_SUCCESS(rc))
2954	{
2955	#ifdef IN_RING3
2956	pVCpu->pgm.s.apGstPaePDsR3[i] = (PX86PDPAE)HCPtr;
2957	pVCpu->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
2958	#else
2959	pVCpu->pgm.s.apGstPaePDsR3[i] = NIL_RTR3PTR;
2960	pVCpu->pgm.s.apGstPaePDsR0[i] = (PX86PDPAE)HCPtr;
2961	#endif
2962	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
2963	continue;
2964	}
2965	AssertMsgFailed(("PGMPhysMapPaePdpes: rc2=%d GCPhys=%RGp i=%d\n", rc, GCPhys, i));
2966	}
2967	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
2968	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
2969	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
2970	}
2971	return VINF_SUCCESS;
2972	}
2973
2974
2975	/**
2976	* Validates and maps the PDPT and PAE PDPEs referenced by the given CR3.
2977	*
2978	* @returns VBox status code.
2979	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2980	* @param cr3 The guest CR3 value.
2981	*
2982	* @remarks This function may be invoked during the process of changing the guest
2983	* paging mode to PAE but the guest state (CR0, CR4 etc.) may not reflect
2984	* PAE paging just yet.
2985	*/
2986	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3)
2987	{
2988	/*
2989	* Read the page-directory-pointer table (PDPT) at CR3.
2990	*/
2991	RTGCPHYS GCPhysCR3 = (cr3 & X86_CR3_PAE_PAGE_MASK);
2992	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhysCR3);
2993
2994	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2995	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
2996	{
2997	RTGCPHYS GCPhysOut;
2998	int const rc = pgmGstSlatTranslateCr3(pVCpu, GCPhysCR3, &GCPhysOut);
2999	if (RT_SUCCESS(rc))
3000	GCPhysCR3 = GCPhysOut;
3001	else
3002	{
3003	Log(("Failed to load CR3 at %#RX64. rc=%Rrc\n", GCPhysCR3, rc));
3004	return rc;
3005	}
3006	}
3007	#endif
3008
3009	RTHCPTR HCPtrGuestCr3;
3010	int rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCr3);
3011	if (RT_SUCCESS(rc))
3012	{
3013	/*
3014	* Validate the page-directory-pointer table entries (PDPE).
3015	*/
3016	X86PDPE aPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
3017	memcpy(&aPaePdpes[0], HCPtrGuestCr3, sizeof(aPaePdpes));
3018	if (PGMGstArePaePdpesValid(pVCpu, &aPaePdpes[0]))
3019	{
3020	/*
3021	* Map the PDPT.
3022	* We deliberately don't update PGM's GCPhysCR3 here as it's expected
3023	* that PGMFlushTLB will be called soon and only a change to CR3 then
3024	* will cause the shadow page tables to be updated.
3025	*/
3026	#ifdef IN_RING3
3027	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCr3;
3028	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
3029	#else
3030	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
3031	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCr3;
3032	#endif
3033
3034	/*
3035	* Update CPUM and map the 4 PAE PDPEs.
3036	*/
3037	CPUMSetGuestPaePdpes(pVCpu, &aPaePdpes[0]);
3038	rc = PGMGstMapPaePdpes(pVCpu, &aPaePdpes[0]);
3039	if (RT_SUCCESS(rc))
3040	{
3041	#ifdef IN_RING3
3042	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
3043	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
3044	#else
3045	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
3046	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
3047	#endif
3048	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
3049	}
3050	}
3051	else
3052	rc = VERR_PGM_PAE_PDPE_RSVD;
3053	}
3054	return rc;
3055	}
3056
3057
3058	/**
3059	* Called whenever CR0 or CR4 in a way which may affect the paging mode.
3060	*
3061	* @returns VBox status code, with the following informational code for
3062	* VM scheduling.
3063	* @retval VINF_SUCCESS if the was no change, or it was successfully dealt with.
3064	* @retval VINF_EM_SUSPEND or VINF_EM_OFF on a fatal runtime error. (R3 only)
3065	*
3066	* @param pVCpu The cross context virtual CPU structure.
3067	* @param cr0 The new cr0.
3068	* @param cr4 The new cr4.
3069	* @param efer The new extended feature enable register.
3070	* @param fForce Whether to force a mode change.
3071	*/
3072	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce)
3073	{
3074	VMCPU_ASSERT_EMT(pVCpu);
3075
3076	/*
3077	* Calc the new guest mode.
3078	*
3079	* Note! We check PG before PE and without requiring PE because of the
3080	* special AMD-V paged real mode (APM vol 2, rev 3.28, 15.9).
3081	*/
3082	PGMMODE enmGuestMode;
3083	if (cr0 & X86_CR0_PG)
3084	{
3085	if (!(cr4 & X86_CR4_PAE))
3086	{
3087	bool const fPse = !!(cr4 & X86_CR4_PSE);
3088	if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
3089	Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
3090	pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
3091	enmGuestMode = PGMMODE_32_BIT;
3092	}
3093	else if (!(efer & MSR_K6_EFER_LME))
3094	{
3095	if (!(efer & MSR_K6_EFER_NXE))
3096	enmGuestMode = PGMMODE_PAE;
3097	else
3098	enmGuestMode = PGMMODE_PAE_NX;
3099	}
3100	else
3101	{
3102	if (!(efer & MSR_K6_EFER_NXE))
3103	enmGuestMode = PGMMODE_AMD64;
3104	else
3105	enmGuestMode = PGMMODE_AMD64_NX;
3106	}
3107	}
3108	else if (!(cr0 & X86_CR0_PE))
3109	enmGuestMode = PGMMODE_REAL;
3110	else
3111	enmGuestMode = PGMMODE_PROTECTED;
3112
3113	/*
3114	* Did it change?
3115	*/
3116	if ( !fForce
3117	&& pVCpu->pgm.s.enmGuestMode == enmGuestMode)
3118	return VINF_SUCCESS;
3119
3120	/* Flush the TLB */
3121	PGM_INVL_VCPU_TLBS(pVCpu);
3122	return PGMHCChangeMode(pVCpu->CTX_SUFF(pVM), pVCpu, enmGuestMode, fForce);
3123	}
3124
3125
3126	/**
3127	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3128	*
3129	* @returns PGM_TYPE_*.
3130	* @param pgmMode The mode value to convert.
3131	*/
3132	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3133	{
3134	switch (pgmMode)
3135	{
3136	case PGMMODE_REAL: return PGM_TYPE_REAL;
3137	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3138	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3139	case PGMMODE_PAE:
3140	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3141	case PGMMODE_AMD64:
3142	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3143	case PGMMODE_NESTED_32BIT: return PGM_TYPE_NESTED_32BIT;
3144	case PGMMODE_NESTED_PAE: return PGM_TYPE_NESTED_PAE;
3145	case PGMMODE_NESTED_AMD64: return PGM_TYPE_NESTED_AMD64;
3146	case PGMMODE_EPT: return PGM_TYPE_EPT;
3147	case PGMMODE_NONE: return PGM_TYPE_NONE;
3148	default:
3149	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3150	}
3151	}
3152
3153
3154	/**
3155	* Calculates the shadow paging mode.
3156	*
3157	* @returns The shadow paging mode.
3158	* @param pVM The cross context VM structure.
3159	* @param enmGuestMode The guest mode.
3160	* @param enmHostMode The host mode.
3161	* @param enmShadowMode The current shadow mode.
3162	*/
3163	static PGMMODE pgmCalcShadowMode(PVMCC pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode)
3164	{
3165	switch (enmGuestMode)
3166	{
3167	case PGMMODE_REAL:
3168	case PGMMODE_PROTECTED:
3169	switch (enmHostMode)
3170	{
3171	case SUPPAGINGMODE_32_BIT:
3172	case SUPPAGINGMODE_32_BIT_GLOBAL:
3173	enmShadowMode = PGMMODE_32_BIT;
3174	break;
3175
3176	case SUPPAGINGMODE_PAE:
3177	case SUPPAGINGMODE_PAE_NX:
3178	case SUPPAGINGMODE_PAE_GLOBAL:
3179	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3180	enmShadowMode = PGMMODE_PAE;
3181	break;
3182
3183	case SUPPAGINGMODE_AMD64:
3184	case SUPPAGINGMODE_AMD64_GLOBAL:
3185	case SUPPAGINGMODE_AMD64_NX:
3186	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3187	enmShadowMode = PGMMODE_PAE;
3188	break;
3189
3190	default:
3191	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3192	}
3193	break;
3194
3195	case PGMMODE_32_BIT:
3196	switch (enmHostMode)
3197	{
3198	case SUPPAGINGMODE_32_BIT:
3199	case SUPPAGINGMODE_32_BIT_GLOBAL:
3200	enmShadowMode = PGMMODE_32_BIT;
3201	break;
3202
3203	case SUPPAGINGMODE_PAE:
3204	case SUPPAGINGMODE_PAE_NX:
3205	case SUPPAGINGMODE_PAE_GLOBAL:
3206	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3207	enmShadowMode = PGMMODE_PAE;
3208	break;
3209
3210	case SUPPAGINGMODE_AMD64:
3211	case SUPPAGINGMODE_AMD64_GLOBAL:
3212	case SUPPAGINGMODE_AMD64_NX:
3213	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3214	enmShadowMode = PGMMODE_PAE;
3215	break;
3216
3217	default:
3218	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3219	}
3220	break;
3221
3222	case PGMMODE_PAE:
3223	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3224	switch (enmHostMode)
3225	{
3226	case SUPPAGINGMODE_32_BIT:
3227	case SUPPAGINGMODE_32_BIT_GLOBAL:
3228	enmShadowMode = PGMMODE_PAE;
3229	break;
3230
3231	case SUPPAGINGMODE_PAE:
3232	case SUPPAGINGMODE_PAE_NX:
3233	case SUPPAGINGMODE_PAE_GLOBAL:
3234	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3235	enmShadowMode = PGMMODE_PAE;
3236	break;
3237
3238	case SUPPAGINGMODE_AMD64:
3239	case SUPPAGINGMODE_AMD64_GLOBAL:
3240	case SUPPAGINGMODE_AMD64_NX:
3241	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3242	enmShadowMode = PGMMODE_PAE;
3243	break;
3244
3245	default:
3246	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3247	}
3248	break;
3249
3250	case PGMMODE_AMD64:
3251	case PGMMODE_AMD64_NX:
3252	switch (enmHostMode)
3253	{
3254	case SUPPAGINGMODE_32_BIT:
3255	case SUPPAGINGMODE_32_BIT_GLOBAL:
3256	enmShadowMode = PGMMODE_AMD64;
3257	break;
3258
3259	case SUPPAGINGMODE_PAE:
3260	case SUPPAGINGMODE_PAE_NX:
3261	case SUPPAGINGMODE_PAE_GLOBAL:
3262	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3263	enmShadowMode = PGMMODE_AMD64;
3264	break;
3265
3266	case SUPPAGINGMODE_AMD64:
3267	case SUPPAGINGMODE_AMD64_GLOBAL:
3268	case SUPPAGINGMODE_AMD64_NX:
3269	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3270	enmShadowMode = PGMMODE_AMD64;
3271	break;
3272
3273	default:
3274	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", enmHostMode), PGMMODE_INVALID);
3275	}
3276	break;
3277
3278	default:
3279	AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), PGMMODE_INVALID);
3280	}
3281
3282	/*
3283	* Override the shadow mode when NEM, IEM or nested paging is active.
3284	*/
3285	if (!VM_IS_HM_ENABLED(pVM))
3286	{
3287	Assert(VM_IS_NEM_ENABLED(pVM) \|\| VM_IS_EXEC_ENGINE_IEM(pVM));
3288	pVM->pgm.s.fNestedPaging = true;
3289	enmShadowMode = PGMMODE_NONE;
3290	}
3291	else
3292	{
3293	bool fNestedPaging = HMIsNestedPagingActive(pVM);
3294	pVM->pgm.s.fNestedPaging = fNestedPaging;
3295	if (fNestedPaging)
3296	{
3297	if (HMIsVmxActive(pVM))
3298	enmShadowMode = PGMMODE_EPT;
3299	else
3300	{
3301	/* The nested SVM paging depends on the host one. */
3302	Assert(HMIsSvmActive(pVM));
3303	if ( enmGuestMode == PGMMODE_AMD64
3304	\|\| enmGuestMode == PGMMODE_AMD64_NX)
3305	enmShadowMode = PGMMODE_NESTED_AMD64;
3306	else
3307	switch (pVM->pgm.s.enmHostMode)
3308	{
3309	case SUPPAGINGMODE_32_BIT:
3310	case SUPPAGINGMODE_32_BIT_GLOBAL:
3311	enmShadowMode = PGMMODE_NESTED_32BIT;
3312	break;
3313
3314	case SUPPAGINGMODE_PAE:
3315	case SUPPAGINGMODE_PAE_GLOBAL:
3316	case SUPPAGINGMODE_PAE_NX:
3317	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3318	enmShadowMode = PGMMODE_NESTED_PAE;
3319	break;
3320
3321	case SUPPAGINGMODE_AMD64:
3322	case SUPPAGINGMODE_AMD64_GLOBAL:
3323	case SUPPAGINGMODE_AMD64_NX:
3324	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3325	enmShadowMode = PGMMODE_NESTED_AMD64;
3326	break;
3327
3328	default:
3329	AssertLogRelMsgFailedReturn(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3330	}
3331	}
3332	}
3333	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3334	else
3335	{
3336	/* Nested paging is a requirement for nested VT-x. */
3337	AssertLogRelMsgReturn(enmGuestMode != PGMMODE_EPT, ("enmHostMode=%d\n", pVM->pgm.s.enmHostMode), PGMMODE_INVALID);
3338	}
3339	#endif
3340	}
3341
3342	return enmShadowMode;
3343	}
3344
3345
3346	/**
3347	* Performs the actual mode change.
3348	* This is called by PGMChangeMode and pgmR3InitPaging().
3349	*
3350	* @returns VBox status code. May suspend or power off the VM on error, but this
3351	* will trigger using FFs and not informational status codes.
3352	*
3353	* @param pVM The cross context VM structure.
3354	* @param pVCpu The cross context virtual CPU structure.
3355	* @param enmGuestMode The new guest mode. This is assumed to be different from
3356	* the current mode.
3357	* @param fForce Whether to force a shadow paging mode change.
3358	*/
3359	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce)
3360	{
3361	Log(("PGMHCChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3362	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3363
3364	/*
3365	* Calc the shadow mode and switcher.
3366	*/
3367	PGMMODE const enmShadowMode = pgmCalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode);
3368	bool const fShadowModeChanged = enmShadowMode != pVCpu->pgm.s.enmShadowMode \|\| fForce;
3369
3370	/*
3371	* Exit old mode(s).
3372	*/
3373	/* shadow */
3374	if (fShadowModeChanged)
3375	{
3376	LogFlow(("PGMHCChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3377	uintptr_t idxOldShw = pVCpu->pgm.s.idxShadowModeData;
3378	if ( idxOldShw < RT_ELEMENTS(g_aPgmShadowModeData)
3379	&& g_aPgmShadowModeData[idxOldShw].pfnExit)
3380	{
3381	int rc = g_aPgmShadowModeData[idxOldShw].pfnExit(pVCpu);
3382	AssertMsgRCReturn(rc, ("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc), rc);
3383	}
3384	}
3385	else
3386	LogFlow(("PGMHCChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3387
3388	/* guest */
3389	uintptr_t const idxOldGst = pVCpu->pgm.s.idxGuestModeData;
3390	if ( idxOldGst < RT_ELEMENTS(g_aPgmGuestModeData)
3391	&& g_aPgmGuestModeData[idxOldGst].pfnExit)
3392	{
3393	int rc = g_aPgmGuestModeData[idxOldGst].pfnExit(pVCpu);
3394	AssertMsgReturn(RT_SUCCESS(rc), ("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc), rc);
3395	}
3396	pVCpu->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
3397	pVCpu->pgm.s.GCPhysNstGstCR3 = NIL_RTGCPHYS;
3398	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
3399	Assert(!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped));
3400
3401	/*
3402	* Change the paging mode data indexes.
3403	*/
3404	uintptr_t idxNewGst = pVCpu->pgm.s.idxGuestModeData = pgmModeToType(enmGuestMode);
3405	AssertReturn(idxNewGst < RT_ELEMENTS(g_aPgmGuestModeData), VERR_PGM_MODE_IPE);
3406	AssertReturn(g_aPgmGuestModeData[idxNewGst].uType == idxNewGst, VERR_PGM_MODE_IPE);
3407	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnGetPage, VERR_PGM_MODE_IPE);
3408	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnModifyPage, VERR_PGM_MODE_IPE);
3409	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnExit, VERR_PGM_MODE_IPE);
3410	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnEnter, VERR_PGM_MODE_IPE);
3411	#ifdef IN_RING3
3412	AssertPtrReturn(g_aPgmGuestModeData[idxNewGst].pfnRelocate, VERR_PGM_MODE_IPE);
3413	#endif
3414
3415	uintptr_t const idxNewShw = pVCpu->pgm.s.idxShadowModeData = pgmModeToType(enmShadowMode);
3416	AssertReturn(idxNewShw < RT_ELEMENTS(g_aPgmShadowModeData), VERR_PGM_MODE_IPE);
3417	AssertReturn(g_aPgmShadowModeData[idxNewShw].uType == idxNewShw, VERR_PGM_MODE_IPE);
3418	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnGetPage, VERR_PGM_MODE_IPE);
3419	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnModifyPage, VERR_PGM_MODE_IPE);
3420	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnExit, VERR_PGM_MODE_IPE);
3421	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnEnter, VERR_PGM_MODE_IPE);
3422	#ifdef IN_RING3
3423	AssertPtrReturn(g_aPgmShadowModeData[idxNewShw].pfnRelocate, VERR_PGM_MODE_IPE);
3424	#endif
3425
3426	uintptr_t const idxNewBth = pVCpu->pgm.s.idxBothModeData = (idxNewShw - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END + idxNewGst;
3427	AssertReturn(g_aPgmBothModeData[idxNewBth].uShwType == idxNewShw, VERR_PGM_MODE_IPE);
3428	AssertReturn(g_aPgmBothModeData[idxNewBth].uGstType == idxNewGst, VERR_PGM_MODE_IPE);
3429	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnInvalidatePage, VERR_PGM_MODE_IPE);
3430	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnSyncCR3, VERR_PGM_MODE_IPE);
3431	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnPrefetchPage, VERR_PGM_MODE_IPE);
3432	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnVerifyAccessSyncPage, VERR_PGM_MODE_IPE);
3433	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnMapCR3, VERR_PGM_MODE_IPE);
3434	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
3435	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnEnter, VERR_PGM_MODE_IPE);
3436	#ifdef VBOX_STRICT
3437	AssertPtrReturn(g_aPgmBothModeData[idxNewBth].pfnAssertCR3, VERR_PGM_MODE_IPE);
3438	#endif
3439
3440	/*
3441	* Determine SLAT mode -before- entering the new shadow mode!
3442	*/
3443	pVCpu->pgm.s.enmGuestSlatMode = !CPUMIsGuestVmxEptPagingEnabled(pVCpu) ? PGMSLAT_DIRECT : PGMSLAT_EPT;
3444
3445	/*
3446	* Enter new shadow mode (if changed).
3447	*/
3448	if (fShadowModeChanged)
3449	{
3450	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3451	int rc = g_aPgmShadowModeData[idxNewShw].pfnEnter(pVCpu);
3452	AssertLogRelMsgRCReturnStmt(rc, ("Entering enmShadowMode=%s failed: %Rrc\n", PGMGetModeName(enmShadowMode), rc),
3453	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID, rc);
3454	}
3455
3456	/*
3457	* Always flag the necessary updates
3458	*/
3459	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3460
3461	/*
3462	* Enter the new guest and shadow+guest modes.
3463	*/
3464	/* Calc the new CR3 value. */
3465	RTGCPHYS GCPhysCR3;
3466	switch (enmGuestMode)
3467	{
3468	case PGMMODE_REAL:
3469	case PGMMODE_PROTECTED:
3470	GCPhysCR3 = NIL_RTGCPHYS;
3471	break;
3472
3473	case PGMMODE_32_BIT:
3474	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3475	break;
3476
3477	case PGMMODE_PAE_NX:
3478	case PGMMODE_PAE:
3479	if (!pVM->cpum.ro.GuestFeatures.fPae)
3480	#ifdef IN_RING3 /** @todo r=bird: wrong place, probably hasn't really worked for a while. */
3481	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3482	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (System/Processor)"));
3483	#else
3484	AssertLogRelMsgFailedReturn(("enmGuestMode=%s - Try enable PAE for the guest!\n", PGMGetModeName(enmGuestMode)), VERR_PGM_MODE_IPE);
3485
3486	#endif
3487	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3488	break;
3489
3490	#ifdef VBOX_WITH_64_BITS_GUESTS
3491	case PGMMODE_AMD64_NX:
3492	case PGMMODE_AMD64:
3493	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_AMD64_PAGE_MASK;
3494	break;
3495	#endif
3496	default:
3497	AssertLogRelMsgFailedReturn(("enmGuestMode=%d\n", enmGuestMode), VERR_PGM_MODE_IPE);
3498	}
3499
3500	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3501	/*
3502	* If a nested-guest is using EPT paging:
3503	* - Update the second-level address translation (SLAT) mode.
3504	* - Indicate that the CR3 is nested-guest physical address.
3505	*/
3506	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
3507	{
3508	if (PGMMODE_WITH_PAGING(enmGuestMode))
3509	{
3510	/*
3511	* Translate CR3 to its guest-physical address.
3512	* We don't use pgmGstSlatTranslateCr3() here as we want to update GCPhysNstGstCR3 -after-
3513	* switching modes to keep it consistent with how GCPhysCR3 is updated.
3514	*/
3515	PGMPTWALK Walk;
3516	PGMPTWALKGST GstWalk;
3517	int const rc = pgmGstSlatWalk(pVCpu, GCPhysCR3, false /* fIsLinearAddrValid /, 0 / GCPtrNested */, &Walk,
3518	&GstWalk);
3519	if (RT_SUCCESS(rc))
3520	{ /* likely */ }
3521	else
3522	{
3523	/*
3524	* SLAT failed but we avoid reporting this to the caller because the caller
3525	* is not supposed to fail. The only time the caller needs to indicate a
3526	* failure to software is when PAE paging is used by the nested-guest, but
3527	* we handle the PAE case separately (e.g., see VMX transition in IEM).
3528	* In all other cases, the failure will be indicated when CR3 tries to be
3529	* translated on the next linear-address memory access.
3530	* See Intel spec. 27.2.1 "EPT Overview".
3531	*/
3532	Log(("SLAT failed for CR3 %#RX64 rc=%Rrc\n", GCPhysCR3, rc));
3533
3534	/* Trying to coax PGM to succeed for the time being... */
3535	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3536	pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3537	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3538	HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3539	return VINF_SUCCESS;
3540	}
3541	pVCpu->pgm.s.GCPhysNstGstCR3 = GCPhysCR3;
3542	GCPhysCR3 = Walk.GCPhys & X86_CR3_EPT_PAGE_MASK;
3543	}
3544	}
3545	else
3546	Assert(pVCpu->pgm.s.GCPhysNstGstCR3 == NIL_RTGCPHYS);
3547	#endif
3548
3549	/*
3550	* Enter the new guest mode.
3551	*/
3552	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3553	int rc = g_aPgmGuestModeData[idxNewGst].pfnEnter(pVCpu, GCPhysCR3);
3554	int rc2 = g_aPgmBothModeData[idxNewBth].pfnEnter(pVCpu, GCPhysCR3);
3555
3556	/* Set the new guest CR3 (and nested-guest CR3). */
3557	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3558
3559	/* status codes. */
3560	AssertRC(rc);
3561	AssertRC(rc2);
3562	if (RT_SUCCESS(rc))
3563	{
3564	rc = rc2;
3565	if (RT_SUCCESS(rc)) /* no informational status codes. */
3566	rc = VINF_SUCCESS;
3567	}
3568
3569	/*
3570	* Notify HM.
3571	*/
3572	HMHCChangedPagingMode(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3573	return rc;
3574	}
3575
3576
3577	/**
3578	* Called by CPUM or REM when CR0.WP changes to 1.
3579	*
3580	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3581	* @thread EMT
3582	*/
3583	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu)
3584	{
3585	/*
3586	* Netware WP0+RO+US hack cleanup when WP0 -> WP1.
3587	*
3588	* Use the counter to judge whether there might be pool pages with active
3589	* hacks in them. If there are, we will be running the risk of messing up
3590	* the guest by allowing it to write to read-only pages. Thus, we have to
3591	* clear the page pool ASAP if there is the slightest chance.
3592	*/
3593	if (pVCpu->pgm.s.cNetwareWp0Hacks > 0)
3594	{
3595	Assert(pVCpu->CTX_SUFF(pVM)->cCpus == 1);
3596
3597	Log(("PGMCr0WpEnabled: %llu WP0 hacks active - clearing page pool\n", pVCpu->pgm.s.cNetwareWp0Hacks));
3598	pVCpu->pgm.s.cNetwareWp0Hacks = 0;
3599	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3600	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3601	}
3602	}
3603
3604
3605	/**
3606	* Gets the current guest paging mode.
3607	*
3608	* If you just need the CPU mode (real/protected/long), use CPUMGetGuestMode().
3609	*
3610	* @returns The current paging mode.
3611	* @param pVCpu The cross context virtual CPU structure.
3612	*/
3613	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu)
3614	{
3615	return pVCpu->pgm.s.enmGuestMode;
3616	}
3617
3618
3619	/**
3620	* Gets the current shadow paging mode.
3621	*
3622	* @returns The current paging mode.
3623	* @param pVCpu The cross context virtual CPU structure.
3624	*/
3625	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu)
3626	{
3627	return pVCpu->pgm.s.enmShadowMode;
3628	}
3629
3630
3631	/**
3632	* Gets the current host paging mode.
3633	*
3634	* @returns The current paging mode.
3635	* @param pVM The cross context VM structure.
3636	*/
3637	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM)
3638	{
3639	switch (pVM->pgm.s.enmHostMode)
3640	{
3641	case SUPPAGINGMODE_32_BIT:
3642	case SUPPAGINGMODE_32_BIT_GLOBAL:
3643	return PGMMODE_32_BIT;
3644
3645	case SUPPAGINGMODE_PAE:
3646	case SUPPAGINGMODE_PAE_GLOBAL:
3647	return PGMMODE_PAE;
3648
3649	case SUPPAGINGMODE_PAE_NX:
3650	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3651	return PGMMODE_PAE_NX;
3652
3653	case SUPPAGINGMODE_AMD64:
3654	case SUPPAGINGMODE_AMD64_GLOBAL:
3655	return PGMMODE_AMD64;
3656
3657	case SUPPAGINGMODE_AMD64_NX:
3658	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3659	return PGMMODE_AMD64_NX;
3660
3661	default: AssertMsgFailed(("enmHostMode=%d\n", pVM->pgm.s.enmHostMode)); break;
3662	}
3663
3664	return PGMMODE_INVALID;
3665	}
3666
3667
3668	/**
3669	* Get mode name.
3670	*
3671	* @returns read-only name string.
3672	* @param enmMode The mode which name is desired.
3673	*/
3674	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode)
3675	{
3676	switch (enmMode)
3677	{
3678	case PGMMODE_REAL: return "Real";
3679	case PGMMODE_PROTECTED: return "Protected";
3680	case PGMMODE_32_BIT: return "32-bit";
3681	case PGMMODE_PAE: return "PAE";
3682	case PGMMODE_PAE_NX: return "PAE+NX";
3683	case PGMMODE_AMD64: return "AMD64";
3684	case PGMMODE_AMD64_NX: return "AMD64+NX";
3685	case PGMMODE_NESTED_32BIT: return "Nested-32";
3686	case PGMMODE_NESTED_PAE: return "Nested-PAE";
3687	case PGMMODE_NESTED_AMD64: return "Nested-AMD64";
3688	case PGMMODE_EPT: return "EPT";
3689	case PGMMODE_NONE: return "None";
3690	default: return "unknown mode value";
3691	}
3692	}
3693
3694
3695	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3696	/**
3697	* Gets the SLAT mode name.
3698	*
3699	* @returns The read-only SLAT mode descriptive string.
3700	* @param enmSlatMode The SLAT mode value.
3701	*/
3702	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode)
3703	{
3704	switch (enmSlatMode)
3705	{
3706	case PGMSLAT_DIRECT: return "Direct";
3707	case PGMSLAT_EPT: return "EPT";
3708	case PGMSLAT_32BIT: return "32-bit";
3709	case PGMSLAT_PAE: return "PAE";
3710	case PGMSLAT_AMD64: return "AMD64";
3711	default: return "Unknown";
3712	}
3713	}
3714	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
3715
3716
3717	/**
3718	* Gets the physical address represented in the guest CR3 as PGM sees it.
3719	*
3720	* This is mainly for logging and debugging.
3721	*
3722	* @returns PGM's guest CR3 value.
3723	* @param pVCpu The cross context virtual CPU structure.
3724	*/
3725	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu)
3726	{
3727	return pVCpu->pgm.s.GCPhysCR3;
3728	}
3729
3730
3731
3732	/**
3733	* Notification from CPUM that the EFER.NXE bit has changed.
3734	*
3735	* @param pVCpu The cross context virtual CPU structure of the CPU for
3736	* which EFER changed.
3737	* @param fNxe The new NXE state.
3738	*/
3739	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe)
3740	{
3741	/** @todo VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu); */
3742	Log(("PGMNotifyNxeChanged: fNxe=%RTbool\n", fNxe));
3743
3744	pVCpu->pgm.s.fNoExecuteEnabled = fNxe;
3745	if (fNxe)
3746	{
3747	/pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A /
3748	pVCpu->pgm.s.fGstPaeMbzPteMask &= ~X86_PTE_PAE_NX;
3749	pVCpu->pgm.s.fGstPaeMbzPdeMask &= ~X86_PDE_PAE_NX;
3750	pVCpu->pgm.s.fGstPaeMbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3751	/pVCpu->pgm.s.fGstPaeMbzPdpeMask - N/A /
3752	pVCpu->pgm.s.fGstAmd64MbzPteMask &= ~X86_PTE_PAE_NX;
3753	pVCpu->pgm.s.fGstAmd64MbzPdeMask &= ~X86_PDE_PAE_NX;
3754	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask &= ~X86_PDE2M_PAE_NX;
3755	pVCpu->pgm.s.fGstAmd64MbzPdpeMask &= ~X86_PDPE_LM_NX;
3756	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask &= ~X86_PDPE_LM_NX;
3757	pVCpu->pgm.s.fGstAmd64MbzPml4eMask &= ~X86_PML4E_NX;
3758
3759	pVCpu->pgm.s.fGst64ShadowedPteMask \|= X86_PTE_PAE_NX;
3760	pVCpu->pgm.s.fGst64ShadowedPdeMask \|= X86_PDE_PAE_NX;
3761	pVCpu->pgm.s.fGst64ShadowedBigPdeMask \|= X86_PDE2M_PAE_NX;
3762	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask \|= X86_PDE2M_PAE_NX;
3763	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask \|= X86_PDPE_LM_NX;
3764	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask \|= X86_PML4E_NX;
3765	}
3766	else
3767	{
3768	/pVCpu->pgm.s.fGst32BitMbzBigPdeMask - N/A /
3769	pVCpu->pgm.s.fGstPaeMbzPteMask \|= X86_PTE_PAE_NX;
3770	pVCpu->pgm.s.fGstPaeMbzPdeMask \|= X86_PDE_PAE_NX;
3771	pVCpu->pgm.s.fGstPaeMbzBigPdeMask \|= X86_PDE2M_PAE_NX;
3772	/pVCpu->pgm.s.fGstPaeMbzPdpeMask -N/A /
3773	pVCpu->pgm.s.fGstAmd64MbzPteMask \|= X86_PTE_PAE_NX;
3774	pVCpu->pgm.s.fGstAmd64MbzPdeMask \|= X86_PDE_PAE_NX;
3775	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask \|= X86_PDE2M_PAE_NX;
3776	pVCpu->pgm.s.fGstAmd64MbzPdpeMask \|= X86_PDPE_LM_NX;
3777	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask \|= X86_PDPE_LM_NX;
3778	pVCpu->pgm.s.fGstAmd64MbzPml4eMask \|= X86_PML4E_NX;
3779
3780	pVCpu->pgm.s.fGst64ShadowedPteMask &= ~X86_PTE_PAE_NX;
3781	pVCpu->pgm.s.fGst64ShadowedPdeMask &= ~X86_PDE_PAE_NX;
3782	pVCpu->pgm.s.fGst64ShadowedBigPdeMask &= ~X86_PDE2M_PAE_NX;
3783	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask &= ~X86_PDE2M_PAE_NX;
3784	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask &= ~X86_PDPE_LM_NX;
3785	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask &= ~X86_PML4E_NX;
3786	}
3787	}
3788
3789
3790	/**
3791	* Check if any pgm pool pages are marked dirty (not monitored)
3792	*
3793	* @returns bool locked/not locked
3794	* @param pVM The cross context VM structure.
3795	*/
3796	VMMDECL(bool) PGMHasDirtyPages(PVM pVM)
3797	{
3798	return pVM->pgm.s.CTX_SUFF(pPool)->cDirtyPages != 0;
3799	}
3800
3801
3802	/**
3803	* Check if this VCPU currently owns the PGM lock.
3804	*
3805	* @returns bool owner/not owner
3806	* @param pVM The cross context VM structure.
3807	*/
3808	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM)
3809	{
3810	return PDMCritSectIsOwner(pVM, &pVM->pgm.s.CritSectX);
3811	}
3812
3813
3814	/**
3815	* Enable or disable large page usage
3816	*
3817	* @returns VBox status code.
3818	* @param pVM The cross context VM structure.
3819	* @param fUseLargePages Use/not use large pages
3820	*/
3821	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages)
3822	{
3823	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3824
3825	pVM->pgm.s.fUseLargePages = fUseLargePages;
3826	return VINF_SUCCESS;
3827	}
3828
3829
3830	/**
3831	* Acquire the PGM lock.
3832	*
3833	* @returns VBox status code
3834	* @param pVM The cross context VM structure.
3835	* @param fVoid Set if the caller cannot handle failure returns.
3836	* @param SRC_POS The source position of the caller (RT_SRC_POS).
3837	*/
3838	#if defined(VBOX_STRICT) \|\| defined(DOXYGEN_RUNNING)
3839	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL)
3840	#else
3841	int pgmLock(PVMCC pVM, bool fVoid)
3842	#endif
3843	{
3844	#if defined(VBOX_STRICT)
3845	int rc = PDMCritSectEnterDebug(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS, (uintptr_t)ASMReturnAddress(), RT_SRC_POS_ARGS);
3846	#else
3847	int rc = PDMCritSectEnter(pVM, &pVM->pgm.s.CritSectX, VINF_SUCCESS);
3848	#endif
3849	if (RT_SUCCESS(rc))
3850	return rc;
3851	if (fVoid)
3852	PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pgm.s.CritSectX, rc);
3853	else
3854	AssertRC(rc);
3855	return rc;
3856	}
3857
3858
3859	/**
3860	* Release the PGM lock.
3861	*
3862	* @param pVM The cross context VM structure.
3863	*/
3864	void pgmUnlock(PVMCC pVM)
3865	{
3866	uint32_t cDeprecatedPageLocks = pVM->pgm.s.cDeprecatedPageLocks;
3867	pVM->pgm.s.cDeprecatedPageLocks = 0;
3868	int rc = PDMCritSectLeave(pVM, &pVM->pgm.s.CritSectX);
3869	if (rc == VINF_SEM_NESTED)
3870	pVM->pgm.s.cDeprecatedPageLocks = cDeprecatedPageLocks;
3871	}
3872
3873
3874	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
3875
3876	/** Format handler for PGMPAGE.
3877	* @copydoc FNRTSTRFORMATTYPE */
3878	static DECLCALLBACK(size_t) pgmFormatTypeHandlerPage(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3879	const char pszType, void const pvValue,
3880	int cchWidth, int cchPrecision, unsigned fFlags,
3881	void *pvUser)
3882	{
3883	size_t cch;
3884	PCPGMPAGE pPage = (PCPGMPAGE)pvValue;
3885	if (RT_VALID_PTR(pPage))
3886	{
3887	char szTmp[64+80];
3888
3889	cch = 0;
3890
3891	/* The single char state stuff. */
3892	static const char s_achPageStates[4] = { 'Z', 'A', 'W', 'S' };
3893	szTmp[cch++] = s_achPageStates[PGM_PAGE_GET_STATE_NA(pPage)];
3894
3895	# define IS_PART_INCLUDED(lvl) ( !(fFlags & RTSTR_F_PRECISION) \|\| cchPrecision == (lvl) \|\| cchPrecision >= (lvl)+10 )
3896	if (IS_PART_INCLUDED(5))
3897	{
3898	static const char s_achHandlerStates[4*2] = { '-', 't', 'w', 'a' , '_', 'T', 'W', 'A' };
3899	szTmp[cch++] = s_achHandlerStates[ PGM_PAGE_GET_HNDL_PHYS_STATE(pPage)
3900	\| ((uint8_t)PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage) << 2)];
3901	}
3902
3903	/* The type. */
3904	if (IS_PART_INCLUDED(4))
3905	{
3906	szTmp[cch++] = ':';
3907	static const char s_achPageTypes[8][4] = { "INV", "RAM", "MI2", "M2A", "SHA", "ROM", "MIO", "BAD" };
3908	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][0];
3909	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][1];
3910	szTmp[cch++] = s_achPageTypes[PGM_PAGE_GET_TYPE_NA(pPage)][2];
3911	}
3912
3913	/* The numbers. */
3914	if (IS_PART_INCLUDED(3))
3915	{
3916	szTmp[cch++] = ':';
3917	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_HCPHYS_NA(pPage), 16, 12, 0, RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
3918	}
3919
3920	if (IS_PART_INCLUDED(2))
3921	{
3922	szTmp[cch++] = ':';
3923	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_PAGEID(pPage), 16, 7, 0, RTSTR_F_ZEROPAD \| RTSTR_F_32BIT);
3924	}
3925
3926	if (IS_PART_INCLUDED(6))
3927	{
3928	szTmp[cch++] = ':';
3929	static const char s_achRefs[4] = { '-', 'U', '!', 'L' };
3930	szTmp[cch++] = s_achRefs[PGM_PAGE_GET_TD_CREFS_NA(pPage)];
3931	cch += RTStrFormatNumber(&szTmp[cch], PGM_PAGE_GET_TD_IDX_NA(pPage), 16, 4, 0, RTSTR_F_ZEROPAD \| RTSTR_F_16BIT);
3932	}
3933	# undef IS_PART_INCLUDED
3934
3935	cch = pfnOutput(pvArgOutput, szTmp, cch);
3936	#if 0
3937	size_t cch2 = 0;
3938	szTmp[cch2++] = '(';
3939	cch2 += RTStrFormatNumber(&szTmp[cch2], (uintptr_t)pPage, 16, 18, 0, RTSTR_F_SPECIAL \| RTSTR_F_ZEROPAD \| RTSTR_F_64BIT);
3940	szTmp[cch2++] = ')';
3941	szTmp[cch2] = '\0';
3942	cch += pfnOutput(pvArgOutput, szTmp, cch2);
3943	#endif
3944	}
3945	else
3946	cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmpage-ptr>"));
3947	NOREF(pszType); NOREF(cchWidth); NOREF(pvUser);
3948	return cch;
3949	}
3950
3951
3952	/** Format handler for PGMRAMRANGE.
3953	* @copydoc FNRTSTRFORMATTYPE */
3954	static DECLCALLBACK(size_t) pgmFormatTypeHandlerRamRange(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
3955	const char pszType, void const pvValue,
3956	int cchWidth, int cchPrecision, unsigned fFlags,
3957	void *pvUser)
3958	{
3959	size_t cch;
3960	PGMRAMRANGE const pRam = (PGMRAMRANGE const )pvValue;
3961	if (RT_VALID_PTR(pRam))
3962	{
3963	char szTmp[80];
3964	cch = RTStrPrintf(szTmp, sizeof(szTmp), "%RGp-%RGp", pRam->GCPhys, pRam->GCPhysLast);
3965	cch = pfnOutput(pvArgOutput, szTmp, cch);
3966	}
3967	else
3968	cch = pfnOutput(pvArgOutput, RT_STR_TUPLE("<bad-pgmramrange-ptr>"));
3969	NOREF(pszType); NOREF(cchWidth); NOREF(cchPrecision); NOREF(pvUser); NOREF(fFlags);
3970	return cch;
3971	}
3972
3973	/** Format type andlers to be registered/deregistered. */
3974	static const struct
3975	{
3976	char szType[24];
3977	PFNRTSTRFORMATTYPE pfnHandler;
3978	} g_aPgmFormatTypes[] =
3979	{
3980	{ "pgmpage", pgmFormatTypeHandlerPage },
3981	{ "pgmramrange", pgmFormatTypeHandlerRamRange }
3982	};
3983
3984	#endif /* !IN_R0 \|\| LOG_ENABLED */
3985
3986	/**
3987	* Registers the global string format types.
3988	*
3989	* This should be called at module load time or in some other manner that ensure
3990	* that it's called exactly one time.
3991	*
3992	* @returns IPRT status code on RTStrFormatTypeRegister failure.
3993	*/
3994	VMMDECL(int) PGMRegisterStringFormatTypes(void)
3995	{
3996	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
3997	int rc = VINF_SUCCESS;
3998	unsigned i;
3999	for (i = 0; RT_SUCCESS(rc) && i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
4000	{
4001	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
4002	# ifdef IN_RING0
4003	if (rc == VERR_ALREADY_EXISTS)
4004	{
4005	/* in case of cleanup failure in ring-0 */
4006	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4007	rc = RTStrFormatTypeRegister(g_aPgmFormatTypes[i].szType, g_aPgmFormatTypes[i].pfnHandler, NULL);
4008	}
4009	# endif
4010	}
4011	if (RT_FAILURE(rc))
4012	while (i-- > 0)
4013	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4014
4015	return rc;
4016	#else
4017	return VINF_SUCCESS;
4018	#endif
4019	}
4020
4021
4022	/**
4023	* Deregisters the global string format types.
4024	*
4025	* This should be called at module unload time or in some other manner that
4026	* ensure that it's called exactly one time.
4027	*/
4028	VMMDECL(void) PGMDeregisterStringFormatTypes(void)
4029	{
4030	#if !defined(IN_R0) \|\| defined(LOG_ENABLED)
4031	for (unsigned i = 0; i < RT_ELEMENTS(g_aPgmFormatTypes); i++)
4032	RTStrFormatTypeDeregister(g_aPgmFormatTypes[i].szType);
4033	#endif
4034	}
4035
4036
4037	#ifdef VBOX_STRICT
4038	/**
4039	* Asserts that everything related to the guest CR3 is correctly shadowed.
4040	*
4041	* This will call PGMAssertNoMappingConflicts() and PGMAssertHandlerAndFlagsInSync(),
4042	* and assert the correctness of the guest CR3 mapping before asserting that the
4043	* shadow page tables is in sync with the guest page tables.
4044	*
4045	* @returns Number of conflicts.
4046	* @param pVM The cross context VM structure.
4047	* @param pVCpu The cross context virtual CPU structure.
4048	* @param cr3 The current guest CR3 register value.
4049	* @param cr4 The current guest CR4 register value.
4050	*/
4051	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4)
4052	{
4053	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4054
4055	uintptr_t const idxBth = pVCpu->pgm.s.idxBothModeData;
4056	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), -VERR_PGM_MODE_IPE);
4057	AssertReturn(g_aPgmBothModeData[idxBth].pfnAssertCR3, -VERR_PGM_MODE_IPE);
4058
4059	PGM_LOCK_VOID(pVM);
4060	unsigned cErrors = g_aPgmBothModeData[idxBth].pfnAssertCR3(pVCpu, cr3, cr4, 0, ~(RTGCPTR)0);
4061	PGM_UNLOCK(pVM);
4062
4063	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncCR3), a);
4064	return cErrors;
4065	}
4066	#endif /* VBOX_STRICT */
4067
4068
4069	/**
4070	* Updates PGM's copy of the guest's EPT pointer.
4071	*
4072	* @param pVCpu The cross context virtual CPU structure.
4073	* @param uEptPtr The EPT pointer.
4074	*
4075	* @remarks This can be called as part of VM-entry so we might be in the midst of
4076	* switching to VMX non-root mode.
4077	*/
4078	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr)
4079	{
4080	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4081	PGM_LOCK_VOID(pVM);
4082	pVCpu->pgm.s.uEptPtr = uEptPtr;
4083	pVCpu->pgm.s.pGstEptPml4R3 = 0;
4084	pVCpu->pgm.s.pGstEptPml4R0 = 0;
4085	PGM_UNLOCK(pVM);
4086	}
4087
4088	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
4089
4090	/**
4091	* Helper for checking whether XMM0 is zero, possibly retriving external state.
4092	*/
4093	static bool pgmHandlePageZeroingIsXmm0Zero(PVMCPUCC pVCpu, PCPUMCTX pCtx)
4094	{
4095	if (pCtx->fExtrn & CPUMCTX_EXTRN_SSE_AVX)
4096	{
4097	int rc = CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_SSE_AVX);
4098	AssertRCReturn(rc, false);
4099	}
4100	return pCtx->XState.x87.aXMM[0].au64[0] == 0
4101	&& pCtx->XState.x87.aXMM[0].au64[1] == 0
4102	&& pCtx->XState.x87.aXMM[0].au64[2] == 0
4103	&& pCtx->XState.x87.aXMM[0].au64[3] == 0;
4104	}
4105
4106
4107	/**
4108	* Helper for comparing opcode bytes.
4109	*/
4110	static bool pgmHandlePageZeroingMatchOpcodes(PVMCPUCC pVCpu, PCPUMCTX pCtx, uint8_t const *pbOpcodes, uint32_t cbOpcodes)
4111	{
4112	uint8_t abTmp[64];
4113	AssertMsgReturn(cbOpcodes <= sizeof(abTmp), ("cbOpcodes=%#x\n", cbOpcodes), false);
4114	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abTmp, pCtx->rip + pCtx->cs.u64Base, cbOpcodes);
4115	if (RT_SUCCESS(rc))
4116	return memcmp(abTmp, pbOpcodes, cbOpcodes) == 0;
4117	return false;
4118	}
4119
4120
4121	/**
4122	* Called on faults on ZERO pages to check if the guest is trying to zero it.
4123	*
4124	* Since it's a waste of time to zero a ZERO page and it will cause an
4125	* unnecessary page allocation, we'd like to detect and avoid this.
4126	* If any known page zeroing code is detected, this function will update the CPU
4127	* state to pretend the page was zeroed by the code.
4128	*
4129	* @returns true if page zeroing code was detected and CPU state updated to skip
4130	* the code.
4131	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4132	* @param pCtx The guest register context.
4133	*/
4134	static bool pgmHandlePageZeroingCode(PVMCPUCC pVCpu, PCPUMCTX pCtx)
4135	{
4136	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
4137
4138	/*
4139	* Sort by mode first.
4140	*/
4141	if (CPUMIsGuestInLongModeEx(pCtx))
4142	{
4143	if (CPUMIsGuestIn64BitCodeEx(pCtx))
4144	{
4145	/*
4146	* 64-bit code.
4147	*/
4148	Log9(("pgmHandlePageZeroingCode: not page zeroing - 64-bit\n"));
4149	}
4150	else if (pCtx->cs.Attr.n.u1DefBig)
4151	Log9(("pgmHandlePageZeroingCode: not page zeroing - 32-bit lm\n"));
4152	else
4153	Log9(("pgmHandlePageZeroingCode: not page zeroing - 16-bit lm\n"));
4154	}
4155	else if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
4156	{
4157	if (pCtx->cs.Attr.n.u1DefBig)
4158	{
4159	/*
4160	* 32-bit paged protected mode code.
4161	*/
4162	CPUMCTX_ASSERT_NOT_EXTRN(pCtx, CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX \| CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RBX
4163	\| CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP \| CPUMCTX_EXTRN_RSI \| CPUMCTX_EXTRN_RDI
4164	\| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
4165
4166	/* 1. Generic 'rep stosd' detection. */
4167	static uint8_t const s_abRepStosD[] = { 0xf3, 0xab };
4168	if ( pCtx->eax == 0
4169	&& pCtx->ecx == X86_PAGE_SIZE / 4
4170	&& !(pCtx->edi & X86_PAGE_OFFSET_MASK)
4171	&& pgmHandlePageZeroingMatchOpcodes(pVCpu, pCtx, s_abRepStosD, sizeof(s_abRepStosD)))
4172	{
4173	pCtx->ecx = 0;
4174	pCtx->edi += X86_PAGE_SIZE;
4175	Log9(("pgmHandlePageZeroingCode: REP STOSD: eip=%RX32 -> %RX32\n", pCtx->eip, pCtx->eip + sizeof(s_abRepStosD)));
4176	pCtx->eip += sizeof(s_abRepStosD);
4177	return true;
4178	}
4179
4180	/* 2. Windows 2000 sp4 KiXMMIZeroPageNoSave loop code: */
4181	static uint8_t const s_abW2kSp4XmmZero[] =
4182	{
4183	0x0f, 0x2b, 0x01,
4184	0x0f, 0x2b, 0x41, 0x10,
4185	0x0f, 0x2b, 0x41, 0x20,
4186	0x0f, 0x2b, 0x41, 0x30,
4187	0x83, 0xc1, 0x40,
4188	0x48,
4189	0x75, 0xeb,
4190	};
4191	if ( pCtx->eax == 64
4192	&& !(pCtx->ecx & X86_PAGE_OFFSET_MASK)
4193	&& pgmHandlePageZeroingMatchOpcodes(pVCpu, pCtx, s_abW2kSp4XmmZero, sizeof(s_abW2kSp4XmmZero))
4194	&& pgmHandlePageZeroingIsXmm0Zero(pVCpu, pCtx))
4195	{
4196	pCtx->eax = 1;
4197	pCtx->ecx += X86_PAGE_SIZE;
4198	Log9(("pgmHandlePageZeroingCode: w2k sp4 xmm: eip=%RX32 -> %RX32\n",
4199	pCtx->eip, pCtx->eip + sizeof(s_abW2kSp4XmmZero) - 3));
4200	pCtx->eip += sizeof(s_abW2kSp4XmmZero) - 3;
4201	return true;
4202	}
4203	Log9(("pgmHandlePageZeroingCode: not page zeroing - 32-bit\n"));
4204	}
4205	else if (!pCtx->eflags.Bits.u1VM)
4206	Log9(("pgmHandlePageZeroingCode: not page zeroing - 16-bit\n"));
4207	else
4208	Log9(("pgmHandlePageZeroingCode: not page zeroing - v86\n"));
4209	}
4210	return false;
4211	}
4212
4213	#endif /* PGM_WITH_PAGE_ZEROING_DETECTION */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAll.cpp@ 103025

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