VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 98743

Last change on this file since 98743 was 98103, checked in by vboxsync, 23 months ago

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1/* $Id: PDMAll.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PDM
33#include "PDMInternal.h"
34#include <VBox/vmm/pdm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/vmcc.h>
37#include <VBox/err.h>
38#include <VBox/vmm/apic.h>
39
40#include <VBox/log.h>
41#include <iprt/asm.h>
42#include <iprt/assert.h>
43
44#include "PDMInline.h"
45#include "dtrace/VBoxVMM.h"
46
47
48
49/**
50 * Gets the pending interrupt.
51 *
52 * @returns VBox status code.
53 * @retval VINF_SUCCESS on success.
54 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
55 * can't be delivered due to TPR priority.
56 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
57 * has been software-disabled since it flagged something was pending,
58 * or other reasons).
59 *
60 * @param pVCpu The cross context virtual CPU structure.
61 * @param pu8Interrupt Where to store the interrupt.
62 */
63VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
64{
65 /*
66 * The local APIC has a higher priority than the PIC.
67 */
68 int rc = VERR_NO_DATA;
69 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
70 {
71 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
72 uint32_t uTagSrc;
73 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
74 if (RT_SUCCESS(rc))
75 {
76 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
77 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (apic)\n", *pu8Interrupt, uTagSrc));
78 return VINF_SUCCESS;
79 }
80 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
81 interrupts shouldn't prevent ExtINT from being delivered. */
82 }
83
84 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
85 pdmLock(pVM);
86
87 /*
88 * Check the PIC.
89 */
90 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
91 {
92 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
93 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
94 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
95 uint32_t uTagSrc;
96 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
97 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
98 if (i >= 0)
99 {
100 pdmUnlock(pVM);
101 *pu8Interrupt = (uint8_t)i;
102 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
103 Log8(("PDMGetInterrupt: irq=%#x tag=%#x (pic)\n", i, uTagSrc));
104 return VINF_SUCCESS;
105 }
106 }
107
108 /*
109 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
110 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
111 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
112 * without returning a valid interrupt still needs to be handled for the TPR masked case,
113 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
114 */
115
116 pdmUnlock(pVM);
117 return rc;
118}
119
120
121/**
122 * Sets the pending interrupt coming from ISA source or HPET.
123 *
124 * @returns VBox status code.
125 * @param pVM The cross context VM structure.
126 * @param u8Irq The IRQ line.
127 * @param u8Level The new level.
128 * @param uTagSrc The IRQ tag and source tracer ID.
129 */
130VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
131{
132 pdmLock(pVM);
133
134 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
135 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
136 {
137 if (u8Level == PDM_IRQ_LEVEL_HIGH)
138 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
139 else
140 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
141 }
142 Log9(("PDMIsaSetIrq: irq=%#x lvl=%u tag=%#x\n", u8Irq, u8Level, uTagSrc));
143
144 int rc = VERR_PDM_NO_PIC_INSTANCE;
145/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
146 * are always ring-0 enabled! */
147 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
148 {
149 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
150 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
151 rc = VINF_SUCCESS;
152 }
153
154 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
155 {
156 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
157
158 /*
159 * Apply Interrupt Source Override rules.
160 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
161 * interrupt source override.
162 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
163 * notably recent OS X rely upon this configuration.
164 * If changing, also update override rules in MADT and MPS.
165 */
166 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
167 if (u8Irq == 0)
168 u8Irq = 2;
169
170 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
171 rc = VINF_SUCCESS;
172 }
173
174 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
175 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
176 pdmUnlock(pVM);
177 return rc;
178}
179
180
181/**
182 * Sets the pending I/O APIC interrupt.
183 *
184 * @returns VBox status code.
185 * @param pVM The cross context VM structure.
186 * @param u8Irq The IRQ line.
187 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
188 * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
189 * @param u8Level The new level.
190 * @param uTagSrc The IRQ tag and source tracer ID.
191 */
192VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
193{
194 Log9(("PDMIoApicSetIrq: irq=%#x lvl=%u tag=%#x src=%#x\n", u8Irq, u8Level, uTagSrc, uBusDevFn));
195 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
196 {
197 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
198 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
199 return VINF_SUCCESS;
200 }
201 return VERR_PDM_NO_PIC_INSTANCE;
202}
203
204
205/**
206 * Broadcasts an EOI to the I/O APIC(s).
207 *
208 * @param pVM The cross context VM structure.
209 * @param uVector The interrupt vector corresponding to the EOI.
210 */
211VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
212{
213 /*
214 * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
215 * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
216 */
217 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
218#ifdef IN_RING0
219 if (pIoApic->pDevInsR0)
220 {
221 Assert(pIoApic->pfnSetEoiR0);
222 pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
223 }
224 else if (pIoApic->pDevInsR3)
225 {
226 /* Queue for ring-3 execution. */
227 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
228 if (pTask)
229 {
230 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
231 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
232 pTask->u.IoApicSetEoi.uVector = uVector;
233 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
234 }
235 else
236 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
237 }
238#else
239 if (pIoApic->pDevInsR3)
240 {
241 Assert(pIoApic->pfnSetEoiR3);
242 pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
243 }
244#endif
245}
246
247
248/**
249 * Send a MSI to an I/O APIC.
250 *
251 * @param pVM The cross context VM structure.
252 * @param uBusDevFn The bus:device:function of the device initiating the MSI.
253 * @param pMsi The MSI to send.
254 * @param uTagSrc The IRQ tag and source tracer ID.
255 */
256VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
257{
258 Log9(("PDMIoApicSendMsi: addr=%#RX64 data=%#RX32 tag=%#x src=%#x\n", pMsi->Addr.u64, pMsi->Data.u32, uTagSrc, uBusDevFn));
259 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
260#ifdef IN_RING0
261 if (pIoApic->pDevInsR0)
262 pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
263 else if (pIoApic->pDevInsR3)
264 {
265 /* Queue for ring-3 execution. */
266 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM, pVM->pdm.s.hDevHlpQueue, pVM);
267 if (pTask)
268 {
269 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
270 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
271 pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
272 pTask->u.IoApicSendMsi.Msi = *pMsi;
273 pTask->u.IoApicSendMsi.uTagSrc = uTagSrc;
274 PDMQueueInsert(pVM, pVM->pdm.s.hDevHlpQueue, pVM, &pTask->Core);
275 }
276 else
277 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
278 }
279#else
280 if (pIoApic->pDevInsR3)
281 {
282 Assert(pIoApic->pfnSendMsiR3);
283 pIoApic->pfnSendMsiR3(pIoApic->pDevInsR3, uBusDevFn, pMsi, uTagSrc);
284 }
285#endif
286}
287
288
289
290/**
291 * Returns the presence of an IO-APIC.
292 *
293 * @returns true if an IO-APIC is present.
294 * @param pVM The cross context VM structure.
295 */
296VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
297{
298 return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
299}
300
301
302/**
303 * Returns the presence of an APIC.
304 *
305 * @returns true if an APIC is present.
306 * @param pVM The cross context VM structure.
307 */
308VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
309{
310 return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
311}
312
313
314/**
315 * Translates a ring-0 device instance index to a pointer.
316 *
317 * This is used by PGM for device access handlers.
318 *
319 * @returns Device instance pointer if valid index, otherwise NULL (asserted).
320 * @param pVM The cross context VM structure.
321 * @param idxR0Device The ring-0 device instance index.
322 */
323VMM_INT_DECL(PPDMDEVINS) PDMDeviceRing0IdxToInstance(PVMCC pVM, uint64_t idxR0Device)
324{
325#ifdef IN_RING0
326 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdmr0.s.apDevInstances), ("%#RX64\n", idxR0Device), NULL);
327 PPDMDEVINS pDevIns = pVM->pdmr0.s.apDevInstances[idxR0Device];
328#elif defined(IN_RING3)
329 AssertMsgReturn(idxR0Device < RT_ELEMENTS(pVM->pdm.s.apDevRing0Instances), ("%#RX64\n", idxR0Device), NULL);
330 PPDMDEVINS pDevIns = pVM->pdm.s.apDevRing0Instances[idxR0Device];
331#else
332# error "Unsupported context"
333#endif
334 AssertMsg(pDevIns, ("%#RX64\n", idxR0Device));
335 return pDevIns;
336}
337
338
339/**
340 * Locks PDM.
341 *
342 * This might block.
343 *
344 * @param pVM The cross context VM structure.
345 */
346void pdmLock(PVMCC pVM)
347{
348 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VINF_SUCCESS);
349 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc);
350}
351
352
353/**
354 * Locks PDM but don't go to ring-3 if it's owned by someone.
355 *
356 * @returns VINF_SUCCESS on success.
357 * @returns rc if we're in GC or R0 and can't get the lock.
358 * @param pVM The cross context VM structure.
359 * @param rcBusy The RC to return in GC or R0 when we can't get the lock.
360 */
361int pdmLockEx(PVMCC pVM, int rcBusy)
362{
363 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy);
364}
365
366
367/**
368 * Unlocks PDM.
369 *
370 * @param pVM The cross context VM structure.
371 */
372void pdmUnlock(PVMCC pVM)
373{
374 PDMCritSectLeave(pVM, &pVM->pdm.s.CritSect);
375}
376
377
378/**
379 * Checks if this thread is owning the PDM lock.
380 *
381 * @returns @c true if the lock is taken, @c false otherwise.
382 * @param pVM The cross context VM structure.
383 */
384bool pdmLockIsOwner(PVMCC pVM)
385{
386 return PDMCritSectIsOwner(pVM, &pVM->pdm.s.CritSect);
387}
388
389
390/**
391 * Converts ring 3 VMM heap pointer to a guest physical address
392 *
393 * @returns VBox status code.
394 * @param pVM The cross context VM structure.
395 * @param pv Ring-3 pointer.
396 * @param pGCPhys GC phys address (out).
397 */
398VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
399{
400 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
401 {
402 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
403 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
404 {
405 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
406 return VINF_SUCCESS;
407 }
408
409 /* Don't assert here as this is called before we can catch ring-0 assertions. */
410 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
411 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
412 }
413 else
414 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
415 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
416}
417
418
419/**
420 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
421 *
422 * @returns dev heap enabled status (true/false)
423 * @param pVM The cross context VM structure.
424 */
425VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
426{
427 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
428}
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