VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 60307

Last change on this file since 60307 was 60307, checked in by vboxsync, 9 years ago

VMM: APIC rewrite. Initial commit, work in progress.
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1/* $Id: PDMAll.cpp 60307 2016-04-04 15:23:11Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/vm.h>
27#include <VBox/err.h>
28
29#include <VBox/log.h>
30#include <iprt/asm.h>
31#include <iprt/assert.h>
32
33#include "PDMInline.h"
34#include "dtrace/VBoxVMM.h"
35
36
37
38/**
39 * Gets the pending interrupt.
40 *
41 * @returns VBox status code.
42 * @param pVCpu The cross context virtual CPU structure.
43 * @param pu8Interrupt Where to store the interrupt on success.
44 */
45VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
46{
47 PVM pVM = pVCpu->CTX_SUFF(pVM);
48
49 pdmLock(pVM);
50
51 /*
52 * The local APIC has a higher priority than the PIC.
53 */
54 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
55 {
56 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
57 Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
58 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
59 uint32_t uTagSrc;
60 int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uTagSrc);
61 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
62 if (i >= 0)
63 {
64 pdmUnlock(pVM);
65 *pu8Interrupt = (uint8_t)i;
66 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
67 return VINF_SUCCESS;
68 }
69 }
70
71 /*
72 * Check the PIC.
73 */
74 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
75 {
76 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
77 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
78 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
79 uint32_t uTagSrc;
80 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
81 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
82 if (i >= 0)
83 {
84 pdmUnlock(pVM);
85 *pu8Interrupt = (uint8_t)i;
86 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
87 return VINF_SUCCESS;
88 }
89 }
90
91 /** @todo Figure out exactly why we can get here without anything being set. (REM) */
92
93 pdmUnlock(pVM);
94 return VERR_NO_DATA;
95}
96
97
98/**
99 * Sets the pending interrupt coming from ISA source or HPET.
100 *
101 * @returns VBox status code.
102 * @param pVM The cross context VM structure.
103 * @param u8Irq The IRQ line.
104 * @param u8Level The new level.
105 * @param uTagSrc The IRQ tag and source tracer ID.
106 */
107VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
108{
109 pdmLock(pVM);
110
111 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
112 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
113 {
114 if (u8Level == PDM_IRQ_LEVEL_HIGH)
115 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
116 else
117 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
118 }
119
120 int rc = VERR_PDM_NO_PIC_INSTANCE;
121 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
122 {
123 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
124 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
125 rc = VINF_SUCCESS;
126 }
127
128 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
129 {
130 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
131
132 /*
133 * Apply Interrupt Source Override rules.
134 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
135 * interrupt source override.
136 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
137 * notably recent OS X rely upon this configuration.
138 * If changing, also update override rules in MADT and MPS.
139 */
140 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
141 if (u8Irq == 0)
142 u8Irq = 2;
143
144 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
145 rc = VINF_SUCCESS;
146 }
147
148 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
149 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
150 pdmUnlock(pVM);
151 return rc;
152}
153
154
155/**
156 * Sets the pending I/O APIC interrupt.
157 *
158 * @returns VBox status code.
159 * @param pVM The cross context VM structure.
160 * @param u8Irq The IRQ line.
161 * @param u8Level The new level.
162 * @param uTagSrc The IRQ tag and source tracer ID.
163 */
164VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
165{
166 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
167 {
168 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
169 pdmLock(pVM);
170 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
171 pdmUnlock(pVM);
172 return VINF_SUCCESS;
173 }
174 return VERR_PDM_NO_PIC_INSTANCE;
175}
176
177/**
178 * Send a MSI to an I/O APIC.
179 *
180 * @returns VBox status code.
181 * @param pVM The cross context VM structure.
182 * @param GCAddr Request address.
183 * @param uValue Request value.
184 * @param uTagSrc The IRQ tag and source tracer ID.
185 */
186VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
187{
188 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
189 {
190 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
191 pdmLock(pVM);
192 pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);
193 pdmUnlock(pVM);
194 return VINF_SUCCESS;
195 }
196 return VERR_PDM_NO_PIC_INSTANCE;
197}
198
199
200
201/**
202 * Returns the presence of an IO-APIC.
203 *
204 * @returns VBox true if an IO-APIC is present.
205 * @param pVM The cross context VM structure.
206 */
207VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
208{
209 return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
210}
211
212
213/**
214 * Returns the presence of a Local APIC.
215 *
216 * @returns VBox true if a Local APIC is present.
217 * @param pVM The cross context VM structure.
218 */
219VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
220{
221 return pVM->pdm.s.Apic.CTX_SUFF(pDevIns) != NULL;
222}
223
224
225/**
226 * Set the APIC base.
227 *
228 * @returns Strict VBox status code.
229 * @param pVCpu The cross context virtual CPU structure.
230 * @param u64Base The new base.
231 */
232VMMDECL(VBOXSTRICTRC) PDMApicSetBaseMsr(PVMCPU pVCpu, uint64_t u64Base)
233{
234 PVM pVM = pVCpu->CTX_SUFF(pVM);
235 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
236 {
237 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBaseMsr));
238 pdmLock(pVM);
239 VBOXSTRICTRC rcStrict = pVM->pdm.s.Apic.CTX_SUFF(pfnSetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u64Base);
240
241 /* Update CPUM's copy of the APIC base. */
242 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
243 Assert(pCtx);
244 pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu);
245
246 pdmUnlock(pVM);
247 return rcStrict;
248 }
249
250#ifdef IN_RING3
251 LogRelMax(5, ("PDM: APIC%U: Writing APIC base MSR (%#x) invalid since there isn't an APIC -> #GP(0)\n", pVCpu->idCpu,
252 MSR_IA32_APICBASE));
253 return VERR_CPUM_RAISE_GP_0;
254#else
255 return VINF_CPUM_R3_MSR_WRITE;
256#endif
257}
258
259
260/**
261 * Get the APIC base MSR from the APIC device.
262 *
263 * @returns Strict VBox status code.
264 * @param pVCpu The cross context virtual CPU structure.
265 * @param pu64Base Where to store the APIC base.
266 */
267VMMDECL(VBOXSTRICTRC) PDMApicGetBaseMsr(PVMCPU pVCpu, uint64_t *pu64Base)
268{
269 PVM pVM = pVCpu->CTX_SUFF(pVM);
270 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
271 {
272 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr));
273#ifdef VBOX_WITH_NEW_APIC
274 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu);
275#else
276 pdmLock(pVM);
277 *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBaseMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu);
278 pdmUnlock(pVM);
279#endif
280 return VINF_SUCCESS;
281 }
282
283 *pu64Base = 0;
284#ifdef IN_RING3
285 LogRelMax(5, ("PDM: APIC%u: Reading APIC base MSR (%#x) invalid without an APIC instance -> #GP(0)\n", pVCpu->idCpu,
286 MSR_IA32_APICBASE));
287 return VERR_CPUM_RAISE_GP_0;
288#else
289 return VINF_CPUM_R3_MSR_WRITE;
290#endif
291}
292
293
294/**
295 * Check if the APIC has a pending interrupt/if a TPR change would active one.
296 *
297 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
298 * @param pVCpu The cross context virtual CPU structure.
299 * @param pfPending Pending state (out).
300 */
301VMM_INT_DECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending)
302{
303 PVM pVM = pVCpu->CTX_SUFF(pVM);
304 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
305 {
306 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq));
307 pdmLock(pVM);
308 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, NULL /*pu8PendingIrq*/);
309 pdmUnlock(pVM);
310 return VINF_SUCCESS;
311 }
312 return VERR_PDM_NO_APIC_INSTANCE;
313}
314
315
316/**
317 * Set the TPR (task priority register).
318 *
319 * @returns VBox status code.
320 * @param pVCpu The cross context virtual CPU structure.
321 * @param u8TPR The new TPR.
322 */
323VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
324{
325 PVM pVM = pVCpu->CTX_SUFF(pVM);
326 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
327 {
328 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTpr));
329 pdmLock(pVM);
330 pVM->pdm.s.Apic.CTX_SUFF(pfnSetTpr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u8TPR);
331 pdmUnlock(pVM);
332 return VINF_SUCCESS;
333 }
334 return VERR_PDM_NO_APIC_INSTANCE;
335}
336
337
338/**
339 * Get the TPR (task priority register).
340 *
341 * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
342 * @param pVCpu The cross context virtual CPU structure.
343 * @param pu8TPR Where to store the TRP.
344 * @param pfPending Pending interrupt state (out, optional).
345 * @param pu8PendingIrq Where to store the highest-priority pending IRQ
346 * (out, optional).
347 *
348 * @remarks No-long-jump zone!!!
349 */
350VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIrq)
351{
352 PVM pVM = pVCpu->CTX_SUFF(pVM);
353 PPDMDEVINS pApicIns = pVM->pdm.s.Apic.CTX_SUFF(pDevIns);
354 if (pApicIns)
355 {
356 /*
357 * Note! We don't acquire the PDM lock here as we're just reading
358 * information. Doing so causes massive contention as this
359 * function is called very often by each and every VCPU.
360 */
361 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTpr));
362 *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTpr)(pApicIns, pVCpu);
363 if (pfPending)
364 *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pApicIns, pVCpu, pu8PendingIrq);
365 return VINF_SUCCESS;
366 }
367 *pu8TPR = 0;
368 return VERR_PDM_NO_APIC_INSTANCE;
369}
370
371
372/**
373 * Write a MSR in APIC range.
374 *
375 * @returns Strict VBox status code.
376 * @param pVCpu The cross context virtual CPU structure.
377 * @param iCpu Target CPU.
378 * @param u32Reg MSR to write.
379 * @param u64Value Value to write.
380 */
381VMM_INT_DECL(VBOXSTRICTRC) PDMApicWriteMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
382{
383 PVM pVM = pVCpu->CTX_SUFF(pVM);
384 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
385 {
386 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMsr));
387 return pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u32Reg, u64Value);
388 }
389 return VERR_CPUM_RAISE_GP_0;
390}
391
392
393/**
394 * Read a MSR in APIC range.
395 *
396 * @returns Strict VBox status code.
397 * @param pVCpu The cross context virtual CPU structure.
398 * @param iCpu Target CPU.
399 * @param u32Reg MSR to read.
400 * @param pu64Value Value read.
401 */
402VMM_INT_DECL(VBOXSTRICTRC) PDMApicReadMsr(PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
403{
404 PVM pVM = pVCpu->CTX_SUFF(pVM);
405 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
406 {
407 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMsr));
408 return pVM->pdm.s.Apic.CTX_SUFF(pfnReadMsr)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, u32Reg, pu64Value);
409 }
410 return VERR_CPUM_RAISE_GP_0;
411}
412
413
414/**
415 * Gets the frequency of the APIC timer.
416 *
417 * @returns VBox status code.
418 * @param pVM The cross context VM structure.
419 * @param pu64Value Where to store the frequency.
420 */
421VMM_INT_DECL(int) PDMApicGetTimerFreq(PVM pVM, uint64_t *pu64Value)
422{
423 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
424 {
425 AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq));
426 *pu64Value = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTimerFreq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
427 return VINF_SUCCESS;
428 }
429 return VERR_PDM_NO_APIC_INSTANCE;
430}
431
432
433/**
434 * Locks PDM.
435 * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
436 *
437 * @param pVM The cross context VM structure.
438 */
439void pdmLock(PVM pVM)
440{
441#ifdef IN_RING3
442 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
443#else
444 int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
445 if (rc == VERR_GENERAL_FAILURE)
446 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
447#endif
448 AssertRC(rc);
449}
450
451
452/**
453 * Locks PDM but don't go to ring-3 if it's owned by someone.
454 *
455 * @returns VINF_SUCCESS on success.
456 * @returns rc if we're in GC or R0 and can't get the lock.
457 * @param pVM The cross context VM structure.
458 * @param rc The RC to return in GC or R0 when we can't get the lock.
459 */
460int pdmLockEx(PVM pVM, int rc)
461{
462 return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
463}
464
465
466/**
467 * Unlocks PDM.
468 *
469 * @param pVM The cross context VM structure.
470 */
471void pdmUnlock(PVM pVM)
472{
473 PDMCritSectLeave(&pVM->pdm.s.CritSect);
474}
475
476
477/**
478 * Converts ring 3 VMM heap pointer to a guest physical address
479 *
480 * @returns VBox status code.
481 * @param pVM The cross context VM structure.
482 * @param pv Ring-3 pointer.
483 * @param pGCPhys GC phys address (out).
484 */
485VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
486{
487 /* Don't assert here as this is called before we can catch ring-0 assertions. */
488 if (RT_UNLIKELY((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap >= pVM->pdm.s.cbVMMDevHeap))
489 {
490 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
491 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
492 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
493 }
494
495 *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
496 return VINF_SUCCESS;
497}
498
499/**
500 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
501 *
502 * @returns dev heap enabled status (true/false)
503 * @param pVM The cross context VM structure.
504 */
505VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
506{
507 return (pVM->pdm.s.pvVMMDevHeap != NULL);
508}
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