1 | /* $Id: PDMAll.cpp 46420 2013-06-06 16:27:25Z vboxsync $ */
|
---|
2 | /** @file
|
---|
3 | * PDM Critical Sections
|
---|
4 | */
|
---|
5 |
|
---|
6 | /*
|
---|
7 | * Copyright (C) 2006-2013 Oracle Corporation
|
---|
8 | *
|
---|
9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
10 | * available from http://www.virtualbox.org. This file is free software;
|
---|
11 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
12 | * General Public License (GPL) as published by the Free Software
|
---|
13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
16 | */
|
---|
17 |
|
---|
18 |
|
---|
19 | /*******************************************************************************
|
---|
20 | * Header Files *
|
---|
21 | *******************************************************************************/
|
---|
22 | #define LOG_GROUP LOG_GROUP_PDM
|
---|
23 | #include "PDMInternal.h"
|
---|
24 | #include <VBox/vmm/pdm.h>
|
---|
25 | #include <VBox/vmm/mm.h>
|
---|
26 | #include <VBox/vmm/vm.h>
|
---|
27 | #include <VBox/err.h>
|
---|
28 |
|
---|
29 | #include <VBox/log.h>
|
---|
30 | #include <iprt/asm.h>
|
---|
31 | #include <iprt/assert.h>
|
---|
32 |
|
---|
33 | #include "PDMInline.h"
|
---|
34 | #include "dtrace/VBoxVMM.h"
|
---|
35 |
|
---|
36 |
|
---|
37 |
|
---|
38 | /**
|
---|
39 | * Gets the pending interrupt.
|
---|
40 | *
|
---|
41 | * @returns VBox status code.
|
---|
42 | * @param pVCpu Pointer to the VMCPU.
|
---|
43 | * @param pu8Interrupt Where to store the interrupt on success.
|
---|
44 | */
|
---|
45 | VMMDECL(int) PDMGetInterrupt(PVMCPU pVCpu, uint8_t *pu8Interrupt)
|
---|
46 | {
|
---|
47 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
48 |
|
---|
49 | pdmLock(pVM);
|
---|
50 |
|
---|
51 | /*
|
---|
52 | * The local APIC has a higher priority than the PIC.
|
---|
53 | */
|
---|
54 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
|
---|
55 | {
|
---|
56 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
|
---|
57 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pDevIns));
|
---|
58 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt));
|
---|
59 | uint32_t uTagSrc;
|
---|
60 | int i = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, &uTagSrc);
|
---|
61 | AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
|
---|
62 | if (i >= 0)
|
---|
63 | {
|
---|
64 | pdmUnlock(pVM);
|
---|
65 | *pu8Interrupt = (uint8_t)i;
|
---|
66 | VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
|
---|
67 | return VINF_SUCCESS;
|
---|
68 | }
|
---|
69 | }
|
---|
70 |
|
---|
71 | /*
|
---|
72 | * Check the PIC.
|
---|
73 | */
|
---|
74 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
|
---|
75 | {
|
---|
76 | VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
|
---|
77 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
|
---|
78 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
|
---|
79 | uint32_t uTagSrc;
|
---|
80 | int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
|
---|
81 | AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
|
---|
82 | if (i >= 0)
|
---|
83 | {
|
---|
84 | pdmUnlock(pVM);
|
---|
85 | *pu8Interrupt = (uint8_t)i;
|
---|
86 | VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
|
---|
87 | return VINF_SUCCESS;
|
---|
88 | }
|
---|
89 | }
|
---|
90 |
|
---|
91 | /** @todo Figure out exactly why we can get here without anything being set. (REM) */
|
---|
92 |
|
---|
93 | pdmUnlock(pVM);
|
---|
94 | return VERR_NO_DATA;
|
---|
95 | }
|
---|
96 |
|
---|
97 |
|
---|
98 | /**
|
---|
99 | * Sets the pending interrupt coming from ISA source or HPET.
|
---|
100 | *
|
---|
101 | * @returns VBox status code.
|
---|
102 | * @param pVM Pointer to the VM.
|
---|
103 | * @param u8Irq The IRQ line.
|
---|
104 | * @param u8Level The new level.
|
---|
105 | * @param uTagSrc The IRQ tag and source tracer ID.
|
---|
106 | */
|
---|
107 | VMMDECL(int) PDMIsaSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
|
---|
108 | {
|
---|
109 | pdmLock(pVM);
|
---|
110 |
|
---|
111 | /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
|
---|
112 | if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
|
---|
113 | {
|
---|
114 | if (u8Level == PDM_IRQ_LEVEL_HIGH)
|
---|
115 | VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
|
---|
116 | else
|
---|
117 | VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
|
---|
118 | }
|
---|
119 |
|
---|
120 | int rc = VERR_PDM_NO_PIC_INSTANCE;
|
---|
121 | if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
|
---|
122 | {
|
---|
123 | Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
|
---|
124 | pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
|
---|
125 | rc = VINF_SUCCESS;
|
---|
126 | }
|
---|
127 |
|
---|
128 | if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
|
---|
129 | {
|
---|
130 | Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
|
---|
131 |
|
---|
132 | /*
|
---|
133 | * Apply Interrupt Source Override rules.
|
---|
134 | * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
|
---|
135 | * interrupt source override.
|
---|
136 | * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
|
---|
137 | * notably recent OS X rely upon this configuration.
|
---|
138 | * If changing, also update override rules in MADT and MPS.
|
---|
139 | */
|
---|
140 | /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
|
---|
141 | if (u8Irq == 0)
|
---|
142 | u8Irq = 2;
|
---|
143 |
|
---|
144 | pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
|
---|
145 | rc = VINF_SUCCESS;
|
---|
146 | }
|
---|
147 |
|
---|
148 | if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
|
---|
149 | VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
|
---|
150 | pdmUnlock(pVM);
|
---|
151 | return rc;
|
---|
152 | }
|
---|
153 |
|
---|
154 |
|
---|
155 | /**
|
---|
156 | * Sets the pending I/O APIC interrupt.
|
---|
157 | *
|
---|
158 | * @returns VBox status code.
|
---|
159 | * @param pVM Pointer to the VM.
|
---|
160 | * @param u8Irq The IRQ line.
|
---|
161 | * @param u8Level The new level.
|
---|
162 | * @param uTagSrc The IRQ tag and source tracer ID.
|
---|
163 | */
|
---|
164 | VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
|
---|
165 | {
|
---|
166 | if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
|
---|
167 | {
|
---|
168 | Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
|
---|
169 | pdmLock(pVM);
|
---|
170 | pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
|
---|
171 | pdmUnlock(pVM);
|
---|
172 | return VINF_SUCCESS;
|
---|
173 | }
|
---|
174 | return VERR_PDM_NO_PIC_INSTANCE;
|
---|
175 | }
|
---|
176 |
|
---|
177 | /**
|
---|
178 | * Send a MSI to an I/O APIC.
|
---|
179 | *
|
---|
180 | * @returns VBox status code.
|
---|
181 | * @param pVM Pointer to the VM.
|
---|
182 | * @param GCAddr Request address.
|
---|
183 | * @param u8Value Request value.
|
---|
184 | * @param uTagSrc The IRQ tag and source tracer ID.
|
---|
185 | */
|
---|
186 | VMM_INT_DECL(int) PDMIoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
|
---|
187 | {
|
---|
188 | if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
|
---|
189 | {
|
---|
190 | Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi));
|
---|
191 | pdmLock(pVM);
|
---|
192 | pVM->pdm.s.IoApic.CTX_SUFF(pfnSendMsi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), GCAddr, uValue, uTagSrc);
|
---|
193 | pdmUnlock(pVM);
|
---|
194 | return VINF_SUCCESS;
|
---|
195 | }
|
---|
196 | return VERR_PDM_NO_PIC_INSTANCE;
|
---|
197 | }
|
---|
198 |
|
---|
199 |
|
---|
200 |
|
---|
201 | /**
|
---|
202 | * Returns presence of an IO-APIC
|
---|
203 | *
|
---|
204 | * @returns VBox true if IO-APIC is present
|
---|
205 | * @param pVM Pointer to the VM.
|
---|
206 | */
|
---|
207 | VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
|
---|
208 | {
|
---|
209 | return pVM->pdm.s.IoApic.CTX_SUFF(pDevIns) != NULL;
|
---|
210 | }
|
---|
211 |
|
---|
212 |
|
---|
213 | /**
|
---|
214 | * Set the APIC base.
|
---|
215 | *
|
---|
216 | * @returns VBox status code.
|
---|
217 | * @param pVM Pointer to the VMCPU.
|
---|
218 | * @param u64Base The new base.
|
---|
219 | */
|
---|
220 | VMMDECL(int) PDMApicSetBase(PVMCPU pVCpu, uint64_t u64Base)
|
---|
221 | {
|
---|
222 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
223 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
224 | {
|
---|
225 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase));
|
---|
226 | pdmLock(pVM);
|
---|
227 | pVM->pdm.s.Apic.CTX_SUFF(pfnSetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u64Base);
|
---|
228 |
|
---|
229 | /* Update CPUM's copy of the APIC base. */
|
---|
230 | PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
|
---|
231 | Assert(pCtx);
|
---|
232 | pCtx->msrApicBase = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
|
---|
233 |
|
---|
234 | pdmUnlock(pVM);
|
---|
235 | return VINF_SUCCESS;
|
---|
236 | }
|
---|
237 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
238 | }
|
---|
239 |
|
---|
240 |
|
---|
241 | /**
|
---|
242 | * Get the APIC base from the APIC device. This is slow and involves
|
---|
243 | * taking the PDM lock, this is currently only used by CPUM to cache the APIC
|
---|
244 | * base once (during init./load state), all other callers should use
|
---|
245 | * PDMApicGetBase() and not this function.
|
---|
246 | *
|
---|
247 | * @returns VBox status code.
|
---|
248 | * @param pVM Pointer to the VMCPU.
|
---|
249 | * @param pu64Base Where to store the APIC base.
|
---|
250 | */
|
---|
251 | VMMDECL(int) PDMApicGetBase(PVMCPU pVCpu, uint64_t *pu64Base)
|
---|
252 | {
|
---|
253 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
254 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
255 | {
|
---|
256 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase));
|
---|
257 | pdmLock(pVM);
|
---|
258 | *pu64Base = pVM->pdm.s.Apic.CTX_SUFF(pfnGetBase)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
|
---|
259 | pdmUnlock(pVM);
|
---|
260 | return VINF_SUCCESS;
|
---|
261 | }
|
---|
262 | *pu64Base = 0;
|
---|
263 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
264 | }
|
---|
265 |
|
---|
266 |
|
---|
267 | /**
|
---|
268 | * Check if the APIC has a pending interrupt/if a TPR change would active one.
|
---|
269 | *
|
---|
270 | * @returns VINF_SUCCESS or VERR_PDM_NO_APIC_INSTANCE.
|
---|
271 | * @param pVCpu Pointer to the VMCPU.
|
---|
272 | * @param pfPending Pending state (out).
|
---|
273 | */
|
---|
274 | VMM_INT_DECL(int) PDMApicHasPendingIrq(PVMCPU pVCpu, bool *pfPending)
|
---|
275 | {
|
---|
276 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
277 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
278 | {
|
---|
279 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
|
---|
280 | pdmLock(pVM);
|
---|
281 | *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu,
|
---|
282 | NULL /* pu8PendingIrq */);
|
---|
283 | pdmUnlock(pVM);
|
---|
284 | return VINF_SUCCESS;
|
---|
285 | }
|
---|
286 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
287 | }
|
---|
288 |
|
---|
289 |
|
---|
290 | /**
|
---|
291 | * Set the TPR (task priority register?).
|
---|
292 | *
|
---|
293 | * @returns VBox status code.
|
---|
294 | * @param pVCpu Pointer to the VMCPU.
|
---|
295 | * @param u8TPR The new TPR.
|
---|
296 | */
|
---|
297 | VMMDECL(int) PDMApicSetTPR(PVMCPU pVCpu, uint8_t u8TPR)
|
---|
298 | {
|
---|
299 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
300 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
301 | {
|
---|
302 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR));
|
---|
303 | pdmLock(pVM);
|
---|
304 | pVM->pdm.s.Apic.CTX_SUFF(pfnSetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu, u8TPR);
|
---|
305 | pdmUnlock(pVM);
|
---|
306 | return VINF_SUCCESS;
|
---|
307 | }
|
---|
308 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
309 | }
|
---|
310 |
|
---|
311 |
|
---|
312 | /**
|
---|
313 | * Get the TPR (task priority register).
|
---|
314 | *
|
---|
315 | * @returns The current TPR.
|
---|
316 | * @param pVCpu Pointer to the VMCPU.
|
---|
317 | * @param pu8TPR Where to store the TRP.
|
---|
318 | * @param pfPending Pending interrupt state (out).
|
---|
319 | * @param pu8PendingIrq Where to store the highest-priority pending IRQ
|
---|
320 | * (optional, can be NULL) (out).
|
---|
321 | *
|
---|
322 | * @remarks No-long-jump zone!!!
|
---|
323 | */
|
---|
324 | VMMDECL(int) PDMApicGetTPR(PVMCPU pVCpu, uint8_t *pu8TPR, bool *pfPending, uint8_t *pu8PendingIrq)
|
---|
325 | {
|
---|
326 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
327 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
328 | {
|
---|
329 | /*
|
---|
330 | * Note! We don't acquire the PDM lock here as we're just reading
|
---|
331 | * information. Doing so causes massive contention as this
|
---|
332 | * function is called very often by each and every VCPU.
|
---|
333 | */
|
---|
334 | Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR));
|
---|
335 | *pu8TPR = pVM->pdm.s.Apic.CTX_SUFF(pfnGetTPR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu);
|
---|
336 | if (pfPending)
|
---|
337 | {
|
---|
338 | *pfPending = pVM->pdm.s.Apic.CTX_SUFF(pfnHasPendingIrq)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu->idCpu,
|
---|
339 | pu8PendingIrq);
|
---|
340 | }
|
---|
341 | return VINF_SUCCESS;
|
---|
342 | }
|
---|
343 | *pu8TPR = 0;
|
---|
344 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
345 | }
|
---|
346 |
|
---|
347 |
|
---|
348 | /**
|
---|
349 | * Write a MSR in APIC range.
|
---|
350 | *
|
---|
351 | * @returns VBox status code.
|
---|
352 | * @param pVM Pointer to the VM.
|
---|
353 | * @param iCpu Target CPU.
|
---|
354 | * @param u32Reg MSR to write.
|
---|
355 | * @param u64Value Value to write.
|
---|
356 | */
|
---|
357 | VMM_INT_DECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)
|
---|
358 | {
|
---|
359 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
360 | {
|
---|
361 | AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR));
|
---|
362 | return pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);
|
---|
363 | }
|
---|
364 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
365 | }
|
---|
366 |
|
---|
367 |
|
---|
368 | /**
|
---|
369 | * Read a MSR in APIC range.
|
---|
370 | *
|
---|
371 | * @returns VBox status code.
|
---|
372 | * @param pVM Pointer to the VM.
|
---|
373 | * @param iCpu Target CPU.
|
---|
374 | * @param u32Reg MSR to read.
|
---|
375 | * @param pu64Value Value read.
|
---|
376 | */
|
---|
377 | VMM_INT_DECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)
|
---|
378 | {
|
---|
379 | if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns))
|
---|
380 | {
|
---|
381 | AssertPtr(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR));
|
---|
382 | int rc = pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);
|
---|
383 | return rc;
|
---|
384 | }
|
---|
385 | return VERR_PDM_NO_APIC_INSTANCE;
|
---|
386 | }
|
---|
387 |
|
---|
388 |
|
---|
389 | /**
|
---|
390 | * Locks PDM.
|
---|
391 | * This might call back to Ring-3 in order to deal with lock contention in GC and R3.
|
---|
392 | *
|
---|
393 | * @param pVM Pointer to the VM.
|
---|
394 | */
|
---|
395 | void pdmLock(PVM pVM)
|
---|
396 | {
|
---|
397 | #ifdef IN_RING3
|
---|
398 | int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_IGNORED);
|
---|
399 | #else
|
---|
400 | int rc = PDMCritSectEnter(&pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
|
---|
401 | if (rc == VERR_GENERAL_FAILURE)
|
---|
402 | rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
|
---|
403 | #endif
|
---|
404 | AssertRC(rc);
|
---|
405 | }
|
---|
406 |
|
---|
407 |
|
---|
408 | /**
|
---|
409 | * Locks PDM but don't go to ring-3 if it's owned by someone.
|
---|
410 | *
|
---|
411 | * @returns VINF_SUCCESS on success.
|
---|
412 | * @returns rc if we're in GC or R0 and can't get the lock.
|
---|
413 | * @param pVM Pointer to the VM.
|
---|
414 | * @param rc The RC to return in GC or R0 when we can't get the lock.
|
---|
415 | */
|
---|
416 | int pdmLockEx(PVM pVM, int rc)
|
---|
417 | {
|
---|
418 | return PDMCritSectEnter(&pVM->pdm.s.CritSect, rc);
|
---|
419 | }
|
---|
420 |
|
---|
421 |
|
---|
422 | /**
|
---|
423 | * Unlocks PDM.
|
---|
424 | *
|
---|
425 | * @param pVM Pointer to the VM.
|
---|
426 | */
|
---|
427 | void pdmUnlock(PVM pVM)
|
---|
428 | {
|
---|
429 | PDMCritSectLeave(&pVM->pdm.s.CritSect);
|
---|
430 | }
|
---|
431 |
|
---|
432 |
|
---|
433 | /**
|
---|
434 | * Converts ring 3 VMM heap pointer to a guest physical address
|
---|
435 | *
|
---|
436 | * @returns VBox status code.
|
---|
437 | * @param pVM Pointer to the VM.
|
---|
438 | * @param pv Ring-3 pointer.
|
---|
439 | * @param pGCPhys GC phys address (out).
|
---|
440 | */
|
---|
441 | VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
|
---|
442 | {
|
---|
443 | /* Don't assert here as this is called before we can catch ring-0 assertions. */
|
---|
444 | if (RT_UNLIKELY((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap >= pVM->pdm.s.cbVMMDevHeap))
|
---|
445 | {
|
---|
446 | Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
|
---|
447 | pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
|
---|
448 | return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
|
---|
449 | }
|
---|
450 |
|
---|
451 | *pGCPhys = (pVM->pdm.s.GCPhysVMMDevHeap + ((RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap));
|
---|
452 | return VINF_SUCCESS;
|
---|
453 | }
|
---|
454 |
|
---|
455 | /**
|
---|
456 | * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
|
---|
457 | *
|
---|
458 | * @returns dev heap enabled status (true/false)
|
---|
459 | * @param pVM Pointer to the VM.
|
---|
460 | */
|
---|
461 | VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
|
---|
462 | {
|
---|
463 | return (pVM->pdm.s.pvVMMDevHeap != NULL);
|
---|
464 | }
|
---|