VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PDMAll.cpp@ 90803

Last change on this file since 90803 was 90436, checked in by vboxsync, 3 years ago

VMM,Dev*: Handle PDMCritSectEnter failures in relation to the PDM critsect. bugref:6695
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1/* $Id: PDMAll.cpp 90436 2021-07-30 16:03:48Z vboxsync $ */
2/** @file
3 * PDM Critical Sections
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/vmcc.h>
27#include <VBox/err.h>
28#include <VBox/vmm/apic.h>
29
30#include <VBox/log.h>
31#include <iprt/asm.h>
32#include <iprt/assert.h>
33
34#include "PDMInline.h"
35#include "dtrace/VBoxVMM.h"
36
37
38
39/**
40 * Gets the pending interrupt.
41 *
42 * @returns VBox status code.
43 * @retval VINF_SUCCESS on success.
44 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but
45 * can't be delivered due to TPR priority.
46 * @retval VERR_NO_DATA if there is no interrupt to be delivered (either APIC
47 * has been software-disabled since it flagged something was pending,
48 * or other reasons).
49 *
50 * @param pVCpu The cross context virtual CPU structure.
51 * @param pu8Interrupt Where to store the interrupt.
52 */
53VMMDECL(int) PDMGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Interrupt)
54{
55 /*
56 * The local APIC has a higher priority than the PIC.
57 */
58 int rc = VERR_NO_DATA;
59 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
60 {
61 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
62 uint32_t uTagSrc;
63 rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
64 if (RT_SUCCESS(rc))
65 {
66 if (rc == VINF_SUCCESS)
67 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), *pu8Interrupt);
68 return rc;
69 }
70 /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
71 interrupts shouldn't prevent ExtINT from being delivered. */
72 }
73
74 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
75 pdmLock(pVM);
76
77 /*
78 * Check the PIC.
79 */
80 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
81 {
82 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
83 Assert(pVM->pdm.s.Pic.CTX_SUFF(pDevIns));
84 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt));
85 uint32_t uTagSrc;
86 int i = pVM->pdm.s.Pic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), &uTagSrc);
87 AssertMsg(i <= 255 && i >= 0, ("i=%d\n", i));
88 if (i >= 0)
89 {
90 pdmUnlock(pVM);
91 *pu8Interrupt = (uint8_t)i;
92 VBOXVMM_PDM_IRQ_GET(pVCpu, RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc), i);
93 return VINF_SUCCESS;
94 }
95 }
96
97 /*
98 * One scenario where we may possibly get here is if the APIC signaled a pending interrupt,
99 * got an APIC MMIO/MSR VM-exit which disabled the APIC. We could, in theory, clear the APIC
100 * force-flag from all the places which disables the APIC but letting PDMGetInterrupt() fail
101 * without returning a valid interrupt still needs to be handled for the TPR masked case,
102 * so we shall just handle it here regardless if we choose to update the APIC code in the future.
103 */
104
105 pdmUnlock(pVM);
106 return rc;
107}
108
109
110/**
111 * Sets the pending interrupt coming from ISA source or HPET.
112 *
113 * @returns VBox status code.
114 * @param pVM The cross context VM structure.
115 * @param u8Irq The IRQ line.
116 * @param u8Level The new level.
117 * @param uTagSrc The IRQ tag and source tracer ID.
118 */
119VMMDECL(int) PDMIsaSetIrq(PVMCC pVM, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
120{
121 pdmLock(pVM);
122
123 /** @todo put the IRQ13 code elsewhere to avoid this unnecessary bloat. */
124 if (!uTagSrc && (u8Level & PDM_IRQ_LEVEL_HIGH)) /* FPU IRQ */
125 {
126 if (u8Level == PDM_IRQ_LEVEL_HIGH)
127 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), 0, 0);
128 else
129 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), 0, 0);
130 }
131
132 int rc = VERR_PDM_NO_PIC_INSTANCE;
133/** @todo r=bird: This code is incorrect, as it ASSUMES the PIC and I/O APIC
134 * are always ring-0 enabled! */
135 if (pVM->pdm.s.Pic.CTX_SUFF(pDevIns))
136 {
137 Assert(pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq));
138 pVM->pdm.s.Pic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.Pic.CTX_SUFF(pDevIns), u8Irq, u8Level, uTagSrc);
139 rc = VINF_SUCCESS;
140 }
141
142 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
143 {
144 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
145
146 /*
147 * Apply Interrupt Source Override rules.
148 * See ACPI 4.0 specification 5.2.12.4 and 5.2.12.5 for details on
149 * interrupt source override.
150 * Shortly, ISA IRQ0 is electically connected to pin 2 on IO-APIC, and some OSes,
151 * notably recent OS X rely upon this configuration.
152 * If changing, also update override rules in MADT and MPS.
153 */
154 /* ISA IRQ0 routed to pin 2, all others ISA sources are identity mapped */
155 if (u8Irq == 0)
156 u8Irq = 2;
157
158 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), NIL_PCIBDF, u8Irq, u8Level, uTagSrc);
159 rc = VINF_SUCCESS;
160 }
161
162 if (!uTagSrc && u8Level == PDM_IRQ_LEVEL_LOW)
163 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), 0, 0);
164 pdmUnlock(pVM);
165 return rc;
166}
167
168
169/**
170 * Sets the pending I/O APIC interrupt.
171 *
172 * @returns VBox status code.
173 * @param pVM The cross context VM structure.
174 * @param u8Irq The IRQ line.
175 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
176 * Pass NIL_PCIBDF when it's not a PCI device or interrupt.
177 * @param u8Level The new level.
178 * @param uTagSrc The IRQ tag and source tracer ID.
179 */
180VMM_INT_DECL(int) PDMIoApicSetIrq(PVM pVM, PCIBDF uBusDevFn, uint8_t u8Irq, uint8_t u8Level, uint32_t uTagSrc)
181{
182 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
183 {
184 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq));
185 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetIrq)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), uBusDevFn, u8Irq, u8Level, uTagSrc);
186 return VINF_SUCCESS;
187 }
188 return VERR_PDM_NO_PIC_INSTANCE;
189}
190
191
192/**
193 * Broadcasts an EOI to the I/O APIC(s).
194 *
195 * @param pVM The cross context VM structure.
196 * @param uVector The interrupt vector corresponding to the EOI.
197 */
198VMM_INT_DECL(void) PDMIoApicBroadcastEoi(PVMCC pVM, uint8_t uVector)
199{
200 /*
201 * At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
202 * multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs.
203 */
204 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
205#ifdef IN_RING0
206 if (pIoApic->pDevInsR0)
207 {
208 Assert(pIoApic->pfnSetEoiR0);
209 pIoApic->pfnSetEoiR0(pIoApic->pDevInsR0, uVector);
210 }
211 else if (pIoApic->pDevInsR3)
212 {
213 /* Queue for ring-3 execution. */
214 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
215 if (pTask)
216 {
217 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_EOI;
218 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
219 pTask->u.IoApicSetEoi.uVector = uVector;
220 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
221 }
222 else
223 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
224 }
225#else
226 if (pIoApic->pDevInsR3)
227 {
228 Assert(pIoApic->pfnSetEoiR3);
229 pIoApic->pfnSetEoiR3(pIoApic->pDevInsR3, uVector);
230 }
231#endif
232}
233
234
235/**
236 * Send a MSI to an I/O APIC.
237 *
238 * @param pVM The cross context VM structure.
239 * @param uBusDevFn The bus:device:function of the device initiating the MSI.
240 * @param pMsi The MSI to send.
241 * @param uTagSrc The IRQ tag and source tracer ID.
242 */
243VMM_INT_DECL(void) PDMIoApicSendMsi(PVMCC pVM, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
244{
245 PCPDMIOAPIC pIoApic = &pVM->pdm.s.IoApic;
246#ifdef IN_RING0
247 if (pIoApic->pDevInsR0)
248 pIoApic->pfnSendMsiR0(pIoApic->pDevInsR0, uBusDevFn, pMsi, uTagSrc);
249 else if (pIoApic->pDevInsR3)
250 {
251 /* Queue for ring-3 execution. */
252 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
253 if (pTask)
254 {
255 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SEND_MSI;
256 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
257 pTask->u.IoApicSendMsi.uBusDevFn = uBusDevFn;
258 pTask->u.IoApicSendMsi.Msi = *pMsi;
259 pTask->u.IoApicSendMsi.uTagSrc = uTagSrc;
260 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
261 }
262 else
263 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
264 }
265#else
266 if (pIoApic->pDevInsR3)
267 {
268 Assert(pIoApic->pfnSendMsiR3);
269 pIoApic->pfnSendMsiR3(pIoApic->pDevInsR3, uBusDevFn, pMsi, uTagSrc);
270 }
271#endif
272}
273
274
275
276/**
277 * Returns the presence of an IO-APIC.
278 *
279 * @returns true if an IO-APIC is present.
280 * @param pVM The cross context VM structure.
281 */
282VMM_INT_DECL(bool) PDMHasIoApic(PVM pVM)
283{
284 return pVM->pdm.s.IoApic.pDevInsR3 != NULL;
285}
286
287
288/**
289 * Returns the presence of an APIC.
290 *
291 * @returns true if an APIC is present.
292 * @param pVM The cross context VM structure.
293 */
294VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
295{
296 return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
297}
298
299
300/**
301 * Locks PDM.
302 *
303 * This might call back to Ring-3 in order to deal with lock contention in RC
304 * and R0.
305 *
306 * @param pVM The cross context VM structure.
307 */
308void pdmLock(PVMCC pVM)
309{
310#ifdef IN_RING3
311 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VERR_IGNORED);
312 AssertRC(rc);
313#else
314 int rc = PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, VERR_GENERAL_FAILURE);
315 if (RT_SUCCESS(rc))
316 { /* likely */ }
317 else
318 {
319 if (rc == VERR_GENERAL_FAILURE)
320 rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PDM_LOCK, 0);
321 PDM_CRITSECT_RELEASE_ASSERT_RC(pVM, &pVM->pdm.s.CritSect, rc);
322 }
323#endif
324}
325
326
327/**
328 * Locks PDM but don't go to ring-3 if it's owned by someone.
329 *
330 * @returns VINF_SUCCESS on success.
331 * @returns rc if we're in GC or R0 and can't get the lock.
332 * @param pVM The cross context VM structure.
333 * @param rcBusy The RC to return in GC or R0 when we can't get the lock.
334 */
335int pdmLockEx(PVMCC pVM, int rcBusy)
336{
337 return PDMCritSectEnter(pVM, &pVM->pdm.s.CritSect, rcBusy);
338}
339
340
341/**
342 * Unlocks PDM.
343 *
344 * @param pVM The cross context VM structure.
345 */
346void pdmUnlock(PVMCC pVM)
347{
348 PDMCritSectLeave(pVM, &pVM->pdm.s.CritSect);
349}
350
351
352/**
353 * Checks if this thread is owning the PDM lock.
354 *
355 * @returns @c true if the lock is taken, @c false otherwise.
356 * @param pVM The cross context VM structure.
357 */
358bool pdmLockIsOwner(PVMCC pVM)
359{
360 return PDMCritSectIsOwner(pVM, &pVM->pdm.s.CritSect);
361}
362
363
364/**
365 * Converts ring 3 VMM heap pointer to a guest physical address
366 *
367 * @returns VBox status code.
368 * @param pVM The cross context VM structure.
369 * @param pv Ring-3 pointer.
370 * @param pGCPhys GC phys address (out).
371 */
372VMM_INT_DECL(int) PDMVmmDevHeapR3ToGCPhys(PVM pVM, RTR3PTR pv, RTGCPHYS *pGCPhys)
373{
374 if (RT_LIKELY(pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS))
375 {
376 RTR3UINTPTR const offHeap = (RTR3UINTPTR)pv - (RTR3UINTPTR)pVM->pdm.s.pvVMMDevHeap;
377 if (RT_LIKELY(offHeap < pVM->pdm.s.cbVMMDevHeap))
378 {
379 *pGCPhys = pVM->pdm.s.GCPhysVMMDevHeap + offHeap;
380 return VINF_SUCCESS;
381 }
382
383 /* Don't assert here as this is called before we can catch ring-0 assertions. */
384 Log(("PDMVmmDevHeapR3ToGCPhys: pv=%p pvVMMDevHeap=%p cbVMMDevHeap=%#x\n",
385 pv, pVM->pdm.s.pvVMMDevHeap, pVM->pdm.s.cbVMMDevHeap));
386 }
387 else
388 Log(("PDMVmmDevHeapR3ToGCPhys: GCPhysVMMDevHeap=%RGp (pv=%p)\n", pVM->pdm.s.GCPhysVMMDevHeap, pv));
389 return VERR_PDM_DEV_HEAP_R3_TO_GCPHYS;
390}
391
392
393/**
394 * Checks if the vmm device heap is enabled (== vmm device's pci region mapped)
395 *
396 * @returns dev heap enabled status (true/false)
397 * @param pVM The cross context VM structure.
398 */
399VMM_INT_DECL(bool) PDMVmmDevHeapIsEnabled(PVM pVM)
400{
401 return pVM->pdm.s.GCPhysVMMDevHeap != NIL_RTGCPHYS;
402}
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