PATMAll.cpp@ 47427

Last change on this file since 47427 was 47427, checked in by vboxsync, 11 years ago
PATM,IEM: Added interface for safely and quickly reading patch code.
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1	/* $Id: PATMAll.cpp 47427 2013-07-26 16:06:01Z vboxsync $ */
2	/** @file
3	* PATM - The Patch Manager, all contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_PATM
22	#include <VBox/vmm/patm.h>
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/selm.h>
27	#include <VBox/vmm/mm.h>
28	#include "PATMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/vmm.h>
31	#include "PATMA.h"
32
33	#include <VBox/dis.h>
34	#include <VBox/disopcode.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39
40
41	/**
42	* Load virtualized flags.
43	*
44	* This function is called from CPUMRawEnter(). It doesn't have to update the
45	* IF and IOPL eflags bits, the caller will enforce those to set and 0 respectively.
46	*
47	* @param pVM Pointer to the VM.
48	* @param pCtxCore The cpu context core.
49	* @see pg_raw
50	*/
51	VMM_INT_DECL(void) PATMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore)
52	{
53	Assert(!HMIsEnabled(pVM));
54
55	/*
56	* Currently we don't bother to check whether PATM is enabled or not.
57	* For all cases where it isn't, IOPL will be safe and IF will be set.
58	*/
59	uint32_t efl = pCtxCore->eflags.u32;
60	CTXSUFF(pVM->patm.s.pGCState)->uVMFlags = efl & PATM_VIRTUAL_FLAGS_MASK;
61
62	AssertMsg((efl & X86_EFL_IF) \|\| PATMShouldUseRawMode(pVM, (RTRCPTR)pCtxCore->eip),
63	("X86_EFL_IF is clear and PATM is disabled! (eip=%RRv eflags=%08x fPATM=%d pPATMGC=%RRv-%RRv\n",
64	pCtxCore->eip, pCtxCore->eflags.u32, PATMIsEnabled(pVM), pVM->patm.s.pPatchMemGC,
65	pVM->patm.s.pPatchMemGC + pVM->patm.s.cbPatchMem));
66
67	AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF \|\| PATMIsPatchGCAddr(pVM, pCtxCore->eip),
68	("fPIF=%d eip=%RRv\n", pVM->patm.s.CTXSUFF(pGCState)->fPIF, pCtxCore->eip));
69
70	efl &= ~PATM_VIRTUAL_FLAGS_MASK;
71	efl \|= X86_EFL_IF;
72	pCtxCore->eflags.u32 = efl;
73
74	#ifdef IN_RING3
75	# ifdef PATM_EMULATE_SYSENTER
76	PCPUMCTX pCtx;
77
78	/* Check if the sysenter handler has changed. */
79	pCtx = CPUMQueryGuestCtxPtr(pVM);
80	if ( pCtx->SysEnter.cs != 0
81	&& pCtx->SysEnter.eip != 0
82	)
83	{
84	if (pVM->patm.s.pfnSysEnterGC != (RTRCPTR)pCtx->SysEnter.eip)
85	{
86	pVM->patm.s.pfnSysEnterPatchGC = 0;
87	pVM->patm.s.pfnSysEnterGC = 0;
88
89	Log2(("PATMRawEnter: installing sysenter patch for %RRv\n", pCtx->SysEnter.eip));
90	pVM->patm.s.pfnSysEnterPatchGC = PATMR3QueryPatchGCPtr(pVM, pCtx->SysEnter.eip);
91	if (pVM->patm.s.pfnSysEnterPatchGC == 0)
92	{
93	rc = PATMR3InstallPatch(pVM, pCtx->SysEnter.eip, PATMFL_SYSENTER \| PATMFL_CODE32);
94	if (rc == VINF_SUCCESS)
95	{
96	pVM->patm.s.pfnSysEnterPatchGC = PATMR3QueryPatchGCPtr(pVM, pCtx->SysEnter.eip);
97	pVM->patm.s.pfnSysEnterGC = (RTRCPTR)pCtx->SysEnter.eip;
98	Assert(pVM->patm.s.pfnSysEnterPatchGC);
99	}
100	}
101	else
102	pVM->patm.s.pfnSysEnterGC = (RTRCPTR)pCtx->SysEnter.eip;
103	}
104	}
105	else
106	{
107	pVM->patm.s.pfnSysEnterPatchGC = 0;
108	pVM->patm.s.pfnSysEnterGC = 0;
109	}
110	# endif /* PATM_EMULATE_SYSENTER */
111	#endif
112	}
113
114
115	/**
116	* Restores virtualized flags.
117	*
118	* This function is called from CPUMRawLeave(). It will update the eflags register.
119	*
120	** @note Only here we are allowed to switch back to guest code (without a special reason such as a trap in patch code)!!
121	*
122	* @param pVM Pointer to the VM.
123	* @param pCtxCore The cpu context core.
124	* @param rawRC Raw mode return code
125	* @see @ref pg_raw
126	*/
127	VMM_INT_DECL(void) PATMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rawRC)
128	{
129	Assert(!HMIsEnabled(pVM));
130	bool fPatchCode = PATMIsPatchGCAddr(pVM, pCtxCore->eip);
131
132	/*
133	* We will only be called if PATMRawEnter was previously called.
134	*/
135	uint32_t efl = pCtxCore->eflags.u32;
136	efl = (efl & ~PATM_VIRTUAL_FLAGS_MASK) \| (CTXSUFF(pVM->patm.s.pGCState)->uVMFlags & PATM_VIRTUAL_FLAGS_MASK);
137	pCtxCore->eflags.u32 = efl;
138	CTXSUFF(pVM->patm.s.pGCState)->uVMFlags = X86_EFL_IF;
139
140	AssertReleaseMsg((efl & X86_EFL_IF) \|\| fPatchCode \|\| rawRC == VINF_PATM_PENDING_IRQ_AFTER_IRET \|\| RT_FAILURE(rawRC), ("Inconsistent state at %RRv rc=%Rrc\n", pCtxCore->eip, rawRC));
141	AssertReleaseMsg(CTXSUFF(pVM->patm.s.pGCState)->fPIF \|\| fPatchCode \|\| RT_FAILURE(rawRC), ("fPIF=%d eip=%RRv rc=%Rrc\n", CTXSUFF(pVM->patm.s.pGCState)->fPIF, pCtxCore->eip, rawRC));
142
143	#ifdef IN_RING3
144	if ( (efl & X86_EFL_IF)
145	&& fPatchCode)
146	{
147	if ( rawRC < VINF_PATM_LEAVE_RC_FIRST
148	\|\| rawRC > VINF_PATM_LEAVE_RC_LAST)
149	{
150	/*
151	* Golden rules:
152	* - Don't interrupt special patch streams that replace special instructions
153	* - Don't break instruction fusing (sti, pop ss, mov ss)
154	* - Don't go back to an instruction that has been overwritten by a patch jump
155	* - Don't interrupt an idt handler on entry (1st instruction); technically incorrect
156	*
157	*/
158	if (CTXSUFF(pVM->patm.s.pGCState)->fPIF == 1) /* consistent patch instruction state */
159	{
160	PATMTRANSSTATE enmState;
161	RTRCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtxCore->eip, &enmState);
162
163	AssertRelease(pOrgInstrGC);
164
165	Assert(enmState != PATMTRANS_OVERWRITTEN);
166	if (enmState == PATMTRANS_SAFE)
167	{
168	Assert(!patmFindActivePatchByEntrypoint(pVM, pOrgInstrGC));
169	Log(("Switchback from %RRv to %RRv (Psp=%x)\n", pCtxCore->eip, pOrgInstrGC, CTXSUFF(pVM->patm.s.pGCState)->Psp));
170	STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBack);
171	pCtxCore->eip = pOrgInstrGC;
172	fPatchCode = false; /* to reset the stack ptr */
173
174	CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts = 0; /* reset this pointer; safe otherwise the state would be PATMTRANS_INHIBITIRQ */
175	}
176	else
177	{
178	LogFlow(("Patch address %RRv can't be interrupted (state=%d)!\n", pCtxCore->eip, enmState));
179	STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBackFail);
180	}
181	}
182	else
183	{
184	LogFlow(("Patch address %RRv can't be interrupted (fPIF=%d)!\n", pCtxCore->eip, CTXSUFF(pVM->patm.s.pGCState)->fPIF));
185	STAM_COUNTER_INC(&pVM->patm.s.StatSwitchBackFail);
186	}
187	}
188	}
189	#else /* !IN_RING3 */
190	/*
191	* When leaving raw-mode state while IN_RC, it's generally for interpreting
192	* a single original guest instruction.
193	*/
194	AssertMsg(!fPatchCode, ("eip=%RRv\n", pCtxCore->eip));
195	#endif /* !IN_RING3 */
196
197	if (!fPatchCode)
198	{
199	if (CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts == (RTRCPTR)pCtxCore->eip)
200	{
201	EMSetInhibitInterruptsPC(VMMGetCpu0(pVM), pCtxCore->eip);
202	}
203	CTXSUFF(pVM->patm.s.pGCState)->GCPtrInhibitInterrupts = 0;
204
205	/* Reset the stack pointer to the top of the stack. */
206	#ifdef DEBUG
207	if (CTXSUFF(pVM->patm.s.pGCState)->Psp != PATM_STACK_SIZE)
208	{
209	LogFlow(("PATMRawLeave: Reset PATM stack (Psp = %x)\n", CTXSUFF(pVM->patm.s.pGCState)->Psp));
210	}
211	#endif
212	CTXSUFF(pVM->patm.s.pGCState)->Psp = PATM_STACK_SIZE;
213	}
214	}
215
216	/**
217	* Get the EFLAGS.
218	* This is a worker for CPUMRawGetEFlags().
219	*
220	* @returns The eflags.
221	* @param pVM Pointer to the VM.
222	* @param pCtxCore The context core.
223	*/
224	VMM_INT_DECL(uint32_t) PATMRawGetEFlags(PVM pVM, PCCPUMCTXCORE pCtxCore)
225	{
226	Assert(!HMIsEnabled(pVM));
227	uint32_t efl = pCtxCore->eflags.u32;
228	efl &= ~PATM_VIRTUAL_FLAGS_MASK;
229	efl \|= pVM->patm.s.CTXSUFF(pGCState)->uVMFlags & PATM_VIRTUAL_FLAGS_MASK;
230	return efl;
231	}
232
233	/**
234	* Updates the EFLAGS.
235	* This is a worker for CPUMRawSetEFlags().
236	*
237	* @param pVM Pointer to the VM.
238	* @param pCtxCore The context core.
239	* @param efl The new EFLAGS value.
240	*/
241	VMM_INT_DECL(void) PATMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t efl)
242	{
243	Assert(!HMIsEnabled(pVM));
244	pVM->patm.s.CTXSUFF(pGCState)->uVMFlags = efl & PATM_VIRTUAL_FLAGS_MASK;
245	efl &= ~PATM_VIRTUAL_FLAGS_MASK;
246	efl \|= X86_EFL_IF;
247	pCtxCore->eflags.u32 = efl;
248	}
249
250	/**
251	* Check if we must use raw mode (patch code being executed)
252	*
253	* @param pVM Pointer to the VM.
254	* @param pAddrGC Guest context address
255	*/
256	VMM_INT_DECL(bool) PATMShouldUseRawMode(PVM pVM, RTRCPTR pAddrGC)
257	{
258	return ( PATMIsEnabled(pVM)
259	&& ((pAddrGC >= (RTRCPTR)pVM->patm.s.pPatchMemGC && pAddrGC < (RTRCPTR)((RTRCUINTPTR)pVM->patm.s.pPatchMemGC + pVM->patm.s.cbPatchMem)))) ? true : false;
260	}
261
262	/**
263	* Returns the guest context pointer and size of the GC context structure
264	*
265	* @returns VBox status code.
266	* @param pVM Pointer to the VM.
267	*/
268	VMM_INT_DECL(RCPTRTYPE(PPATMGCSTATE)) PATMGetGCState(PVM pVM)
269	{
270	AssertReturn(!HMIsEnabled(pVM), NIL_RTRCPTR);
271	return pVM->patm.s.pGCStateGC;
272	}
273
274	/**
275	* Checks whether the GC address is part of our patch region
276	*
277	* @returns VBox status code.
278	* @param pVM Pointer to the VM.
279	* @param pAddrGC Guest context address
280	* @internal
281	*/
282	VMMDECL(bool) PATMIsPatchGCAddr(PVM pVM, RTRCUINTPTR pAddrGC)
283	{
284	return (PATMIsEnabled(pVM) && pAddrGC - (RTRCUINTPTR)pVM->patm.s.pPatchMemGC < pVM->patm.s.cbPatchMem) ? true : false;
285	}
286
287	/**
288	* Reads patch code.
289	*
290	* @returns
291	* @retval VINF_SUCCESS on success.
292	* @retval VERR_PATCH_NOT_FOUND if the request is entirely outside the patch
293	* code.
294	*
295	* @param pVM The cross context VM structure.
296	* @param GCPtrPatchCode The patch address to start reading at.
297	* @param pvDst Where to return the patch code.
298	* @param cbToRead Number of bytes to read.
299	* @param pcbRead Where to return the actual number of bytes we've
300	* read. Optional.
301	*/
302	VMM_INT_DECL(int) PATMReadPatchCode(PVM pVM, RTGCPTR GCPtrPatchCode, void pvDst, size_t cbToRead, size_t pcbRead)
303	{
304	/* Shortcut. */
305	if (!PATMIsEnabled(pVM))
306	return VERR_PATCH_NOT_FOUND;
307	Assert(!HMIsEnabled(pVM));
308
309	RTGCPTR offPatchedInstr = GCPtrPatchCode - (RTGCPTR32)pVM->patm.s.pPatchMemGC;
310	if (offPatchedInstr >= pVM->patm.s.cbPatchMem)
311	return VERR_PATCH_NOT_FOUND;
312
313	uint32_t cbMaxRead = pVM->patm.s.cbPatchMem - (uint32_t)offPatchedInstr;
314	if (cbToRead > cbMaxRead)
315	cbToRead = cbMaxRead;
316
317	#ifdef IN_RC
318	memcpy(pvDst, pVM->patm.s.pPatchMemGC + (uint32_t)offPatchedInstr, cbToRead);
319	#else
320	memcpy(pvDst, pVM->patm.s.pPatchMemHC + (uint32_t)offPatchedInstr, cbToRead);
321	#endif
322	if (pcbRead)
323	*pcbRead = cbToRead;
324	return VINF_SUCCESS;
325	}
326
327	/**
328	* Set parameters for pending MMIO patch operation
329	*
330	* @returns VBox status code.
331	* @param pDevIns Device instance.
332	* @param GCPhys MMIO physical address
333	* @param pCachedData GC pointer to cached data
334	*/
335	VMM_INT_DECL(int) PATMSetMMIOPatchInfo(PVM pVM, RTGCPHYS GCPhys, RTRCPTR pCachedData)
336	{
337	if (!HMIsEnabled(pVM))
338	{
339	pVM->patm.s.mmio.GCPhys = GCPhys;
340	pVM->patm.s.mmio.pCachedData = (RTRCPTR)pCachedData;
341	}
342
343	return VINF_SUCCESS;
344	}
345
346	/**
347	* Checks if the interrupt flag is enabled or not.
348	*
349	* @returns true if it's enabled.
350	* @returns false if it's disabled.
351	*
352	* @param pVM Pointer to the VM.
353	* @todo CPUM should wrap this, EM.cpp shouldn't call us.
354	*/
355	VMM_INT_DECL(bool) PATMAreInterruptsEnabled(PVM pVM)
356	{
357	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
358
359	return PATMAreInterruptsEnabledByCtxCore(pVM, CPUMCTX2CORE(pCtx));
360	}
361
362	/**
363	* Checks if the interrupt flag is enabled or not.
364	*
365	* @returns true if it's enabled.
366	* @returns false if it's disabled.
367	*
368	* @param pVM Pointer to the VM.
369	* @param pCtxCore CPU context
370	* @todo CPUM should wrap this, EM.cpp shouldn't call us.
371	*/
372	VMM_INT_DECL(bool) PATMAreInterruptsEnabledByCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
373	{
374	if (PATMIsEnabled(pVM))
375	{
376	Assert(!HMIsEnabled(pVM));
377	if (PATMIsPatchGCAddr(pVM, pCtxCore->eip))
378	return false;
379	}
380	return !!(pCtxCore->eflags.u32 & X86_EFL_IF);
381	}
382
383	/**
384	* Check if the instruction is patched as a duplicated function
385	*
386	* @returns patch record
387	* @param pVM Pointer to the VM.
388	* @param pInstrGC Guest context point to the instruction
389	*
390	*/
391	PPATMPATCHREC patmQueryFunctionPatch(PVM pVM, RTRCPTR pInstrGC)
392	{
393	PPATMPATCHREC pRec;
394
395	AssertCompile(sizeof(AVLOU32KEY) == sizeof(pInstrGC));
396	pRec = (PPATMPATCHREC)RTAvloU32Get(&CTXSUFF(pVM->patm.s.PatchLookupTree)->PatchTree, (AVLOU32KEY)pInstrGC);
397	if ( pRec
398	&& (pRec->patch.uState == PATCH_ENABLED)
399	&& (pRec->patch.flags & (PATMFL_DUPLICATE_FUNCTION\|PATMFL_CALLABLE_AS_FUNCTION))
400	)
401	return pRec;
402	return 0;
403	}
404
405	/**
406	* Checks if the int 3 was caused by a patched instruction
407	*
408	* @returns VBox status
409	*
410	* @param pVM Pointer to the VM.
411	* @param pInstrGC Instruction pointer
412	* @param pOpcode Original instruction opcode (out, optional)
413	* @param pSize Original instruction size (out, optional)
414	*/
415	VMM_INT_DECL(bool) PATMIsInt3Patch(PVM pVM, RTRCPTR pInstrGC, uint32_t pOpcode, uint32_t pSize)
416	{
417	PPATMPATCHREC pRec;
418	Assert(!HMIsEnabled(pVM));
419
420	pRec = (PPATMPATCHREC)RTAvloU32Get(&CTXSUFF(pVM->patm.s.PatchLookupTree)->PatchTree, (AVLOU32KEY)pInstrGC);
421	if ( pRec
422	&& (pRec->patch.uState == PATCH_ENABLED)
423	&& (pRec->patch.flags & (PATMFL_INT3_REPLACEMENT\|PATMFL_INT3_REPLACEMENT_BLOCK))
424	)
425	{
426	if (pOpcode) *pOpcode = pRec->patch.opcode;
427	if (pSize) *pSize = pRec->patch.cbPrivInstr;
428	return true;
429	}
430	return false;
431	}
432
433	/**
434	* Emulate sysenter, sysexit and syscall instructions
435	*
436	* @returns VBox status
437	*
438	* @param pVM Pointer to the VM.
439	* @param pCtxCore The relevant core context.
440	* @param pCpu Disassembly context
441	*/
442	VMMDECL(int) PATMSysCall(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu)
443	{
444	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpu0(pVM));
445	AssertReturn(!HMIsEnabled(pVM), VERR_PATM_HM_IPE);
446
447	if (pCpu->pCurInstr->uOpcode == OP_SYSENTER)
448	{
449	if ( pCtx->SysEnter.cs == 0
450	\|\| pRegFrame->eflags.Bits.u1VM
451	\|\| (pRegFrame->cs.Sel & X86_SEL_RPL) != 3
452	\|\| pVM->patm.s.pfnSysEnterPatchGC == 0
453	\|\| pVM->patm.s.pfnSysEnterGC != (RTRCPTR)(RTRCUINTPTR)pCtx->SysEnter.eip
454	\|\| !(PATMRawGetEFlags(pVM, pRegFrame) & X86_EFL_IF))
455	goto end;
456
457	Log2(("PATMSysCall: sysenter from %RRv to %RRv\n", pRegFrame->eip, pVM->patm.s.pfnSysEnterPatchGC));
458	/** @todo the base and limit are forced to 0 & 4G-1 resp. We assume the selector is wide open here. */
459	/** @note The Intel manual suggests that the OS is responsible for this. */
460	pRegFrame->cs.Sel = (pCtx->SysEnter.cs & ~X86_SEL_RPL) \| 1;
461	pRegFrame->eip = /** @todo ugly conversion! */(uint32_t)pVM->patm.s.pfnSysEnterPatchGC;
462	pRegFrame->ss.Sel = pRegFrame->cs.Sel + 8; /* SysEnter.cs + 8 */
463	pRegFrame->esp = pCtx->SysEnter.esp;
464	pRegFrame->eflags.u32 &= ~(X86_EFL_VM \| X86_EFL_RF);
465	pRegFrame->eflags.u32 \|= X86_EFL_IF;
466
467	/* Turn off interrupts. */
468	pVM->patm.s.CTXSUFF(pGCState)->uVMFlags &= ~X86_EFL_IF;
469
470	STAM_COUNTER_INC(&pVM->patm.s.StatSysEnter);
471
472	return VINF_SUCCESS;
473	}
474	if (pCpu->pCurInstr->uOpcode == OP_SYSEXIT)
475	{
476	if ( pCtx->SysEnter.cs == 0
477	\|\| (pRegFrame->cs.Sel & X86_SEL_RPL) != 1
478	\|\| pRegFrame->eflags.Bits.u1VM
479	\|\| !(PATMRawGetEFlags(pVM, pRegFrame) & X86_EFL_IF))
480	goto end;
481
482	Log2(("PATMSysCall: sysexit from %RRv to %RRv\n", pRegFrame->eip, pRegFrame->edx));
483
484	pRegFrame->cs.Sel = ((pCtx->SysEnter.cs + 16) & ~X86_SEL_RPL) \| 3;
485	pRegFrame->eip = pRegFrame->edx;
486	pRegFrame->ss.Sel = pRegFrame->cs.Sel + 8; /* SysEnter.cs + 24 */
487	pRegFrame->esp = pRegFrame->ecx;
488
489	STAM_COUNTER_INC(&pVM->patm.s.StatSysExit);
490
491	return VINF_SUCCESS;
492	}
493	if (pCpu->pCurInstr->uOpcode == OP_SYSCALL)
494	{
495	/** @todo implement syscall */
496	}
497	else
498	if (pCpu->pCurInstr->uOpcode == OP_SYSRET)
499	{
500	/** @todo implement sysret */
501	}
502
503	end:
504	return VINF_EM_RAW_RING_SWITCH;
505	}
506
507	/**
508	* Adds branch pair to the lookup cache of the particular branch instruction
509	*
510	* @returns VBox status
511	* @param pVM Pointer to the VM.
512	* @param pJumpTableGC Pointer to branch instruction lookup cache
513	* @param pBranchTarget Original branch target
514	* @param pRelBranchPatch Relative duplicated function address
515	*/
516	int patmAddBranchToLookupCache(PVM pVM, RTRCPTR pJumpTableGC, RTRCPTR pBranchTarget, RTRCUINTPTR pRelBranchPatch)
517	{
518	PPATCHJUMPTABLE pJumpTable;
519
520	Log(("PATMAddBranchToLookupCache: Adding (%RRv->%RRv (%RRv)) to table %RRv\n", pBranchTarget, pRelBranchPatch + pVM->patm.s.pPatchMemGC, pRelBranchPatch, pJumpTableGC));
521
522	AssertReturn(PATMIsPatchGCAddr(pVM, (RTRCUINTPTR)pJumpTableGC), VERR_INVALID_PARAMETER);
523
524	#ifdef IN_RC
525	pJumpTable = (PPATCHJUMPTABLE) pJumpTableGC;
526	#else
527	pJumpTable = (PPATCHJUMPTABLE) (pJumpTableGC - pVM->patm.s.pPatchMemGC + pVM->patm.s.pPatchMemHC);
528	#endif
529	Log(("Nr addresses = %d, insert pos = %d\n", pJumpTable->cAddresses, pJumpTable->ulInsertPos));
530	if (pJumpTable->cAddresses < pJumpTable->nrSlots)
531	{
532	uint32_t i;
533
534	for (i=0;i<pJumpTable->nrSlots;i++)
535	{
536	if (pJumpTable->Slot[i].pInstrGC == 0)
537	{
538	pJumpTable->Slot[i].pInstrGC = pBranchTarget;
539	/* Relative address - eases relocation */
540	pJumpTable->Slot[i].pRelPatchGC = pRelBranchPatch;
541	pJumpTable->cAddresses++;
542	break;
543	}
544	}
545	AssertReturn(i < pJumpTable->nrSlots, VERR_INTERNAL_ERROR);
546	#ifdef VBOX_WITH_STATISTICS
547	STAM_COUNTER_INC(&pVM->patm.s.StatFunctionLookupInsert);
548	if (pVM->patm.s.StatU32FunctionMaxSlotsUsed < i)
549	pVM->patm.s.StatU32FunctionMaxSlotsUsed = i + 1;
550	#endif
551	}
552	else
553	{
554	/* Replace an old entry. */
555	/** @todo replacement strategy isn't really bright. change to something better if required. */
556	Assert(pJumpTable->ulInsertPos < pJumpTable->nrSlots);
557	Assert((pJumpTable->nrSlots & 1) == 0);
558
559	pJumpTable->ulInsertPos &= (pJumpTable->nrSlots-1);
560	pJumpTable->Slot[pJumpTable->ulInsertPos].pInstrGC = pBranchTarget;
561	/* Relative address - eases relocation */
562	pJumpTable->Slot[pJumpTable->ulInsertPos].pRelPatchGC = pRelBranchPatch;
563
564	pJumpTable->ulInsertPos = (pJumpTable->ulInsertPos+1) & (pJumpTable->nrSlots-1);
565
566	STAM_COUNTER_INC(&pVM->patm.s.StatFunctionLookupReplace);
567	}
568
569	return VINF_SUCCESS;
570	}
571
572
573	#if defined(VBOX_WITH_STATISTICS) \|\| defined(LOG_ENABLED)
574	/**
575	* Return the name of the patched instruction
576	*
577	* @returns instruction name
578	*
579	* @param opcode DIS instruction opcode
580	* @param fPatchFlags Patch flags
581	*/
582	const char *patmGetInstructionString(uint32_t opcode, uint32_t fPatchFlags)
583	{
584	const char *pszInstr = NULL;
585
586	switch (opcode)
587	{
588	case OP_CLI:
589	pszInstr = "cli";
590	break;
591	case OP_PUSHF:
592	pszInstr = "pushf";
593	break;
594	case OP_POPF:
595	pszInstr = "popf";
596	break;
597	case OP_STR:
598	pszInstr = "str";
599	break;
600	case OP_LSL:
601	pszInstr = "lsl";
602	break;
603	case OP_LAR:
604	pszInstr = "lar";
605	break;
606	case OP_SGDT:
607	pszInstr = "sgdt";
608	break;
609	case OP_SLDT:
610	pszInstr = "sldt";
611	break;
612	case OP_SIDT:
613	pszInstr = "sidt";
614	break;
615	case OP_SMSW:
616	pszInstr = "smsw";
617	break;
618	case OP_VERW:
619	pszInstr = "verw";
620	break;
621	case OP_VERR:
622	pszInstr = "verr";
623	break;
624	case OP_CPUID:
625	pszInstr = "cpuid";
626	break;
627	case OP_JMP:
628	pszInstr = "jmp";
629	break;
630	case OP_JO:
631	pszInstr = "jo";
632	break;
633	case OP_JNO:
634	pszInstr = "jno";
635	break;
636	case OP_JC:
637	pszInstr = "jc";
638	break;
639	case OP_JNC:
640	pszInstr = "jnc";
641	break;
642	case OP_JE:
643	pszInstr = "je";
644	break;
645	case OP_JNE:
646	pszInstr = "jne";
647	break;
648	case OP_JBE:
649	pszInstr = "jbe";
650	break;
651	case OP_JNBE:
652	pszInstr = "jnbe";
653	break;
654	case OP_JS:
655	pszInstr = "js";
656	break;
657	case OP_JNS:
658	pszInstr = "jns";
659	break;
660	case OP_JP:
661	pszInstr = "jp";
662	break;
663	case OP_JNP:
664	pszInstr = "jnp";
665	break;
666	case OP_JL:
667	pszInstr = "jl";
668	break;
669	case OP_JNL:
670	pszInstr = "jnl";
671	break;
672	case OP_JLE:
673	pszInstr = "jle";
674	break;
675	case OP_JNLE:
676	pszInstr = "jnle";
677	break;
678	case OP_JECXZ:
679	pszInstr = "jecxz";
680	break;
681	case OP_LOOP:
682	pszInstr = "loop";
683	break;
684	case OP_LOOPNE:
685	pszInstr = "loopne";
686	break;
687	case OP_LOOPE:
688	pszInstr = "loope";
689	break;
690	case OP_MOV:
691	if (fPatchFlags & PATMFL_IDTHANDLER)
692	pszInstr = "mov (Int/Trap Handler)";
693	else
694	pszInstr = "mov (cs)";
695	break;
696	case OP_SYSENTER:
697	pszInstr = "sysenter";
698	break;
699	case OP_PUSH:
700	pszInstr = "push (cs)";
701	break;
702	case OP_CALL:
703	pszInstr = "call";
704	break;
705	case OP_IRET:
706	pszInstr = "iret";
707	break;
708	}
709	return pszInstr;
710	}
711	#endif

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source: vbox/trunk/src/VBox/VMM/VMMAll/PATMAll.cpp@ 47427

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