VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h@ 108434

Last change on this file since 108434 was 108434, checked in by vboxsync, 4 weeks ago

VMM/NEM/Hyper-V: Started implementing a NEM/Hyper-V specific APIC emulation utilizing the LocalApicEmulation feature of Hyper-V, bugref:9993
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1/* $Id: NEMAllNativeTemplate-win.cpp.h 108434 2025-03-04 11:24:21Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, Windows code template ring-0/3.
4 */
5
6/*
7 * Copyright (C) 2018-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef IN_RING3
29# error "This is ring-3 only now"
30#endif
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36/** Copy back a segment from hyper-V. */
37#define NEM_WIN_COPY_BACK_SEG(a_Dst, a_Src) \
38 do { \
39 (a_Dst).u64Base = (a_Src).Base; \
40 (a_Dst).u32Limit = (a_Src).Limit; \
41 (a_Dst).ValidSel = (a_Dst).Sel = (a_Src).Selector; \
42 (a_Dst).Attr.u = (a_Src).Attributes; \
43 (a_Dst).fFlags = CPUMSELREG_FLAGS_VALID; \
44 } while (0)
45
46/** @def NEMWIN_ASSERT_MSG_REG_VAL
47 * Asserts the correctness of a register value in a message/context.
48 */
49#if 0
50# define NEMWIN_NEED_GET_REGISTER
51# define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) \
52 do { \
53 WHV_REGISTER_VALUE TmpVal; \
54 nemR3WinGetRegister(a_pVCpu, a_enmReg, &TmpVal); \
55 AssertMsg(a_Expr, a_Msg); \
56 } while (0)
57#else
58# define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, a_Expr, a_Msg) do { } while (0)
59#endif
60
61/** @def NEMWIN_ASSERT_MSG_REG_VAL
62 * Asserts the correctness of a 64-bit register value in a message/context.
63 */
64#define NEMWIN_ASSERT_MSG_REG_VAL64(a_pVCpu, a_enmReg, a_u64Val) \
65 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, (a_u64Val) == TmpVal.Reg64, \
66 (#a_u64Val "=%#RX64, expected %#RX64\n", (a_u64Val), TmpVal.Reg64))
67/** @def NEMWIN_ASSERT_MSG_REG_VAL
68 * Asserts the correctness of a segment register value in a message/context.
69 */
70#define NEMWIN_ASSERT_MSG_REG_SEG(a_pVCpu, a_enmReg, a_SReg) \
71 NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_enmReg, \
72 (a_SReg).Base == TmpVal.Segment.Base \
73 && (a_SReg).Limit == TmpVal.Segment.Limit \
74 && (a_SReg).Selector == TmpVal.Segment.Selector \
75 && (a_SReg).Attributes == TmpVal.Segment.Attributes, \
76 ( #a_SReg "=%#RX16 {%#RX64 LB %#RX32,%#RX16} expected %#RX16 {%#RX64 LB %#RX32,%#RX16}\n", \
77 (a_SReg).Selector, (a_SReg).Base, (a_SReg).Limit, (a_SReg).Attributes, \
78 TmpVal.Segment.Selector, TmpVal.Segment.Base, TmpVal.Segment.Limit, TmpVal.Segment.Attributes))
79
80
81#ifndef NTDDI_WIN10_19H1
82# define NTDDI_WIN10_19H1 0x0a000007
83#endif
84
85/** WHvRegisterPendingEvent0 was renamed to WHvRegisterPendingEvent between
86 * SDK 17134 and 18362. */
87#if WDK_NTDDI_VERSION < NTDDI_WIN10_19H1
88# define WHvRegisterPendingEvent WHvRegisterPendingEvent0
89#endif
90
91
92/*********************************************************************************************************************************
93* Global Variables *
94*********************************************************************************************************************************/
95/** NEM_WIN_PAGE_STATE_XXX names. */
96NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
97
98/** HV_INTERCEPT_ACCESS_TYPE names. */
99static const char * const g_apszHvInterceptAccessTypes[4] = { "read", "write", "exec", "!undefined!" };
100
101
102/*********************************************************************************************************************************
103* Internal Functions *
104*********************************************************************************************************************************/
105NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
106 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
107
108
109
110NEM_TMPL_STATIC int nemHCWinCopyStateToHyperV(PVMCC pVM, PVMCPUCC pVCpu)
111{
112 /*
113 * The following is very similar to what nemR0WinExportState() does.
114 */
115 WHV_REGISTER_NAME aenmNames[128];
116 WHV_REGISTER_VALUE aValues[128];
117
118 uint64_t const fWhat = ~pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
119 if ( !fWhat
120 && pVCpu->nem.s.fCurrentInterruptWindows == pVCpu->nem.s.fDesiredInterruptWindows)
121 return VINF_SUCCESS;
122 uintptr_t iReg = 0;
123
124#define ADD_REG64(a_enmName, a_uValue) do { \
125 aenmNames[iReg] = (a_enmName); \
126 aValues[iReg].Reg128.High64 = 0; \
127 aValues[iReg].Reg64 = (a_uValue); \
128 iReg++; \
129 } while (0)
130#define ADD_REG128(a_enmName, a_uValueLo, a_uValueHi) do { \
131 aenmNames[iReg] = (a_enmName); \
132 aValues[iReg].Reg128.Low64 = (a_uValueLo); \
133 aValues[iReg].Reg128.High64 = (a_uValueHi); \
134 iReg++; \
135 } while (0)
136
137 /* GPRs */
138 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
139 {
140 if (fWhat & CPUMCTX_EXTRN_RAX)
141 ADD_REG64(WHvX64RegisterRax, pVCpu->cpum.GstCtx.rax);
142 if (fWhat & CPUMCTX_EXTRN_RCX)
143 ADD_REG64(WHvX64RegisterRcx, pVCpu->cpum.GstCtx.rcx);
144 if (fWhat & CPUMCTX_EXTRN_RDX)
145 ADD_REG64(WHvX64RegisterRdx, pVCpu->cpum.GstCtx.rdx);
146 if (fWhat & CPUMCTX_EXTRN_RBX)
147 ADD_REG64(WHvX64RegisterRbx, pVCpu->cpum.GstCtx.rbx);
148 if (fWhat & CPUMCTX_EXTRN_RSP)
149 ADD_REG64(WHvX64RegisterRsp, pVCpu->cpum.GstCtx.rsp);
150 if (fWhat & CPUMCTX_EXTRN_RBP)
151 ADD_REG64(WHvX64RegisterRbp, pVCpu->cpum.GstCtx.rbp);
152 if (fWhat & CPUMCTX_EXTRN_RSI)
153 ADD_REG64(WHvX64RegisterRsi, pVCpu->cpum.GstCtx.rsi);
154 if (fWhat & CPUMCTX_EXTRN_RDI)
155 ADD_REG64(WHvX64RegisterRdi, pVCpu->cpum.GstCtx.rdi);
156 if (fWhat & CPUMCTX_EXTRN_R8_R15)
157 {
158 ADD_REG64(WHvX64RegisterR8, pVCpu->cpum.GstCtx.r8);
159 ADD_REG64(WHvX64RegisterR9, pVCpu->cpum.GstCtx.r9);
160 ADD_REG64(WHvX64RegisterR10, pVCpu->cpum.GstCtx.r10);
161 ADD_REG64(WHvX64RegisterR11, pVCpu->cpum.GstCtx.r11);
162 ADD_REG64(WHvX64RegisterR12, pVCpu->cpum.GstCtx.r12);
163 ADD_REG64(WHvX64RegisterR13, pVCpu->cpum.GstCtx.r13);
164 ADD_REG64(WHvX64RegisterR14, pVCpu->cpum.GstCtx.r14);
165 ADD_REG64(WHvX64RegisterR15, pVCpu->cpum.GstCtx.r15);
166 }
167 }
168
169 /* RIP & Flags */
170 if (fWhat & CPUMCTX_EXTRN_RIP)
171 ADD_REG64(WHvX64RegisterRip, pVCpu->cpum.GstCtx.rip);
172 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
173 ADD_REG64(WHvX64RegisterRflags, pVCpu->cpum.GstCtx.rflags.u);
174
175 /* Segments */
176#define ADD_SEG(a_enmName, a_SReg) \
177 do { \
178 aenmNames[iReg] = a_enmName; \
179 aValues[iReg].Segment.Base = (a_SReg).u64Base; \
180 aValues[iReg].Segment.Limit = (a_SReg).u32Limit; \
181 aValues[iReg].Segment.Selector = (a_SReg).Sel; \
182 aValues[iReg].Segment.Attributes = (a_SReg).Attr.u; \
183 iReg++; \
184 } while (0)
185 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
186 {
187 if (fWhat & CPUMCTX_EXTRN_ES)
188 ADD_SEG(WHvX64RegisterEs, pVCpu->cpum.GstCtx.es);
189 if (fWhat & CPUMCTX_EXTRN_CS)
190 ADD_SEG(WHvX64RegisterCs, pVCpu->cpum.GstCtx.cs);
191 if (fWhat & CPUMCTX_EXTRN_SS)
192 ADD_SEG(WHvX64RegisterSs, pVCpu->cpum.GstCtx.ss);
193 if (fWhat & CPUMCTX_EXTRN_DS)
194 ADD_SEG(WHvX64RegisterDs, pVCpu->cpum.GstCtx.ds);
195 if (fWhat & CPUMCTX_EXTRN_FS)
196 ADD_SEG(WHvX64RegisterFs, pVCpu->cpum.GstCtx.fs);
197 if (fWhat & CPUMCTX_EXTRN_GS)
198 ADD_SEG(WHvX64RegisterGs, pVCpu->cpum.GstCtx.gs);
199 }
200
201 /* Descriptor tables & task segment. */
202 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
203 {
204 if (fWhat & CPUMCTX_EXTRN_LDTR)
205 ADD_SEG(WHvX64RegisterLdtr, pVCpu->cpum.GstCtx.ldtr);
206 if (fWhat & CPUMCTX_EXTRN_TR)
207 ADD_SEG(WHvX64RegisterTr, pVCpu->cpum.GstCtx.tr);
208 if (fWhat & CPUMCTX_EXTRN_IDTR)
209 {
210 aenmNames[iReg] = WHvX64RegisterIdtr;
211 aValues[iReg].Table.Limit = pVCpu->cpum.GstCtx.idtr.cbIdt;
212 aValues[iReg].Table.Base = pVCpu->cpum.GstCtx.idtr.pIdt;
213 iReg++;
214 }
215 if (fWhat & CPUMCTX_EXTRN_GDTR)
216 {
217 aenmNames[iReg] = WHvX64RegisterGdtr;
218 aValues[iReg].Table.Limit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
219 aValues[iReg].Table.Base = pVCpu->cpum.GstCtx.gdtr.pGdt;
220 iReg++;
221 }
222 }
223
224 /* Control registers. */
225 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
226 {
227 if (fWhat & CPUMCTX_EXTRN_CR0)
228 ADD_REG64(WHvX64RegisterCr0, pVCpu->cpum.GstCtx.cr0);
229 if (fWhat & CPUMCTX_EXTRN_CR2)
230 ADD_REG64(WHvX64RegisterCr2, pVCpu->cpum.GstCtx.cr2);
231 if (fWhat & CPUMCTX_EXTRN_CR3)
232 ADD_REG64(WHvX64RegisterCr3, pVCpu->cpum.GstCtx.cr3);
233 if (fWhat & CPUMCTX_EXTRN_CR4)
234 ADD_REG64(WHvX64RegisterCr4, pVCpu->cpum.GstCtx.cr4);
235 }
236 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
237 ADD_REG64(WHvX64RegisterCr8, CPUMGetGuestCR8(pVCpu));
238
239 /* Debug registers. */
240/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
241 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
242 {
243 ADD_REG64(WHvX64RegisterDr0, pVCpu->cpum.GstCtx.dr[0]); // CPUMGetHyperDR0(pVCpu));
244 ADD_REG64(WHvX64RegisterDr1, pVCpu->cpum.GstCtx.dr[1]); // CPUMGetHyperDR1(pVCpu));
245 ADD_REG64(WHvX64RegisterDr2, pVCpu->cpum.GstCtx.dr[2]); // CPUMGetHyperDR2(pVCpu));
246 ADD_REG64(WHvX64RegisterDr3, pVCpu->cpum.GstCtx.dr[3]); // CPUMGetHyperDR3(pVCpu));
247 }
248 if (fWhat & CPUMCTX_EXTRN_DR6)
249 ADD_REG64(WHvX64RegisterDr6, pVCpu->cpum.GstCtx.dr[6]); // CPUMGetHyperDR6(pVCpu));
250 if (fWhat & CPUMCTX_EXTRN_DR7)
251 ADD_REG64(WHvX64RegisterDr7, pVCpu->cpum.GstCtx.dr[7]); // CPUMGetHyperDR7(pVCpu));
252
253 /* Floating point state. */
254 if (fWhat & CPUMCTX_EXTRN_X87)
255 {
256 ADD_REG128(WHvX64RegisterFpMmx0, pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[1]);
257 ADD_REG128(WHvX64RegisterFpMmx1, pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[1]);
258 ADD_REG128(WHvX64RegisterFpMmx2, pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[1]);
259 ADD_REG128(WHvX64RegisterFpMmx3, pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[1]);
260 ADD_REG128(WHvX64RegisterFpMmx4, pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[1]);
261 ADD_REG128(WHvX64RegisterFpMmx5, pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[1]);
262 ADD_REG128(WHvX64RegisterFpMmx6, pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[1]);
263 ADD_REG128(WHvX64RegisterFpMmx7, pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[1]);
264
265 aenmNames[iReg] = WHvX64RegisterFpControlStatus;
266 aValues[iReg].FpControlStatus.FpControl = pVCpu->cpum.GstCtx.XState.x87.FCW;
267 aValues[iReg].FpControlStatus.FpStatus = pVCpu->cpum.GstCtx.XState.x87.FSW;
268 aValues[iReg].FpControlStatus.FpTag = pVCpu->cpum.GstCtx.XState.x87.FTW;
269 aValues[iReg].FpControlStatus.Reserved = pVCpu->cpum.GstCtx.XState.x87.FTW >> 8;
270 aValues[iReg].FpControlStatus.LastFpOp = pVCpu->cpum.GstCtx.XState.x87.FOP;
271 aValues[iReg].FpControlStatus.LastFpRip = (pVCpu->cpum.GstCtx.XState.x87.FPUIP)
272 | ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.CS << 32)
273 | ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.Rsrvd1 << 48);
274 iReg++;
275
276 aenmNames[iReg] = WHvX64RegisterXmmControlStatus;
277 aValues[iReg].XmmControlStatus.LastFpRdp = (pVCpu->cpum.GstCtx.XState.x87.FPUDP)
278 | ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.DS << 32)
279 | ((uint64_t)pVCpu->cpum.GstCtx.XState.x87.Rsrvd2 << 48);
280 aValues[iReg].XmmControlStatus.XmmStatusControl = pVCpu->cpum.GstCtx.XState.x87.MXCSR;
281 aValues[iReg].XmmControlStatus.XmmStatusControlMask = pVCpu->cpum.GstCtx.XState.x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
282 iReg++;
283 }
284
285 /* Vector state. */
286 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
287 {
288 ADD_REG128(WHvX64RegisterXmm0, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Hi);
289 ADD_REG128(WHvX64RegisterXmm1, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Hi);
290 ADD_REG128(WHvX64RegisterXmm2, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Hi);
291 ADD_REG128(WHvX64RegisterXmm3, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Hi);
292 ADD_REG128(WHvX64RegisterXmm4, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Hi);
293 ADD_REG128(WHvX64RegisterXmm5, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Hi);
294 ADD_REG128(WHvX64RegisterXmm6, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Hi);
295 ADD_REG128(WHvX64RegisterXmm7, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Hi);
296 ADD_REG128(WHvX64RegisterXmm8, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Hi);
297 ADD_REG128(WHvX64RegisterXmm9, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Hi);
298 ADD_REG128(WHvX64RegisterXmm10, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Hi);
299 ADD_REG128(WHvX64RegisterXmm11, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Hi);
300 ADD_REG128(WHvX64RegisterXmm12, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Hi);
301 ADD_REG128(WHvX64RegisterXmm13, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Hi);
302 ADD_REG128(WHvX64RegisterXmm14, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Hi);
303 ADD_REG128(WHvX64RegisterXmm15, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Hi);
304 }
305
306 /* MSRs */
307 // WHvX64RegisterTsc - don't touch
308 if (fWhat & CPUMCTX_EXTRN_EFER)
309 ADD_REG64(WHvX64RegisterEfer, pVCpu->cpum.GstCtx.msrEFER);
310 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
311 ADD_REG64(WHvX64RegisterKernelGsBase, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
312 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
313 {
314 ADD_REG64(WHvX64RegisterSysenterCs, pVCpu->cpum.GstCtx.SysEnter.cs);
315 ADD_REG64(WHvX64RegisterSysenterEip, pVCpu->cpum.GstCtx.SysEnter.eip);
316 ADD_REG64(WHvX64RegisterSysenterEsp, pVCpu->cpum.GstCtx.SysEnter.esp);
317 }
318 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
319 {
320 ADD_REG64(WHvX64RegisterStar, pVCpu->cpum.GstCtx.msrSTAR);
321 ADD_REG64(WHvX64RegisterLstar, pVCpu->cpum.GstCtx.msrLSTAR);
322 ADD_REG64(WHvX64RegisterCstar, pVCpu->cpum.GstCtx.msrCSTAR);
323 ADD_REG64(WHvX64RegisterSfmask, pVCpu->cpum.GstCtx.msrSFMASK);
324 }
325 if (fWhat & (CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
326 {
327 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
328 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
329 ADD_REG64(WHvX64RegisterTscAux, pCtxMsrs->msr.TscAux);
330 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
331 {
332 ADD_REG64(WHvX64RegisterApicBase, PDMApicGetBaseMsrNoCheck(pVCpu));
333 ADD_REG64(WHvX64RegisterPat, pVCpu->cpum.GstCtx.msrPAT);
334#if 0 /** @todo check if WHvX64RegisterMsrMtrrCap works here... */
335 ADD_REG64(WHvX64RegisterMsrMtrrCap, CPUMGetGuestIa32MtrrCap(pVCpu));
336#endif
337 ADD_REG64(WHvX64RegisterMsrMtrrDefType, pCtxMsrs->msr.MtrrDefType);
338 ADD_REG64(WHvX64RegisterMsrMtrrFix64k00000, pCtxMsrs->msr.MtrrFix64K_00000);
339 ADD_REG64(WHvX64RegisterMsrMtrrFix16k80000, pCtxMsrs->msr.MtrrFix16K_80000);
340 ADD_REG64(WHvX64RegisterMsrMtrrFix16kA0000, pCtxMsrs->msr.MtrrFix16K_A0000);
341 ADD_REG64(WHvX64RegisterMsrMtrrFix4kC0000, pCtxMsrs->msr.MtrrFix4K_C0000);
342 ADD_REG64(WHvX64RegisterMsrMtrrFix4kC8000, pCtxMsrs->msr.MtrrFix4K_C8000);
343 ADD_REG64(WHvX64RegisterMsrMtrrFix4kD0000, pCtxMsrs->msr.MtrrFix4K_D0000);
344 ADD_REG64(WHvX64RegisterMsrMtrrFix4kD8000, pCtxMsrs->msr.MtrrFix4K_D8000);
345 ADD_REG64(WHvX64RegisterMsrMtrrFix4kE0000, pCtxMsrs->msr.MtrrFix4K_E0000);
346 ADD_REG64(WHvX64RegisterMsrMtrrFix4kE8000, pCtxMsrs->msr.MtrrFix4K_E8000);
347 ADD_REG64(WHvX64RegisterMsrMtrrFix4kF0000, pCtxMsrs->msr.MtrrFix4K_F0000);
348 ADD_REG64(WHvX64RegisterMsrMtrrFix4kF8000, pCtxMsrs->msr.MtrrFix4K_F8000);
349 if (pVM->nem.s.fDoIa32SpecCtrl)
350 ADD_REG64(WHvX64RegisterSpecCtrl, pCtxMsrs->msr.SpecCtrl);
351
352#if 0 /** @todo these registers aren't available? Might explain something.. .*/
353 const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM);
354 if (enmCpuVendor != CPUMCPUVENDOR_AMD)
355 {
356 ADD_REG64(HvX64RegisterIa32MiscEnable, pCtxMsrs->msr.MiscEnable);
357 ADD_REG64(HvX64RegisterIa32FeatureControl, CPUMGetGuestIa32FeatureControl(pVCpu));
358 }
359#endif
360 }
361 }
362
363 /* event injection (clear it). */
364 if (fWhat & CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)
365 ADD_REG64(WHvRegisterPendingInterruption, 0);
366
367 if (!pVM->nem.s.fLocalApicEmulation)
368 {
369 /* Interruptibility state. This can get a little complicated since we get
370 half of the state via HV_X64_VP_EXECUTION_STATE. */
371 if ( (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
372 == (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI) )
373 {
374 ADD_REG64(WHvRegisterInterruptState, 0);
375 if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
376 aValues[iReg - 1].InterruptState.InterruptShadow = 1;
377 aValues[iReg - 1].InterruptState.NmiMasked = CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx);
378 }
379 else if (fWhat & CPUMCTX_EXTRN_INHIBIT_INT)
380 {
381 if ( pVCpu->nem.s.fLastInterruptShadow
382 || CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
383 {
384 ADD_REG64(WHvRegisterInterruptState, 0);
385 if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
386 aValues[iReg - 1].InterruptState.InterruptShadow = 1;
387 /** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */
388 //if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
389 // aValues[iReg - 1].InterruptState.NmiMasked = 1;
390 }
391 }
392 else
393 Assert(!(fWhat & CPUMCTX_EXTRN_INHIBIT_NMI));
394
395 /* Interrupt windows. Always set if active as Hyper-V seems to be forgetful. */
396 uint8_t const fDesiredIntWin = pVCpu->nem.s.fDesiredInterruptWindows;
397 if ( fDesiredIntWin
398 || pVCpu->nem.s.fCurrentInterruptWindows != fDesiredIntWin)
399 {
400 pVCpu->nem.s.fCurrentInterruptWindows = pVCpu->nem.s.fDesiredInterruptWindows;
401 Log8(("Setting WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin=%X\n", fDesiredIntWin));
402 ADD_REG64(WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin);
403 Assert(aValues[iReg - 1].DeliverabilityNotifications.NmiNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_NMI));
404 Assert(aValues[iReg - 1].DeliverabilityNotifications.InterruptNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_REGULAR));
405 Assert(aValues[iReg - 1].DeliverabilityNotifications.InterruptPriority == (unsigned)((fDesiredIntWin & NEM_WIN_INTW_F_PRIO_MASK) >> NEM_WIN_INTW_F_PRIO_SHIFT));
406 }
407 }
408 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
409 {
410 Log8(("Setting WHvX64RegisterDeliverabilityNotifications, fDesiredIntWin=%X fPicReadyForInterrupt=%RTbool\n",
411 pVCpu->nem.s.fDesiredInterruptWindows, pVCpu->nem.s.fPicReadyForInterrupt));
412
413 if ( pVCpu->nem.s.fDesiredInterruptWindows
414 && pVCpu->nem.s.fPicReadyForInterrupt)
415 {
416 ADD_REG64(WHvRegisterPendingEvent, 0);
417
418 uint8_t bInterrupt;
419 int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
420 AssertRC(rc);
421
422 aValues[iReg - 1].Reg64 = 0;
423 aValues[iReg - 1].ExtIntEvent.EventPending = 1;
424 aValues[iReg - 1].ExtIntEvent.EventType = WHvX64PendingEventExtInt;
425 aValues[iReg - 1].ExtIntEvent.Vector = bInterrupt;
426 }
427
428 if (!pVCpu->nem.s.fIrqWindowRegistered)
429 {
430 ADD_REG64(WHvX64RegisterDeliverabilityNotifications, 0);
431 aValues[iReg - 1].DeliverabilityNotifications.InterruptNotification = 1;
432 pVCpu->nem.s.fIrqWindowRegistered = true;
433 }
434 }
435
436#undef ADD_REG64
437#undef ADD_REG128
438#undef ADD_SEG
439
440 /*
441 * Set the registers.
442 */
443 Assert(iReg < RT_ELEMENTS(aValues));
444 Assert(iReg < RT_ELEMENTS(aenmNames));
445#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
446 Log12(("Calling WHvSetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
447 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues));
448#endif
449
450 pVCpu->nem.s.fPicReadyForInterrupt = false;
451
452 if (!iReg)
453 return VINF_SUCCESS;
454
455 HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, iReg, aValues);
456 if (SUCCEEDED(hrc))
457 {
458 pVCpu->cpum.GstCtx.fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK | CPUMCTX_EXTRN_KEEPER_NEM;
459 return VINF_SUCCESS;
460 }
461 AssertLogRelMsgFailed(("WHvSetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
462 pVM->nem.s.hPartition, pVCpu->idCpu, iReg,
463 hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
464 return VERR_INTERNAL_ERROR;
465}
466
467
468NEM_TMPL_STATIC int nemHCWinCopyStateFromHyperV(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
469{
470 WHV_REGISTER_NAME aenmNames[128];
471
472 fWhat &= pVCpu->cpum.GstCtx.fExtrn;
473 uintptr_t iReg = 0;
474
475 /* GPRs */
476 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
477 {
478 if (fWhat & CPUMCTX_EXTRN_RAX)
479 aenmNames[iReg++] = WHvX64RegisterRax;
480 if (fWhat & CPUMCTX_EXTRN_RCX)
481 aenmNames[iReg++] = WHvX64RegisterRcx;
482 if (fWhat & CPUMCTX_EXTRN_RDX)
483 aenmNames[iReg++] = WHvX64RegisterRdx;
484 if (fWhat & CPUMCTX_EXTRN_RBX)
485 aenmNames[iReg++] = WHvX64RegisterRbx;
486 if (fWhat & CPUMCTX_EXTRN_RSP)
487 aenmNames[iReg++] = WHvX64RegisterRsp;
488 if (fWhat & CPUMCTX_EXTRN_RBP)
489 aenmNames[iReg++] = WHvX64RegisterRbp;
490 if (fWhat & CPUMCTX_EXTRN_RSI)
491 aenmNames[iReg++] = WHvX64RegisterRsi;
492 if (fWhat & CPUMCTX_EXTRN_RDI)
493 aenmNames[iReg++] = WHvX64RegisterRdi;
494 if (fWhat & CPUMCTX_EXTRN_R8_R15)
495 {
496 aenmNames[iReg++] = WHvX64RegisterR8;
497 aenmNames[iReg++] = WHvX64RegisterR9;
498 aenmNames[iReg++] = WHvX64RegisterR10;
499 aenmNames[iReg++] = WHvX64RegisterR11;
500 aenmNames[iReg++] = WHvX64RegisterR12;
501 aenmNames[iReg++] = WHvX64RegisterR13;
502 aenmNames[iReg++] = WHvX64RegisterR14;
503 aenmNames[iReg++] = WHvX64RegisterR15;
504 }
505 }
506
507 /* RIP & Flags */
508 if (fWhat & CPUMCTX_EXTRN_RIP)
509 aenmNames[iReg++] = WHvX64RegisterRip;
510 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
511 aenmNames[iReg++] = WHvX64RegisterRflags;
512
513 /* Segments */
514 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
515 {
516 if (fWhat & CPUMCTX_EXTRN_ES)
517 aenmNames[iReg++] = WHvX64RegisterEs;
518 if (fWhat & CPUMCTX_EXTRN_CS)
519 aenmNames[iReg++] = WHvX64RegisterCs;
520 if (fWhat & CPUMCTX_EXTRN_SS)
521 aenmNames[iReg++] = WHvX64RegisterSs;
522 if (fWhat & CPUMCTX_EXTRN_DS)
523 aenmNames[iReg++] = WHvX64RegisterDs;
524 if (fWhat & CPUMCTX_EXTRN_FS)
525 aenmNames[iReg++] = WHvX64RegisterFs;
526 if (fWhat & CPUMCTX_EXTRN_GS)
527 aenmNames[iReg++] = WHvX64RegisterGs;
528 }
529
530 /* Descriptor tables. */
531 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
532 {
533 if (fWhat & CPUMCTX_EXTRN_LDTR)
534 aenmNames[iReg++] = WHvX64RegisterLdtr;
535 if (fWhat & CPUMCTX_EXTRN_TR)
536 aenmNames[iReg++] = WHvX64RegisterTr;
537 if (fWhat & CPUMCTX_EXTRN_IDTR)
538 aenmNames[iReg++] = WHvX64RegisterIdtr;
539 if (fWhat & CPUMCTX_EXTRN_GDTR)
540 aenmNames[iReg++] = WHvX64RegisterGdtr;
541 }
542
543 /* Control registers. */
544 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
545 {
546 if (fWhat & CPUMCTX_EXTRN_CR0)
547 aenmNames[iReg++] = WHvX64RegisterCr0;
548 if (fWhat & CPUMCTX_EXTRN_CR2)
549 aenmNames[iReg++] = WHvX64RegisterCr2;
550 if (fWhat & CPUMCTX_EXTRN_CR3)
551 aenmNames[iReg++] = WHvX64RegisterCr3;
552 if (fWhat & CPUMCTX_EXTRN_CR4)
553 aenmNames[iReg++] = WHvX64RegisterCr4;
554 }
555 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
556 aenmNames[iReg++] = WHvX64RegisterCr8;
557
558 /* Debug registers. */
559 if (fWhat & CPUMCTX_EXTRN_DR7)
560 aenmNames[iReg++] = WHvX64RegisterDr7;
561 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
562 {
563 if (!(fWhat & CPUMCTX_EXTRN_DR7) && (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_DR7))
564 {
565 fWhat |= CPUMCTX_EXTRN_DR7;
566 aenmNames[iReg++] = WHvX64RegisterDr7;
567 }
568 aenmNames[iReg++] = WHvX64RegisterDr0;
569 aenmNames[iReg++] = WHvX64RegisterDr1;
570 aenmNames[iReg++] = WHvX64RegisterDr2;
571 aenmNames[iReg++] = WHvX64RegisterDr3;
572 }
573 if (fWhat & CPUMCTX_EXTRN_DR6)
574 aenmNames[iReg++] = WHvX64RegisterDr6;
575
576 /* Floating point state. */
577 if (fWhat & CPUMCTX_EXTRN_X87)
578 {
579 aenmNames[iReg++] = WHvX64RegisterFpMmx0;
580 aenmNames[iReg++] = WHvX64RegisterFpMmx1;
581 aenmNames[iReg++] = WHvX64RegisterFpMmx2;
582 aenmNames[iReg++] = WHvX64RegisterFpMmx3;
583 aenmNames[iReg++] = WHvX64RegisterFpMmx4;
584 aenmNames[iReg++] = WHvX64RegisterFpMmx5;
585 aenmNames[iReg++] = WHvX64RegisterFpMmx6;
586 aenmNames[iReg++] = WHvX64RegisterFpMmx7;
587 aenmNames[iReg++] = WHvX64RegisterFpControlStatus;
588 }
589 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX))
590 aenmNames[iReg++] = WHvX64RegisterXmmControlStatus;
591
592 /* Vector state. */
593 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
594 {
595 aenmNames[iReg++] = WHvX64RegisterXmm0;
596 aenmNames[iReg++] = WHvX64RegisterXmm1;
597 aenmNames[iReg++] = WHvX64RegisterXmm2;
598 aenmNames[iReg++] = WHvX64RegisterXmm3;
599 aenmNames[iReg++] = WHvX64RegisterXmm4;
600 aenmNames[iReg++] = WHvX64RegisterXmm5;
601 aenmNames[iReg++] = WHvX64RegisterXmm6;
602 aenmNames[iReg++] = WHvX64RegisterXmm7;
603 aenmNames[iReg++] = WHvX64RegisterXmm8;
604 aenmNames[iReg++] = WHvX64RegisterXmm9;
605 aenmNames[iReg++] = WHvX64RegisterXmm10;
606 aenmNames[iReg++] = WHvX64RegisterXmm11;
607 aenmNames[iReg++] = WHvX64RegisterXmm12;
608 aenmNames[iReg++] = WHvX64RegisterXmm13;
609 aenmNames[iReg++] = WHvX64RegisterXmm14;
610 aenmNames[iReg++] = WHvX64RegisterXmm15;
611 }
612
613 /* MSRs */
614 // WHvX64RegisterTsc - don't touch
615 if (fWhat & CPUMCTX_EXTRN_EFER)
616 aenmNames[iReg++] = WHvX64RegisterEfer;
617 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
618 aenmNames[iReg++] = WHvX64RegisterKernelGsBase;
619 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
620 {
621 aenmNames[iReg++] = WHvX64RegisterSysenterCs;
622 aenmNames[iReg++] = WHvX64RegisterSysenterEip;
623 aenmNames[iReg++] = WHvX64RegisterSysenterEsp;
624 }
625 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
626 {
627 aenmNames[iReg++] = WHvX64RegisterStar;
628 aenmNames[iReg++] = WHvX64RegisterLstar;
629 aenmNames[iReg++] = WHvX64RegisterCstar;
630 aenmNames[iReg++] = WHvX64RegisterSfmask;
631 }
632
633//#ifdef LOG_ENABLED
634// const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM);
635//#endif
636 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
637 aenmNames[iReg++] = WHvX64RegisterTscAux;
638 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
639 {
640 aenmNames[iReg++] = WHvX64RegisterApicBase; /// @todo APIC BASE
641 aenmNames[iReg++] = WHvX64RegisterPat;
642#if 0 /*def LOG_ENABLED*/ /** @todo Check if WHvX64RegisterMsrMtrrCap works... */
643 aenmNames[iReg++] = WHvX64RegisterMsrMtrrCap;
644#endif
645 aenmNames[iReg++] = WHvX64RegisterMsrMtrrDefType;
646 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix64k00000;
647 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix16k80000;
648 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix16kA0000;
649 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kC0000;
650 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kC8000;
651 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kD0000;
652 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kD8000;
653 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kE0000;
654 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kE8000;
655 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kF0000;
656 aenmNames[iReg++] = WHvX64RegisterMsrMtrrFix4kF8000;
657 if (pVM->nem.s.fDoIa32SpecCtrl)
658 aenmNames[iReg++] = WHvX64RegisterSpecCtrl;
659 /** @todo look for HvX64RegisterIa32MiscEnable and HvX64RegisterIa32FeatureControl? */
660//#ifdef LOG_ENABLED
661// if (enmCpuVendor != CPUMCPUVENDOR_AMD)
662// aenmNames[iReg++] = HvX64RegisterIa32FeatureControl;
663//#endif
664 }
665
666 /* Interruptibility. */
667 if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
668 {
669 aenmNames[iReg++] = WHvRegisterInterruptState;
670 aenmNames[iReg++] = WHvX64RegisterRip;
671 }
672
673 /* event injection */
674 aenmNames[iReg++] = WHvRegisterPendingInterruption;
675 aenmNames[iReg++] = WHvRegisterPendingEvent;
676
677 size_t const cRegs = iReg;
678 Assert(cRegs < RT_ELEMENTS(aenmNames));
679
680 /*
681 * Get the registers.
682 */
683 WHV_REGISTER_VALUE aValues[128];
684 RT_ZERO(aValues);
685 Assert(RT_ELEMENTS(aValues) >= cRegs);
686 Assert(RT_ELEMENTS(aenmNames) >= cRegs);
687#ifdef NEM_WIN_INTERCEPT_NT_IO_CTLS
688 Log12(("Calling WHvGetVirtualProcessorRegisters(%p, %u, %p, %u, %p)\n",
689 pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, cRegs, aValues));
690#endif
691 HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, (uint32_t)cRegs, aValues);
692 AssertLogRelMsgReturn(SUCCEEDED(hrc),
693 ("WHvGetVirtualProcessorRegisters(%p, %u,,%u,) -> %Rhrc (Last=%#x/%u)\n",
694 pVM->nem.s.hPartition, pVCpu->idCpu, cRegs, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
695 , VERR_NEM_GET_REGISTERS_FAILED);
696
697 iReg = 0;
698#define GET_REG64(a_DstVar, a_enmName) do { \
699 Assert(aenmNames[iReg] == (a_enmName)); \
700 (a_DstVar) = aValues[iReg].Reg64; \
701 iReg++; \
702 } while (0)
703#define GET_REG64_LOG7(a_DstVar, a_enmName, a_szLogName) do { \
704 Assert(aenmNames[iReg] == (a_enmName)); \
705 if ((a_DstVar) != aValues[iReg].Reg64) \
706 Log7(("NEM/%u: " a_szLogName " changed %RX64 -> %RX64\n", pVCpu->idCpu, (a_DstVar), aValues[iReg].Reg64)); \
707 (a_DstVar) = aValues[iReg].Reg64; \
708 iReg++; \
709 } while (0)
710#define GET_REG128(a_DstVarLo, a_DstVarHi, a_enmName) do { \
711 Assert(aenmNames[iReg] == a_enmName); \
712 (a_DstVarLo) = aValues[iReg].Reg128.Low64; \
713 (a_DstVarHi) = aValues[iReg].Reg128.High64; \
714 iReg++; \
715 } while (0)
716#define GET_SEG(a_SReg, a_enmName) do { \
717 Assert(aenmNames[iReg] == (a_enmName)); \
718 NEM_WIN_COPY_BACK_SEG(a_SReg, aValues[iReg].Segment); \
719 iReg++; \
720 } while (0)
721
722 /* GPRs */
723 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
724 {
725 if (fWhat & CPUMCTX_EXTRN_RAX)
726 GET_REG64(pVCpu->cpum.GstCtx.rax, WHvX64RegisterRax);
727 if (fWhat & CPUMCTX_EXTRN_RCX)
728 GET_REG64(pVCpu->cpum.GstCtx.rcx, WHvX64RegisterRcx);
729 if (fWhat & CPUMCTX_EXTRN_RDX)
730 GET_REG64(pVCpu->cpum.GstCtx.rdx, WHvX64RegisterRdx);
731 if (fWhat & CPUMCTX_EXTRN_RBX)
732 GET_REG64(pVCpu->cpum.GstCtx.rbx, WHvX64RegisterRbx);
733 if (fWhat & CPUMCTX_EXTRN_RSP)
734 GET_REG64(pVCpu->cpum.GstCtx.rsp, WHvX64RegisterRsp);
735 if (fWhat & CPUMCTX_EXTRN_RBP)
736 GET_REG64(pVCpu->cpum.GstCtx.rbp, WHvX64RegisterRbp);
737 if (fWhat & CPUMCTX_EXTRN_RSI)
738 GET_REG64(pVCpu->cpum.GstCtx.rsi, WHvX64RegisterRsi);
739 if (fWhat & CPUMCTX_EXTRN_RDI)
740 GET_REG64(pVCpu->cpum.GstCtx.rdi, WHvX64RegisterRdi);
741 if (fWhat & CPUMCTX_EXTRN_R8_R15)
742 {
743 GET_REG64(pVCpu->cpum.GstCtx.r8, WHvX64RegisterR8);
744 GET_REG64(pVCpu->cpum.GstCtx.r9, WHvX64RegisterR9);
745 GET_REG64(pVCpu->cpum.GstCtx.r10, WHvX64RegisterR10);
746 GET_REG64(pVCpu->cpum.GstCtx.r11, WHvX64RegisterR11);
747 GET_REG64(pVCpu->cpum.GstCtx.r12, WHvX64RegisterR12);
748 GET_REG64(pVCpu->cpum.GstCtx.r13, WHvX64RegisterR13);
749 GET_REG64(pVCpu->cpum.GstCtx.r14, WHvX64RegisterR14);
750 GET_REG64(pVCpu->cpum.GstCtx.r15, WHvX64RegisterR15);
751 }
752 }
753
754 /* RIP & Flags */
755 if (fWhat & CPUMCTX_EXTRN_RIP)
756 GET_REG64(pVCpu->cpum.GstCtx.rip, WHvX64RegisterRip);
757 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
758 GET_REG64(pVCpu->cpum.GstCtx.rflags.u, WHvX64RegisterRflags);
759
760 /* Segments */
761 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
762 {
763 if (fWhat & CPUMCTX_EXTRN_ES)
764 GET_SEG(pVCpu->cpum.GstCtx.es, WHvX64RegisterEs);
765 if (fWhat & CPUMCTX_EXTRN_CS)
766 GET_SEG(pVCpu->cpum.GstCtx.cs, WHvX64RegisterCs);
767 if (fWhat & CPUMCTX_EXTRN_SS)
768 GET_SEG(pVCpu->cpum.GstCtx.ss, WHvX64RegisterSs);
769 if (fWhat & CPUMCTX_EXTRN_DS)
770 GET_SEG(pVCpu->cpum.GstCtx.ds, WHvX64RegisterDs);
771 if (fWhat & CPUMCTX_EXTRN_FS)
772 GET_SEG(pVCpu->cpum.GstCtx.fs, WHvX64RegisterFs);
773 if (fWhat & CPUMCTX_EXTRN_GS)
774 GET_SEG(pVCpu->cpum.GstCtx.gs, WHvX64RegisterGs);
775 }
776
777 /* Descriptor tables and the task segment. */
778 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
779 {
780 if (fWhat & CPUMCTX_EXTRN_LDTR)
781 GET_SEG(pVCpu->cpum.GstCtx.ldtr, WHvX64RegisterLdtr);
782
783 if (fWhat & CPUMCTX_EXTRN_TR)
784 {
785 /* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
786 avoid to trigger sanity assertions around the code, always fix this. */
787 GET_SEG(pVCpu->cpum.GstCtx.tr, WHvX64RegisterTr);
788 switch (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type)
789 {
790 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
791 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
792 break;
793 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
794 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
795 break;
796 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
797 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
798 break;
799 }
800 }
801 if (fWhat & CPUMCTX_EXTRN_IDTR)
802 {
803 Assert(aenmNames[iReg] == WHvX64RegisterIdtr);
804 pVCpu->cpum.GstCtx.idtr.cbIdt = aValues[iReg].Table.Limit;
805 pVCpu->cpum.GstCtx.idtr.pIdt = aValues[iReg].Table.Base;
806 iReg++;
807 }
808 if (fWhat & CPUMCTX_EXTRN_GDTR)
809 {
810 Assert(aenmNames[iReg] == WHvX64RegisterGdtr);
811 pVCpu->cpum.GstCtx.gdtr.cbGdt = aValues[iReg].Table.Limit;
812 pVCpu->cpum.GstCtx.gdtr.pGdt = aValues[iReg].Table.Base;
813 iReg++;
814 }
815 }
816
817 /* Control registers. */
818 bool fMaybeChangedMode = false;
819 bool fUpdateCr3 = false;
820 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
821 {
822 if (fWhat & CPUMCTX_EXTRN_CR0)
823 {
824 Assert(aenmNames[iReg] == WHvX64RegisterCr0);
825 if (pVCpu->cpum.GstCtx.cr0 != aValues[iReg].Reg64)
826 {
827 CPUMSetGuestCR0(pVCpu, aValues[iReg].Reg64);
828 fMaybeChangedMode = true;
829 }
830 iReg++;
831 }
832 if (fWhat & CPUMCTX_EXTRN_CR2)
833 GET_REG64(pVCpu->cpum.GstCtx.cr2, WHvX64RegisterCr2);
834 if (fWhat & CPUMCTX_EXTRN_CR3)
835 {
836 if (pVCpu->cpum.GstCtx.cr3 != aValues[iReg].Reg64)
837 {
838 CPUMSetGuestCR3(pVCpu, aValues[iReg].Reg64);
839 fUpdateCr3 = true;
840 }
841 iReg++;
842 }
843 if (fWhat & CPUMCTX_EXTRN_CR4)
844 {
845 if (pVCpu->cpum.GstCtx.cr4 != aValues[iReg].Reg64)
846 {
847 CPUMSetGuestCR4(pVCpu, aValues[iReg].Reg64);
848 fMaybeChangedMode = true;
849 }
850 iReg++;
851 }
852 }
853 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
854 {
855 Assert(aenmNames[iReg] == WHvX64RegisterCr8);
856 PDMApicSetTpr(pVCpu, (uint8_t)aValues[iReg].Reg64 << 4);
857 iReg++;
858 }
859
860 /* Debug registers. */
861 if (fWhat & CPUMCTX_EXTRN_DR7)
862 {
863 Assert(aenmNames[iReg] == WHvX64RegisterDr7);
864 if (pVCpu->cpum.GstCtx.dr[7] != aValues[iReg].Reg64)
865 CPUMSetGuestDR7(pVCpu, aValues[iReg].Reg64);
866 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_DR7; /* Hack alert! Avoids asserting when processing CPUMCTX_EXTRN_DR0_DR3. */
867 iReg++;
868 }
869 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
870 {
871 Assert(aenmNames[iReg] == WHvX64RegisterDr0);
872 Assert(aenmNames[iReg+3] == WHvX64RegisterDr3);
873 if (pVCpu->cpum.GstCtx.dr[0] != aValues[iReg].Reg64)
874 CPUMSetGuestDR0(pVCpu, aValues[iReg].Reg64);
875 iReg++;
876 if (pVCpu->cpum.GstCtx.dr[1] != aValues[iReg].Reg64)
877 CPUMSetGuestDR1(pVCpu, aValues[iReg].Reg64);
878 iReg++;
879 if (pVCpu->cpum.GstCtx.dr[2] != aValues[iReg].Reg64)
880 CPUMSetGuestDR2(pVCpu, aValues[iReg].Reg64);
881 iReg++;
882 if (pVCpu->cpum.GstCtx.dr[3] != aValues[iReg].Reg64)
883 CPUMSetGuestDR3(pVCpu, aValues[iReg].Reg64);
884 iReg++;
885 }
886 if (fWhat & CPUMCTX_EXTRN_DR6)
887 {
888 Assert(aenmNames[iReg] == WHvX64RegisterDr6);
889 if (pVCpu->cpum.GstCtx.dr[6] != aValues[iReg].Reg64)
890 CPUMSetGuestDR6(pVCpu, aValues[iReg].Reg64);
891 iReg++;
892 }
893
894 /* Floating point state. */
895 if (fWhat & CPUMCTX_EXTRN_X87)
896 {
897 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[0].au64[1], WHvX64RegisterFpMmx0);
898 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[1].au64[1], WHvX64RegisterFpMmx1);
899 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[2].au64[1], WHvX64RegisterFpMmx2);
900 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[3].au64[1], WHvX64RegisterFpMmx3);
901 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[4].au64[1], WHvX64RegisterFpMmx4);
902 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[5].au64[1], WHvX64RegisterFpMmx5);
903 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[6].au64[1], WHvX64RegisterFpMmx6);
904 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[0], pVCpu->cpum.GstCtx.XState.x87.aRegs[7].au64[1], WHvX64RegisterFpMmx7);
905
906 Assert(aenmNames[iReg] == WHvX64RegisterFpControlStatus);
907 pVCpu->cpum.GstCtx.XState.x87.FCW = aValues[iReg].FpControlStatus.FpControl;
908 pVCpu->cpum.GstCtx.XState.x87.FSW = aValues[iReg].FpControlStatus.FpStatus;
909 pVCpu->cpum.GstCtx.XState.x87.FTW = aValues[iReg].FpControlStatus.FpTag
910 /*| (aValues[iReg].FpControlStatus.Reserved << 8)*/;
911 pVCpu->cpum.GstCtx.XState.x87.FOP = aValues[iReg].FpControlStatus.LastFpOp;
912 pVCpu->cpum.GstCtx.XState.x87.FPUIP = (uint32_t)aValues[iReg].FpControlStatus.LastFpRip;
913 pVCpu->cpum.GstCtx.XState.x87.CS = (uint16_t)(aValues[iReg].FpControlStatus.LastFpRip >> 32);
914 pVCpu->cpum.GstCtx.XState.x87.Rsrvd1 = (uint16_t)(aValues[iReg].FpControlStatus.LastFpRip >> 48);
915 iReg++;
916 }
917
918 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX))
919 {
920 Assert(aenmNames[iReg] == WHvX64RegisterXmmControlStatus);
921 if (fWhat & CPUMCTX_EXTRN_X87)
922 {
923 pVCpu->cpum.GstCtx.XState.x87.FPUDP = (uint32_t)aValues[iReg].XmmControlStatus.LastFpRdp;
924 pVCpu->cpum.GstCtx.XState.x87.DS = (uint16_t)(aValues[iReg].XmmControlStatus.LastFpRdp >> 32);
925 pVCpu->cpum.GstCtx.XState.x87.Rsrvd2 = (uint16_t)(aValues[iReg].XmmControlStatus.LastFpRdp >> 48);
926 }
927 pVCpu->cpum.GstCtx.XState.x87.MXCSR = aValues[iReg].XmmControlStatus.XmmStatusControl;
928 pVCpu->cpum.GstCtx.XState.x87.MXCSR_MASK = aValues[iReg].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
929 iReg++;
930 }
931
932 /* Vector state. */
933 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
934 {
935 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 0].uXmm.s.Hi, WHvX64RegisterXmm0);
936 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 1].uXmm.s.Hi, WHvX64RegisterXmm1);
937 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 2].uXmm.s.Hi, WHvX64RegisterXmm2);
938 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 3].uXmm.s.Hi, WHvX64RegisterXmm3);
939 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 4].uXmm.s.Hi, WHvX64RegisterXmm4);
940 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 5].uXmm.s.Hi, WHvX64RegisterXmm5);
941 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 6].uXmm.s.Hi, WHvX64RegisterXmm6);
942 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 7].uXmm.s.Hi, WHvX64RegisterXmm7);
943 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 8].uXmm.s.Hi, WHvX64RegisterXmm8);
944 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[ 9].uXmm.s.Hi, WHvX64RegisterXmm9);
945 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[10].uXmm.s.Hi, WHvX64RegisterXmm10);
946 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[11].uXmm.s.Hi, WHvX64RegisterXmm11);
947 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[12].uXmm.s.Hi, WHvX64RegisterXmm12);
948 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[13].uXmm.s.Hi, WHvX64RegisterXmm13);
949 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[14].uXmm.s.Hi, WHvX64RegisterXmm14);
950 GET_REG128(pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Lo, pVCpu->cpum.GstCtx.XState.x87.aXMM[15].uXmm.s.Hi, WHvX64RegisterXmm15);
951 }
952
953 /* MSRs */
954 // WHvX64RegisterTsc - don't touch
955 if (fWhat & CPUMCTX_EXTRN_EFER)
956 {
957 Assert(aenmNames[iReg] == WHvX64RegisterEfer);
958 if (aValues[iReg].Reg64 != pVCpu->cpum.GstCtx.msrEFER)
959 {
960 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, aValues[iReg].Reg64));
961 if ((aValues[iReg].Reg64 ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
962 PGMNotifyNxeChanged(pVCpu, RT_BOOL(aValues[iReg].Reg64 & MSR_K6_EFER_NXE));
963 pVCpu->cpum.GstCtx.msrEFER = aValues[iReg].Reg64;
964 fMaybeChangedMode = true;
965 }
966 iReg++;
967 }
968 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
969 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrKERNELGSBASE, WHvX64RegisterKernelGsBase, "MSR KERNEL_GS_BASE");
970 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
971 {
972 GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.cs, WHvX64RegisterSysenterCs, "MSR SYSENTER.CS");
973 GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.eip, WHvX64RegisterSysenterEip, "MSR SYSENTER.EIP");
974 GET_REG64_LOG7(pVCpu->cpum.GstCtx.SysEnter.esp, WHvX64RegisterSysenterEsp, "MSR SYSENTER.ESP");
975 }
976 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
977 {
978 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrSTAR, WHvX64RegisterStar, "MSR STAR");
979 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrLSTAR, WHvX64RegisterLstar, "MSR LSTAR");
980 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrCSTAR, WHvX64RegisterCstar, "MSR CSTAR");
981 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrSFMASK, WHvX64RegisterSfmask, "MSR SFMASK");
982 }
983 if (fWhat & (CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
984 {
985 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
986 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
987 GET_REG64_LOG7(pCtxMsrs->msr.TscAux, WHvX64RegisterTscAux, "MSR TSC_AUX");
988 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
989 {
990 Assert(aenmNames[iReg] == WHvX64RegisterApicBase);
991 const uint64_t uOldBase = PDMApicGetBaseMsrNoCheck(pVCpu);
992 if (aValues[iReg].Reg64 != uOldBase)
993 {
994 Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
995 pVCpu->idCpu, uOldBase, aValues[iReg].Reg64, aValues[iReg].Reg64 ^ uOldBase));
996 int rc2 = PDMApicSetBaseMsr(pVCpu, aValues[iReg].Reg64);
997 AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", rc2, aValues[iReg].Reg64));
998 }
999 iReg++;
1000
1001 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterPat, "MSR PAT");
1002#if 0 /*def LOG_ENABLED*/ /** @todo something's wrong with HvX64RegisterMtrrCap? (AMD) */
1003 GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterMsrMtrrCap);
1004#endif
1005 GET_REG64_LOG7(pCtxMsrs->msr.MtrrDefType, WHvX64RegisterMsrMtrrDefType, "MSR MTRR_DEF_TYPE");
1006 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix64K_00000, WHvX64RegisterMsrMtrrFix64k00000, "MSR MTRR_FIX_64K_00000");
1007 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_80000, WHvX64RegisterMsrMtrrFix16k80000, "MSR MTRR_FIX_16K_80000");
1008 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_A0000, WHvX64RegisterMsrMtrrFix16kA0000, "MSR MTRR_FIX_16K_A0000");
1009 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C0000, WHvX64RegisterMsrMtrrFix4kC0000, "MSR MTRR_FIX_4K_C0000");
1010 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C8000, WHvX64RegisterMsrMtrrFix4kC8000, "MSR MTRR_FIX_4K_C8000");
1011 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D0000, WHvX64RegisterMsrMtrrFix4kD0000, "MSR MTRR_FIX_4K_D0000");
1012 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D8000, WHvX64RegisterMsrMtrrFix4kD8000, "MSR MTRR_FIX_4K_D8000");
1013 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E0000, WHvX64RegisterMsrMtrrFix4kE0000, "MSR MTRR_FIX_4K_E0000");
1014 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E8000, WHvX64RegisterMsrMtrrFix4kE8000, "MSR MTRR_FIX_4K_E8000");
1015 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F0000, WHvX64RegisterMsrMtrrFix4kF0000, "MSR MTRR_FIX_4K_F0000");
1016 GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F8000, WHvX64RegisterMsrMtrrFix4kF8000, "MSR MTRR_FIX_4K_F8000");
1017 if (pVM->nem.s.fDoIa32SpecCtrl)
1018 GET_REG64_LOG7(pCtxMsrs->msr.SpecCtrl, WHvX64RegisterSpecCtrl, "MSR IA32_SPEC_CTRL");
1019 /** @todo look for HvX64RegisterIa32MiscEnable and HvX64RegisterIa32FeatureControl? */
1020 }
1021 }
1022
1023 /* Interruptibility. */
1024 if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
1025 {
1026 Assert(aenmNames[iReg] == WHvRegisterInterruptState);
1027 Assert(aenmNames[iReg + 1] == WHvX64RegisterRip);
1028
1029 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
1030 pVCpu->nem.s.fLastInterruptShadow = CPUMUpdateInterruptShadowEx(&pVCpu->cpum.GstCtx,
1031 aValues[iReg].InterruptState.InterruptShadow,
1032 aValues[iReg + 1].Reg64);
1033
1034 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
1035 CPUMUpdateInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx, aValues[iReg].InterruptState.NmiMasked);
1036
1037 fWhat |= CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI;
1038 iReg += 2;
1039 }
1040
1041 /* Event injection. */
1042 /// @todo WHvRegisterPendingInterruption
1043 Assert(aenmNames[iReg] == WHvRegisterPendingInterruption);
1044 if (aValues[iReg].PendingInterruption.InterruptionPending)
1045 {
1046 Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
1047 aValues[iReg].PendingInterruption.InterruptionType, aValues[iReg].PendingInterruption.InterruptionVector,
1048 aValues[iReg].PendingInterruption.DeliverErrorCode, aValues[iReg].PendingInterruption.ErrorCode,
1049 aValues[iReg].PendingInterruption.InstructionLength, aValues[iReg].PendingInterruption.NestedEvent));
1050 AssertMsg((aValues[iReg].PendingInterruption.AsUINT64 & UINT64_C(0xfc00)) == 0,
1051 ("%#RX64\n", aValues[iReg].PendingInterruption.AsUINT64));
1052 }
1053
1054 /// @todo WHvRegisterPendingEvent
1055
1056 /* Almost done, just update extrn flags and maybe change PGM mode. */
1057 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1058 if (!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT))))
1059 pVCpu->cpum.GstCtx.fExtrn = 0;
1060
1061 /* Typical. */
1062 if (!fMaybeChangedMode && !fUpdateCr3)
1063 return VINF_SUCCESS;
1064
1065 /*
1066 * Slow.
1067 */
1068 if (fMaybeChangedMode)
1069 {
1070 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1071 false /* fForce */);
1072 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1073 }
1074
1075 if (fUpdateCr3)
1076 {
1077 int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);
1078 if (rc == VINF_SUCCESS)
1079 { /* likely */ }
1080 else
1081 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1082 }
1083
1084 return VINF_SUCCESS;
1085}
1086
1087
1088/**
1089 * Interface for importing state on demand (used by IEM).
1090 *
1091 * @returns VBox status code.
1092 * @param pVCpu The cross context CPU structure.
1093 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1094 */
1095VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1096{
1097 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1098 return nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, fWhat);
1099}
1100
1101
1102/**
1103 * Query the CPU tick counter and optionally the TSC_AUX MSR value.
1104 *
1105 * @returns VBox status code.
1106 * @param pVCpu The cross context CPU structure.
1107 * @param pcTicks Where to return the CPU tick count.
1108 * @param puAux Where to return the TSC_AUX register value.
1109 */
1110VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
1111{
1112 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1113
1114 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1115 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
1116 AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
1117
1118 /* Call the offical API. */
1119 WHV_REGISTER_NAME aenmNames[2] = { WHvX64RegisterTsc, WHvX64RegisterTscAux };
1120 WHV_REGISTER_VALUE aValues[2] = { { { { 0, 0 } } }, { { { 0, 0 } } } };
1121 Assert(RT_ELEMENTS(aenmNames) == RT_ELEMENTS(aValues));
1122 HRESULT hrc = WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, aenmNames, 2, aValues);
1123 AssertLogRelMsgReturn(SUCCEEDED(hrc),
1124 ("WHvGetVirtualProcessorRegisters(%p, %u,{tsc,tsc_aux},2,) -> %Rhrc (Last=%#x/%u)\n",
1125 pVM->nem.s.hPartition, pVCpu->idCpu, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1126 , VERR_NEM_GET_REGISTERS_FAILED);
1127 *pcTicks = aValues[0].Reg64;
1128 if (puAux)
1129 *puAux = pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_TSC_AUX ? aValues[1].Reg64 : CPUMGetGuestTscAux(pVCpu);
1130 return VINF_SUCCESS;
1131}
1132
1133
1134/**
1135 * Resumes CPU clock (TSC) on all virtual CPUs.
1136 *
1137 * This is called by TM when the VM is started, restored, resumed or similar.
1138 *
1139 * @returns VBox status code.
1140 * @param pVM The cross context VM structure.
1141 * @param pVCpu The cross context CPU structure of the calling EMT.
1142 * @param uPausedTscValue The TSC value at the time of pausing.
1143 */
1144VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1145{
1146 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
1147 AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
1148
1149 /*
1150 * Call the offical API to do the job.
1151 */
1152 if (pVM->cCpus > 1)
1153 RTThreadYield(); /* Try decrease the chance that we get rescheduled in the middle. */
1154
1155 /* Start with the first CPU. */
1156 WHV_REGISTER_NAME enmName = WHvX64RegisterTsc;
1157 WHV_REGISTER_VALUE Value = { { { 0, 0 } } };
1158 Value.Reg64 = uPausedTscValue;
1159 uint64_t const uFirstTsc = ASMReadTSC();
1160 HRESULT hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, 0 /*iCpu*/, &enmName, 1, &Value);
1161 AssertLogRelMsgReturn(SUCCEEDED(hrc),
1162 ("WHvSetVirtualProcessorRegisters(%p, 0,{tsc},2,%#RX64) -> %Rhrc (Last=%#x/%u)\n",
1163 pVM->nem.s.hPartition, uPausedTscValue, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1164 , VERR_NEM_SET_TSC);
1165
1166 /* Do the other CPUs, adjusting for elapsed TSC and keeping finger crossed
1167 that we don't introduce too much drift here. */
1168 for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
1169 {
1170 Assert(enmName == WHvX64RegisterTsc);
1171 const uint64_t offDelta = (ASMReadTSC() - uFirstTsc);
1172 Value.Reg64 = uPausedTscValue + offDelta;
1173 hrc = WHvSetVirtualProcessorRegisters(pVM->nem.s.hPartition, iCpu, &enmName, 1, &Value);
1174 AssertLogRelMsgReturn(SUCCEEDED(hrc),
1175 ("WHvSetVirtualProcessorRegisters(%p, 0,{tsc},2,%#RX64 + %#RX64) -> %Rhrc (Last=%#x/%u)\n",
1176 pVM->nem.s.hPartition, iCpu, uPausedTscValue, offDelta, hrc, RTNtLastStatusValue(), RTNtLastErrorValue())
1177 , VERR_NEM_SET_TSC);
1178 }
1179
1180 return VINF_SUCCESS;
1181}
1182
1183#ifdef LOG_ENABLED
1184
1185/**
1186 * Get the virtual processor running status.
1187 */
1188DECLINLINE(VID_PROCESSOR_STATUS) nemHCWinCpuGetRunningStatus(PVMCPUCC pVCpu)
1189{
1190 RTERRVARS Saved;
1191 RTErrVarsSave(&Saved);
1192
1193 /*
1194 * This API is disabled in release builds, it seems. On build 17101 it requires
1195 * the following patch to be enabled (windbg): eb vid+12180 0f 84 98 00 00 00
1196 */
1197 VID_PROCESSOR_STATUS enmCpuStatus = VidProcessorStatusUndefined;
1198 NTSTATUS rcNt = g_pfnVidGetVirtualProcessorRunningStatus(pVCpu->pVMR3->nem.s.hPartitionDevice, pVCpu->idCpu, &enmCpuStatus);
1199 AssertMsg(NT_SUCCESS(rcNt), ("rcNt=%#x\n", rcNt));
1200
1201 RTErrVarsRestore(&Saved);
1202 return enmCpuStatus;
1203}
1204
1205
1206/**
1207 * Logs the current CPU state.
1208 */
1209NEM_TMPL_STATIC void nemHCWinLogState(PVMCC pVM, PVMCPUCC pVCpu)
1210{
1211 if (LogIs3Enabled())
1212 {
1213# if 0 // def IN_RING3 - causes lazy state import assertions all over CPUM.
1214 char szRegs[4096];
1215 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
1216 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
1217 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
1218 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
1219 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
1220 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
1221 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
1222 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
1223 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
1224 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
1225 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
1226 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
1227 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
1228 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
1229 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
1230 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
1231 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
1232 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
1233 " efer=%016VR{efer}\n"
1234 " pat=%016VR{pat}\n"
1235 " sf_mask=%016VR{sf_mask}\n"
1236 "krnl_gs_base=%016VR{krnl_gs_base}\n"
1237 " lstar=%016VR{lstar}\n"
1238 " star=%016VR{star} cstar=%016VR{cstar}\n"
1239 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
1240 );
1241
1242 char szInstr[256];
1243 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
1244 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
1245 szInstr, sizeof(szInstr), NULL);
1246 Log3(("%s%s\n", szRegs, szInstr));
1247# else
1248 /** @todo stat logging in ring-0 */
1249 RT_NOREF(pVM, pVCpu);
1250# endif
1251 }
1252}
1253
1254#endif /* LOG_ENABLED */
1255
1256/**
1257 * Translates the execution stat bitfield into a short log string, WinHv version.
1258 *
1259 * @returns Read-only log string.
1260 * @param pExitCtx The exit context which state to summarize.
1261 */
1262static const char *nemR3WinExecStateToLogStr(WHV_VP_EXIT_CONTEXT const *pExitCtx)
1263{
1264 unsigned u = (unsigned)pExitCtx->ExecutionState.InterruptionPending
1265 | ((unsigned)pExitCtx->ExecutionState.DebugActive << 1)
1266 | ((unsigned)pExitCtx->ExecutionState.InterruptShadow << 2);
1267#define SWITCH_IT(a_szPrefix) \
1268 do \
1269 switch (u)\
1270 { \
1271 case 0x00: return a_szPrefix ""; \
1272 case 0x01: return a_szPrefix ",Pnd"; \
1273 case 0x02: return a_szPrefix ",Dbg"; \
1274 case 0x03: return a_szPrefix ",Pnd,Dbg"; \
1275 case 0x04: return a_szPrefix ",Shw"; \
1276 case 0x05: return a_szPrefix ",Pnd,Shw"; \
1277 case 0x06: return a_szPrefix ",Shw,Dbg"; \
1278 case 0x07: return a_szPrefix ",Pnd,Shw,Dbg"; \
1279 default: AssertFailedReturn("WTF?"); \
1280 } \
1281 while (0)
1282 if (pExitCtx->ExecutionState.EferLma)
1283 SWITCH_IT("LM");
1284 else if (pExitCtx->ExecutionState.Cr0Pe)
1285 SWITCH_IT("PM");
1286 else
1287 SWITCH_IT("RM");
1288#undef SWITCH_IT
1289}
1290
1291
1292/**
1293 * Advances the guest RIP and clear EFLAGS.RF, WinHv version.
1294 *
1295 * This may clear VMCPU_FF_INHIBIT_INTERRUPTS.
1296 *
1297 * @param pVCpu The cross context virtual CPU structure.
1298 * @param pExitCtx The exit context.
1299 * @param cbMinInstr The minimum instruction length, or 1 if not unknown.
1300 */
1301DECLINLINE(void) nemR3WinAdvanceGuestRipAndClearRF(PVMCPUCC pVCpu, WHV_VP_EXIT_CONTEXT const *pExitCtx, uint8_t cbMinInstr)
1302{
1303 Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
1304
1305 /* Advance the RIP. */
1306 Assert(pExitCtx->InstructionLength >= cbMinInstr); RT_NOREF_PV(cbMinInstr);
1307 pVCpu->cpum.GstCtx.rip += pExitCtx->InstructionLength;
1308 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
1309 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
1310}
1311
1312
1313/**
1314 * State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
1315 * and nemHCWinHandleMemoryAccessPageCheckerCallback.
1316 */
1317typedef struct NEMHCWINHMACPCCSTATE
1318{
1319 /** Input: Write access. */
1320 bool fWriteAccess;
1321 /** Output: Set if we did something. */
1322 bool fDidSomething;
1323 /** Output: Set it we should resume. */
1324 bool fCanResume;
1325} NEMHCWINHMACPCCSTATE;
1326
1327/**
1328 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1329 * Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1330 * NEMHCWINHMACPCCSTATE structure. }
1331 */
1332NEM_TMPL_STATIC DECLCALLBACK(int)
1333nemHCWinHandleMemoryAccessPageCheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1334{
1335 NEMHCWINHMACPCCSTATE *pState = (NEMHCWINHMACPCCSTATE *)pvUser;
1336 pState->fDidSomething = false;
1337 pState->fCanResume = false;
1338
1339 /* If A20 is disabled, we may need to make another query on the masked
1340 page to get the correct protection information. */
1341 uint8_t u2State = pInfo->u2NemState;
1342 RTGCPHYS GCPhysSrc;
1343#ifdef NEM_WIN_WITH_A20
1344 if ( pVM->nem.s.fA20Enabled
1345 || !NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
1346#endif
1347 GCPhysSrc = GCPhys;
1348#ifdef NEM_WIN_WITH_A20
1349 else
1350 {
1351 GCPhysSrc = GCPhys & ~(RTGCPHYS)RT_BIT_32(20);
1352 PGMPHYSNEMPAGEINFO Info2;
1353 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhysSrc, pState->fWriteAccess, &Info2, NULL, NULL);
1354 AssertRCReturn(rc, rc);
1355
1356 *pInfo = Info2;
1357 pInfo->u2NemState = u2State;
1358 }
1359#endif
1360
1361 /*
1362 * Consolidate current page state with actual page protection and access type.
1363 * We don't really consider downgrades here, as they shouldn't happen.
1364 */
1365 /** @todo Someone at microsoft please explain:
1366 * I'm not sure WTF was going on, but I ended up in a loop if I remapped a
1367 * readonly page as writable (unmap, then map again). Specifically, this was an
1368 * issue with the big VRAM mapping at 0xe0000000 when booing DSL 4.4.1. So, in
1369 * a hope to work around that we no longer pre-map anything, just unmap stuff
1370 * and do it lazily here. And here we will first unmap, restart, and then remap
1371 * with new protection or backing.
1372 */
1373 int rc;
1374 switch (u2State)
1375 {
1376 case NEM_WIN_PAGE_STATE_UNMAPPED:
1377 case NEM_WIN_PAGE_STATE_NOT_SET:
1378 if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1379 {
1380 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1381 return VINF_SUCCESS;
1382 }
1383
1384 /* Don't bother remapping it if it's a write request to a non-writable page. */
1385 if ( pState->fWriteAccess
1386 && !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1387 {
1388 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1389 return VINF_SUCCESS;
1390 }
1391
1392 /* Map the page. */
1393 rc = nemHCNativeSetPhysPage(pVM,
1394 pVCpu,
1395 GCPhysSrc & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1396 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1397 pInfo->fNemProt,
1398 &u2State,
1399 true /*fBackingState*/);
1400 pInfo->u2NemState = u2State;
1401 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1402 GCPhys, g_apszPageStates[u2State], rc));
1403 pState->fDidSomething = true;
1404 pState->fCanResume = true;
1405 return rc;
1406
1407 case NEM_WIN_PAGE_STATE_READABLE:
1408 if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1409 && (pInfo->fNemProt & (NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE)))
1410 {
1411 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1412 return VINF_SUCCESS;
1413 }
1414
1415 break;
1416
1417 case NEM_WIN_PAGE_STATE_WRITABLE:
1418 if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1419 {
1420 if (pInfo->u2OldNemState == NEM_WIN_PAGE_STATE_WRITABLE)
1421 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3a\n", GCPhys));
1422 else
1423 {
1424 pState->fCanResume = true;
1425 Log4(("nemHCWinHandleMemoryAccessPageCheckerCallback: %RGp - #3b (%s -> %s)\n",
1426 GCPhys, g_apszPageStates[pInfo->u2OldNemState], g_apszPageStates[u2State]));
1427 }
1428 return VINF_SUCCESS;
1429 }
1430 break;
1431
1432 default:
1433 AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_NEM_IPE_4);
1434 }
1435
1436 /*
1437 * Unmap and restart the instruction.
1438 * If this fails, which it does every so often, just unmap everything for now.
1439 */
1440 /** @todo figure out whether we mess up the state or if it's WHv. */
1441 STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
1442 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
1443 STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
1444 if (SUCCEEDED(hrc))
1445 {
1446 pState->fDidSomething = true;
1447 pState->fCanResume = true;
1448 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
1449 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
1450 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
1451 Log5(("NEM GPA unmapped/exit: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[u2State], cMappedPages));
1452 return VINF_SUCCESS;
1453 }
1454 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
1455 LogRel(("nemHCWinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s hrc=%Rhrc (%#x)\n",
1456 GCPhys, g_apszPageStates[u2State], hrc, hrc));
1457 return VERR_NEM_UNMAP_PAGES_FAILED;
1458}
1459
1460
1461/**
1462 * Wrapper around nemHCWinCopyStateFromHyperV.
1463 *
1464 * Unlike the wrapped APIs, this checks whether it's necessary.
1465 *
1466 * @returns VBox strict status code.
1467 * @param pVCpu The cross context per CPU structure.
1468 * @param fWhat What to import.
1469 * @param pszCaller Who is doing the importing.
1470 */
1471DECLINLINE(VBOXSTRICTRC) nemHCWinImportStateIfNeededStrict(PVMCPUCC pVCpu, uint64_t fWhat, const char *pszCaller)
1472{
1473 if (pVCpu->cpum.GstCtx.fExtrn & fWhat)
1474 {
1475 RT_NOREF(pszCaller);
1476 int rc = nemHCWinCopyStateFromHyperV(pVCpu->pVMR3, pVCpu, fWhat);
1477 AssertRCReturn(rc, rc);
1478 }
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/**
1484 * Copies register state from the (common) exit context.
1485 *
1486 * ASSUMES no state copied yet.
1487 *
1488 * @param pVCpu The cross context per CPU structure.
1489 * @param pExitCtx The common exit context.
1490 * @sa nemHCWinCopyStateFromX64Header
1491 */
1492DECLINLINE(void) nemR3WinCopyStateFromX64Header(PVMCPUCC pVCpu, WHV_VP_EXIT_CONTEXT const *pExitCtx)
1493{
1494 Assert( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_INHIBIT_INT))
1495 == (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_INHIBIT_INT));
1496
1497 NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.cs, pExitCtx->Cs);
1498 pVCpu->cpum.GstCtx.rip = pExitCtx->Rip;
1499 pVCpu->cpum.GstCtx.rflags.u = pExitCtx->Rflags;
1500 pVCpu->nem.s.fLastInterruptShadow = CPUMUpdateInterruptShadowEx(&pVCpu->cpum.GstCtx,
1501 pExitCtx->ExecutionState.InterruptShadow,
1502 pExitCtx->Rip);
1503 PDMApicSetTpr(pVCpu, pExitCtx->Cr8 << 4);
1504
1505 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_APIC_TPR);
1506}
1507
1508
1509/**
1510 * Deals with memory access exits (WHvRunVpExitReasonMemoryAccess).
1511 *
1512 * @returns Strict VBox status code.
1513 * @param pVM The cross context VM structure.
1514 * @param pVCpu The cross context per CPU structure.
1515 * @param pExit The VM exit information to handle.
1516 * @sa nemHCWinHandleMessageMemory
1517 */
1518NEM_TMPL_STATIC VBOXSTRICTRC
1519nemR3WinHandleExitMemory(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1520{
1521 uint64_t const uHostTsc = ASMReadTSC();
1522 Assert(pExit->MemoryAccess.AccessInfo.AccessType != 3);
1523
1524 /*
1525 * Whatever we do, we must clear pending event injection upon resume.
1526 */
1527 if (pExit->VpContext.ExecutionState.InterruptionPending)
1528 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1529
1530 /*
1531 * Ask PGM for information about the given GCPhys. We need to check if we're
1532 * out of sync first.
1533 */
1534 NEMHCWINHMACPCCSTATE State = { pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite, false, false };
1535 PGMPHYSNEMPAGEINFO Info;
1536 int rc = PGMPhysNemPageInfoChecker(pVM, pVCpu, pExit->MemoryAccess.Gpa, State.fWriteAccess, &Info,
1537 nemHCWinHandleMemoryAccessPageCheckerCallback, &State);
1538 if (RT_SUCCESS(rc))
1539 {
1540 if (Info.fNemProt & ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1541 ? NEM_PAGE_PROT_WRITE : NEM_PAGE_PROT_READ))
1542 {
1543 if (State.fCanResume)
1544 {
1545 Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp (=>%RHp) %s fProt=%u%s%s%s; restarting (%s)\n",
1546 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1547 pExit->MemoryAccess.Gpa, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1548 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1549 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1550 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_MEMORY_ACCESS),
1551 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc);
1552 return VINF_SUCCESS;
1553 }
1554 }
1555 Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp (=>%RHp) %s fProt=%u%s%s%s; emulating (%s)\n",
1556 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1557 pExit->MemoryAccess.Gpa, Info.HCPhys, g_apszPageStates[Info.u2NemState], Info.fNemProt,
1558 Info.fHasHandlers ? " handlers" : "", Info.fZeroPage ? " zero-pg" : "",
1559 State.fDidSomething ? "" : " no-change", g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1560 }
1561 else
1562 Log4(("MemExit/%u: %04x:%08RX64/%s: %RGp rc=%Rrc%s; emulating (%s)\n",
1563 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1564 pExit->MemoryAccess.Gpa, rc, State.fDidSomething ? " modified-backing" : "",
1565 g_apszHvInterceptAccessTypes[pExit->MemoryAccess.AccessInfo.AccessType]));
1566
1567 /*
1568 * Emulate the memory access, either access handler or special memory.
1569 */
1570 PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1571 pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1572 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1573 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1574 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, uHostTsc);
1575 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1576 rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1577 AssertRCReturn(rc, rc);
1578 if (pExit->VpContext.ExecutionState.Reserved0 || pExit->VpContext.ExecutionState.Reserved1)
1579 Log(("MemExit/Hdr/State: Reserved0=%#x Reserved1=%#x\n", pExit->VpContext.ExecutionState.Reserved0, pExit->VpContext.ExecutionState.Reserved1));
1580
1581 VBOXSTRICTRC rcStrict;
1582 if (!pExitRec)
1583 {
1584 //if (pMsg->InstructionByteCount > 0)
1585 // Log4(("InstructionByteCount=%#x %.16Rhxs\n", pMsg->InstructionByteCount, pMsg->InstructionBytes));
1586 if (pExit->MemoryAccess.InstructionByteCount > 0)
1587 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip, pExit->MemoryAccess.InstructionBytes, pExit->MemoryAccess.InstructionByteCount);
1588 else
1589 rcStrict = IEMExecOne(pVCpu);
1590 /** @todo do we need to do anything wrt debugging here? */
1591 }
1592 else
1593 {
1594 /* Frequent access or probing. */
1595 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1596 Log4(("MemExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1597 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1598 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1599 }
1600 return rcStrict;
1601}
1602
1603
1604/**
1605 * Deals with I/O port access exits (WHvRunVpExitReasonX64IoPortAccess).
1606 *
1607 * @returns Strict VBox status code.
1608 * @param pVM The cross context VM structure.
1609 * @param pVCpu The cross context per CPU structure.
1610 * @param pExit The VM exit information to handle.
1611 * @sa nemHCWinHandleMessageIoPort
1612 */
1613NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitIoPort(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1614{
1615 Assert( pExit->IoPortAccess.AccessInfo.AccessSize == 1
1616 || pExit->IoPortAccess.AccessInfo.AccessSize == 2
1617 || pExit->IoPortAccess.AccessInfo.AccessSize == 4);
1618
1619 /*
1620 * Whatever we do, we must clear pending event injection upon resume.
1621 */
1622 if (pExit->VpContext.ExecutionState.InterruptionPending)
1623 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
1624
1625 /*
1626 * Add history first to avoid two paths doing EMHistoryExec calls.
1627 */
1628 PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1629 !pExit->IoPortAccess.AccessInfo.StringOp
1630 ? ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1631 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE)
1632 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ))
1633 : ( pExit->MemoryAccess.AccessInfo.AccessType == WHvMemoryAccessWrite
1634 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)
1635 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)),
1636 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1637 if (!pExitRec)
1638 {
1639 VBOXSTRICTRC rcStrict;
1640 if (!pExit->IoPortAccess.AccessInfo.StringOp)
1641 {
1642 /*
1643 * Simple port I/O.
1644 */
1645 static uint32_t const s_fAndMask[8] =
1646 { UINT32_MAX, UINT32_C(0xff), UINT32_C(0xffff), UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX, UINT32_MAX };
1647 uint32_t const fAndMask = s_fAndMask[pExit->IoPortAccess.AccessInfo.AccessSize];
1648 if (pExit->IoPortAccess.AccessInfo.IsWrite)
1649 {
1650 rcStrict = IOMIOPortWrite(pVM, pVCpu, pExit->IoPortAccess.PortNumber,
1651 (uint32_t)pExit->IoPortAccess.Rax & fAndMask,
1652 pExit->IoPortAccess.AccessInfo.AccessSize);
1653 Log4(("IOExit/%u: %04x:%08RX64/%s: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
1654 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1655 pExit->IoPortAccess.PortNumber, (uint32_t)pExit->IoPortAccess.Rax & fAndMask,
1656 pExit->IoPortAccess.AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
1657 if (IOM_SUCCESS(rcStrict))
1658 {
1659 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1660 nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 1);
1661 }
1662 }
1663 else
1664 {
1665 uint32_t uValue = 0;
1666 rcStrict = IOMIOPortRead(pVM, pVCpu, pExit->IoPortAccess.PortNumber, &uValue,
1667 pExit->IoPortAccess.AccessInfo.AccessSize);
1668 Log4(("IOExit/%u: %04x:%08RX64/%s: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
1669 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1670 pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1671 if (IOM_SUCCESS(rcStrict))
1672 {
1673 if (pExit->IoPortAccess.AccessInfo.AccessSize != 4)
1674 pVCpu->cpum.GstCtx.rax = (pExit->IoPortAccess.Rax & ~(uint64_t)fAndMask) | (uValue & fAndMask);
1675 else
1676 pVCpu->cpum.GstCtx.rax = uValue;
1677 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_RAX;
1678 Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pExit->IoPortAccess.Rax, pVCpu->cpum.GstCtx.rax));
1679 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1680 nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 1);
1681 }
1682 }
1683 }
1684 else
1685 {
1686 /*
1687 * String port I/O.
1688 */
1689 /** @todo Someone at Microsoft please explain how we can get the address mode
1690 * from the IoPortAccess.VpContext. CS.Attributes is only sufficient for
1691 * getting the default mode, it can always be overridden by a prefix. This
1692 * forces us to interpret the instruction from opcodes, which is suboptimal.
1693 * Both AMD-V and VT-x includes the address size in the exit info, at least on
1694 * CPUs that are reasonably new.
1695 *
1696 * Of course, it's possible this is an undocumented and we just need to do some
1697 * experiments to figure out how it's communicated. Alternatively, we can scan
1698 * the opcode bytes for possible evil prefixes.
1699 */
1700 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1701 pVCpu->cpum.GstCtx.fExtrn &= ~( CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDI | CPUMCTX_EXTRN_RSI
1702 | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1703 NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.ds, pExit->IoPortAccess.Ds);
1704 NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.es, pExit->IoPortAccess.Es);
1705 pVCpu->cpum.GstCtx.rax = pExit->IoPortAccess.Rax;
1706 pVCpu->cpum.GstCtx.rcx = pExit->IoPortAccess.Rcx;
1707 pVCpu->cpum.GstCtx.rdi = pExit->IoPortAccess.Rdi;
1708 pVCpu->cpum.GstCtx.rsi = pExit->IoPortAccess.Rsi;
1709 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1710 AssertRCReturn(rc, rc);
1711
1712 Log4(("IOExit/%u: %04x:%08RX64/%s: %s%s %#x LB %u (emulating)\n",
1713 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1714 pExit->IoPortAccess.AccessInfo.RepPrefix ? "REP " : "",
1715 pExit->IoPortAccess.AccessInfo.IsWrite ? "OUTS" : "INS",
1716 pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize ));
1717 rcStrict = IEMExecOne(pVCpu);
1718 }
1719 if (IOM_SUCCESS(rcStrict))
1720 {
1721 /*
1722 * Do debug checks.
1723 */
1724 if ( pExit->VpContext.ExecutionState.DebugActive /** @todo Microsoft: Does DebugActive this only reflect DR7? */
1725 || (pExit->VpContext.Rflags & X86_EFL_TF)
1726 || DBGFBpIsHwIoArmed(pVM) )
1727 {
1728 /** @todo Debugging. */
1729 }
1730 }
1731 return rcStrict;
1732 }
1733
1734 /*
1735 * Frequent exit or something needing probing.
1736 * Get state and call EMHistoryExec.
1737 */
1738 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1739 if (!pExit->IoPortAccess.AccessInfo.StringOp)
1740 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_RAX;
1741 else
1742 {
1743 pVCpu->cpum.GstCtx.fExtrn &= ~( CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDI | CPUMCTX_EXTRN_RSI
1744 | CPUMCTX_EXTRN_DS | CPUMCTX_EXTRN_ES);
1745 NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.ds, pExit->IoPortAccess.Ds);
1746 NEM_WIN_COPY_BACK_SEG(pVCpu->cpum.GstCtx.es, pExit->IoPortAccess.Es);
1747 pVCpu->cpum.GstCtx.rcx = pExit->IoPortAccess.Rcx;
1748 pVCpu->cpum.GstCtx.rdi = pExit->IoPortAccess.Rdi;
1749 pVCpu->cpum.GstCtx.rsi = pExit->IoPortAccess.Rsi;
1750 }
1751 pVCpu->cpum.GstCtx.rax = pExit->IoPortAccess.Rax;
1752 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1753 AssertRCReturn(rc, rc);
1754 Log4(("IOExit/%u: %04x:%08RX64/%s: %s%s%s %#x LB %u -> EMHistoryExec\n",
1755 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1756 pExit->IoPortAccess.AccessInfo.RepPrefix ? "REP " : "",
1757 pExit->IoPortAccess.AccessInfo.IsWrite ? "OUT" : "IN",
1758 pExit->IoPortAccess.AccessInfo.StringOp ? "S" : "",
1759 pExit->IoPortAccess.PortNumber, pExit->IoPortAccess.AccessInfo.AccessSize));
1760 VBOXSTRICTRC rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1761 Log4(("IOExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1762 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1763 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1764 return rcStrict;
1765}
1766
1767
1768/**
1769 * Deals with interrupt window exits (WHvRunVpExitReasonX64InterruptWindow).
1770 *
1771 * @returns Strict VBox status code.
1772 * @param pVM The cross context VM structure.
1773 * @param pVCpu The cross context per CPU structure.
1774 * @param pExit The VM exit information to handle.
1775 * @sa nemHCWinHandleMessageInterruptWindow
1776 */
1777NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitInterruptWindow(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1778{
1779 /*
1780 * Assert message sanity.
1781 */
1782 AssertMsg( pExit->InterruptWindow.DeliverableType == WHvX64PendingInterrupt
1783 || pExit->InterruptWindow.DeliverableType == WHvX64PendingNmi,
1784 ("%#x\n", pExit->InterruptWindow.DeliverableType));
1785
1786 /*
1787 * Just copy the state we've got and handle it in the loop for now.
1788 */
1789 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),
1790 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1791
1792 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1793 Log4(("IntWinExit/%u: %04x:%08RX64/%s: %u IF=%d InterruptShadow=%d CR8=%#x\n",
1794 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1795 pExit->InterruptWindow.DeliverableType, RT_BOOL(pExit->VpContext.Rflags & X86_EFL_IF),
1796 pExit->VpContext.ExecutionState.InterruptShadow, pExit->VpContext.Cr8));
1797
1798 pVCpu->nem.s.fIrqWindowRegistered = false;
1799 pVCpu->nem.s.fPicReadyForInterrupt = true;
1800
1801 /** @todo call nemHCWinHandleInterruptFF */
1802 RT_NOREF(pVM);
1803 return VINF_SUCCESS;
1804}
1805
1806
1807/**
1808 * Deals with CPUID exits (WHvRunVpExitReasonX64Cpuid).
1809 *
1810 * @returns Strict VBox status code.
1811 * @param pVM The cross context VM structure.
1812 * @param pVCpu The cross context per CPU structure.
1813 * @param pExit The VM exit information to handle.
1814 * @sa nemHCWinHandleMessageCpuId
1815 */
1816NEM_TMPL_STATIC VBOXSTRICTRC
1817nemR3WinHandleExitCpuId(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1818{
1819 PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID),
1820 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1821 if (!pExitRec)
1822 {
1823 /*
1824 * Soak up state and execute the instruction.
1825 */
1826 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1827 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu,
1828 IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
1829 | CPUMCTX_EXTRN_CR3, /* May call PGMChangeMode() requiring cr3 (due to cr0 being imported). */
1830 "CPUID");
1831 if (rcStrict == VINF_SUCCESS)
1832 {
1833 /* Copy in the low register values (top is always cleared). */
1834 pVCpu->cpum.GstCtx.rax = (uint32_t)pExit->CpuidAccess.Rax;
1835 pVCpu->cpum.GstCtx.rcx = (uint32_t)pExit->CpuidAccess.Rcx;
1836 pVCpu->cpum.GstCtx.rdx = (uint32_t)pExit->CpuidAccess.Rdx;
1837 pVCpu->cpum.GstCtx.rbx = (uint32_t)pExit->CpuidAccess.Rbx;
1838 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
1839
1840 /* Execute the decoded instruction. */
1841 rcStrict = IEMExecDecodedCpuid(pVCpu, pExit->VpContext.InstructionLength);
1842
1843 Log4(("CpuIdExit/%u: %04x:%08RX64/%s: rax=%08RX64 / rcx=%08RX64 / rdx=%08RX64 / rbx=%08RX64 -> %08RX32 / %08RX32 / %08RX32 / %08RX32 (hv: %08RX64 / %08RX64 / %08RX64 / %08RX64)\n",
1844 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1845 pExit->CpuidAccess.Rax, pExit->CpuidAccess.Rcx, pExit->CpuidAccess.Rdx, pExit->CpuidAccess.Rbx,
1846 pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.ebx,
1847 pExit->CpuidAccess.DefaultResultRax, pExit->CpuidAccess.DefaultResultRcx, pExit->CpuidAccess.DefaultResultRdx, pExit->CpuidAccess.DefaultResultRbx));
1848 }
1849
1850 RT_NOREF_PV(pVM);
1851 return rcStrict;
1852 }
1853
1854 /*
1855 * Frequent exit or something needing probing.
1856 * Get state and call EMHistoryExec.
1857 */
1858 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1859 pVCpu->cpum.GstCtx.rax = pExit->CpuidAccess.Rax;
1860 pVCpu->cpum.GstCtx.rcx = pExit->CpuidAccess.Rcx;
1861 pVCpu->cpum.GstCtx.rdx = pExit->CpuidAccess.Rdx;
1862 pVCpu->cpum.GstCtx.rbx = pExit->CpuidAccess.Rbx;
1863 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
1864 Log4(("CpuIdExit/%u: %04x:%08RX64/%s: rax=%08RX64 / rcx=%08RX64 / rdx=%08RX64 / rbx=%08RX64 (hv: %08RX64 / %08RX64 / %08RX64 / %08RX64) ==> EMHistoryExec\n",
1865 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1866 pExit->CpuidAccess.Rax, pExit->CpuidAccess.Rcx, pExit->CpuidAccess.Rdx, pExit->CpuidAccess.Rbx,
1867 pExit->CpuidAccess.DefaultResultRax, pExit->CpuidAccess.DefaultResultRcx, pExit->CpuidAccess.DefaultResultRdx, pExit->CpuidAccess.DefaultResultRbx));
1868 int rc = nemHCWinCopyStateFromHyperV(pVM, pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM);
1869 AssertRCReturn(rc, rc);
1870 VBOXSTRICTRC rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1871 Log4(("CpuIdExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1872 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1873 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1874 return rcStrict;
1875}
1876
1877
1878/**
1879 * Deals with MSR access exits (WHvRunVpExitReasonX64MsrAccess).
1880 *
1881 * @returns Strict VBox status code.
1882 * @param pVM The cross context VM structure.
1883 * @param pVCpu The cross context per CPU structure.
1884 * @param pExit The VM exit information to handle.
1885 * @sa nemHCWinHandleMessageMsr
1886 */
1887NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitMsr(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
1888{
1889 /*
1890 * Check CPL as that's common to both RDMSR and WRMSR.
1891 */
1892 VBOXSTRICTRC rcStrict;
1893 if (pExit->VpContext.ExecutionState.Cpl == 0)
1894 {
1895 /*
1896 * Get all the MSR state. Since we're getting EFER, we also need to
1897 * get CR0, CR4 and CR3.
1898 */
1899 PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu,
1900 pExit->MsrAccess.AccessInfo.IsWrite
1901 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE)
1902 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ),
1903 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
1904 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
1905 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu,
1906 (!pExitRec ? 0 : IEM_CPUMCTX_EXTRN_MUST_MASK)
1907 | CPUMCTX_EXTRN_ALL_MSRS | CPUMCTX_EXTRN_CR0
1908 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4,
1909 "MSRs");
1910 if (rcStrict == VINF_SUCCESS)
1911 {
1912 if (!pExitRec)
1913 {
1914 /*
1915 * Handle writes.
1916 */
1917 if (pExit->MsrAccess.AccessInfo.IsWrite)
1918 {
1919 rcStrict = CPUMSetGuestMsr(pVCpu, pExit->MsrAccess.MsrNumber,
1920 RT_MAKE_U64((uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx));
1921 Log4(("MsrExit/%u: %04x:%08RX64/%s: WRMSR %08x, %08x:%08x -> %Rrc\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1922 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->MsrAccess.MsrNumber,
1923 (uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx, VBOXSTRICTRC_VAL(rcStrict) ));
1924 if (rcStrict == VINF_SUCCESS)
1925 {
1926 nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 2);
1927 return VINF_SUCCESS;
1928 }
1929 LogRel(("MsrExit/%u: %04x:%08RX64/%s: WRMSR %08x, %08x:%08x -> %Rrc!\n", pVCpu->idCpu,
1930 pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1931 pExit->MsrAccess.MsrNumber, (uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx,
1932 VBOXSTRICTRC_VAL(rcStrict) ));
1933 }
1934 /*
1935 * Handle reads.
1936 */
1937 else
1938 {
1939 uint64_t uValue = 0;
1940 rcStrict = CPUMQueryGuestMsr(pVCpu, pExit->MsrAccess.MsrNumber, &uValue);
1941 Log4(("MsrExit/%u: %04x:%08RX64/%s: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu,
1942 pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1943 pExit->MsrAccess.MsrNumber, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1944 if (rcStrict == VINF_SUCCESS)
1945 {
1946 pVCpu->cpum.GstCtx.rax = (uint32_t)uValue;
1947 pVCpu->cpum.GstCtx.rdx = uValue >> 32;
1948 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
1949 nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pExit->VpContext, 2);
1950 return VINF_SUCCESS;
1951 }
1952 LogRel(("MsrExit/%u: %04x:%08RX64/%s: RDMSR %08x -> %08RX64 / %Rrc\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1953 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->MsrAccess.MsrNumber,
1954 uValue, VBOXSTRICTRC_VAL(rcStrict) ));
1955 }
1956 }
1957 else
1958 {
1959 /*
1960 * Handle frequent exit or something needing probing.
1961 */
1962 Log4(("MsrExit/%u: %04x:%08RX64/%s: %sMSR %#08x\n",
1963 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1964 pExit->MsrAccess.AccessInfo.IsWrite ? "WR" : "RD", pExit->MsrAccess.MsrNumber));
1965 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
1966 Log4(("MsrExit/%u: %04x:%08RX64/%s: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
1967 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1968 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
1969 return rcStrict;
1970 }
1971 }
1972 else
1973 {
1974 LogRel(("MsrExit/%u: %04x:%08RX64/%s: %sMSR %08x -> %Rrc - msr state import\n",
1975 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
1976 pExit->MsrAccess.AccessInfo.IsWrite ? "WR" : "RD", pExit->MsrAccess.MsrNumber, VBOXSTRICTRC_VAL(rcStrict) ));
1977 return rcStrict;
1978 }
1979 }
1980 else if (pExit->MsrAccess.AccessInfo.IsWrite)
1981 Log4(("MsrExit/%u: %04x:%08RX64/%s: CPL %u -> #GP(0); WRMSR %08x, %08x:%08x\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1982 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.ExecutionState.Cpl,
1983 pExit->MsrAccess.MsrNumber, (uint32_t)pExit->MsrAccess.Rax, (uint32_t)pExit->MsrAccess.Rdx ));
1984 else
1985 Log4(("MsrExit/%u: %04x:%08RX64/%s: CPL %u -> #GP(0); RDMSR %08x\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
1986 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.ExecutionState.Cpl,
1987 pExit->MsrAccess.MsrNumber));
1988
1989 /*
1990 * If we get down here, we're supposed to #GP(0).
1991 */
1992 rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL_MSRS, "MSR");
1993 if (rcStrict == VINF_SUCCESS)
1994 {
1995 rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_GP, TRPM_TRAP, 0, 0, 0);
1996 if (rcStrict == VINF_IEM_RAISED_XCPT)
1997 rcStrict = VINF_SUCCESS;
1998 else if (rcStrict != VINF_SUCCESS)
1999 Log4(("MsrExit/%u: Injecting #GP(0) failed: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
2000 }
2001
2002 RT_NOREF_PV(pVM);
2003 return rcStrict;
2004}
2005
2006
2007/**
2008 * Worker for nemHCWinHandleMessageException & nemR3WinHandleExitException that
2009 * checks if the given opcodes are of interest at all.
2010 *
2011 * @returns true if interesting, false if not.
2012 * @param cbOpcodes Number of opcode bytes available.
2013 * @param pbOpcodes The opcode bytes.
2014 * @param f64BitMode Whether we're in 64-bit mode.
2015 */
2016DECLINLINE(bool) nemHcWinIsInterestingUndefinedOpcode(uint8_t cbOpcodes, uint8_t const *pbOpcodes, bool f64BitMode)
2017{
2018 /*
2019 * Currently only interested in VMCALL and VMMCALL.
2020 */
2021 while (cbOpcodes >= 3)
2022 {
2023 switch (pbOpcodes[0])
2024 {
2025 case 0x0f:
2026 switch (pbOpcodes[1])
2027 {
2028 case 0x01:
2029 switch (pbOpcodes[2])
2030 {
2031 case 0xc1: /* 0f 01 c1 VMCALL */
2032 return true;
2033 case 0xd9: /* 0f 01 d9 VMMCALL */
2034 return true;
2035 default:
2036 break;
2037 }
2038 break;
2039 }
2040 break;
2041
2042 default:
2043 return false;
2044
2045 /* prefixes */
2046 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
2047 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2048 if (!f64BitMode)
2049 return false;
2050 RT_FALL_THRU();
2051 case X86_OP_PRF_CS:
2052 case X86_OP_PRF_SS:
2053 case X86_OP_PRF_DS:
2054 case X86_OP_PRF_ES:
2055 case X86_OP_PRF_FS:
2056 case X86_OP_PRF_GS:
2057 case X86_OP_PRF_SIZE_OP:
2058 case X86_OP_PRF_SIZE_ADDR:
2059 case X86_OP_PRF_LOCK:
2060 case X86_OP_PRF_REPZ:
2061 case X86_OP_PRF_REPNZ:
2062 cbOpcodes--;
2063 pbOpcodes++;
2064 continue;
2065 }
2066 break;
2067 }
2068 return false;
2069}
2070
2071
2072/**
2073 * Copies state included in a exception intercept exit.
2074 *
2075 * @param pVCpu The cross context per CPU structure.
2076 * @param pExit The VM exit information.
2077 * @param fClearXcpt Clear pending exception.
2078 */
2079DECLINLINE(void) nemR3WinCopyStateFromExceptionMessage(PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit, bool fClearXcpt)
2080{
2081 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2082 if (fClearXcpt)
2083 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
2084}
2085
2086
2087/**
2088 * Advances the guest RIP by the number of bytes specified in @a cb.
2089 *
2090 * @param pVCpu The cross context virtual CPU structure.
2091 * @param cb RIP increment value in bytes.
2092 */
2093DECLINLINE(void) nemHcWinAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
2094{
2095 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2096 pCtx->rip += cb;
2097 /** @todo Why not clear RF too? */
2098 CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
2099}
2100
2101
2102/**
2103 * Hacks its way around the lovely mesa driver's backdoor accesses.
2104 *
2105 * @sa hmR0VmxHandleMesaDrvGp
2106 * @sa hmR0SvmHandleMesaDrvGp
2107 */
2108static int nemHcWinHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx)
2109{
2110 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_GPRS_MASK)));
2111 RT_NOREF(pCtx);
2112
2113 /* For now we'll just skip the instruction. */
2114 nemHcWinAdvanceRip(pVCpu, 1);
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/**
2120 * Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
2121 * backdoor logging w/o checking what it is running inside.
2122 *
2123 * This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
2124 * backdoor port and magic numbers loaded in registers.
2125 *
2126 * @returns true if it is, false if it isn't.
2127 * @sa hmR0VmxIsMesaDrvGp
2128 * @sa hmR0SvmIsMesaDrvGp
2129 */
2130DECLINLINE(bool) nemHcWinIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, const uint8_t *pbInsn, uint32_t cbInsn)
2131{
2132 /* #GP(0) is already checked by caller. */
2133
2134 /* Check magic and port. */
2135 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RAX)));
2136 if (pCtx->dx != UINT32_C(0x5658))
2137 return false;
2138 if (pCtx->rax != UINT32_C(0x564d5868))
2139 return false;
2140
2141 /* Flat ring-3 CS. */
2142 if (CPUMGetGuestCPL(pVCpu) != 3)
2143 return false;
2144 if (pCtx->cs.u64Base != 0)
2145 return false;
2146
2147 /* 0xed: IN eAX,dx */
2148 if (cbInsn < 1) /* Play safe (shouldn't happen). */
2149 {
2150 uint8_t abInstr[1];
2151 int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
2152 if (RT_FAILURE(rc))
2153 return false;
2154 if (abInstr[0] != 0xed)
2155 return false;
2156 }
2157 else
2158 {
2159 if (pbInsn[0] != 0xed)
2160 return false;
2161 }
2162
2163 return true;
2164}
2165
2166
2167/**
2168 * Deals with MSR access exits (WHvRunVpExitReasonException).
2169 *
2170 * @returns Strict VBox status code.
2171 * @param pVM The cross context VM structure.
2172 * @param pVCpu The cross context per CPU structure.
2173 * @param pExit The VM exit information to handle.
2174 * @sa nemR3WinHandleExitException
2175 */
2176NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitException(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2177{
2178 /*
2179 * Get most of the register state since we'll end up making IEM inject the
2180 * event. The exception isn't normally flaged as a pending event, so duh.
2181 *
2182 * Note! We can optimize this later with event injection.
2183 */
2184 Log4(("XcptExit/%u: %04x:%08RX64/%s: %x errcd=%#x parm=%RX64\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2185 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpException.ExceptionType,
2186 pExit->VpException.ErrorCode, pExit->VpException.ExceptionParameter ));
2187 nemR3WinCopyStateFromExceptionMessage(pVCpu, pExit, true /*fClearXcpt*/);
2188 uint64_t fWhat = NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2189 if (pExit->VpException.ExceptionType == X86_XCPT_DB)
2190 fWhat |= CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6;
2191 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, fWhat, "Xcpt");
2192 if (rcStrict != VINF_SUCCESS)
2193 return rcStrict;
2194
2195 /*
2196 * Handle the intercept.
2197 */
2198 TRPMEVENT enmEvtType = TRPM_TRAP;
2199 switch (pExit->VpException.ExceptionType)
2200 {
2201 /*
2202 * We get undefined opcodes on VMMCALL(AMD) & VMCALL(Intel) instructions
2203 * and need to turn them over to GIM.
2204 *
2205 * Note! We do not check fGIMTrapXcptUD here ASSUMING that GIM only wants
2206 * #UD for handling non-native hypercall instructions. (IEM will
2207 * decode both and let the GIM provider decide whether to accept it.)
2208 */
2209 case X86_XCPT_UD:
2210 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUd);
2211 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_UD),
2212 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2213 if (nemHcWinIsInterestingUndefinedOpcode(pExit->VpException.InstructionByteCount, pExit->VpException.InstructionBytes,
2214 pExit->VpContext.ExecutionState.EferLma && pExit->VpContext.Cs.Long ))
2215 {
2216 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip,
2217 pExit->VpException.InstructionBytes,
2218 pExit->VpException.InstructionByteCount);
2219 Log4(("XcptExit/%u: %04x:%08RX64/%s: #UD -> emulated -> %Rrc\n",
2220 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2221 nemR3WinExecStateToLogStr(&pExit->VpContext), VBOXSTRICTRC_VAL(rcStrict) ));
2222 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUdHandled);
2223 return rcStrict;
2224 }
2225
2226 Log4(("XcptExit/%u: %04x:%08RX64/%s: #UD [%.*Rhxs] -> re-injected\n", pVCpu->idCpu,
2227 pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext),
2228 pExit->VpException.InstructionByteCount, pExit->VpException.InstructionBytes ));
2229 break;
2230
2231 /*
2232 * Workaround the lovely mesa driver assuming that vmsvga means vmware
2233 * hypervisor and tries to log stuff to the host.
2234 */
2235 case X86_XCPT_GP:
2236 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionGp);
2237 /** @todo r=bird: Need workaround in IEM for this, right?
2238 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_GP),
2239 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC()); */
2240 if ( !pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv
2241 || !nemHcWinIsMesaDrvGp(pVCpu, &pVCpu->cpum.GstCtx, pExit->VpException.InstructionBytes,
2242 pExit->VpException.InstructionByteCount))
2243 {
2244#if 1 /** @todo Need to emulate instruction or we get a triple fault when trying to inject the \#GP... */
2245 rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, pExit->VpContext.Rip,
2246 pExit->VpException.InstructionBytes,
2247 pExit->VpException.InstructionByteCount);
2248 Log4(("XcptExit/%u: %04x:%08RX64/%s: #GP -> emulated -> %Rrc\n",
2249 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2250 nemR3WinExecStateToLogStr(&pExit->VpContext), VBOXSTRICTRC_VAL(rcStrict) ));
2251 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionUdHandled);
2252 return rcStrict;
2253#else
2254 break;
2255#endif
2256 }
2257 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionGpMesa);
2258 return nemHcWinHandleMesaDrvGp(pVCpu, &pVCpu->cpum.GstCtx);
2259
2260 /*
2261 * Filter debug exceptions.
2262 */
2263 case X86_XCPT_DB:
2264 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionDb);
2265 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_DB),
2266 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2267 Log4(("XcptExit/%u: %04x:%08RX64/%s: #DB - TODO\n",
2268 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext) ));
2269 break;
2270
2271 case X86_XCPT_BP:
2272 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitExceptionBp);
2273 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_XCPT_BP),
2274 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2275 Log4(("XcptExit/%u: %04x:%08RX64/%s: #BP - TODO - %u\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2276 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.InstructionLength));
2277 enmEvtType = TRPM_SOFTWARE_INT; /* We're at the INT3 instruction, not after it. */
2278 break;
2279
2280 /* This shouldn't happen. */
2281 default:
2282 AssertLogRelMsgFailedReturn(("ExceptionType=%#x\n", pExit->VpException.ExceptionType), VERR_IEM_IPE_6);
2283 }
2284
2285 /*
2286 * Inject it.
2287 */
2288 rcStrict = IEMInjectTrap(pVCpu, pExit->VpException.ExceptionType, enmEvtType, pExit->VpException.ErrorCode,
2289 pExit->VpException.ExceptionParameter /*??*/, pExit->VpContext.InstructionLength);
2290 Log4(("XcptExit/%u: %04x:%08RX64/%s: %#u -> injected -> %Rrc\n",
2291 pVCpu->idCpu, pExit->VpContext.Cs.Selector, pExit->VpContext.Rip,
2292 nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpException.ExceptionType, VBOXSTRICTRC_VAL(rcStrict) ));
2293
2294 RT_NOREF_PV(pVM);
2295 return rcStrict;
2296}
2297
2298
2299/**
2300 * Deals with MSR access exits (WHvRunVpExitReasonUnrecoverableException).
2301 *
2302 * @returns Strict VBox status code.
2303 * @param pVM The cross context VM structure.
2304 * @param pVCpu The cross context per CPU structure.
2305 * @param pExit The VM exit information to handle.
2306 * @sa nemHCWinHandleMessageUnrecoverableException
2307 */
2308NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExitUnrecoverableException(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2309{
2310#if 0
2311 /*
2312 * Just copy the state we've got and handle it in the loop for now.
2313 */
2314 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2315 Log(("TripleExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_EM_TRIPLE_FAULT\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2316 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags));
2317 RT_NOREF_PV(pVM);
2318 return VINF_EM_TRIPLE_FAULT;
2319#else
2320 /*
2321 * Let IEM decide whether this is really it.
2322 */
2323 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_UNRECOVERABLE_EXCEPTION),
2324 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2325 nemR3WinCopyStateFromX64Header(pVCpu, &pExit->VpContext);
2326 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM | CPUMCTX_EXTRN_ALL, "TripleExit");
2327 if (rcStrict == VINF_SUCCESS)
2328 {
2329 rcStrict = IEMExecOne(pVCpu);
2330 if (rcStrict == VINF_SUCCESS)
2331 {
2332 Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_SUCCESS\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2333 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags));
2334 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT; /* Make sure to reset pending #DB(0). */
2335 return VINF_SUCCESS;
2336 }
2337 if (rcStrict == VINF_EM_TRIPLE_FAULT)
2338 Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_EM_TRIPLE_FAULT!\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2339 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2340 else
2341 Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> %Rrc (IEMExecOne)\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2342 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2343 }
2344 else
2345 Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> %Rrc (state import)\n", pVCpu->idCpu, pExit->VpContext.Cs.Selector,
2346 pExit->VpContext.Rip, nemR3WinExecStateToLogStr(&pExit->VpContext), pExit->VpContext.Rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2347 RT_NOREF_PV(pVM);
2348 return rcStrict;
2349#endif
2350}
2351
2352
2353/**
2354 * Handles VM exits.
2355 *
2356 * @returns Strict VBox status code.
2357 * @param pVM The cross context VM structure.
2358 * @param pVCpu The cross context per CPU structure.
2359 * @param pExit The VM exit information to handle.
2360 * @sa nemHCWinHandleMessage
2361 */
2362NEM_TMPL_STATIC VBOXSTRICTRC nemR3WinHandleExit(PVMCC pVM, PVMCPUCC pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
2363{
2364 switch (pExit->ExitReason)
2365 {
2366 case WHvRunVpExitReasonMemoryAccess:
2367 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMemUnmapped);
2368 return nemR3WinHandleExitMemory(pVM, pVCpu, pExit);
2369
2370 case WHvRunVpExitReasonX64IoPortAccess:
2371 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitPortIo);
2372 return nemR3WinHandleExitIoPort(pVM, pVCpu, pExit);
2373
2374 case WHvRunVpExitReasonX64Halt:
2375 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2376 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),
2377 pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
2378 Log4(("HaltExit/%u\n", pVCpu->idCpu));
2379 return VINF_EM_HALT;
2380
2381 case WHvRunVpExitReasonCanceled:
2382 Log4(("CanceledExit/%u\n", pVCpu->idCpu));
2383 return VINF_SUCCESS;
2384
2385 case WHvRunVpExitReasonX64InterruptWindow:
2386 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInterruptWindow);
2387 return nemR3WinHandleExitInterruptWindow(pVM, pVCpu, pExit);
2388
2389 case WHvRunVpExitReasonX64Cpuid:
2390 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitCpuId);
2391 return nemR3WinHandleExitCpuId(pVM, pVCpu, pExit);
2392
2393 case WHvRunVpExitReasonX64MsrAccess:
2394 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMsr);
2395 return nemR3WinHandleExitMsr(pVM, pVCpu, pExit);
2396
2397 case WHvRunVpExitReasonException:
2398 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitException);
2399 return nemR3WinHandleExitException(pVM, pVCpu, pExit);
2400
2401 case WHvRunVpExitReasonUnrecoverableException:
2402 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitUnrecoverable);
2403 return nemR3WinHandleExitUnrecoverableException(pVM, pVCpu, pExit);
2404
2405 case WHvRunVpExitReasonX64ApicEoi:
2406 Assert(pVM->nem.s.fLocalApicEmulation);
2407 PDMIoApicBroadcastEoi(pVCpu->CTX_SUFF(pVM), pExit->ApicEoi.InterruptVector);
2408 return VINF_SUCCESS;
2409
2410 case WHvRunVpExitReasonUnsupportedFeature:
2411 case WHvRunVpExitReasonInvalidVpRegisterValue:
2412 LogRel(("Unimplemented exit:\n%.*Rhxd\n", (int)sizeof(*pExit), pExit));
2413 AssertLogRelMsgFailedReturn(("Unexpected exit on CPU #%u: %#x\n%.32Rhxd\n",
2414 pVCpu->idCpu, pExit->ExitReason, pExit), VERR_NEM_IPE_3);
2415
2416 /* Undesired exits: */
2417 case WHvRunVpExitReasonNone:
2418 default:
2419 LogRel(("Unknown exit:\n%.*Rhxd\n", (int)sizeof(*pExit), pExit));
2420 AssertLogRelMsgFailedReturn(("Unknown exit on CPU #%u: %#x!\n", pVCpu->idCpu, pExit->ExitReason), VERR_NEM_IPE_3);
2421 }
2422}
2423
2424
2425/**
2426 * Deals with pending interrupt related force flags, may inject interrupt.
2427 *
2428 * @returns VBox strict status code.
2429 * @param pVM The cross context VM structure.
2430 * @param pVCpu The cross context per CPU structure.
2431 * @param pfInterruptWindows Where to return interrupt window flags.
2432 */
2433NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinHandleInterruptFF(PVMCC pVM, PVMCPUCC pVCpu, uint8_t *pfInterruptWindows)
2434{
2435 Assert(!TRPMHasTrap(pVCpu) && !pVM->nem.s.fLocalApicEmulation);
2436 RT_NOREF_PV(pVM);
2437
2438 /*
2439 * First update APIC. We ASSUME this won't need TPR/CR8.
2440 */
2441 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2442 {
2443 PDMApicUpdatePendingInterrupts(pVCpu);
2444 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
2445 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2446 return VINF_SUCCESS;
2447 }
2448
2449 /*
2450 * We don't currently implement SMIs.
2451 */
2452 AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
2453
2454 /*
2455 * Check if we've got the minimum of state required for deciding whether we
2456 * can inject interrupts and NMIs. If we don't have it, get all we might require
2457 * for injection via IEM.
2458 */
2459 bool const fPendingNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2460 uint64_t fNeedExtrn = CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS
2461 | (fPendingNmi ? CPUMCTX_EXTRN_INHIBIT_NMI : 0);
2462 if (pVCpu->cpum.GstCtx.fExtrn & fNeedExtrn)
2463 {
2464 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "IntFF");
2465 if (rcStrict != VINF_SUCCESS)
2466 return rcStrict;
2467 }
2468
2469 /*
2470 * NMI? Try deliver it first.
2471 */
2472 if (fPendingNmi)
2473 {
2474 if ( !CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx)
2475 && !CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
2476 {
2477 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI");
2478 if (rcStrict == VINF_SUCCESS)
2479 {
2480 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2481 rcStrict = IEMInjectTrap(pVCpu, X86_XCPT_NMI, TRPM_HARDWARE_INT, 0, 0, 0);
2482 Log8(("Injected NMI on %u (%d)\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2483 }
2484 return rcStrict;
2485 }
2486 *pfInterruptWindows |= NEM_WIN_INTW_F_NMI;
2487 Log8(("NMI window pending on %u\n", pVCpu->idCpu));
2488 }
2489
2490 /*
2491 * APIC or PIC interrupt?
2492 */
2493 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2494 {
2495 /** @todo check NMI inhibiting here too! */
2496 if ( !CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx)
2497 && pVCpu->cpum.GstCtx.rflags.Bits.u1IF)
2498 {
2499 AssertCompile(NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT & CPUMCTX_EXTRN_APIC_TPR);
2500 VBOXSTRICTRC rcStrict = nemHCWinImportStateIfNeededStrict(pVCpu, NEM_WIN_CPUMCTX_EXTRN_MASK_FOR_IEM_XCPT, "NMI");
2501 if (rcStrict == VINF_SUCCESS)
2502 {
2503 uint8_t bInterrupt;
2504 int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2505 if (RT_SUCCESS(rc))
2506 {
2507 Log8(("Injecting interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags.u));
2508 rcStrict = IEMInjectTrap(pVCpu, bInterrupt, TRPM_HARDWARE_INT, 0, 0, 0);
2509 Log8(("Injected interrupt %#x on %u (%d)\n", bInterrupt, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2510 }
2511 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2512 {
2513 *pfInterruptWindows |= ((bInterrupt >> 4) << NEM_WIN_INTW_F_PRIO_SHIFT) | NEM_WIN_INTW_F_REGULAR;
2514 Log8(("VERR_APIC_INTR_MASKED_BY_TPR: *pfInterruptWindows=%#x\n", *pfInterruptWindows));
2515 }
2516 else
2517 Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2518 }
2519 return rcStrict;
2520 }
2521
2522 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC) && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
2523 {
2524 /* If only an APIC interrupt is pending, we need to know its priority. Otherwise we'll
2525 * likely get pointless deliverability notifications with IF=1 but TPR still too high.
2526 */
2527 bool fPendingIntr = false;
2528 uint8_t bTpr = 0;
2529 uint8_t bPendingIntr = 0;
2530 int rc = PDMApicGetTpr(pVCpu, &bTpr, &fPendingIntr, &bPendingIntr);
2531 AssertRC(rc);
2532 *pfInterruptWindows |= ((bPendingIntr >> 4) << NEM_WIN_INTW_F_PRIO_SHIFT) | NEM_WIN_INTW_F_REGULAR;
2533 Log8(("Interrupt window pending on %u: %#x (bTpr=%#x fPendingIntr=%d bPendingIntr=%#x)\n",
2534 pVCpu->idCpu, *pfInterruptWindows, bTpr, fPendingIntr, bPendingIntr));
2535 }
2536 else
2537 {
2538 *pfInterruptWindows |= NEM_WIN_INTW_F_REGULAR;
2539 Log8(("Interrupt window pending on %u: %#x\n", pVCpu->idCpu, *pfInterruptWindows));
2540 }
2541 }
2542
2543 return VINF_SUCCESS;
2544}
2545
2546
2547/**
2548 * Inner NEM runloop for windows.
2549 *
2550 * @returns Strict VBox status code.
2551 * @param pVM The cross context VM structure.
2552 * @param pVCpu The cross context per CPU structure.
2553 */
2554NEM_TMPL_STATIC VBOXSTRICTRC nemHCWinRunGC(PVMCC pVM, PVMCPUCC pVCpu)
2555{
2556 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u));
2557#ifdef LOG_ENABLED
2558 if (LogIs3Enabled())
2559 nemHCWinLogState(pVM, pVCpu);
2560#endif
2561
2562 /*
2563 * Try switch to NEM runloop state.
2564 */
2565 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2566 { /* likely */ }
2567 else
2568 {
2569 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2570 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2571 return VINF_SUCCESS;
2572 }
2573
2574 /*
2575 * The run loop.
2576 *
2577 * Current approach to state updating to use the sledgehammer and sync
2578 * everything every time. This will be optimized later.
2579 */
2580 const bool fSingleStepping = DBGFIsStepping(pVCpu);
2581// const uint32_t fCheckVmFFs = !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK
2582// : VM_FF_HP_R0_PRE_HM_STEP_MASK;
2583// const uint32_t fCheckCpuFFs = !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK;
2584 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2585 for (unsigned iLoop = 0;; iLoop++)
2586 {
2587 /*
2588 * Pending interrupts or such? Need to check and deal with this prior
2589 * to the state syncing.
2590 */
2591 pVCpu->nem.s.fDesiredInterruptWindows = 0;
2592 if (!pVM->nem.s.fLocalApicEmulation)
2593 {
2594 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC
2595 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2596 {
2597 /* Try inject interrupt. */
2598 rcStrict = nemHCWinHandleInterruptFF(pVM, pVCpu, &pVCpu->nem.s.fDesiredInterruptWindows);
2599 if (rcStrict == VINF_SUCCESS)
2600 { /* likely */ }
2601 else
2602 {
2603 LogFlow(("NEM/%u: breaking: nemHCWinHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2604 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2605 break;
2606 }
2607 }
2608 }
2609 else
2610 {
2611 /* We only need to handle the PIC usign ExtInt here, the APIC is handled through the NEM APIC backend. */
2612 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC));
2613
2614 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC))
2615 pVCpu->nem.s.fDesiredInterruptWindows |= NEM_WIN_INTW_F_REGULAR;
2616 }
2617
2618#ifndef NEM_WIN_WITH_A20
2619 /*
2620 * Do not execute in hyper-V if the A20 isn't enabled.
2621 */
2622 if (PGMPhysIsA20Enabled(pVCpu))
2623 { /* likely */ }
2624 else
2625 {
2626 rcStrict = VINF_EM_RESCHEDULE_REM;
2627 LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2628 break;
2629 }
2630#endif
2631
2632 /*
2633 * Ensure that hyper-V has the whole state.
2634 * (We always update the interrupt windows settings when active as hyper-V seems
2635 * to forget about it after an exit.)
2636 */
2637 if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK))
2638 != (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK)
2639 || ( ( pVCpu->nem.s.fDesiredInterruptWindows
2640 || pVCpu->nem.s.fCurrentInterruptWindows != pVCpu->nem.s.fDesiredInterruptWindows) ) )
2641 {
2642 int rc2 = nemHCWinCopyStateToHyperV(pVM, pVCpu);
2643 AssertRCReturn(rc2, rc2);
2644 }
2645
2646 /*
2647 * Poll timers and run for a bit.
2648 *
2649 * With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2650 * so we take the time of the next timer event and uses that as a deadline.
2651 * The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2652 */
2653 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2654 * the whole polling job when timers have changed... */
2655 uint64_t offDeltaIgnored;
2656 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2657 if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
2658 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2659 {
2660 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2661 {
2662#ifdef LOG_ENABLED
2663 if (LogIsFlowEnabled())
2664 {
2665 static const WHV_REGISTER_NAME s_aNames[6] = { WHvX64RegisterCs, WHvX64RegisterRip, WHvX64RegisterRflags,
2666 WHvX64RegisterSs, WHvX64RegisterRsp, WHvX64RegisterCr0 };
2667 WHV_REGISTER_VALUE aRegs[RT_ELEMENTS(s_aNames)] = { { { {0, 0} } } };
2668 WHvGetVirtualProcessorRegisters(pVM->nem.s.hPartition, pVCpu->idCpu, s_aNames, RT_ELEMENTS(s_aNames), aRegs);
2669 LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2670 pVCpu->idCpu, aRegs[0].Segment.Selector, aRegs[1].Reg64, RT_BOOL(aRegs[2].Reg64 & X86_EFL_IF),
2671 aRegs[2].Reg64, aRegs[3].Segment.Selector, aRegs[4].Reg64, aRegs[5].Reg64));
2672 }
2673#endif
2674 WHV_RUN_VP_EXIT_CONTEXT ExitReason = {0};
2675 TMNotifyStartOfExecution(pVM, pVCpu);
2676
2677 HRESULT hrc = WHvRunVirtualProcessor(pVM->nem.s.hPartition, pVCpu->idCpu, &ExitReason, sizeof(ExitReason));
2678
2679 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2680 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2681#ifdef LOG_ENABLED
2682 LogFlow(("NEM/%u: Exit @ %04X:%08RX64 IF=%d CR8=%#x Reason=%#x\n", pVCpu->idCpu, ExitReason.VpContext.Cs.Selector,
2683 ExitReason.VpContext.Rip, RT_BOOL(ExitReason.VpContext.Rflags & X86_EFL_IF), ExitReason.VpContext.Cr8,
2684 ExitReason.ExitReason));
2685#endif
2686 if (SUCCEEDED(hrc))
2687 {
2688 /*
2689 * Deal with the message.
2690 */
2691 rcStrict = nemR3WinHandleExit(pVM, pVCpu, &ExitReason);
2692 if (rcStrict == VINF_SUCCESS)
2693 { /* hopefully likely */ }
2694 else
2695 {
2696 LogFlow(("NEM/%u: breaking: nemHCWinHandleMessage -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2697 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2698 break;
2699 }
2700 }
2701 else
2702 AssertLogRelMsgFailedReturn(("WHvRunVirtualProcessor failed for CPU #%u: %#x (%u)\n",
2703 pVCpu->idCpu, hrc, GetLastError()),
2704 VERR_NEM_IPE_0);
2705
2706 /*
2707 * If no relevant FFs are pending, loop.
2708 */
2709 if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2710 && !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2711 continue;
2712
2713 /** @todo Try handle pending flags, not just return to EM loops. Take care
2714 * not to set important RCs here unless we've handled a message. */
2715 LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2716 pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2717 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2718 }
2719 else
2720 {
2721 LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2722 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2723 }
2724 }
2725 else
2726 {
2727 LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2728 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2729 }
2730 break;
2731 } /* the run loop */
2732
2733
2734 /*
2735 * If the CPU is running, make sure to stop it before we try sync back the
2736 * state and return to EM. We don't sync back the whole state if we can help it.
2737 */
2738 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2739 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2740
2741 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)))
2742 {
2743 /* Try anticipate what we might need. */
2744 uint64_t fImport = IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI;
2745 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2746 || RT_FAILURE(rcStrict))
2747 fImport = CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT);
2748 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC
2749 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2750 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2751
2752 if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2753 {
2754 int rc2 = nemHCWinCopyStateFromHyperV(pVM, pVCpu, fImport | CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT);
2755 if (RT_SUCCESS(rc2))
2756 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2757 else if (RT_SUCCESS(rcStrict))
2758 rcStrict = rc2;
2759 if (!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL | (CPUMCTX_EXTRN_NEM_WIN_MASK & ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT))))
2760 pVCpu->cpum.GstCtx.fExtrn = 0;
2761 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2762 }
2763 else
2764 {
2765 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2766 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
2767 }
2768 }
2769 else
2770 {
2771 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2772 pVCpu->cpum.GstCtx.fExtrn = 0;
2773 }
2774
2775 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel,
2776 pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, VBOXSTRICTRC_VAL(rcStrict) ));
2777 return rcStrict;
2778}
2779
2780
2781/**
2782 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE}
2783 */
2784NEM_TMPL_STATIC DECLCALLBACK(int) nemHCWinUnsetForA20CheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
2785 PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
2786{
2787 /* We'll just unmap the memory. */
2788 if (pInfo->u2NemState > NEM_WIN_PAGE_STATE_UNMAPPED)
2789 {
2790 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhys, X86_PAGE_SIZE);
2791 if (SUCCEEDED(hrc))
2792 {
2793 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
2794 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2795 Log5(("NEM GPA unmapped/A20: %RGp (was %s, cMappedPages=%u)\n", GCPhys, g_apszPageStates[pInfo->u2NemState], cMappedPages));
2796 pInfo->u2NemState = NEM_WIN_PAGE_STATE_UNMAPPED;
2797 }
2798 else
2799 {
2800 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
2801 LogRel(("nemHCWinUnsetForA20CheckerCallback/unmap: GCPhys=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2802 GCPhys, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2803 return VERR_NEM_IPE_2;
2804 }
2805 }
2806 RT_NOREF(pVCpu, pvUser);
2807 return VINF_SUCCESS;
2808}
2809
2810
2811/**
2812 * Unmaps a page from Hyper-V for the purpose of emulating A20 gate behavior.
2813 *
2814 * @returns The PGMPhysNemQueryPageInfo result.
2815 * @param pVM The cross context VM structure.
2816 * @param pVCpu The cross context virtual CPU structure.
2817 * @param GCPhys The page to unmap.
2818 */
2819NEM_TMPL_STATIC int nemHCWinUnmapPageForA20Gate(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys)
2820{
2821 PGMPHYSNEMPAGEINFO Info;
2822 return PGMPhysNemPageInfoChecker(pVM, pVCpu, GCPhys, false /*fMakeWritable*/, &Info,
2823 nemHCWinUnsetForA20CheckerCallback, NULL);
2824}
2825
2826
2827void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2828{
2829 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2830 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2831}
2832
2833
2834VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2835 RTR3PTR pvMemR3, uint8_t *pu2State)
2836{
2837 Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2838 GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2839
2840 *pu2State = UINT8_MAX;
2841 if (pvMemR3)
2842 {
2843 STAM_REL_PROFILE_START(&pVM->nem.s.StatProfMapGpaRange, a);
2844 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvMemR3, GCPhys, cb,
2845 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute | WHvMapGpaRangeFlagWrite);
2846 STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfMapGpaRange, a);
2847 if (SUCCEEDED(hrc))
2848 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2849 else
2850 AssertLogRelMsgFailed(("NEMHCNotifyHandlerPhysicalDeregister: WHvMapGpaRange(,%p,%RGp,%RGp,) -> %Rhrc\n",
2851 pvMemR3, GCPhys, cb, hrc));
2852 }
2853 RT_NOREF(enmKind);
2854}
2855
2856
2857void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2858 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2859{
2860 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2861 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2862 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2863}
2864
2865
2866/**
2867 * Worker that maps pages into Hyper-V.
2868 *
2869 * This is used by the PGM physical page notifications as well as the memory
2870 * access VMEXIT handlers.
2871 *
2872 * @returns VBox status code.
2873 * @param pVM The cross context VM structure.
2874 * @param pVCpu The cross context virtual CPU structure of the
2875 * calling EMT.
2876 * @param GCPhysSrc The source page address.
2877 * @param GCPhysDst The hyper-V destination page. This may differ from
2878 * GCPhysSrc when A20 is disabled.
2879 * @param fPageProt NEM_PAGE_PROT_XXX.
2880 * @param pu2State Our page state (input/output).
2881 * @param fBackingChanged Set if the page backing is being changed.
2882 * @thread EMT(pVCpu)
2883 */
2884NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
2885 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
2886{
2887 /*
2888 * Looks like we need to unmap a page before we can change the backing
2889 * or even modify the protection. This is going to be *REALLY* efficient.
2890 * PGM lends us two bits to keep track of the state here.
2891 */
2892 RT_NOREF(pVCpu);
2893 uint8_t const u2OldState = *pu2State;
2894 uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_WIN_PAGE_STATE_WRITABLE
2895 : fPageProt & NEM_PAGE_PROT_READ ? NEM_WIN_PAGE_STATE_READABLE : NEM_WIN_PAGE_STATE_UNMAPPED;
2896 if ( fBackingChanged
2897 || u2NewState != u2OldState)
2898 {
2899 if (u2OldState > NEM_WIN_PAGE_STATE_UNMAPPED)
2900 {
2901 STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
2902 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst, X86_PAGE_SIZE);
2903 STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
2904 if (SUCCEEDED(hrc))
2905 {
2906 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2907 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
2908 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2909 if (u2NewState == NEM_WIN_PAGE_STATE_UNMAPPED)
2910 {
2911 Log5(("NEM GPA unmapped/set: %RGp (was %s, cMappedPages=%u)\n",
2912 GCPhysDst, g_apszPageStates[u2OldState], cMappedPages));
2913 return VINF_SUCCESS;
2914 }
2915 }
2916 else
2917 {
2918 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
2919 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2920 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2921 return VERR_NEM_INIT_FAILED;
2922 }
2923 }
2924 }
2925
2926 /*
2927 * Writeable mapping?
2928 */
2929 if (fPageProt & NEM_PAGE_PROT_WRITE)
2930 {
2931 void *pvPage;
2932 int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
2933 if (RT_SUCCESS(rc))
2934 {
2935 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, pvPage, GCPhysDst, X86_PAGE_SIZE,
2936 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute | WHvMapGpaRangeFlagWrite);
2937 if (SUCCEEDED(hrc))
2938 {
2939 *pu2State = NEM_WIN_PAGE_STATE_WRITABLE;
2940 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
2941 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2942 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2943 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2944 return VINF_SUCCESS;
2945 }
2946 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
2947 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2948 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2949 return VERR_NEM_INIT_FAILED;
2950 }
2951 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2952 return rc;
2953 }
2954
2955 if (fPageProt & NEM_PAGE_PROT_READ)
2956 {
2957 const void *pvPage;
2958 int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
2959 if (RT_SUCCESS(rc))
2960 {
2961 STAM_REL_PROFILE_START(&pVM->nem.s.StatProfMapGpaRangePage, a);
2962 HRESULT hrc = WHvMapGpaRange(pVM->nem.s.hPartition, (void *)pvPage, GCPhysDst, X86_PAGE_SIZE,
2963 WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute);
2964 STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfMapGpaRangePage, a);
2965 if (SUCCEEDED(hrc))
2966 {
2967 *pu2State = NEM_WIN_PAGE_STATE_READABLE;
2968 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
2969 uint32_t cMappedPages = ASMAtomicIncU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
2970 Log5(("NEM GPA mapped/set: %RGp %s (was %s, cMappedPages=%u)\n",
2971 GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState], cMappedPages));
2972 return VINF_SUCCESS;
2973 }
2974 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
2975 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp hrc=%Rhrc (%#x) Last=%#x/%u\n",
2976 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
2977 return VERR_NEM_INIT_FAILED;
2978 }
2979 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
2980 return rc;
2981 }
2982
2983 /* We already unmapped it above. */
2984 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2985 return VINF_SUCCESS;
2986}
2987
2988
2989NEM_TMPL_STATIC int nemHCJustUnmapPageFromHyperV(PVMCC pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
2990{
2991 if (*pu2State <= NEM_WIN_PAGE_STATE_UNMAPPED)
2992 {
2993 Log5(("nemHCJustUnmapPageFromHyperV: %RGp == unmapped\n", GCPhysDst));
2994 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
2995 return VINF_SUCCESS;
2996 }
2997
2998 STAM_REL_PROFILE_START(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
2999 HRESULT hrc = WHvUnmapGpaRange(pVM->nem.s.hPartition, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
3000 STAM_REL_PROFILE_STOP(&pVM->nem.s.StatProfUnmapGpaRangePage, a);
3001 if (SUCCEEDED(hrc))
3002 {
3003 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
3004 uint32_t cMappedPages = ASMAtomicDecU32(&pVM->nem.s.cMappedPages); NOREF(cMappedPages);
3005 *pu2State = NEM_WIN_PAGE_STATE_UNMAPPED;
3006 Log5(("nemHCJustUnmapPageFromHyperV: %RGp => unmapped (total %u)\n", GCPhysDst, cMappedPages));
3007 return VINF_SUCCESS;
3008 }
3009 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
3010 LogRel(("nemHCJustUnmapPageFromHyperV(%RGp): failed! hrc=%Rhrc (%#x) Last=%#x/%u\n",
3011 GCPhysDst, hrc, hrc, RTNtLastStatusValue(), RTNtLastErrorValue()));
3012 return VERR_NEM_IPE_6;
3013}
3014
3015
3016int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
3017 PGMPAGETYPE enmType, uint8_t *pu2State)
3018{
3019 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3020 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3021 RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
3022
3023 int rc;
3024 RT_NOREF_PV(fPageProt);
3025#ifdef NEM_WIN_WITH_A20
3026 if ( pVM->nem.s.fA20Enabled
3027 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3028#endif
3029 rc = nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3030#ifdef NEM_WIN_WITH_A20
3031 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3032 rc = nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3033 else
3034 rc = VINF_SUCCESS; /* ignore since we've got the alias page at this address. */
3035#endif
3036 return rc;
3037}
3038
3039
3040VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
3041 PGMPAGETYPE enmType, uint8_t *pu2State)
3042{
3043 Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3044 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3045 Assert(VM_IS_NEM_ENABLED(pVM));
3046 RT_NOREF(HCPhys, enmType, pvR3);
3047
3048 RT_NOREF_PV(fPageProt);
3049#ifdef NEM_WIN_WITH_A20
3050 if ( pVM->nem.s.fA20Enabled
3051 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3052#endif
3053 nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3054#ifdef NEM_WIN_WITH_A20
3055 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3056 nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3057 /* else: ignore since we've got the alias page at this address. */
3058#endif
3059}
3060
3061
3062VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
3063 RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
3064{
3065 Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
3066 GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
3067 Assert(VM_IS_NEM_ENABLED(pVM));
3068 RT_NOREF(HCPhysPrev, HCPhysNew, pvNewR3, enmType);
3069
3070 RT_NOREF_PV(fPageProt);
3071#ifdef NEM_WIN_WITH_A20
3072 if ( pVM->nem.s.fA20Enabled
3073 || !NEM_WIN_IS_RELEVANT_TO_A20(GCPhys))
3074#endif
3075 nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3076#ifdef NEM_WIN_WITH_A20
3077 else if (!NEM_WIN_IS_SUBJECT_TO_A20(GCPhys))
3078 nemHCJustUnmapPageFromHyperV(pVM, GCPhys, pu2State);
3079 /* else: ignore since we've got the alias page at this address. */
3080#endif
3081}
3082
3083
3084/**
3085 * Returns features supported by the NEM backend.
3086 *
3087 * @returns Flags of features supported by the native NEM backend.
3088 * @param pVM The cross context VM structure.
3089 */
3090VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3091{
3092 RT_NOREF(pVM);
3093 /** @todo Make use of the WHvGetVirtualProcessorXsaveState/WHvSetVirtualProcessorXsaveState
3094 * interface added in 2019 to enable passthrough of xsave/xrstor (and depending) features to the guest. */
3095 /** @todo Is NEM_FEAT_F_FULL_GST_EXEC always true? */
3096 return NEM_FEAT_F_NESTED_PAGING | NEM_FEAT_F_FULL_GST_EXEC;
3097}
3098
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